Width-adaptive data mirroring processing method and device, equipment and storage medium

Abstract

The invention is applicable to the technical field of computers, and provides a width-adaptive data mirroring processing method, device and equipment and a storage medium, and is characterized in that the method comprises the following steps: receiving input to-be-processed data, caching the to-be-processed data, segmenting the to-be-processed data according to a preset target data width, and storing the segmented to-be-processed data in a storage medium; obtaining cache addresses of all segmented to-be-processed data; and sequentially reading the cache addresses of all the segmented to-be-processed data, and processing the segmented to-be-processed data corresponding to the sequentially read cache addresses to obtain target data. According to the data mirroring processing method based on the adaptive width, the data processing efficiency and flexibility are effectively improved, the compatibility and expansibility in different application scenes are remarkably improved, and the efficient and reliable data mirroring processing function based on the adaptive width is achieved.

Description

Technical Field

[0001] This invention belongs to the field of data processing technology, and particularly relates to an adaptive width data mirroring processing method, apparatus, device and storage medium. Background Technology

[0002] In existing data processing systems, data transmission and processing need to adapt to diverse application scenarios and data formats. Therefore, data width often needs to be dynamically adjusted according to different application scenarios and data formats, and flexible adjustment of data width has become one of the core requirements.

[0003] However, traditional mirror processing devices generally suffer from the design limitation of fixed data width, only adapting to a single data processing scenario and failing to meet diverse data processing needs. For example, in the field of image signal processing, image acquisition and output at different resolutions often correspond to data streams with different bit widths, such as 8-bit, 16-bit, and 32-bit; and in high-speed communication scenarios, various communication protocols also have significantly different requirements for data transmission width. Traditional mirror devices with fixed data widths cannot dynamically respond to these changes, not only requiring additional format conversion steps during data processing, leading to low data processing efficiency and increased latency, but also limiting the system's compatibility with different data formats due to insufficient adaptability, thus restricting the scalability of the entire data processing system and making it difficult to adapt to the evolving needs of emerging application scenarios. Summary of the Invention

[0004] The purpose of this invention is to provide an adaptive width data mirroring processing method, apparatus, device, and storage medium, aiming to solve the problems of low data processing efficiency, poor compatibility, and poor scalability caused by the fixed data width in traditional mirroring processing technology, which cannot flexibly adapt to diverse data processing scenarios.

[0005] In a first aspect, the present invention provides an adaptive width data mirroring processing method, the method comprising: Receive input data to be processed, cache the data to be processed, segment the data to be processed according to a preset target data width, and obtain the cache address of all segments of data to be processed. Read the cache addresses of all segments of data to be processed in sequence, process the segments of data to be processed corresponding to the cache addresses read in sequence, and obtain the target data.

[0006] In some embodiments, the step of receiving input data to be processed and caching the data to be processed includes: The data to be processed is stored sequentially in a data FIFO buffer queue to cache the data.

[0007] In some embodiments, the step of segmenting the data to be processed according to a preset target data width to obtain the cache addresses of all segments of data to be processed includes: Perform data width detection on the data to be processed that is sequentially stored in the data FIFO buffer queue; When it is detected that the width of the data stored in the data FIFO buffer queue is equal to the target data width, the cache address of the current data segment to be processed is obtained, and the cache address of the current data segment to be processed is stored in the address FIFO buffer queue; The data width is then checked on the data to be processed that is sequentially stored in the data FIFO buffer queue until the cache addresses of all data segments to be processed are obtained, and all the obtained cache addresses are stored in the address FIFO buffer queue.

[0008] In some embodiments, the step of sequentially reading the cache addresses of all segments of data to be processed and processing the segments of data to be processed corresponding to the sequentially read cache addresses includes: Read the cache address of the data segment to be processed with the target data width from the address FIFO buffer queue; Using the read cache address as the starting address, read the current data segment to be processed from the data FIFO buffer queue in the direction of address decrease; The current data segment to be processed is processed, and the next data segment to be processed is read and processed iteratively to complete the processing of the data to be processed.

[0009] In some embodiments, the step of obtaining the cache address of the currently pending data segment includes: Determine whether the width of the current data segment to be processed is greater than the depth of the data FIFO buffer queue; When the width of the current data segment to be processed is less than or equal to the depth of the data FIFO buffer queue, obtain the cache address of the current data segment to be processed; When the width of the current data segment to be processed is greater than the depth of the data FIFO buffer queue, the current cache address of the current data segment to be processed is obtained, and the depth of the data FIFO buffer queue is subtracted from the obtained current cache address to obtain the actual cache address of the current data segment to be processed.

[0010] In some embodiments, the target data width is set based on the target data.

[0011] Secondly, the present invention provides an adaptive width data mirroring processing apparatus, the apparatus comprising: The cache address acquisition unit is used to receive the input data to be processed, cache the data to be processed, segment the data to be processed according to the preset target data width, and obtain the cache address of all segments of data to be processed. The data processing unit is used to sequentially read the cache addresses of all segments of data to be processed, process the segments of data to be processed corresponding to the sequentially read cache addresses, and obtain the target data.

[0012] In some embodiments, the cache address acquisition unit includes: A data caching unit is used to sequentially store the data to be processed into a data FIFO buffer queue to cache the data to be processed.

[0013] The address caching unit is used to store the cache address of the current data segment to be processed into the address FIFO buffer queue.

[0014] Thirdly, the present invention also provides a computing device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method described above.

[0015] Fourthly, the present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method described above.

[0016] This invention, through segmenting the data to be processed according to a preset target data width, enables the data to be processed within that target width, significantly improving the flexibility of data processing and adapting to diverse data stream bit width requirements in different scenarios. It also significantly enhances the compatibility and scalability of data processing in various application scenarios. By generating a cache address for each segment, errors during data transmission and processing are avoided. Furthermore, by sequentially reading the segmented data to be processed corresponding to the cache address, precise location, rapid reading, and processing of the target data are achieved, shortening the data processing cycle and effectively improving data processing efficiency. This results in efficient and reliable adaptive width data mirroring processing. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating an adaptive width data mirroring processing method according to an embodiment of the present invention; Figure 2 This is a specific example diagram of adaptive width data mirroring processing provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of an adaptive width data mirroring processing device provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a computing device provided in an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0019] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described feature, integral, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. Furthermore, the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. The terms "first," "second," and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Words such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Above," "below," "left," "right," etc., are used only to indicate relative positional relationships, which may change accordingly when the absolute position of the described object changes.

[0020] To keep the following description of the embodiments of the present invention clear and concise, detailed descriptions of some known functions and known components are omitted in this specification.

[0021] The specific implementation of the present invention will be described in detail below with reference to specific embodiments: Figure 1 A flowchart illustrating an adaptive width data mirroring processing method according to an embodiment of the present invention is shown. For ease of explanation, only the parts relevant to the embodiment of the present invention are shown, and are described in detail below: Step S101: Receive the input data to be processed, cache the data to be processed, divide the data to be processed into segments according to the preset target data width, and obtain the cache address of all segments of data to be processed.

[0022] This invention applies to computing devices, such as personal computers and servers. In this embodiment, input data to be processed is first received. This data can be input externally via a high-speed serial interface (HSI) or a parallel interface. The input data is buffered to prevent data loss or interruption during transmission or subsequent processing, ensuring the continuity of the data stream. Then, based on a user-preset target data width, the complete data in the buffer is divided into multiple equal-length segments. After segmentation, a unique buffer address is generated for each segment, indicating its storage location. This ensures accurate and orderly reading and processing of each segment.

[0023] In this embodiment of the invention, when caching the data to be processed, the data to be processed is divided into segments according to a preset target data width, thereby transforming the data to be processed of any length into several segments of data with target data width and corresponding cache addresses, providing an index basis for subsequent segment-by-segment processing, and further adapting to the data width requirements of different processing scenarios.

[0024] Step S102: Read the cache addresses of all segments of data to be processed in sequence, process the segments of data to be processed corresponding to the cache addresses read in sequence, and obtain the target data.

[0025] In this embodiment of the invention, after obtaining the cache addresses of all segmented data to be processed, the pre-generated cache addresses of the segmented data to be processed are read sequentially, and the corresponding segmented data to be processed is read according to each cache address. Then, each segmented data to be processed is processed according to a preset processing method, and finally the results of all segmented processing are integrated to obtain the target data.

[0026] This invention, through the orderly reading of the cache addresses of segmented data to be processed, enables the data to be transformed into the expected target data after being segmented and cached, thereby ensuring the integrity and correctness of data processing and further improving the efficiency and quality of data processing.

[0027] In some embodiments, when receiving input data to be processed and caching the data to be processed, the data to be processed is sequentially stored in a data FIFO buffer queue to cache the data to be processed.

[0028] In this embodiment of the invention, the data FIFO buffer queue adopts a first-in, first-out (FIFO) storage structure, which ensures that data is temporarily stored in the order of receipt, avoiding data corruption or loss. Data to be processed is written to the tail of the data FIFO buffer queue in the order of its arrival, and simultaneously, data to be processed is read from the head of the data FIFO buffer queue in the same order. This embodiment of the invention also dynamically manages the allocation and release of the data FIFO buffer queue, ensuring that the buffer capacity of the data FIFO buffer queue can cover the scale of the data to be processed and the temporary needs of segmented operations, preventing overflow or loss due to a rapid influx of data to be processed, and ensuring that the generated cache address is within the legal range of the cache space, avoiding data access errors caused by address out-of-bounds errors.

[0029] In some embodiments, when the data to be processed is segmented according to a preset target data width to obtain the cache addresses of all segments of data to be processed, the data width of the data to be processed stored sequentially in the data FIFO buffer queue is detected. When it is detected that the data width stored in the data FIFO buffer queue is equal to the target data width, the cache address of the current data segment to be processed is obtained and stored in the address FIFO buffer queue. This process continues to detect the data width of the data to be processed stored sequentially in the data FIFO buffer queue until the cache addresses of all data segments to be processed are obtained and all the obtained cache addresses are stored in the address FIFO buffer queue.

[0030] In this embodiment of the invention, as the data to be processed is continuously stored into the data FIFO buffer queue in sequence, the width of the data to be processed stored in the data FIFO buffer queue is simultaneously detected. Specifically, based on the target data width, a continuous segment of data to be processed is detected, and it is determined whether the actual data width it occupies is equal to the preset target data width. When it is detected that the width of the current data to be processed is equal to the target data width, the cache address of the current data segment to be processed in the data FIFO buffer queue is obtained, and the cache address is stored into the address FIFO buffer queue in sequence, so that the order of the cache addresses is consistent with the storage order of the data segments to be processed in the data FIFO. After obtaining and storing the cache address of the current data segment to be processed, the data width of the data to be processed stored sequentially in the data FIFO buffer queue is checked. The above steps of detecting a continuous data segment to be processed based on the target data width and determining whether the actual data width occupied by it is equal to the preset target data width are repeated. If the width of the current data segment to be processed is equal to the target data width, the cache address of the current data segment to be processed in the data FIFO buffer queue is obtained and the cache address is stored in the address FIFO buffer queue in order. This process continues until the remaining data in the data FIFO buffer queue is insufficient to form a complete data segment to be processed with the target data width or the end of the data FIFO buffer queue has been reached. All the obtained cache addresses are stored in the address FIFO buffer queue, which stores the cache addresses of all segments of data to be processed in the storage order.

[0031] This invention embodiment detects the width of the data to be processed sequentially stored in the data FIFO buffer queue. It compares the detected width of the data stored in the data FIFO buffer queue with the target width. When the width of the current data to be processed is equal to the target width, it obtains the cache address of the current data segment to be processed and stores the cache address of the current data segment to be processed in the address FIFO buffer queue. This ensures a one-to-one correspondence between the data segment to be processed and its cache address, and provides an index basis for subsequently reading the address and processing the corresponding data segment.

[0032] In some embodiments, when sequentially reading the cache addresses of all segments of data to be processed and processing the segments of data to be processed corresponding to the sequentially read cache addresses, the cache address of the data segment to be processed with the target data width is read from the address FIFO buffer queue. The read cache address is used as the starting address, and the current data segment to be processed with the target data width is read from the data FIFO buffer queue in the direction of address decrease. The current data segment to be processed is processed, and so on, the next data segment to be processed is read and processed, thereby completing the processing of the data to be processed.

[0033] In this embodiment of the invention, when starting to sequentially read and process the data to be processed, which is segmented according to the target data width and cached in a data FIFO buffer queue, a cache address is first read from the address FIFO buffer queue. This cache address is the starting address of the current data segment to be processed. Based on the obtained starting address, the current data segment to be processed, with the target data width, is continuously read from the data FIFO buffer queue in a decreasing address direction. The current data segment to be processed successfully read from the data FIFO buffer queue is then subjected to corresponding data processing operations. These operations are not limited to numerical calculations, encoding conversions, filtering, compression, feature extraction, or encryption, etc., to transform the current data segment to be processed into target data of a preset format. After processing the current data segment to be processed, the next cache address is read from the address FIFO buffer queue as the starting address of the next data segment to be processed. Based on this new starting address, the next data segment to be processed, with the target data width, is read from the data FIFO buffer queue in a decreasing address direction, and the same processing operations are performed on this next data segment. This process is repeated continuously, sequentially traversing all segment addresses in the address FIFO buffer queue until all cache addresses corresponding to all segment data have been read and there is no more address information available for reading in the address FIFO buffer queue. This indicates that all data segments to be processed have been scheduled and processed, the iteration ends, and the entire data to be processed is transformed into target data through orderly reading and processing.

[0034] This invention, through its embodiments, reads the cache address of the data segment to be processed with the target data width from the address FIFO buffer queue, uses the read cache address as the starting address, and reads the current data segment to be processed with the target data width from the data FIFO buffer queue in a decreasing direction. The current data segment to be processed is then processed. While efficiently utilizing the data FIFO buffer queue for data caching, it ensures that each segment of data to be processed can be read and processed through its cache address stored in the address FIFO buffer queue, ultimately reliably realizing the transformation from raw input to target data.

[0035] In some embodiments, when obtaining the cache address of the current data segment to be processed, it is determined whether the data width of the current data segment to be processed is greater than the depth of the data FIFO buffer queue. When the data width of the current data segment to be processed is less than or equal to the depth of the data FIFO buffer queue, the cache address of the current data segment to be processed is obtained. When the data width of the current data segment to be processed is greater than the depth of the data FIFO buffer queue, the current cache address of the current data segment to be processed is obtained. The current cache address is subtracted from the depth of the data FIFO buffer queue to obtain the actual cache address of the current data segment to be processed.

[0036] In this embodiment of the invention, in order to obtain the actual cache address of the current data segment to be processed from the data FIFO buffer queue, it is necessary to further determine the cache address based on the depth of the data FIFO buffer queue itself. Specifically, first, it is determined whether the data width of the current data segment to be processed is greater than the depth of the data FIFO buffer queue. If the data width of the current data segment to be processed is less than or equal to the depth of the data FIFO buffer queue, it means that the current data segment to be processed is completely located within the current effective storage area of ​​the queue, without any boundary crossing or wrapping. At this time, the cache address of the current data segment to be processed in the data FIFO buffer queue can be directly obtained. This cache address is the actual cache address and can be directly used as the starting position for subsequent reading. If the determination result is that the data width of the current data segment to be processed is greater than the depth of the data FIFO buffer queue, it means that the current data segment to be processed cannot be completely stored within a continuous physical storage area of ​​the data FIFO buffer queue. It is necessary to utilize the circular wrapping characteristic of the data FIFO buffer queue to achieve complete storage and reading. At this point, before reading the current data segment to be processed, the current cache address of the current data segment to be processed is first obtained in the data FIFO buffer queue. Since the depth of the data FIFO buffer queue represents the maximum data span that the queue can accommodate in a single operation, the actual cache address of the current data segment to be processed in the data FIFO can be calculated by subtracting the depth of the data FIFO buffer queue from this current cache address. This avoids data loss or repeated reading due to address misjudgment when reading data according to the actual cache address in the future.

[0037] In this embodiment of the invention, when the width of the current data segment to be processed is less than or equal to the depth of the data FIFO buffer queue, the cache address of the current data segment to be processed is set as the actual cache address of the current data segment to be processed. When the width of the current data segment to be processed is greater than the depth of the data FIFO buffer queue, the current cache address minus the depth of the data FIFO buffer queue is set as the actual cache address of the current data segment to be processed. This achieves the correct association between the cache address and the data segment to be processed, thereby ensuring that subsequent read and processing operations based on the cache address can completely and orderly obtain the expected current data segment to be processed. This avoids address resolution errors caused by the depth limitation of the data FIFO buffer queue or cyclic overwriting, and improves the robustness of the overall segment address acquisition process and the reliability of data access.

[0038] In some embodiments, the target data width is set based on the target data. Specifically, the target data width is preset according to the format of the final output target data, and then the data to be processed is segmented according to the target data width. For example, the user presets a default target data width, but when different types or different lengths of target data need to be processed, the user can dynamically adjust the target data width according to the specific format requirements corresponding to these different types or different lengths of target data, and re-segment, store and process the data to be processed based on the adjusted target data width, and finally obtain target data that conforms to the adjusted target data width specification.

[0039] Figure 2 A specific example diagram of adaptive width data mirroring processing provided by an embodiment of the present invention is shown. For example... Figure 2 As shown, the current data FIFO buffer queue has a depth of D and a target data width of W. Here, W is a positive integer, and D ranges from 4W. <D<5W。

[0040] As can be seen from the first row of data to be processed, the width of the current data to be processed is less than the depth of the data FIFO buffer queue. The data to be processed is segmented according to the preset target data width W, resulting in a buffer address of W for the first segment, 2W for the second, 3W for the third, and 4W for the fourth. These buffer addresses are then stored sequentially into the address FIFO buffer queue. After storing the fourth segment, the remaining data storage space in the data FIFO buffer queue is insufficient to store the next segment with a target data width of W. Therefore, the corresponding buffer addresses stored sequentially in the address FIFO buffer queue are W, 2W, 3W, and 4W.

[0041] As can be seen from the data to be processed stored in the second row, the width of the current data to be processed is greater than the depth of a data FIFO buffer queue. The data to be processed is segmented according to the preset target data width W. The current cache address of the fifth data segment is 5W, and the actual cache address is corrected to 5W - D. The current cache address of the sixth data segment is 6W, and the actual cache address is corrected to 6W - D. The current cache address of the seventh data segment is 7W, and the actual cache address is corrected to 7W - D. The current cache address of the eighth data segment is 8W, and the actual cache address is corrected to 8W - D. After storing the eighth data segment, the remaining data storage space in the data FIFO buffer queue is insufficient to store the next data segment with a target data width W. Therefore, the corresponding cache addresses stored sequentially in the address FIFO buffer queue are W, 2W, 3W, 4W, 5W - D, 6W - D, 7W - D, and 8W - D.

[0042] As can be seen from the data to be processed stored in the third row, the width of the current data to be processed is greater than the depth of the two data FIFO buffer queues. The data to be processed is segmented according to the preset target data width W. The current cache address of the ninth data segment is 9W, and the actual cache address is 9W - 2D. The current cache address of the tenth data segment is 10W, and the actual cache address is 10W - 2D. The current cache address of the eleventh data segment is 11W, and the actual cache address is 11W - 2D. The current cache address of the twelfth data segment is 12W, and the actual cache address is 12W - 2D. After storing the twelfth data segment, the remaining data storage space in the data FIFO buffer queue is insufficient to store the next data segment with a target data width W. At this point, the corresponding cache addresses stored in the address FIFO buffer queue in sequence are W, 2W, 3W, 4W, 5W-D, 6W-D, 7W-D, 8W-D, 9W-2D, 10W-2D, 11W-2D, and 12W-2D.

[0043] As an example, suppose the cache address read from the address FIFO buffer queue is N=3W. Taking cache address N as the starting address, according to the reading rule, N, N-1, N-2, …, N-W+1 are accessed sequentially in the address decreasing direction until the preset target data width W is covered. Substituting N=3W, the read address sequence is: 3W, 3W−1, 3W−2, …, 3W−W+1; where the ending address of the sequence is 2W+1. Therefore, the actual read address range is from 2W+1 to 3W. By reading the corresponding contiguous stored data from the data FIFO buffer queue according to the above address range of 2W+1 to 3W, the data segment to be processed with a target data width of W can be obtained. Then, the read data segment to be processed is processed accordingly, and the expected target data can be obtained after processing.

[0044] For example, suppose the cache address read from the address FIFO buffer queue is N = 5W - D. Taking cache address N as the starting address, according to the reading rule, N, N-1, N-2, …, N-W+1 are accessed sequentially in the address decreasing direction until the preset target data width W is covered. Substituting N = 5W - D, the read address sequence is: (5W-D), (5W-D-1), (5W-D-2), …, (5W-D-W+1); where the ending address of the sequence is 5W-D-W+1. Therefore, the actual address range read is from 5W-D-W+1 to 5W - D. By reading the corresponding contiguous stored data from the data FIFO buffer queue according to the above address range 5W-D-W+1 to 5W - D, the data segment to be processed with a target data width of W can be obtained. Then, the read data segment to be processed is processed accordingly, and the expected target data can be obtained after processing.

[0045] Figure 3 A schematic diagram of an adaptive width data mirroring processing apparatus according to an embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown, wherein the adaptive width data mirroring processing apparatus includes: The cache address acquisition unit 301 is used to receive the input data to be processed, cache the data to be processed, segment the data to be processed according to the preset target data width, and obtain the cache address of all segments of data to be processed. The data processing unit 302 is used to sequentially read the cache addresses of all segments of data to be processed, process the segments of data to be processed corresponding to the sequentially read cache addresses, and obtain the target data.

[0046] In some embodiments, the cache address acquisition unit includes: The data caching unit is used to sequentially store the data to be processed into the data FIFO buffer queue in order to cache the data to be processed.

[0047] The address caching unit is used to store the cache address of the current data segment to be processed into the address FIFO buffer queue.

[0048] In this embodiment of the invention, for the sake of convenience and brevity, only the division of the above-described functional units and modules is used as an example. In practical applications, the above functions can be allocated to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to achieve all or part of the functions described above. Each unit and module of the device can be implemented by corresponding hardware or software units. Each unit and module can be an independent hardware or software unit, or it can be integrated into a single hardware or software unit, which is not intended to limit the invention. In addition, the specific names of each functional unit and module are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the device can be referred to the corresponding description in the foregoing method embodiments, and will not be repeated here.

[0049] Figure 4 The structure of a computing device provided in an embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown.

[0050] The computing device 4 of this embodiment includes a processor 40, a memory 41, and a computer program 42 stored in the memory 41 and executable on the processor 30. When the processor 40 executes the computer program 42, it implements the steps in the various adaptive width data mirroring method embodiments described above, for example... Figure 1 The steps S101 to S102 are shown. Alternatively, when the processor 40 executes the computer program 42, it implements the functions of each unit in the above-described device embodiments, for example... Figure 3 The function shown is to obtain the cache address from 301 to the data processing unit 302.

[0051] In this embodiment of the invention, the input data to be processed is received, the data to be processed is cached, the data to be processed is segmented according to a preset target data width, and the cache addresses of all segments of data to be processed are obtained; the cache addresses of all segments of data to be processed are read in sequence, and the segments of data to be processed corresponding to the read cache addresses are processed to obtain the target data.

[0052] The computing device 4 in this embodiment of the invention can be a personal computer, mobile device, etc. The steps implemented by the processor 40 in this computing device 4 when executing the computer program 42 to implement the adaptive width data mirroring processing method can be referred to the description of the foregoing method embodiments, and will not be repeated here.

[0053] In this embodiment of the invention, a computer-readable storage medium is provided, which stores a computer program that, when executed by a processor, implements the steps described in the embodiments of the adaptive width data mirroring processing device method. For example... Figure 1 The steps S101 to S102 are shown. Alternatively, when the computer program is executed by the processor, it implements the functions of each unit in the above-described device embodiments, for example... Figure 3 The functions of the cache address acquisition unit 301 to the data processing unit 302 are shown.

[0054] In this embodiment of the invention, the input data to be processed is received, the data to be processed is cached, the data to be processed is segmented according to a preset target data width, and the cache addresses of all segments of data to be processed are obtained; the cache addresses of all segments of data to be processed are read in sequence, and the segments of data to be processed corresponding to the read cache addresses are processed to obtain the target data.

[0055] The computer-readable storage medium of this invention can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EEPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this invention, the computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0056] The above embodiments are merely illustrative of the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the scope of disclosure involved in the above embodiments is not limited to technical solutions formed by specific combinations of the above technical features, but should also cover other technical solutions formed by arbitrary combinations of the above technical features or their equivalent features without departing from the above-disclosed concept. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0057] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in sequential order. In certain circumstances, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the invention. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

Claims

1. A method for processing data mirroring with adaptive width, characterized in that, The method includes: Receive input data to be processed, cache the data to be processed, segment the data to be processed according to a preset target data width, and obtain the cache address of all segments of data to be processed. Read the cache addresses of all segments of data to be processed in sequence, process the segments of data to be processed corresponding to the cache addresses read in sequence, and obtain the target data.

2. The method of claim 1, wherein, The steps of receiving input data to be processed and caching the data to be processed include: The data to be processed is stored sequentially in a data FIFO buffer queue to cache the data.

3. The method of claim 2, wherein, The step of segmenting the data to be processed according to a preset target data width to obtain the cache addresses of all segments of data to be processed includes: Perform data width detection on the data to be processed that is sequentially stored in the data FIFO buffer queue; When it is detected that the width of the data stored in the data FIFO buffer queue is equal to the target data width, the cache address of the current data segment to be processed is obtained, and the cache address of the current data segment to be processed is stored in the address FIFO buffer queue; The data width is then checked on the data to be processed that is sequentially stored in the data FIFO buffer queue until the cache addresses of all data segments to be processed are obtained, and all the obtained cache addresses are stored in the address FIFO buffer queue.

4. The method of claim 3, wherein, The steps of sequentially reading the cache addresses of all segments of data to be processed and processing the segments of data corresponding to the sequentially read cache addresses include: Read the cache address of the data segment to be processed with the target data width from the address FIFO buffer queue; Using the read cache address as the starting address, read the current data segment to be processed from the data FIFO buffer queue in the direction of address decrease; The current data segment to be processed is processed, and the next data segment to be processed is read and processed iteratively to complete the processing of the data to be processed.

5. The method of claim 3, wherein, The steps to obtain the cache address of the currently pending data segment include: Determine whether the width of the current data segment to be processed is greater than the depth of the data FIFO buffer queue; When the width of the current data segment to be processed is less than or equal to the depth of the data FIFO buffer queue, obtain the cache address of the current data segment to be processed; When the width of the current data segment to be processed is greater than the depth of the data FIFO buffer queue, the current cache address of the current data segment to be processed is obtained, and the depth of the data FIFO buffer queue is subtracted from the obtained current cache address to obtain the actual cache address of the current data segment to be processed.

6. The method as described in claim 1, characterized in that, The target data width is set according to the target data.

7. A data mirroring processing device with adaptive width, characterized in that, The device includes: The cache address acquisition unit is used to receive the input data to be processed, cache the data to be processed, segment the data to be processed according to the preset target data width, and obtain the cache address of all segments of data to be processed. The data processing unit is used to sequentially read the cache addresses of all segments of data to be processed, process the segments of data to be processed corresponding to the sequentially read cache addresses, and obtain the target data.

8. The apparatus as claimed in claim 7, characterized in that, The cache address acquisition unit includes: A data caching unit is used to sequentially store the data to be processed into a data FIFO buffer queue to cache the data to be processed. The address caching unit is used to store the cache address of the current data segment to be processed into the address FIFO buffer queue.

9. A computing device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1 to 6.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 6.

Images