Data processing method and device for matrix multiplication kernel function, medium, equipment and product
By introducing a ready state flag and asynchronous signals into the matrix multiplication kernel function, the pipelined overlapping execution of the main loop and the tail stage is achieved, which solves the problem of low hardware resource utilization and improves computational efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 广州壁仞智能科技有限公司
- Filing Date
- 2026-02-09
- Publication Date
- 2026-04-17
AI Technical Summary
In existing technologies, the hardware resource utilization of general matrix multiplication kernel functions is not high, resulting in wasted computing power, especially when the proportion of computational power is large in the final stage.
By configuring a ready status flag for each output block in the main loop phase and updating the status flag using asynchronous signals, the earliest completed output block is allowed to immediately enter the post-processing operation in the tail phase, thereby achieving pipeline overlap execution between the main loop and the tail phase.
It significantly improves the utilization rate of hardware resources and computing efficiency, reduces the idle waiting time of general-purpose cores, and enhances overall computing performance.
Smart Images
Figure CN121880703A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and in particular to a data processing method, apparatus, computer-readable storage medium, electronic device, and computer program product for matrix multiplication kernel functions. Background Technology
[0002] The General Matrix Multiply (GEMM) kernel function typically employs a two-stage structure: a main loop and an epilogue. The main loop iterates through the tensor core (Tcore) to perform matrix multiplication and caches the output in an accumulator register. The epilogue uses the vector core (Vcore) to post-process the output in the accumulator register.
[0003] To ensure the correctness of data computation, certain programming paradigms (such as CUTLASS) require that the final phase only begin after the main loop phase has completely finished. Clearly, existing programming paradigms have low hardware resource utilization and waste computational power. Summary of the Invention
[0004] The purpose of this invention is to provide a data processing method, apparatus, computer-readable storage medium, electronic device, and computer program product for matrix multiplication kernel functions. By using a ready state identifier, the computational status of each output block in the main loop stage is monitored, and the coarse-grained serial logic of "waiting for the full amount" is optimized into fine-grained parallel logic of "processing any output block as soon as it is ready". This can fully tap the parallel potential of heterogeneous computing units and significantly improve the utilization rate of hardware resources and computational efficiency.
[0005] A first aspect of the present invention provides a data processing method for a matrix multiplication kernel function, the matrix multiplication kernel function including a main loop phase and a tail phase; the method includes: For each output block in the main loop phase output results, a corresponding ready status flag is configured; wherein, each ready status flag is updated by the sub-workgroup that executes the related calculation tasks of the corresponding output block. After the nth ready state flag indicates that the main loop computation task of the nth output block has been completed, the post-processing operation of the tailing stage is performed on the nth output block to achieve the overlap of the execution time of the main loop stage and the tailing stage; where 1≤n≤N; N is the total number of output blocks.
[0006] Optionally, the ready status identifier is updated through the following steps: In the main loop phase, when the nth output block is completed, the corresponding sub-workgroup sends an asynchronous signal. Based on the asynchronous signal, the nth ready state flag is updated to a state value representing the completion of the main loop computation task corresponding to the nth output block.
[0007] Optionally, the output of the main loop phase is calculated through the following steps: The left matrix is divided into M1 row sub-blocks, and the right matrix is divided into M2 column sub-blocks; where... ; ; Perform matrix multiplication on each pair of row sub-blocks and column sub-blocks to obtain the output block at the corresponding position in the output result; All output blocks are combined according to their positions to obtain the output result.
[0008] Optionally, the output of the main loop phase is calculated through the following steps: The left matrix is divided into M3 column sub-blocks, and the right matrix is divided into M3 row sub-blocks; where... ; Perform multiplication and summation on each pair of row and column sub-blocks to obtain the corresponding intermediate results; The last intermediate result is taken as the output result.
[0009] Optionally, in the main loop phase, the multiply-accumulate calculation corresponding to the last intermediate result is split into N calculation subtasks, and each calculation subtask is assigned to a corresponding sub-workgroup for execution to complete the calculation of the corresponding output block.
[0010] Optionally, the ready state identifier is created during the calculation of the last intermediate result.
[0011] A second aspect of the present invention provides a data processing apparatus for a matrix multiplication kernel function, the matrix multiplication kernel function including a main loop stage and a tail stage; the apparatus includes: The status flag configuration module is used to configure a corresponding ready status flag for each output block in the main loop stage output result; wherein, each ready status flag is updated by the sub-workgroup that executes the related calculation task of the corresponding output block. The post-processing operation triggering module is used to perform the post-processing operation of the tail stage on the nth output block after the nth ready state flag indicates that the main loop calculation task of the nth output block has been completed, so as to achieve the overlap of the execution time of the main loop stage and the tail stage; where 1≤n≤N; N is the total number of output blocks.
[0012] A third aspect of the present invention provides a computer-readable storage medium comprising a stored computer program; wherein, when the computer program is executed, it controls the device on which the computer-readable storage medium is located to perform the data processing method for a matrix multiplication kernel function as described in any embodiment of the first aspect.
[0013] A fourth aspect of the present invention provides a computer program product, including computer instructions, which, when executed by a processor, implement the data processing method for matrix multiplication kernel functions as described in any embodiment of the first aspect.
[0014] A fifth aspect of the present invention provides an electronic device including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor, when executing the computer program, implements the data processing method for a matrix multiplication kernel function as described in any embodiment of the first aspect.
[0015] Compared with the prior art, the embodiments of the present invention provide a data processing method, apparatus, computer-readable storage medium, electronic device, and computer program product for matrix multiplication kernel functions, which have the following beneficial effects: The embodiments of the present invention refine the synchronization granularity from "thread block level" to "sub-workgroup level" and introduce a ready state flag as a tool for asynchronous coordination, so that the post-processing operation corresponding to the output block that completes the calculation earliest in the main loop phase can start earliest without waiting for other output blocks to complete the calculation. This realizes the pipelined overlapping execution of the main loop phase and the tail phase at the block granularity, which can effectively shorten the idle waiting time of the general core and significantly improve the utilization rate of hardware resources and computing efficiency. Attached Figure Description
[0016] Figure 1 This is a flowchart illustrating an embodiment of the data processing method for matrix multiplication kernel functions provided by the present invention; Figure 2 This is a schematic diagram of an embodiment of the main loop stage and tail stage execution pipeline provided by the present invention; Figure 3 This is a schematic diagram of an embodiment of the calculation output results provided by the present invention; Figure 4 This is a schematic diagram of an embodiment of the data processing device for matrix multiplication kernel functions provided by the present invention; Figure 5 This is a schematic diagram of the structure of an embodiment of the electronic device provided by the present invention; Figure 6 This is a schematic diagram of the structure of an embodiment of the artificial intelligence processor provided by the present invention. Detailed Implementation
[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0018] See Figure 1 This is a flowchart illustrating an embodiment of the data processing method for matrix multiplication kernel functions provided by the present invention.
[0019] A first aspect of the present invention provides a data processing method for a matrix multiplication kernel function, wherein the matrix multiplication kernel function includes a main loop stage and a tail stage; the method includes steps S1 to S2, as follows: Step S1: Configure a corresponding ready status flag for each output block in the main loop stage output results; wherein, each ready status flag is updated by the sub-workgroup that executes the related calculation task of the corresponding output block; Step S2: After the nth ready state flag indicates that the main loop calculation task of the nth output block has been completed, the post-processing operation of the tail stage is performed on the nth output block to achieve the overlap of the execution time of the main loop stage and the tail stage; where 1≤n≤N; N is the total number of output blocks.
[0020] It should be noted that during the main loop phase, the output result of the current thread block is divided into N output blocks; the related computation tasks of each output block are assigned to the corresponding sub-workgroup within the thread block for execution. To establish fine-grained execution dependencies, this embodiment of the invention configures a corresponding ready state flag for each output block. Each ready state flag is used to indicate the computation status (i.e., computation completed / incomplete) of the corresponding output block during the main loop phase.
[0021] The epilogue phase continuously monitors the state changes of all ready status flags. When any ready status flag indicates that the corresponding output block is ready, the epilogue phase immediately performs post-processing operations (such as scaling, activation, quantization, etc.) on that output block. Since different output blocks complete their computation at different times, the triggering times of their corresponding ready status flags also differ. Therefore, the post-processing operations corresponding to the output block that completes its computation earliest can begin earliest, without waiting for other output blocks to finish computation.
[0022] like Figure 2The diagram shown is a schematic representation of an embodiment of the main loop phase and tail phase execution pipeline provided by the present invention. In related technologies, the main loop phase must complete all output blocks (i.e., C1 to C2). N After the calculation of the general core (Vcore) is completed, the system will uniformly enter the epilogue stage to perform post-processing operations. Clearly, the general core (Vcore) must wait for the tensor core (Tcore) to complete before it can be used, resulting in low hardware resource utilization. This is especially true for matrix multiplications with small accumulation dimensions, where the epilogue stage accounts for a large proportion, making the problem of idle computing power in related technologies even more prominent. In contrast, the embodiments of this invention, in any output block C... n Once the calculation is complete, the post-processing phase begins immediately without waiting for other output blocks. In other words, the calculation of subsequent output blocks in the main loop phase and the post-processing of ready output blocks in the epilogue phase can be performed in parallel, thus achieving an overlap in the execution time of the two phases.
[0023] In summary, the embodiments of the present invention refine the synchronization granularity from "thread block level" to "sub-workgroup level" and introduce ready state flags as a tool for asynchronous coordination, so that the earliest available output blocks can be processed by subsequent operations in a timely manner, which can effectively shorten the idle waiting time of Vcore, thereby significantly improving the utilization of hardware resources and computational efficiency.
[0024] In an optional embodiment, the ready state identifier is updated through the following steps: In the main loop phase, when the nth output block is completed, the corresponding sub-workgroup sends an asynchronous signal. Based on the asynchronous signal, the nth ready state flag is updated to a state value representing the completion of the main loop computation task corresponding to the nth output block.
[0025] It should be noted that the ready state identifier in this embodiment of the invention is uniformly managed through an asynchronous completion descriptor object that can be shared by all sub-workgroups within a thread block. Internally, this object maintains an independent signal slot for each sub-workgroup, and each signal slot is bound to a corresponding asynchronous wait signal. The specific implementation process is as follows: ① Subgroup division and setting wait signals: For example, the computation of the last multiply-accumulate data block in the main loop stage is divided into multiple subgroups (such as W1 to W...). N Each sub-workgroup, after issuing a computation instruction, independently sets an asynchronous waiting signal (i.e., a ready state indicator, initially indicating that the computation is not completed, and at the end indicating that the computation is completed), and uses it in the epilogue phase to wait for the "mainloop data of the corresponding sub-workgroup" to complete.
[0026] ② Define the asynchronous completion descriptor: Create an asynchronous completion descriptor, such as a class or struct, to pass asynchronous signals between the main loop and the epilogue. Name it AsyncGmmaAccumDesc and include the multiple asynchronous wait signals set in ①.
[0027] ③ The mainloop returns an asynchronous completion descriptor object: At the end of the mainloop function, an AsyncGmmaAccumDesc object is constructed and returned to the caller (i.e., the epilogue function).
[0028] ④ Epilogue waits for data and performs calculations: After receiving the AsyncGmmaAccumDesc object returned by the mainloop function, the epilogue function must wait for the asynchronous signal corresponding to the sub-workgroup Wn before performing post-processing operations on that sub-workgroup, ensuring that the output blocks C are processed. n It is ready.
[0029] As can be seen from the above, the embodiments of the present invention split the entire thread block-level synchronization into sub-workgroup-level synchronization, so that the sub-workgroup that completes the calculation earliest sends out a hardware signal and enters the epilogue stage in advance, realizing pipeline overlap between the main loop and the epilogue, thereby improving the utilization of hardware resources.
[0030] It is worth noting that the output of the main loop phase can be calculated in at least two ways: the first is by combining the output blocks, and the second is by accumulating the intermediate results, as detailed below: In the first implementation, the output of the main loop phase is calculated through the following steps: The left matrix is divided into M1 row sub-blocks, and the right matrix is divided into M2 column sub-blocks; where... ; ; Perform matrix multiplication on each pair of row sub-blocks and column sub-blocks to obtain the output block at the corresponding position in the output result; All output blocks are combined according to their positions to obtain the output result.
[0031] It should be noted that, in this embodiment of the invention, the left matrix A is divided into M1 row sub-blocks along the row direction, each row sub-block containing several consecutive rows of A; the right matrix B is divided into M2 column sub-blocks along the column direction, each column sub-block containing several consecutive columns of B. Each pair of row and column sub-blocks is calculated through a complete matrix multiplication to obtain the corresponding output block in the output matrix. This matrix multiplication calculation itself needs to be completed through an internal loop iteration. During the iteration, the data in the row and column sub-blocks are multiplied and accumulated, and the results are accumulated in the accumulation register. After all output blocks have been calculated, the complete output result C = A × B is obtained.
[0032] Preferably, in this embodiment of the invention, before the computation begins, the thread block is divided into N = M1 × M2 sub-workgroups, and the computation task of each output block is independently assigned to the corresponding sub-workgroup; for example, sub-workgroup W n Responsible for outputting block C n The entire calculation process.
[0033] In the second implementation, the output of the main loop phase is calculated through the following steps: The left matrix is divided into M3 column sub-blocks, and the right matrix is divided into M3 row sub-blocks; where... ; Perform multiplication and summation on each pair of row and column sub-blocks to obtain the corresponding intermediate results; The last intermediate result is taken as the output result.
[0034] like Figure 3 The diagram shown is a schematic representation of an embodiment of the calculation output provided by this invention. In this embodiment, the left matrix A is divided into M3 column sub-blocks along the column direction. Each column sub-block contains a continuous TileK column of A, as shown below. Figure 3 The data block has a size of TileM×TileK; the right matrix B is divided into M3 row sub-blocks along the row direction, and each row sub-block contains TileK consecutive rows of B, such as... Figure 3 The data block has a size of TileK×TileN; where TileM is the row dimension of A and TileN is the column dimension of B.
[0035] The calculation process in this embodiment of the invention is a sequential iterative multiplication-accumulation operation with M3 iterations. In each iteration, a column sub-block of the left matrix A and the corresponding row sub-block of the right matrix B are taken, the matrix product of these two sub-blocks is calculated, and the product is accumulated in the accumulation register group to obtain the intermediate result corresponding to the current iteration. After all iterations, the intermediate result stored in the accumulation register group is the final output result.
[0036] In an optional embodiment, during the main loop phase, the multiply-accumulate calculation corresponding to the last intermediate result is split into N calculation subtasks, and each calculation subtask is assigned to a corresponding sub-workgroup for execution to complete the calculation of the corresponding output block.
[0037] Furthermore, the ready state identifier is created during the calculation of the last intermediate result.
[0038] It should be noted that, for the second implementation method described above, the last column sub-block of A (denoted as A) sub _ end The last line subblock of B (denoted as B) sub _ end The multiplication and accumulation calculation of the matrix multiplication is performed to obtain the last intermediate result. In this embodiment of the invention, the multiplication and accumulation calculation corresponding to the last intermediate result is divided into N computational subtasks and assigned to N sub-workgroups. Each sub-workgroup will complete one or more matrix multiplication instructions. Figure 3 In the middle, A sub _ end and B sub _ end Further subdivided, sub-working group W1 calculated A sub _ end and B sub _ end The first data block (the orange data block in A and B) completes the final calculation step for output block C1.
[0039] As mentioned earlier, the ready status identifier is uniformly managed through the AsyncGmmaAccumDesc object. The AsyncGmmaAccumDesc object is created at the beginning of the matrix multiplication kernel function execution (when the main loop starts). Functionally, there is no fundamental difference between creating it during the calculation of the last intermediate result and creating it during the initial stage; both can identify the ready status of the output block. However, considering the characteristics of register usage, their impact on kernel function performance differs significantly.
[0040] If the AsyncGmmaAccumDesc object is constructed at the start of the main loop, the compiler will allocate a dedicated register for this object and continuously occupy it when compiling the kernel function code, leading to an unnecessary increase in register pressure. When the register occupancy reaches the hardware limit, register overflow will occur, causing a decrease in the execution efficiency of the matrix multiplication kernel function. Conversely, delaying the creation / construction of the AsyncGmmaAccumDesc object until "during the calculation of the last intermediate result" allows the compiler to reuse registers that have completed their calculations. This "create-on-demand, build-as-you-go" strategy does not introduce additional resource overhead, avoiding both invalid and continuous register occupancy and reducing register pressure. Therefore, this embodiment of the invention limits the creation of the AsyncGmmaAccumDesc object (i.e., the ready state indicator) to "during the calculation of the last intermediate result." Furthermore, the above-mentioned "create-on-demand, build-as-you-go" strategy also applies to the first implementation method.
[0041] See Figure 4 This is a schematic diagram of an embodiment of the data processing device for matrix multiplication kernel functions provided by the present invention.
[0042] A second aspect of the present invention provides a data processing apparatus for a matrix multiplication kernel function, the matrix multiplication kernel function including a main loop stage and a tail stage; the apparatus includes: The status flag configuration module 11 is used to configure a corresponding ready status flag for each output block in the output result of the main loop stage; wherein, each ready status flag is updated by the sub-workgroup that executes the related calculation task of the corresponding output block. The post-processing operation triggering module 12 is used to perform the post-processing operation of the tail stage on the nth output block after the nth ready state flag indicates that the main loop calculation task of the nth output block has been completed, so as to achieve the overlap of the execution time of the main loop stage and the tail stage; where 1≤n≤N; N is the total number of output blocks.
[0043] It should be noted that the data processing apparatus for matrix multiplication kernel functions provided in the second aspect embodiment of the present invention can implement all the processes of the data processing method for matrix multiplication kernel functions described in any of the first aspect embodiments. The functions and technical effects of each module and unit in the apparatus are the same as those of the data processing method for matrix multiplication kernel functions described in any of the first aspect embodiments, and will not be repeated here.
[0044] A third aspect of the present invention provides a computer-readable storage medium comprising a stored computer program; wherein, when the computer program is executed, it controls the device on which the computer-readable storage medium is located to perform the data processing method for matrix multiplication kernel functions described in any of the first aspects of the present invention.
[0045] A fourth aspect of the present invention provides a computer program product, including computer instructions, which, when executed by a processor, implement the data processing method for matrix multiplication kernel functions described in any of the first aspects above.
[0046] See Figure 5 This is a schematic diagram of an embodiment of the electronic device provided by the present invention.
[0047] A fifth aspect of the present invention provides an electronic device including a processor 21, a memory 22, and a computer program stored in the memory 22 and configured to be executed by the processor 21, wherein the processor 21, when executing the computer program, implements the data processing method for matrix multiplication kernel functions described in any of the first aspects above.
[0048] Preferably, the computer program can be divided into one or more modules / units (such as computer program one, computer program two, ...), and the one or more modules / units are stored in the memory 22 and executed by the processor 21 to complete the present invention. The one or more modules / units can be a series of computer program instruction segments capable of performing specific functions, and the instruction segments are used to describe the execution process of the computer program in the electronic device.
[0049] The processor 21 can be any one of a CPU (Central Processing Unit), GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose Computing on Graphics Processing Unit). The processor 21 is the control center of the electronic device, connecting various parts of the electronic device via various interfaces and lines.
[0050] The memory 22 mainly includes a program storage area and a data storage area. The program storage area can store the operating system, applications required for at least one function, etc., and the data storage area can store related data, etc. In addition, the memory 22 can be a high-speed random access memory, or a non-volatile memory, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, and a flash card, etc., or the memory 22 can also be other volatile solid-state storage devices.
[0051] It should be noted that the aforementioned electronic devices may include, but are not limited to, processors and memory, as will be understood by those skilled in the art. Figure 5 The structural block diagram shown is merely a structural example of the above-described electronic device and does not constitute a limitation on the structure of the above-described electronic device. The above-described electronic device may include more or fewer components than shown, or combine certain components, or different components.
[0052] See Figure 6 This is a schematic diagram of an embodiment of the artificial intelligence processor provided by the present invention.
[0053] A sixth aspect of the present invention provides an artificial intelligence processor for executing the data processing method for a matrix multiplication kernel function as described in any of the first aspects. The artificial intelligence processor includes multiple computing units (CUs) and global memory; the CUs are the core components for executing the matrix multiplication kernel function, including: a control and scheduling unit, a thread block composed of multiple sub-workgroups, a tensor core, a general-purpose core, an accumulation register group, a ready status flag register group, and group shared memory (GSM); wherein the accumulation register group is used to cache the output blocks calculated during the main loop phase.
[0054] Specifically, the Tensor Core handles the main loop phase, while the General Core handles the tail phase. Each sub-working group calls the Tensor Core to compute different output blocks in parallel. After completing the main loop computation task for each output block, the corresponding ready status flag in the ready status flag register group is updated. The control and scheduling unit monitors the ready status flags in real time. Once the nth output block is ready, it immediately calls the General Core through the nth sub-working group to execute the corresponding tail processing, thus achieving time overlap between the main loop phase and the tail phase. Furthermore, the GSM is used to cache the final computation result of the matrix multiplication kernel function; this result is further offloaded to the GLM. The GLM is also used to store the operation data required for the matrix multiplication kernel function computation (such as the left and right matrices).
[0055] Clearly, both the tensor core and the general-purpose core are hardware units inside a computer, and specifically, computational circuits within an artificial intelligence processor. This embodiment of the invention, by calling the general-purpose core to execute the post-processing task of the nth output block while the tensor core is executing the main loop computation task of the (n+1)th output block, eliminates idle hardware "bubbles," directly improving hardware computational efficiency and significantly shortening the computation time of the matrix multiplication kernel function.
[0056] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A data processing method for matrix multiplication kernel functions, characterized in that, The matrix multiplication kernel function includes a main loop phase and a tail phase; the method includes: For each output block in the main loop phase output results, a corresponding ready status flag is configured; wherein, each ready status flag is updated by the sub-workgroup that executes the related calculation tasks of the corresponding output block. After the nth ready state flag indicates that the main loop computation task of the nth output block has been completed, the post-processing operation of the tailing stage is performed on the nth output block to achieve the overlap of the execution time of the main loop stage and the tailing stage; where 1≤n≤N; N is the total number of output blocks.
2. The data processing method for matrix multiplication kernel functions as described in claim 1, characterized in that, The ready status flag is updated through the following steps: In the main loop phase, when the nth output block is completed, the corresponding sub-workgroup sends an asynchronous signal. Based on the asynchronous signal, the nth ready state flag is updated to a state value representing the completion of the main loop computation task corresponding to the nth output block.
3. The data processing method for matrix multiplication kernel functions as described in claim 1, characterized in that, The output of the main loop phase is calculated through the following steps: The left matrix is divided into M1 row sub-blocks, and the right matrix is divided into M2 column sub-blocks; where... ; ; Perform matrix multiplication on each pair of row sub-blocks and column sub-blocks to obtain the output block at the corresponding position in the output result; All output blocks are combined according to their positions to obtain the output result.
4. The data processing method for matrix multiplication kernel functions as described in claim 1, characterized in that, The output of the main loop phase is calculated through the following steps: The left matrix is divided into M3 column sub-blocks, and the right matrix is divided into M3 row sub-blocks; where... ; Perform multiplication and summation on each pair of row and column sub-blocks to obtain the corresponding intermediate results; The last intermediate result is taken as the output result.
5. The data processing method for matrix multiplication kernel functions as described in claim 4, characterized in that, During the main loop phase, the multiply-accumulate calculation corresponding to the last intermediate result is split into N calculation subtasks, and each calculation subtask is assigned to the corresponding sub-workgroup for execution to complete the calculation of the corresponding output block.
6. The data processing method for matrix multiplication kernel functions as described in claim 4, characterized in that, The ready status identifier is created during the calculation of the last intermediate result.
7. A data processing apparatus for matrix multiplication kernel functions, characterized in that, The matrix multiplication kernel function includes a main loop phase and a tail phase; the device includes: The status flag configuration module is used to configure a corresponding ready status flag for each output block in the main loop stage output result; wherein, each ready status flag is updated by the sub-workgroup that executes the related calculation task of the corresponding output block. The post-processing operation triggering module is used to perform the post-processing operation of the tail stage on the nth output block after the nth ready state flag indicates that the nth output main loop calculation task has been completed, so as to achieve the execution time overlap of the main loop stage and the tail stage; where 1≤n≤N; N is the total number of output blocks.
8. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored computer program; wherein, when the computer program is executed, it controls the device on which the computer-readable storage medium is located to perform a data processing method for a matrix multiplication kernel function as described in any one of claims 1 to 6.
9. A computer program product, characterized in that, It includes computer instructions that, when executed by a processor, implement the data processing method for a matrix multiplication kernel function as described in any one of claims 1 to 6.
10. An electronic device, characterized in that, It includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor, when executing the computer program, implements the data processing method for a matrix multiplication kernel function as described in any one of claims 1 to 6.