Gate driver and electronic device

Abstract

The invention discloses a gate driver and an electronic device. The gate driver includes a plurality of stages. At least one stage of the plurality of stages includes a logic circuit configured to generate an intermediate carry signal and a carry output signal by sampling a carry input signal based on a clock signal, and generate an intermediate gate signal by performing a logical operation on an output enable signal, the intermediate carry signal, and the carry output signal; a level shift circuit configured to generate a gate signal by level-shifting a voltage of the intermediate gate signal; and a buffer circuit configured to output the gate signal at a gate output node when a high impedance signal has a first level, and to float the gate output node when the high impedance signal has a second level.

Description

Technical Field

[0001] Embodiments of the present invention relate to gate drivers and electronic devices including gate drivers. Background Technology

[0002] A display device, such as an organic light-emitting diode (“OLED”) display device, may include a display panel comprising a plurality of pixels, a data driver that provides data signals to the plurality of pixels, a gate driver (e.g., a scan driver and / or an emitter driver) that provides gate signals to the plurality of pixels via a plurality of gate lines, and a controller that controls the data driver and the gate driver.

[0003] Depending on the load of the display panel, image quality, etc., the gate driver can be arranged only on one side of the display panel to provide a gate signal from one end of each gate line, or two gate drivers can be arranged on opposite sides of the display panel (e.g., left and right sides) to provide the same gate signal from opposite ends of each gate line. Summary of the Invention

[0004] Some embodiments provide a gate driver that is selectively activated in response to a high impedance signal.

[0005] Some embodiments provide a display device that selectively activates gate drivers arranged on opposite sides (e.g., left and right sides) of a display panel.

[0006] According to an embodiment, a gate driver comprising multiple stages is provided. At least one of the multiple stages includes: logic circuitry configured to generate an intermediate carry signal and a carry output signal by sampling a carry input signal based on a clock signal, and to generate an intermediate gate signal by performing logic operations on an output enable signal, the intermediate carry signal, and the carry output signal; a level shifting circuitry configured to generate a gate signal by shifting the voltage level of the intermediate gate signal; and a buffer circuitry configured to output the gate signal at a gate output node when the high impedance signal has a first level, and to float the gate output node when the high impedance signal has a second level.

[0007] In one embodiment, while the high-impedance signal has a second level, the logic circuit can perform a masking operation that converts the clock signal to a low supply voltage.

[0008] In an embodiment, the buffer circuit may include: a first P-type metal-oxide-semiconductor (PMOS) transistor configured to output a high gate voltage as a gate signal at a gate output node in response to a voltage at a first control node; a first N-type metal-oxide-semiconductor (NMOS) transistor configured to output a low gate voltage as a gate signal at a gate output node in response to a voltage at a second control node; a second PMOS transistor configured to transmit a high gate voltage to the first control node in response to an inverted high impedance signal; and a second NMOS transistor configured to transmit a low gate voltage to the second control node in response to a high impedance signal.

[0009] In an embodiment, the first PMOS transistor may include a gate connected to a first control node, a first terminal receiving a high gate voltage, and a second terminal connected to a gate output node; the first NMOS transistor may include a gate connected to a second control node, a first terminal receiving a low gate voltage, and a second terminal connected to a gate output node; the second PMOS transistor may include a gate receiving an inverted high impedance signal, a first terminal receiving a high gate voltage, and a second terminal connected to the first control node; and the second NMOS transistor may include a gate receiving a high impedance signal, a first terminal receiving a low gate voltage, and a second terminal connected to the second control node.

[0010] In an embodiment, the buffer circuit may further include: a first inverter configured to generate an inverted gate signal by inverting a gate signal; a first transmission gate configured to transmit the inverted gate signal to a first control node in response to a high impedance signal and an inverted high impedance signal; and a second transmission gate configured to transmit the inverted gate signal to a second control node in response to a high impedance signal and an inverted high impedance signal.

[0011] In an embodiment, the logic circuit may include: a first AND gate configured to perform an AND operation on a clock signal and an inverted high-impedance signal; a first flip-flop configured to output an intermediate carry signal by sampling a carry input signal at the rising edge of the output signal of the first AND gate; a second inverter configured to invert the output signal of the first AND gate; a second flip-flop configured to output a carry output signal by sampling an intermediate carry signal at the rising edge of the output signal of the second inverter; a second AND gate configured to perform an AND operation on an output enable signal and an intermediate carry signal; and a NAND gate configured to generate an intermediate gate signal by performing a NAND operation on the output signal of the second AND gate and the carry output signal.

[0012] In an embodiment, the level shifting circuit may include: a first level shifter configured to convert a high power supply voltage of the intermediate gate signal to a high gate voltage when the intermediate gate signal has a high power supply voltage; and a second level shifter configured to convert a low power supply voltage of the intermediate gate signal to a low gate voltage when the intermediate gate signal has a low power supply voltage, and output a gate signal having a high gate voltage or a low gate voltage.

[0013] In an embodiment, the level shifting circuit may further include: a third inverter configured to generate an inverted intermediate gate signal by inverting the intermediate gate signal. The first level shifter may include: a third NMOS transistor configured to transmit a low supply voltage to a first node in response to the intermediate gate signal; a fourth NMOS transistor configured to transmit a low supply voltage to a second node in response to the inverted intermediate gate signal; a third PMOS transistor configured to transmit a high gate voltage to the first node in response to the voltage of the second node; a fourth PMOS transistor configured to transmit a high gate voltage to the second node in response to the voltage of the first node; a fourth inverter configured to invert the voltage of the first node; and a fifth inverter configured to invert the voltage of the second node. The second level shifter may include: a fifth PMOS transistor configured to transmit a high gate voltage to the third node in response to the output signal of the fourth inverter; a sixth PMOS transistor configured to transmit a high gate voltage to the fourth node in response to the output signal of the fifth inverter; a fifth NMOS transistor configured to transmit a low gate voltage to the third node in response to the voltage of the fourth node; a sixth NMOS transistor configured to transmit a low gate voltage to the fourth node in response to the voltage of the third node; a sixth inverter configured to generate a gate signal having a high gate voltage or a low gate voltage by inverting the voltage of the third node; and a seventh inverter configured to invert the voltage of the fourth node.

[0014] In an embodiment, the third NMOS transistor may include a gate for receiving an intermediate gate signal, a first terminal for receiving a low power supply voltage, and a second terminal connected to a first node; the fourth NMOS transistor may include a gate for receiving an inverted intermediate gate signal, a first terminal for receiving a low power supply voltage, and a second terminal connected to a second node; the third PMOS transistor may include a gate connected to a second node, a first terminal for receiving a high gate voltage, and a second terminal connected to a first node; the fourth PMOS transistor may include a gate connected to a first node, a first terminal for receiving a high gate voltage, and a second terminal connected to a second node; the fifth PMOS transistor may include a gate connected to the output terminal of a fourth inverter, a first terminal for receiving a high gate voltage, and a second terminal connected to a third node; the sixth PMOS transistor may include a gate connected to the output terminal of a fifth inverter, a first terminal for receiving a high gate voltage, and a second terminal connected to a fourth node; the fifth NMOS transistor may include a gate connected to a fourth node, a first terminal for receiving a low gate voltage, and a second terminal connected to a third node; and the sixth NMOS transistor may include a gate connected to a third node, a first terminal for receiving a low gate voltage, and a second terminal connected to a fourth node.

[0015] In an embodiment, the buffer circuit may include: a plurality of inverters connected in series and configured to buffer gate signals; and a transmission gate configured to transmit the gate signals output from the plurality of inverters to a gate output node in response to a high-impedance signal and an inverted high-impedance signal.

[0016] In an embodiment, the transmission gate can output a gate signal from multiple inverters at the gate output node when the high impedance signal has a first level and the inverted high impedance signal has a second level, and can not output a gate signal when the high impedance signal has a second level and the inverted high impedance signal has a first level.

[0017] According to an embodiment, an electronic device is provided, comprising: a processor configured to provide input image data; and a display device configured to receive the input image data from the processor and display an image based on the input image data. The display device includes: a display panel including a plurality of gate lines and a plurality of pixels connected to the plurality of gate lines; a data driver configured to provide data signals to the plurality of pixels; a first gate driver disposed on a first side of the plurality of pixels and configured to provide a plurality of gate signals to the plurality of pixels through the plurality of gate lines; a second gate driver disposed on a second side of the plurality of pixels opposite to the first side and configured to provide a plurality of gate signals to the plurality of pixels through the plurality of gate lines; and a controller configured to provide a start signal, a clock signal, an output enable signal, and a first high-impedance signal to the first gate driver, and to provide the start signal, clock signal, output enable signal, and a second high-impedance signal to the second gate driver. The first gate driver includes a plurality of first stages, and the second gate driver includes a plurality of second stages. At least one of the plurality of first stages and plurality of second stages includes: a logic circuit configured to generate an intermediate carry signal and a carry output signal by sampling a carry input signal based on a clock signal, and to generate an intermediate gate signal by performing a logic operation on an output enable signal, the intermediate carry signal, and the carry output signal; a level shifting circuit configured to generate a gate signal corresponding to one of the plurality of gate signals by shifting the voltage level of the intermediate gate signal; and a buffer circuit configured to output a gate signal at a gate output node when the high impedance signal corresponding to one of a first high impedance signal and a second high impedance signal has a first level, and to float the gate output node when the high impedance signal has a second level.

[0018] In an embodiment, when both the first high-impedance signal and the second high-impedance signal have a first level, the first gate driver and the second gate driver can provide gate signals to the multiple pixels from both the first and second sides of the multiple pixels through multiple gate lines. When the first high-impedance signal has a first level and the second high-impedance signal has a second level, the first gate driver can provide gate signals to the multiple pixels from the first side of the multiple pixels through multiple gate lines, and the multiple second-stage gate output nodes of the second gate driver can be floated. When the first high-impedance signal has a second level and the second high-impedance signal has a first level, the second gate driver can provide gate signals to the multiple pixels from the second side of the multiple pixels through multiple gate lines, and the multiple first-stage gate output nodes of the first gate driver can be floated.

[0019] In one embodiment, when the first high-impedance signal has a first level and the second high-impedance signal has a second level, the plurality of second stages of the second gate driver can perform a masking operation, which converts the clock signal applied to the plurality of second stages into a low supply voltage. When the first high-impedance signal has a second level and the second high-impedance signal has a first level, the plurality of first stages of the first gate driver can perform a masking operation, which converts the clock signal applied to the plurality of first stages into a low supply voltage.

[0020] In an embodiment, the buffer circuit may include: a first P-type metal-oxide-semiconductor (PMOS) transistor configured to output a high gate voltage as a gate signal at a gate output node in response to a voltage at a first control node; a first N-type metal-oxide-semiconductor (NMOS) transistor configured to output a low gate voltage as a gate signal at a gate output node in response to a voltage at a second control node; a second PMOS transistor configured to transmit a high gate voltage to the first control node in response to an inverted high impedance signal; and a second NMOS transistor configured to transmit a low gate voltage to the second control node in response to a high impedance signal.

[0021] In an embodiment, the buffer circuit may further include: a first inverter configured to generate an inverted gate signal by inverting a gate signal; a first transmission gate configured to transmit the inverted gate signal to a first control node in response to a high impedance signal and an inverted high impedance signal; and a second transmission gate configured to transmit the inverted gate signal to a second control node in response to a high impedance signal and an inverted high impedance signal.

[0022] In an embodiment, the buffer circuit may include: a plurality of inverters connected in series and configured to buffer gate signals; and a transmission gate configured to transmit the gate signals output from the plurality of inverters to a gate output node in response to a high-impedance signal and an inverted high-impedance signal.

[0023] According to an embodiment, an electronic device is provided, comprising: a processor configured to provide input image data; and a display device configured to receive the input image data from the processor and display an image based on the input image data.The display device includes: a display panel, including multiple write lines, multiple compensation lines, multiple first initialization lines, multiple second initialization lines, multiple anode initialization lines, multiple emission lines, and multiple pixels; a data driver configured to provide data signals to the multiple pixels; a left write driver and a right write driver respectively arranged on the left and right sides of the multiple pixels, and the left write driver and the right write driver configured to provide write signals to the multiple pixels through the multiple write lines; a left compensation driver and a right compensation driver respectively arranged on the left and right sides of the multiple pixels, and the left compensation driver and the right compensation driver configured to provide compensation signals to the multiple pixels through multiple compensation lines; and a left first initialization driver. A left and right first initialization driver are respectively arranged on the left and right sides of multiple pixels, and the left and right first initialization drivers are configured to provide a first initialization signal to the multiple pixels through multiple first initialization lines; a left and right second initialization driver are respectively arranged on the left and right sides of multiple pixels, and the left and right second initialization drivers are configured to provide a second initialization signal to the multiple pixels through multiple second initialization lines; a left and right anode initialization driver are respectively arranged on the left and right sides of multiple pixels, and the left and right anode initialization drivers are configured to provide a second initialization signal to the multiple pixels through multiple anode initialization lines. The system provides an anode initialization signal to multiple pixels via multiple transmit lines; a left transmit driver and a right transmit driver are respectively arranged on the left and right sides of the multiple pixels, and the left and right transmit drivers are configured to provide transmit signals to the multiple pixels via multiple transmit lines; and a controller is configured to provide the same clock signal to the left write driver and right write driver, the left compensation driver and right compensation driver, the left first initialization driver and right first initialization driver, the left second initialization driver and right second initialization driver, the left anode initialization driver and right anode initialization driver, and the left transmit driver and right transmit driver, and to provide a left write high impedance signal and a right write high impedance signal to the left write driver and right transmit driver respectively. The input driver and the right write driver provide the left compensation high impedance signal and the right compensation high impedance signal to the left compensation driver and the right compensation driver, respectively. The left first initialization high impedance signal and the right first initialization high impedance signal are provided to the left first initialization driver and the right first initialization driver, respectively. The left second initialization high impedance signal and the right second initialization high impedance signal are provided to the left second initialization driver and the right second initialization driver, respectively. The left anode initialization high impedance signal and the right anode initialization high impedance signal are provided to the left anode initialization driver and the right anode initialization driver, respectively. The left transmit high impedance signal and the right transmit high impedance signal are provided to the left transmit driver and the right transmit driver, respectively.Each of the left write driver and right write driver, left compensation driver and right compensation driver, left first initialization driver and right first initialization driver, left second initialization driver and right second initialization driver, left anode initialization driver and right anode initialization driver, and left transmit driver and right transmit driver comprises multiple stages. At least one of the multiple stages includes: a logic circuit configured to generate an intermediate carry signal and a carry output signal by sampling a carry input signal based on a clock signal, and to generate an intermediate gate signal by performing a logic operation on an output enable signal, the intermediate carry signal, and the carry output signal; a level shifting circuit configured to generate a gate signal corresponding to one of a write signal, a compensation signal, a first initialization signal, a second initialization signal, an anode initialization signal, and a transmit signal by shifting the voltage level of the intermediate gate signal; and a buffer circuit configured to output a gate signal at a gate output node when a high impedance signal corresponding to one of a left write high impedance signal and a right write high impedance signal, a left compensation high impedance signal and a right compensation high impedance signal, a left first initialization high impedance signal and a right first initialization high impedance signal, a left second initialization high impedance signal and a right second initialization high impedance signal, a left anode initialization high impedance signal and a right anode initialization high impedance signal, and a left transmit high impedance signal and a right transmit high impedance signal has a first level, and to float the gate output node when the high impedance signal has a second level.

[0024] In this embodiment, the left write driver and the right write driver can be selectively activated in response to the left write high impedance signal and the right write high impedance signal, respectively; the left compensation driver and the right compensation driver can be selectively activated in response to the left compensation high impedance signal and the right compensation high impedance signal, respectively; the left first initialization driver and the right first initialization driver can be selectively activated in response to the left first initialization high impedance signal and the right first initialization high impedance signal, respectively; the left second initialization driver and the right second initialization driver can be selectively activated in response to the left second initialization high impedance signal and the right second initialization high impedance signal, respectively; the left anode initialization driver and the right anode initialization driver can be selectively activated in response to the left anode initialization high impedance signal and the right anode initialization high impedance signal, respectively; and the left transmit driver and the right transmit driver can be selectively activated in response to the left transmit high impedance signal and the right transmit high impedance signal, respectively.

[0025] In an embodiment, each of the plurality of pixels may include: a capacitor including a first electrode and a second electrode; a first pixel transistor configured to generate a drive current based on the voltage of the second electrode of the capacitor; a second pixel transistor configured to transmit a corresponding data signal of a data signal to the first electrode of the capacitor in response to a corresponding write signal in a write signal; a third pixel transistor configured to diode-connect the first pixel transistor in response to a corresponding compensation signal in a compensation signal; a fourth pixel transistor configured to provide a drive current to a light-emitting element in response to a corresponding emission signal in an emission signal; a fifth pixel transistor configured to provide an initialization voltage to the anode of the light-emitting element in response to a corresponding anode initialization signal in an anode initialization signal; a sixth pixel transistor configured to provide a precharge voltage to the first electrode of the capacitor in response to a corresponding first initialization signal in a first initialization signal; a seventh pixel transistor configured to provide a precharge voltage to the second electrode of the capacitor in response to a corresponding second initialization signal in a second initialization signal; and a light-emitting element configured to emit light based on the drive current generated by the first pixel transistor.

[0026] As described above, in the gate driver according to the embodiment, the buffer circuit of the stage can output a gate signal at the gate output node of the stage when the high impedance signal has a first level, and can float the gate output node when the high impedance signal has a second level. Therefore, the gate driver according to the embodiment can be selectively activated in response to a high impedance signal.

[0027] Furthermore, the display device according to the embodiment may include a first gate driver and a second gate driver arranged on opposite sides (e.g., left and right sides) of the display panel, and the first gate driver and the second gate driver may be selectively activated in response to a first high-impedance signal and a second high-impedance signal, respectively. Therefore, even without redesigning the display device, the display device according to the embodiment may selectively perform a dual-sided driving operation that provides gate signals from opposite sides of the display panel or a single-sided driving operation that provides gate signals from one side of the display panel. Attached Figure Description

[0028] The illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 This is a block diagram illustrating a gate driver according to an embodiment.

[0030] Figure 2 It is used to describe Figure 1 A timing diagram illustrating an example of the operation of a gate driver when a high-impedance signal has a first level.

[0031] Figure 3 It is used to describe Figure 1 A timing diagram illustrating an example of the operation of a gate driver when a high-impedance signal has a second level.

[0032] Figure 4 This is a circuit diagram illustrating a stage of a gate driver according to an embodiment.

[0033] Figure 5 It is shown that it includes Figure 4 A circuit diagram of an example of the first level shifter in the stage.

[0034] Figure 6 It is shown that it includes Figure 4 A circuit diagram of an example of the second-level shifter in the stage.

[0035] Figure 7 It is used to describe Figure 4 A timing diagram illustrating an example of the operation of the stage when a high-impedance signal has a first level.

[0036] Figure 8 It is used to describe Figure 4 A timing diagram illustrating an example of the operation of the stage when the high-impedance signal has a second level.

[0037] Figure 9 This is a circuit diagram illustrating a stage of a gate driver according to an embodiment.

[0038] Figure 10 This is a block diagram illustrating a display device according to an embodiment.

[0039] Figure 11 This is a circuit diagram illustrating an example of pixels included in a display device according to an embodiment.

[0040] Figure 12 This is a block diagram illustrating an electronic device including a display device according to an embodiment. Detailed Implementation

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the terms “a,” “an,” “the,” and “at least one” as used herein do not indicate a limitation on quantity and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, “an element” has the same meaning as “at least one element.” “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” or “having” and / or “possessing” indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0042] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or segments, these elements, components, areas, layers, and / or segments should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or segment from another element, component, area, layer, or segment. Therefore, without departing from the teachings herein, “first element,” “first component,” “first area,” “first layer,” or “first segment” discussed below may be referred to as “second element,” “second component,” “second area,” “second layer,” or “second segment.”

[0043] Embodiments are described more fully below with reference to the accompanying drawings. The same or similar reference numerals always refer to the same or similar elements.

[0044] Figure 1 This is a block diagram illustrating a gate driver according to an embodiment. Figure 2 It is used to describe Figure 1 A timing diagram illustrating an example of the operation of a gate driver when a high-impedance signal has a first level, and Figure 3 It is used to describe Figure 1 A timing diagram illustrating an example of the operation of a gate driver when a high-impedance signal has a second level.

[0045] refer to Figures 1 to 3According to an embodiment, the gate driver 100 may include multiple stages STG1, STG2, STG3, STG4, etc. The gate driver 100 may be implemented as a shift register in which the multiple stages STG1, STG2, STG3, STG4, etc., sequentially output gate signals GS1, GS2, GS3, GS4, etc. According to an embodiment, the gate driver 100 may be a scan driver or an emitter driver included in a display device. For example, the gate driver 100 may be a write driver that sequentially provides write signals to multiple pixels, a compensation driver that sequentially provides compensation signals to multiple pixels, a first initialization driver that sequentially provides first initialization signals to multiple pixels, a second initialization driver that sequentially provides second initialization signals to multiple pixels, an anode initialization driver that sequentially provides anode initialization signals to multiple pixels, or an emitter driver that sequentially provides emitter signals to multiple pixels.

[0046] Multiple stages, such as STG1, STG2, STG3, and STG4, can sequentially output carry output signals CR1, CR2, CR3, CR4, and gate signals GS1, GS2, GS3, GS4, etc., based on a start signal STV, a clock signal CLK, an output enable signal OE, and a high-impedance signal HIZ (and / or an inverted high-impedance signal HIZB). Furthermore, the first stage, STG1, can receive the start signal STV as a carry input signal, and each of the subsequent stages, STG2, STG3, and STG4, can receive the carry output signal of the previous stage as a carry input signal. The gate driver 100 can be selectively activated or enabled in response to the high-impedance signal HIZ and / or the inverted high-impedance signal HIZB. In some embodiments, when the high-impedance signal HIZ has a first level (e.g., low level L), multiple stages STG1, STG2, STG3, STG4, etc., can sequentially output carry output signals CR1, CR2, CR3, CR4, etc., and gate signals GS1, GS2, GS3, GS4, etc. When the high-impedance signal HIZ has a second level (e.g., high level H), multiple stages STG1, STG2, STG3, STG4, etc., can not output carry output signals CR1, CR2, CR3, CR4, etc., and gate signals GS1, GS2, GS3, GS4, etc., and the gate output nodes NGO1, NGO2, NGO3, NGO4, etc., of multiple stages STG1, STG2, STG3, STG4, etc. can be floated.

[0047] For example, such as Figure 2As shown, when the high-impedance signal HIZ has a low level L, the first stage STG1 can output a first carry output signal CR1 by shifting the start signal STV or delaying the period of the clock signal CLK. In some embodiments, the period of the clock signal CLK can correspond to, but is not limited to, a horizontal time 1H. Here, a horizontal time 1H can be the time allocated to one pixel row of the display panel, and can correspond to the time obtained by dividing the frame time by the number of pixel rows of the display panel. Furthermore, the first stage STG1 can perform a logic operation (e.g., a NAND operation) on the first carry output signal CR1 and the output enable signal OE to generate a first gate signal GS1, and output the first gate signal GS1 at the first gate output node NGO1. The second stage STG2 can output a second carry output signal CR2 by shifting the first carry output signal CR1 or delaying the period of the clock signal CLK, and can output the second gate signal GS2 at the second gate output node NGO2 based on the second carry output signal CR2 and the output enable signal OE. The third-stage STG3 can output the third-carry output signal CR3 by shifting or delaying the second-carry output signal CR2 by the period of the clock signal CLK, and can output the third-gate signal GS3 at the third-gate output node NGO3 based on the third-carry output signal CR3 and the output enable signal OE. The fourth-stage STG4 can output the fourth-carry output signal CR4 by shifting or delaying the third-carry output signal CR3 by the period of the clock signal CLK, and can output the fourth-gate signal GS4 at the fourth-gate output node NGO4 based on the fourth-carry output signal CR4 and the output enable signal OE. In this way, multiple stages STG1, STG2, STG3, STG4, etc., can sequentially output carry output signals CR1, CR2, CR3, CR4, etc., and gate signals GS1, GS2, GS3, GS4, etc.

[0048] In another example, such as Figure 3 As shown, when the high-impedance signal HIZ has a high level H, even if the start signal STV, clock signal CLK, and output enable signal OE are applied to multiple stages STG1, STG2, STG3, STG4, etc., these stages may not output carry output signals CR1, CR2, CR3, CR4, etc., or gate signals GS1, GS2, GS3, GS4, etc. Furthermore, the multiple stages STG1, STG2, STG3, STG4, etc., can float the gate output nodes NGO1, NGO2, NGO3, NGO4, etc., so that the load on the gate lines connected to the gate output nodes NGO1, NGO2, NGO3, NGO4, etc., does not increase. In some embodiments, even at high supply voltage VDD (see... Figure 4) and low supply voltage VSS (see Figure 4 A clock signal CLK and / or an output enable signal OE, which periodically switch between multiple stages STG1, STG2, STG3, STG4, etc., can also perform a masking operation to convert or fix the clock signal CLK and / or the output enable signal OE applied to the multiple stages STG1, STG2, STG3, STG4, etc., to a low supply voltage VSS. Therefore, the internal circuitry (e.g., logic circuitry) of the multiple stages STG1, STG2, STG3, STG4, etc., can operate without responding to the clock signal CLK that has been converted or fixed to a low supply voltage VSS, and the power consumption of the gate driver 100 can be reduced.

[0049] As described above, the gate driver 100 according to the embodiment can be selectively activated or enabled in response to a high impedance signal HIZ. Therefore, as referred to below... Figure 10 Even without redesigning the display device including gate drivers 100 arranged on opposite sides (e.g., left and right) of the display panel, the display device can selectively perform dual-sided driving operation or single-sided driving operation by selectively activating each of the plurality of gate drivers 100.

[0050] Figure 4 This is a circuit diagram illustrating the stage of the gate driver according to an embodiment. Figure 5 It is shown that it includes Figure 4 A circuit diagram of an example of the first level shifter in the stage, and Figure 6 It is shown that it includes Figure 4 A circuit diagram of an example of the second-level shifter in the stage.

[0051] refer to Figures 4 to 6 According to the embodiment, the stage 200 of the gate driver may include logic circuitry 220, level shifting circuitry 240, and buffer circuitry 260.

[0052] Logic circuit 220 can generate an intermediate carry signal CR_INT and a carry output signal CR_OUT by sampling the carry input signal CR_IN based on the clock signal CLK. In some embodiments, when stage 200 is the first stage of the gate driver, the carry input signal CR_IN can be... Figure 1The start signal STV is shown, and if stage 200 is one of the subsequent stages of the gate driver, the carry input signal CR_IN can be the carry output signal of the previous stage. Furthermore, logic circuit 220 can generate the intermediate gate signal GS_INT by performing logical operations on the output enable signal OE, the intermediate carry signal CR_INT, and the carry output signal CR_OUT. To perform these operations, in some embodiments, logic circuit 220 may include a first AND gate AND1, a first flip-flop FF1, a second inverter INV2, a second flip-flop FF2, a second AND gate AND2, and a NAND gate NAND.

[0053] The first AND gate AND1 can receive a clock signal CLK that switches periodically between a high supply voltage VDD and a low supply voltage VSS, and can have a second level (e.g., a high level H) on a high impedance signal HIZ. Figure 3 At the same time, or when the inverted high-impedance signal HIZB has a first level (e.g., low level L (see...)). Figure 2 Simultaneously, a masking operation is performed to convert the clock signal CLK to a low supply voltage VSS. Therefore, when the gate driver is deactivated in response to a high-impedance signal HIZB with a second level (e.g., high level H), the clock signal CLK can be masked or pinned to a low supply voltage VSS, thereby reducing the power consumption of the logic circuit 220 in each stage 200 and reducing the power consumption of the gate driver. In some embodiments, the first AND gate AND1 may include a first input terminal receiving the clock signal CLK, a second input terminal receiving the inverted high-impedance signal HIZB, and an output terminal. Furthermore, the first AND gate AND1 can perform an AND operation on the clock signal CLK and the inverted high-impedance signal HIZB. Therefore, the first AND gate AND1 can output a periodically switching clock signal CLK at the output terminal when the inverted high-impedance signal HIZB has a high level H, and can output a clock signal CLK masked or pinned to a low supply voltage VSS at the output terminal when the inverted high-impedance signal HIZB has a low level L.

[0054] The first flip-flop FF1 can output an intermediate carry signal CR_INT in response to the output signal of the first AND gate AND1 by sampling the carry input signal CR_IN. In some embodiments, the first flip-flop FF1 may include a data input terminal D for receiving the carry input signal CR_IN, a data output terminal Q for outputting the intermediate carry signal CR_INT, and a clock terminal for receiving the output signal of the first AND gate AND1. Furthermore, the first flip-flop FF1 can output the intermediate carry signal CR_INT by sampling the carry input signal CR_IN at the rising edge of the output signal of the first AND gate AND1. Therefore, the first flip-flop FF1 can output the intermediate carry signal CR_INT for half a cycle of the clock signal CLK delayed or shifted from the carry input signal CR_IN when the inverted high impedance signal HIZB is high (H), and can remain inactive when the inverted high impedance signal HIZB is low (L).

[0055] The second inverter INV2 inverts the output signal of the first AND gate AND1, and the second flip-flop FF2 outputs a carry output signal CR_OUT in response to the output signal of the second inverter INV2 by sampling the intermediate carry signal CR_INT. In some embodiments, the second flip-flop FF2 may include a data input terminal D for receiving the intermediate carry signal CR_INT, a data output terminal Q for outputting the carry output signal CR_OUT, and a clock terminal for receiving the output signal of the second inverter INV2. Furthermore, the second flip-flop FF2 can output the carry output signal CR_OUT by sampling the intermediate carry signal CR_INT at the rising edge of the output signal of the second inverter INV2. Therefore, the second flip-flop FF2 can output the carry output signal CR_OUT for half a cycle of the clock signal CLK delayed or shifted from the intermediate carry signal CR_INT when the inverted high-impedance signal HIZB is high (H), and can remain inactive when the inverted high-impedance signal HIZB is low (L). Therefore, logic circuit 220 can output carry output signal CR_OUT by delaying or shifting the period of carry input signal CR_IN or shift clock signal CLK.

[0056] The second AND gate AND2 may include a first input terminal for receiving the output enable signal OE, a second input terminal for receiving the intermediate carry signal CR_INT, and an output terminal. Furthermore, the second AND gate AND2 can perform a bitwise AND operation on the output enable signal OE and the intermediate carry signal CR_INT. Therefore, the second AND gate AND2 can output a low-level output signal at the output terminal when either the output enable signal OE or the intermediate carry signal CR_INT is low, and can output a high-level output signal at the output terminal when both the output enable signal OE and the intermediate carry signal CR_INT are high.

[0057] The NAND gate may include a first input terminal for receiving the output signal of the second AND gate AND2, a second input terminal for receiving the carry output signal CR_OUT, and an output terminal. Furthermore, the NAND gate can generate an intermediate gate signal GS_INT by performing a NAND operation on the output signal of the second AND gate AND2 and the carry output signal CR_OUT. Therefore, the NAND gate can output a high-level intermediate gate signal GS_INT at the output terminal when either the output signal of the second AND gate AND2 or the carry output signal CR_OUT is low, and can output a low-level intermediate gate signal GS_INT at the output terminal when both the output signal of the second AND gate AND2 and the carry output signal CR_OUT are high. Therefore, the logic circuit 220 can output a low-level intermediate gate signal GS_INT when the output enable signal OE, the intermediate carry signal CR_INT, and the carry output signal CR_OUT are all high.

[0058] Level shifting circuit 240 generates gate signal GS by shifting the voltage level of intermediate gate signal GS_INT. In some embodiments, intermediate gate signal GS_INT may have a high supply voltage VDD or a low supply voltage VSS, and level shifting circuit 240 can generate gate signal GS with high gate voltage VGH or low gate voltage VGL by changing the high supply voltage VDD of intermediate gate signal GS_INT to a high gate voltage VGH and by changing the low supply voltage VSS of intermediate gate signal GS_INT to a low gate voltage VGL. For example, the voltage difference between high supply voltage VDD and low supply voltage VSS may be smaller than the voltage difference between high gate voltage VGH and low gate voltage VGL. Therefore, logic circuit 220 can operate based on high supply voltage VDD and low supply voltage VSS, and thus the power consumption of logic circuit 220 can be reduced. In some embodiments, level shifting circuit 240 may include a third inverter INV3, a first level shifter LS1, and a second level shifter LS2.

[0059] The third inverter INV3 can generate an inverted intermediate gate signal by inverting the intermediate gate signal GS_INT. When the intermediate gate signal GS_INT has a high power supply voltage VDD, the first level shifter LS1 can convert the high power supply voltage VDD of the intermediate gate signal GS_INT to a high gate voltage VGH. In some embodiments, the first level shifter LS1 may include an input terminal IN, an inverting input terminal INB, an output terminal OUT, and an inverting output terminal OUTB. The input terminal IN receives the intermediate gate signal GS_INT with a high power supply voltage VDD or a low power supply voltage VSS. The inverting input terminal INB receives the inverted intermediate gate signal with a low power supply voltage VSS or a high power supply voltage VDD. The output terminal OUT outputs the intermediate gate signal GS_INT with a high gate voltage VGH or a low power supply voltage VSS. The inverting output terminal OUTB outputs the inverted intermediate gate signal with a low power supply voltage VSS or a high gate voltage VGH.

[0060] In some embodiments, such as Figure 5 As shown, the first level shifter LS1 may include a third N-type metal-oxide-semiconductor (“NMOS”) transistor NT3, a fourth NMOS transistor NT4, a third P-type metal-oxide-semiconductor (“PMOS”) transistor PT3, a fourth PMOS transistor PT4, a fourth inverter INV4, and a fifth inverter INV5. The third NMOS transistor NT3 transmits a low supply voltage VSS to the first node N1 in response to the intermediate gate signal GS_INT. The fourth NMOS transistor NT4 transmits a low supply voltage VSS to the second node N2 in response to the inverted intermediate gate signal GS_INTB. The third PMOS transistor PT3 transmits a high gate voltage VGH to the first node N1 in response to the voltage of the second node N2. The fourth PMOS transistor PT4 transmits a high gate voltage VGH to the second node N2 in response to the voltage of the first node N1. The fourth inverter INV4 inverts the voltage of the first node N1, and the fifth inverter INV5 inverts the voltage of the second node N2. In some embodiments, the third NMOS transistor NT3 may include a gate for receiving an intermediate gate signal GS_INT, a first terminal for receiving a low power supply voltage VSS, and a second terminal connected to the first node N1; the fourth NMOS transistor NT4 may include a gate for receiving an inverted intermediate gate signal GS_INTB, a first terminal for receiving a low power supply voltage VSS, and a second terminal connected to the second node N2; the third PMOS transistor PT3 may include a gate connected to the second node N2, a first terminal for receiving a high gate voltage VGH, and a second terminal connected to the first node N1; and the fourth PMOS transistor PT4 may include a gate connected to the first node N1, a first terminal for receiving a high gate voltage VGH, and a second terminal connected to the second node N2.

[0061] When the intermediate gate signal GS_INT has a high supply voltage VDD and the inverted intermediate gate signal GS_INTB has a low supply voltage VSS, the third NMOS transistor NT3 can be turned on to apply the low supply voltage VSS to the first node N1, and the fourth PMOS transistor PT4 can be turned on to apply the high gate voltage VGH to the second node N2. Furthermore, the fourth NMOS transistor NT4 and the third PMOS transistor PT3 can be turned off. The fourth inverter INV4 can output a high gate voltage VGH at the output terminal OUT by inverting the low supply voltage VSS of the first node N1, and the fifth inverter INV5 can output a low supply voltage VSS at the inverted output terminal OUTB by inverting the high gate voltage VGH of the second node N2. When the intermediate gate signal GS_INT has a low supply voltage VSS and the inverted intermediate gate signal GS_INTB has a high supply voltage VDD, the fourth NMOS transistor NT4 can be turned on to apply the low supply voltage VSS to the second node N2, and the third PMOS transistor PT3 can be turned on to apply the high gate voltage VGH to the first node N1. Furthermore, the third NMOS transistor NT3 and the fourth PMOS transistor PT4 can be turned off. The fourth inverter INV4 can output a low supply voltage VSS at the output terminal OUT by inverting the high gate voltage VGH of the first node N1, and the fifth inverter INV5 can output a high gate voltage VGH at the inverted output terminal OUTB by inverting the low supply voltage VSS of the second node N2. Therefore, the first level shifter LS1 can output an intermediate gate signal GS_INT with either a high gate voltage VGH or a low supply voltage VSS by performing a level shift operation on the intermediate gate signal GS_INT with either a high supply voltage VDD or a low supply voltage VSS.

[0062] The second level shifter LS2 can convert the low power supply voltage VSS of the intermediate gate signal GS_INT to a low gate voltage VGL when the intermediate gate signal GS_INT has a low power supply voltage VSS, and can output a gate signal GS with a high gate voltage VGH or a low gate voltage VGL. In some embodiments, the second level shifter LS2 may include an input terminal IN, an inverting input terminal INB, an output terminal OUT, and an inverting output terminal OUTB. The input terminal IN receives the intermediate gate signal GS_INT with a high gate voltage VGH or a low power supply voltage VSS, the inverting input terminal INB receives the inverted intermediate gate signal GS_INTB with a low power supply voltage VSS or a high gate voltage VGH, and the output terminal OUT outputs the gate signal GS with a high gate voltage VGH or a low gate voltage VGL.

[0063] In some embodiments, such as Figure 6 As shown, the second level shifter LS2 may include a fifth PMOS transistor PT5, a sixth PMOS transistor PT6, a fifth NMOS transistor NT5, a sixth NMOS transistor NT6, a sixth inverter INV6, and a seventh inverter INV7. The fifth PMOS transistor PT5 transmits a high gate voltage VGH to the third node N3 in response to the output signal of the fourth inverter INV4. The sixth PMOS transistor PT6 transmits a high gate voltage VGH to the fourth node N4 in response to the output signal of the fifth inverter INV5. The fifth NMOS transistor NT5 transmits a low gate voltage VGL to the third node N3 in response to the voltage of the fourth node N4. The sixth NMOS transistor NT6 transmits a low gate voltage VGL to the fourth node N4 in response to the voltage of the third node N3. The sixth inverter INV6 inverts the voltage of the third node N3 to generate a gate signal GS with a high gate voltage VGH or a low gate voltage VGL. The seventh inverter INV7 inverts the voltage of the fourth node N4. In some embodiments, the fifth PMOS transistor PT5 may include a gate connected to the fourth inverter INV4, a first terminal receiving a high gate voltage VGH, and a second terminal connected to the third node N3; the sixth PMOS transistor PT6 may include a gate connected to the fifth inverter INV5, a first terminal receiving a high gate voltage VGH, and a second terminal connected to the fourth node N4; the fifth NMOS transistor NT5 may include a gate connected to the fourth node N4, a first terminal receiving a low gate voltage VGL, and a second terminal connected to the third node N3; and the sixth NMOS transistor NT6 may include a gate connected to the third node N3, a first terminal receiving a low gate voltage VGL, and a second terminal connected to the fourth node N4.

[0064] When the intermediate gate signal GS_INT output from the first level shifter LS1 has a high gate voltage VGH and the inverted intermediate gate signal GS_INTB output from the first level shifter LS1 has a low power supply voltage VSS, the sixth PMOS transistor PT6 can be turned on to apply the high gate voltage VGH to the fourth node N4, and the fifth NMOS transistor NT5 can be turned on to apply the low gate voltage VGL to the third node N3. Furthermore, the fifth PMOS transistor PT5 and the sixth NMOS transistor NT6 can be turned off. The sixth inverter INV6 can output a high gate voltage VGH at the output terminal OUT by inverting the low gate voltage VGL of the third node N3, and the seventh inverter INV7 can output a low gate voltage VGL at the inverted output terminal OUTB by inverting the high gate voltage VGH of the fourth node N4. When the intermediate gate signal GS_INT output from the first level shifter LS1 has a low supply voltage VSS and the inverted intermediate gate signal GS_INTB output from the first level shifter LS1 has a high gate voltage VGH, the fifth PMOS transistor PT5 can be turned on to apply the high gate voltage VGH to the third node N3, and the sixth NMOS transistor NT6 can be turned on to apply the low gate voltage VGL to the fourth node N4. Furthermore, the sixth PMOS transistor PT6 and the fifth NMOS transistor NT5 can be turned off. The sixth inverter INV6 can output the low gate voltage VGL at the output terminal OUT by inverting the high gate voltage VGH of the third node N3, and the seventh inverter INV7 can output the high gate voltage VGH at the inverted output terminal OUTB by inverting the low gate voltage VGL of the fourth node N4. Therefore, the second level shifter LS2 can output a gate signal GS with either a high gate voltage VGH or a low gate voltage VGL by performing a level shift operation on the intermediate gate signal GS_INT with either a high gate voltage VGH or a low supply voltage VSS. Therefore, the level shifting circuit 240 can output a gate signal GS with a high gate voltage VGH or a low gate voltage VGL.

[0065] The buffer circuit 260 can output a gate signal GS at the gate output node NGO when the high-impedance signal HIZ has a first level (e.g., low level L) or the inverted high-impedance signal HIZB has a second level (e.g., high level H), and can float the gate output node NGO when the high-impedance signal HIZ has a second level or the inverted high-impedance signal HIZB has a first level. To perform these operations, in some embodiments, the buffer circuit 260 may include a first inverter INV1, a first transmission gate TG1, a second transmission gate TG2, a first PMOS transistor PT1, a first NMOS transistor NT1, a second PMOS transistor PT2, and a second NMOS transistor NT2.

[0066] The first inverter INV1 generates an inverted gate signal by inverting the gate signal GS. The first transmission gate TG1 transmits the inverted gate signal to the first control node NC1 in response to the high-impedance signal HIZ and the inverted high-impedance signal HIZB, and the second transmission gate TG2 transmits the inverted gate signal to the second control node NC2 in response to the high-impedance signal HIZ and the inverted high-impedance signal HIZB. For example, when the high-impedance signal HIZ has a first level (e.g., low level L) or the inverted high-impedance signal HIZB has a second level (e.g., high level H), the first transmission gate TG1 and the second transmission gate TG2 can transmit the inverted gate signal to the first control node NC1 and the second control node NC2. However, when the high-impedance signal HIZ has a second level and the inverted high-impedance signal HIZB has a first level, the first transmission gate TG1 and the second transmission gate TG2 may not transmit the inverted gate signal to the first control node NC1 and the second control node NC2.

[0067] The first PMOS transistor PT1 can respond to the voltage of the first control node NC1 and output a high gate voltage VGH at the gate output node NGO as the gate signal GS. The first NMOS transistor NT1 can respond to the voltage of the second control node NC2 and output a low gate voltage VGL at the gate output node NGO as the gate signal GS. The second PMOS transistor PT2 can respond to the inverted high impedance signal HIZB and transmit the high gate voltage VGH to the first control node NC1. The second NMOS transistor NT2 can respond to the high impedance signal HIZ and transmit the low gate voltage VGL to the second control node NC2. In some embodiments, the first PMOS transistor PT1 may include a gate connected to the first control node NC1, a first terminal receiving a high gate voltage VGH, and a second terminal connected to the gate output node NGO; the first NMOS transistor NT1 may include a gate connected to the second control node NC2, a first terminal receiving a low gate voltage VGL, and a second terminal connected to the gate output node NGO; the second PMOS transistor PT2 may include a gate receiving an inverted high impedance signal HIZB, a first terminal receiving a high gate voltage VGH, and a second terminal connected to the first control node NC1; and the second NMOS transistor NT2 may include a gate receiving a high impedance signal HIZ, a first terminal receiving a low gate voltage VGL, and a second terminal connected to the second control node NC2.

[0068] In the first case where the high-impedance signal HIZ has a first level (e.g., low level L) and the inverted high-impedance signal HIZB has a second level (e.g., high level H), when the gate signal GS has a high gate voltage VGH, the first inverter INV1 can generate an inverted gate signal with a low gate voltage VGL. The first transmission gate TG1 and the second transmission gate TG2 can transmit the inverted gate signal with a low gate voltage VGL to the first control node NC1 and the second control node NC2, and the second PMOS transistor PT2 and the second NMOS transistor NT2 can be turned off. Therefore, the first control node NC1 and the second control node NC2 can have a low gate voltage VGL. Furthermore, the first NMOS transistor NT1 can be turned off in response to the low gate voltage VGL of the second control node NC2, the first PMOS transistor PT1 can be turned on in response to the low gate voltage VGL of the first control node NC1, and the first PMOS transistor PT1 can output a high gate voltage VGH as the gate signal GS at the gate output node NGO. Furthermore, in the first case, when the gate signal GS has a low gate voltage VGL, the first inverter INV1 can generate an inverted gate signal with a high gate voltage VGH, and the first transmission gate TG1 and the second transmission gate TG2 can transmit the inverted gate signal with a high gate voltage VGH to the first control node NC1 and the second control node NC2, and the second PMOS transistor PT2 and the second NMOS transistor NT2 can be turned off. Therefore, the first control node NC1 and the second control node NC2 can have a high gate voltage VGH. Furthermore, the first PMOS transistor PT1 can be turned off in response to the high gate voltage VGH of the first control node NC1, the first NMOS transistor NT1 can be turned on in response to the high gate voltage VGH of the second control node NC2, and the first NMOS transistor NT1 can output a low gate voltage VGL as the gate signal GS at the gate output node NGO. Therefore, in the first case where the high impedance signal HIZ has a first level (e.g., low level L) and the inverted high impedance signal HIZB has a second level (e.g., high level H), the buffer circuit 260 can output the gate signal GS at the gate output node NGO.

[0069] However, in the second case where the high-impedance signal HIZ has a second level (e.g., high level H) and the inverted high-impedance signal HIZB has a first level (e.g., low level L), the first transmission gate TG1 and the second transmission gate TG2 may not transmit the inverted gate signal output from the first inverter INV1 to the first control node NC1 and the second control node NC2. Furthermore, the second PMOS transistor PT2 may transmit a high gate voltage VGH to the first control node NC1 in response to the inverted high-impedance signal HIZB with a low level L, and the second NMOS transistor NT2 may transmit a low gate voltage VGL to the second control node NC2 in response to the high-impedance signal HIZ with a high level H. Therefore, the first control node NC1 may have a high gate voltage VGH, and the second control node NC2 may have a low gate voltage VGL. The first PMOS transistor PT1 may be turned off in response to the high gate voltage VGH of the first control node NC1, the first NMOS transistor NT1 may be turned off in response to the low gate voltage VGL of the second control node NC2, and the gate output node NGO may be floated. Therefore, in the second case where the high-impedance signal HIZ has a second level (e.g., high level H) and the inverted high-impedance signal HIZB has a first level (e.g., low level L), the buffer circuit 260 may not output the gate signal GS and may float the gate output node NGO so that the load on the gate line connected to the gate output node NGO does not increase.

[0070] As described above, in stage 200 of the gate driver according to the embodiment, buffer circuit 260 can output gate signal GS at gate output node NGO when high impedance signal HIZ has a first level, and can float gate output node NGO when high impedance signal HIZ has a second level. Therefore, the gate driver according to the embodiment can be selectively activated in response to high impedance signal HIZ. Furthermore, in stage 200 of the gate driver according to the embodiment, when high impedance signal HIZ has a second level, logic circuit 220 can perform a masking operation to convert clock signal CLK applied to stage 200 into a low supply voltage VSS. Therefore, when the gate driver is disabled, the power consumption of the gate driver can be reduced.

[0071] Figure 7 It is used to describe Figure 4 A timing diagram illustrating an example of the operation of the stage when a high-impedance signal has a first level.

[0072] refer to Figure 4 and Figure 7When the high-impedance signal HIZ has a low level L and the inverted high-impedance signal HIZB has a high level H, the first AND gate AND1 can output an output signal OUT_AND1 that switches periodically based on the periodically switching clock signal CLK and the inverted high-impedance signal HIZB with a high level H. The first flip-flop FF1 can sample the carry input signal CR_IN at the rising edge of the output signal OUT_AND1 of the first AND gate to output an intermediate carry signal CR_INT that is half a cycle of the clock signal CLK delayed or shifted from the carry input signal CR_IN. The second inverter INV2 can invert the output signal OUT_AND1 of the first AND gate, and the second flip-flop FF2 can sample the intermediate carry signal CR_INT at the rising edge of the output signal INV2 to output a carry output signal CR_OUT that is a period of the clock signal CLK delayed or shifted from the carry input signal CR_IN. Furthermore, the second AND gate AND2 and the NAND gate NAND can output an intermediate gate signal GS_INT with a high power supply voltage VDD when at least one of the output enable signal OE, the intermediate carry signal CR_INT, and the carry output signal CR_OUT is low, and can output an intermediate gate signal GS_INT with a low power supply voltage VSS when all three of the output enable signal OE, the intermediate carry signal CR_INT, and the carry output signal CR_OUT are high.

[0073] The level shifting circuit 240 can provide the gate signal GS with a high gate voltage VGH or a low gate voltage VGL to the buffer circuit 260 by performing a level shifting operation on the intermediate carry signal CR_INT with a high power supply voltage VDD or a low power supply voltage VSS.

[0074] The first transmission gate TG1 and the second transmission gate TG2 can be turned on in response to a high-impedance signal HIZ with a low level L and an inverted high-impedance signal HIZB with a high level H. The second PMOS transistor PT2 can be turned off in response to the inverted high-impedance signal HIZB with a high level H, and the second NMOS transistor NT2 can be turned off in response to the high-impedance signal HIZ with a low level L. Therefore, the buffer circuit 260 can output the gate signal GS at the gate output node NGO.

[0075] Figure 8 It is used to describe Figure 4 A timing diagram illustrating an example of the operation of the stage when the high-impedance signal has a second level.

[0076] refer to Figure 4 and Figure 8When the high-impedance signal HIZ has a high level H and the inverting high-impedance signal HIZB has a low level L, the first AND gate AND1 can output an output signal OUT_AND1 with a low power supply voltage VSS by performing a masking operation that converts the periodically switching clock signal CLK to a low power supply voltage VSS. Therefore, the first flip-flop FF1 and the second flip-flop FF2 can be inactive, and the power consumption of the logic circuit 220 can be reduced.

[0077] The first transmission gate TG1 and the second transmission gate TG2 can be turned off in response to a high-impedance signal HIZ with a high level H and an inverted high-impedance signal HIZ with a low level L. The second PMOS transistor PT2 can be turned on in response to an inverted high-impedance signal HIZB with a low level L, and the second NMOS transistor NT2 can be turned on in response to a high-impedance signal HIZ with a high level H. The second PMOS transistor PT2 can transmit a high gate voltage VGH to the first control node NC1, and the second NMOS transistor NT2 can transmit a low gate voltage VGL to the second control node NC2. The first PMOS transistor PT1 can be turned off in response to a high gate voltage VGH at the first control node NC1, and the second NMOS transistor NT2 can be turned off in response to a low gate voltage VGL at the second control node NC2. Therefore, the buffer circuit 260 can not output the gate signal GS, and can make the gate output node NGO float, so that the load on the gate line connected to the gate output node NGO does not increase.

[0078] Figure 9 This is a circuit diagram illustrating a stage of a gate driver according to an embodiment.

[0079] refer to Figure 9 The gate driver stage 300 according to the embodiment may include logic circuitry 220, level shifting circuitry 240, and buffer circuitry 360. In addition to the configuration of buffer circuitry 360, Figure 9 Level 300 can be compared with Figure 4 The Class 200 has a similar configuration and similar operation.

[0080] The buffer circuit 360 may include a plurality of inverters INV1' and INV2' connected in series to buffer the gate signal GS, and a transmission gate TG that transmits the gate signal GS output from the plurality of inverters INV1' and INV2' to the gate output node NGO in response to a high-impedance signal HIZ and an inverted high-impedance signal HIZB. The transmission gate TG may have a first level (e.g., low level L) on the high-impedance signal HIZ (see [reference]). Figure 2 And the inverted high-impedance signal HIZB has a second level (e.g., high level H (see...)). Figure 3When the gate output node NGO outputs the gate signal GS from multiple inverters INV1' and INV2', the gate signal GS can be deactivated when the high-impedance signal HIZ has a second level and the inverted high-impedance signal HIZB has a first level. Therefore, stage 300 and the gate driver can be deactivated when the high-impedance signal HIZ has a first level and the inverted high-impedance signal HIZB has a second level.

[0081] Figure 10 This is a block diagram illustrating a display device according to an embodiment, and Figure 11 This is a circuit diagram illustrating an example of pixels included in a display device according to an embodiment.

[0082] refer to Figure 10 and Figure 11 The display device 500 according to an embodiment may include a display panel 510, a data driver 520, a first gate driver 540, a second gate driver 560, and a controller 580. The display panel 510 includes a plurality of pixels PX. The data driver 520 provides a data signal DS to the plurality of pixels PX. The first gate driver 540 is disposed on a first side (e.g., the left side) of the plurality of pixels PX and provides a gate signal to the plurality of pixels PX. The second gate driver 560 is disposed on a second side (e.g., the right side) of the plurality of pixels PX opposite to the first side and provides a gate signal to the plurality of pixels PX. The controller 580 controls the data driver 520, the first gate driver 540, and the second gate driver 560. Here, the gate signal may be signals GW, GC, EM, EB, GI1, and GI2, and corresponds to... Figures 4 to 9 The gate signal GS in the middle.

[0083] The display panel 510 may include multiple gate lines and multiple pixels PX connected to the multiple gate lines. In some embodiments, the display panel 510 may include multiple write lines GWL, multiple compensation lines GCL, multiple first initialization lines GI1L, multiple second initialization lines GI2L, multiple anode initialization lines EBL, and multiple emitter lines EML as multiple gate lines. Figure 11 As shown, each pixel PX may include a capacitor CST, a first pixel transistor PXT1, a second pixel transistor PXT2, a third pixel transistor PXT3, a fourth pixel transistor PXT4, a fifth pixel transistor PXT5, a sixth pixel transistor PXT6, a seventh pixel transistor PXT7, and a light-emitting element EL.

[0084] The capacitor CST may include a first electrode connected to the second pixel transistor PXT2 and the sixth pixel transistor PXT6, and a second electrode connected to the first pixel transistor PXT1, the third pixel transistor PXT3 and the seventh pixel transistor PXT7.

[0085] The first pixel transistor PXT1 can generate a drive current based on the voltage of the second electrode of the capacitor CST. In some embodiments, the first pixel transistor PXT1 may include a gate connected to the second electrode of the capacitor CST, a first terminal receiving a first pixel power supply voltage ELVDD, and a second terminal connected to the third pixel transistor PXT3 and the fourth pixel transistor PXT4.

[0086] The second pixel transistor PXT2 can transmit a data signal DS to the first electrode of the capacitor CST in response to a write signal GW transmitted via the write line GWL. In some embodiments, the second pixel transistor PXT2 may include a gate connected to the write line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first electrode of the capacitor CST.

[0087] The third pixel transistor PXT3 can diode-connect the first pixel transistor PXT1 in response to a compensation signal GC transmitted via the compensation line GCL. In some embodiments, the third pixel transistor PXT3 may include a gate connected to the compensation line GCL, a first terminal connected to a second terminal of the first pixel transistor PXT1, and a second terminal connected to the gate of the first pixel transistor PXT1.

[0088] The fourth pixel transistor PXT4 can provide drive current to the light-emitting element EL in response to the emission signal EM transmitted through the emission line EML. In some embodiments, the fourth pixel transistor PXT4 may include a gate connected to the emission line EML, a first terminal connected to the second terminal of the first pixel transistor PXT1, and a second terminal connected to the light-emitting element EL.

[0089] The fifth pixel transistor PXT5 can provide an initialization voltage VINT to the anode of the light-emitting element EL in response to an anode initialization signal EB transmitted via the anode initialization line EBL. In some embodiments, the fifth pixel transistor PXT5 may include a gate connected to the anode initialization line EBL, a first terminal receiving the initialization voltage VINT, and a second terminal connected to the anode of the light-emitting element EL.

[0090] The sixth pixel transistor PXT6 can provide a pre-charge voltage VPRE to the first electrode of the capacitor CST in response to a first initialization signal GI1 transmitted via the first initialization line GI1L. In some embodiments, the sixth pixel transistor PXT6 may include a gate connected to the first initialization line GI1L, a first terminal receiving the pre-charge voltage VPRE, and a second terminal connected to the first electrode of the capacitor CST.

[0091] The seventh pixel transistor PXT7 can provide a pre-charge voltage VPRE to the second electrode of the capacitor CST in response to a second initialization signal GI2 transmitted via the second initialization line GI2L. In some embodiments, the seventh pixel transistor PXT7 may include a gate connected to the second initialization line GI2L, a first terminal receiving the pre-charge voltage VPRE, and a second terminal connected to the second electrode of the capacitor CST.

[0092] The light-emitting element EL can emit light based on the drive current generated by the first pixel transistor PXT1. In some embodiments, the light-emitting element EL can be, but is not limited to, an organic light-emitting diode (“OLED”). In other embodiments, the light-emitting element EL can be a nano-light-emitting diode (“NED”), a quantum dot (“QD”) light-emitting diode, a micro-light-emitting diode, an inorganic light-emitting diode, or any other suitable light-emitting element. Furthermore, in some embodiments, the light-emitting element EL can include an anode connected to a second terminal of the fourth pixel transistor PXT4 and a cathode receiving the second pixel power supply voltage ELVSS.

[0093] although Figure 11 An example of a pixel PX with a 7T1C structure is shown, but the pixel PX of the display device 500 according to the embodiment is not limited to... Figure 11 Examples.

[0094] Data driver 520 can generate a data signal DS based on output image data ODAT and data control signal DCTRL received from controller 580, and can provide the data signal DS to multiple pixels PX via multiple data lines. In some embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a level start signal, and a load signal. In some embodiments, data driver 520 and controller 580 may be implemented as a single integrated circuit, and the single integrated circuit may be referred to as a timing controller embedded data driver (“TED”). In other embodiments, data driver 520 and controller 580 may be implemented as separate integrated circuits.

[0095] The first gate driver 540 may be arranged on a first side (e.g., the left side) of a plurality of pixels PX or on a first side (e.g., the left side) of the display panel 510, and may provide gate signals to the plurality of pixels PX via multiple gate lines. In some embodiments, such as Figure 10 As shown, the display device 500 may include a left write driver (left GW driver) 541, a left compensation driver (left GC driver) 542, a left first initialization driver (left GI1 driver) 543, a left second initialization driver (left GI2 driver) 544, a left anode initialization driver (left EB driver) 545, and a left emitter driver (left EM driver) 546 as a first gate driver 540. The left write driver 541 provides the write signal GW to multiple pixels PX through multiple write lines GWL. The left compensation driver 542 provides the write signal GW to multiple pixels PX through multiple compensation lines GWL. The compensation line GCL provides the compensation signal GC to multiple pixels PX. The left first initialization driver 543 provides the first initialization signal GI1 to multiple pixels PX through multiple first initialization lines GI1L. The left second initialization driver 544 provides the second initialization signal GI2 to multiple pixels PX through multiple second initialization lines GI2L. The left anode initialization driver 545 provides the anode initialization signal EB to multiple pixels PX through multiple anode initialization lines EBL. The left transmit driver 546 provides the transmit signal EM to multiple pixels PX through multiple transmit lines EML. Each of the first gate driver 540 or the left write driver 541, left compensation driver 542, left first initialization driver 543, left second initialization driver 544, left anode initialization driver 545, and left transmit driver 546 can include... Figure 4 Level 200 or Figure 9 Level 300 Figure 1 The gate driver 100. Furthermore, in some embodiments, each of the first gate driver 540 or the left write driver 541, left compensation driver 542, left first initialization driver 543, left second initialization driver 544, left anode initialization driver 545, and left emitter driver 546 may be integrated or formed in the left region of the display panel 510. In other embodiments, each of the first gate driver 540 or the left write driver 541, left compensation driver 542, left first initialization driver 543, left second initialization driver 544, left anode initialization driver 545, and left emitter driver 546 may be implemented as one or more integrated circuits and may be connected to the left side of the display panel 510.

[0096] The second gate driver 560 can be arranged on a second side (e.g., the right side) opposite the first side of the plurality of pixels PX or on a second side (e.g., the right side) of the display panel 510, and can provide gate signals to the plurality of pixels PX via multiple gate lines. In some embodiments, such as Figure 10 As shown, the display device 500 may include a right write driver (right GW driver) 561, a right compensation driver (right GC driver) 562, a right first initialization driver (right GI1 driver) 563, a right second initialization driver (right GI2 driver) 564, a right anode initialization driver (right EB driver) 565, and a right emitter driver (right EM driver) 566 as a second gate driver 560. The right write driver 561 provides the write signal GW to multiple pixels PX through multiple write lines GWL. The right compensation driver 562 provides the write signal GW to multiple pixels PX through multiple compensation lines GWL. The compensation line GCL provides the compensation signal GC to multiple pixels PX. The right first initialization driver 563 provides the first initialization signal GI1 to multiple pixels PX through multiple first initialization lines GI1L. The right second initialization driver 564 provides the second initialization signal GI2 to multiple pixels PX through multiple second initialization lines GI2L. The right anode initialization driver 565 provides the anode initialization signal EB to multiple pixels PX through multiple anode initialization lines EBL. The right emitter driver 566 provides the emitter signal EM to multiple pixels PX through multiple emitter lines EML. Each of the second gate driver 560 or the right write driver 561, right compensation driver 562, right first initialization driver 563, right second initialization driver 564, right anode initialization driver 565, and right emitter driver 566 can include... Figure 4 Level 200 or Figure 9 Level 300 Figure 1 The gate driver 100. Furthermore, in some embodiments, the second gate driver 560 or each of the right write driver 561, right compensation driver 562, right first initialization driver 563, right second initialization driver 564, right anode initialization driver 565, and right emitter driver 566 may be integrated or formed in the right region of the display panel 510. In other embodiments, the second gate driver 560 or each of the right write driver 561, right compensation driver 562, right first initialization driver 563, right second initialization driver 564, right anode initialization driver 565, and right emitter driver 566 may be implemented as one or more integrated circuits and may be connected to the right side of the display panel 510.

[0097] Controller 580 (e.g., a timing controller) may receive input image data IDAT and control signal CTRL from an external processor (e.g., an application processor (“AP”), a graphics processing unit (“GPU”), or a graphics card). In some embodiments, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. Controller 580 may generate output image data ODAT and data control signal DCTRL based on the input image data IDAT and control signal CTRL, and may control data driver 520 by providing the output image data ODAT and data control signal DCTRL to data driver 520.

[0098] In addition, the controller 580 can transmit a start signal (e.g., Figure 1 The start signal STV), clock signal CLK, and output enable signal (e.g., Figure 1 The output enable signal (OE) and the first high impedance signal are provided to the first gate driver 540, and the start signal, clock signal CLK, output enable signal, and second high impedance signal can be provided to the second gate driver 560. When both the first high impedance signal and the second high impedance signal have a first level (e.g., low level L, see...),... Figure 2 When the first gate driver 540 and the second gate driver 560 are in operation, gate signals can be provided to the multiple pixels PX from opposite sides or from a first side (e.g., the left side) and a second side (e.g., the right side) via multiple gate lines. When the first high-impedance signal has a first level and the second high-impedance signal has a second level (e.g., a high level H, see...), the signal is delivered to the multiple pixels PX from opposite sides or from a first side (e.g., the left side) and a second side (e.g., the right side). Figure 3When the first high-impedance signal has a second level and the second high-impedance signal has a first level, the second gate driver 560 can provide gate signals to the multiple pixels PX from the first side through multiple gate lines, and the gate output nodes of the multiple second stages of the second gate driver 560 can be floated. In this case, the multiple second stages of the second gate driver 560 can perform a masking operation to convert the clock signal CLK applied to the multiple second stages into a low power supply voltage. When the first high-impedance signal has a second level and the second high-impedance signal has a first level, the second gate driver 560 can provide gate signals to the multiple pixels PX from the second side through multiple gate lines, and the gate output nodes of the multiple first stages of the first gate driver 540 can be floated. In this case, the multiple first stages of the first gate driver 540 can perform a masking operation to convert the clock signal CLK applied to the multiple first stages into a low power supply voltage. In some embodiments, not both the first high-impedance signal and the second high-impedance signal can have a second level, but at least one of the first high-impedance signal and the second high-impedance signal can have a first level, such that at least one of the first gate driver 540 and the second gate driver 560 can be activated.

[0099] In some embodiments, such as Figure 10As shown, controller 580 can provide the same clock signal CLK to left write driver 541 and right write driver 561, left compensation driver 542 and right compensation driver 562, left first initialization driver 543 and right first initialization driver 563, left second initialization driver 544 and right second initialization driver 564, left anode initialization driver 545 and right anode initialization driver 565, and left transmit driver 546 and right transmit driver 566. Furthermore, controller 580 can provide left write high impedance signal L_GW_HIZ and right write high impedance signal R_GW_HIZ to left write driver 541 and right write driver 561 respectively; it can provide left compensation high impedance signal L_GC_HIZ and right compensation high impedance signal R_GC_HIZ to left compensation driver 542 and right compensation driver 562 respectively; and it can provide left first initialization high impedance signal L_GI1_HIZ and right first initialization high impedance signal R_GI1_HIZ to left first initialization driver 543 and right first initialization driver 563 respectively. The left second initialization high impedance signal L_GI2_HIZ and the right second initialization high impedance signal R_GI2_HIZ are provided to the left second initialization driver 544 and the right second initialization driver 564, respectively. The left anode initialization high impedance signal L_EB_HIZ and the right anode initialization high impedance signal R_EB_HIZ are provided to the left anode initialization driver 545 and the right anode initialization driver 565, respectively. Furthermore, the left transmit high impedance signal L_EM_HIZ and the right transmit high impedance signal R_EM_HIZ are provided to the left transmit driver 546 and the right transmit driver 566, respectively. In addition, although in Figure 10 Not shown, but controller 580 may further provide the same write start signal and the same write output enable signal to left write driver 541 and right write driver 561, may further provide the same compensation start signal and the same compensation output enable signal to left compensation driver 542 and right compensation driver 562, may further provide the same first initialization start signal and the same first initialization output enable signal to left first initialization driver 543 and right first initialization driver 563, may further provide the same second initialization start signal and the same second initialization output enable signal to left second initialization driver 544 and right second initialization driver 564, may further provide the same anode initialization start signal and the same anode initialization output enable signal to left anode initialization driver 545 and right anode initialization driver 565, and may further provide the same transmit start signal and the same transmit output enable signal to left transmit driver 546 and right transmit driver 566.

[0100] In the display device 500 according to the embodiment, the left write driver 541 and the right write driver 561 can be selectively activated in response to the left write high impedance signal L_GW_HIZ and the right write high impedance signal R_GW_HIZ, respectively; the left compensation driver 542 and the right compensation driver 562 can be selectively activated in response to the left compensation high impedance signal L_GC_HIZ and the right compensation high impedance signal R_GC_HIZ, respectively; and the left first initialization driver 543 and the right first initialization driver 563 can be selectively activated in response to the left first initialization high impedance signal L_GI1_HIZ and the right first initialization high impedance signal R_GI1_HIZ, respectively. The left second initialization driver 544 and the right second initialization driver 564 can be selectively activated in response to the left second initialization high impedance signal L_GI2_HIZ and the right second initialization high impedance signal R_GI2_HIZ, respectively. The left anode initialization driver 545 and the right anode initialization driver 565 can be selectively activated in response to the left anode initialization high impedance signal L_EB_HIZ and the right anode initialization high impedance signal R_EB_HIZ, respectively. The left transmit driver 546 and the right transmit driver 566 can be selectively activated in response to the left transmit high impedance signal L_EM_HIZ and the right transmit high impedance signal R_EM_HIZ, respectively.

[0101] In conventional display devices, after evaluating the image quality, a dual-sided driving operation (providing gate signals from opposite sides of the display panel) or a single-sided driving operation (providing gate signals from one side of the display panel) can be selected. Therefore, if a single-sided driving operation is selected relative to a conventional display device designed to perform dual-sided driving, or vice versa, the conventional display device should be redesigned. However, the display device 500 according to an embodiment may include a first gate driver 540 and a second gate driver 560 arranged on opposite sides of the display panel 510, and the first gate driver 540 and the second gate driver 560 may be selectively activated in response to a first high-impedance signal and a second high-impedance signal, respectively. Therefore, even without redesigning the display device 500, the display device 500 according to the embodiment can selectively perform either dual-sided driving or single-sided driving.

[0102] Figure 12 This is a block diagram illustrating an electronic device including a display device according to an embodiment.

[0103] refer to Figure 12The electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (“USB”) devices, other electrical devices, etc.

[0104] Processor 1110 can perform various computing functions or tasks. Processor 1110 can be an application processor (“AP”), a microprocessor, a central processing unit (“CPU”), etc. Processor 1110 can be coupled to other components via address buses, control buses, data buses, etc. In addition, in some embodiments, processor 1110 can also be coupled to an expansion bus, such as a peripheral component interconnect (“PCI”) bus. Processor 1110 can provide input image data IDAT to display device 1160.

[0105] The memory device 1120 may store data for the operation of the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano-floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, a ferroelectric random access memory (“FRAM”) device, and / or at least one volatile memory device such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a mobile dynamic random access memory (“mobile DRAM”) device, and the like.

[0106] Storage device 1130 may include a solid-state drive (“SSD”) device, a hard disk drive (“HDD”) device, an optical disc read-only memory (“CD-ROM”) device, etc. I / O device 1140 may be an input device such as a keyboard, keypad, mouse, touchscreen, etc., and an output device such as a printer, speaker, etc. Power supply 1150 can supply power for the operation of electronic device 1100. Display device 1160 can be coupled to other components via a bus or other communication link.

[0107] The display device 1160 may include a first gate driver and a second gate driver disposed on opposite sides (e.g., left and right sides) of a display panel, and the first gate driver and the second gate driver may be selectively activated in response to a first high-impedance signal and a second high-impedance signal, respectively. Therefore, even without redesigning the display device 1160, the display device according to the embodiment may selectively perform a dual-sided driving operation providing gate signals from opposite sides (e.g., left and right sides) of the display panel or a single-sided driving operation providing gate signals from one side of the display panel.

[0108] This invention can be applied to any electronic device 1100 including a display device 1160. The display device 1160 can correspond to Figure 10 Display device 500. For example, the present invention can be applied to virtual reality (“VR”) devices, augmented reality (“AR”) devices, mixed reality (“MR”) devices, extended reality (“XR”) devices, mobile phones, smartphones, televisions (“TV”) (e.g., digital TV, 3D TV, etc.), wearable electronic devices, personal computers (“PC”) (e.g., laptop computers, tablet computers, etc.), home appliances, personal digital assistants (“PDAs”), portable multimedia players (“PMPs”), digital cameras, music players, portable game consoles, navigation devices, etc.

[0109] The foregoing is illustrative of the embodiments and should not be construed as limiting them. Although several embodiments have been described, those skilled in the art will readily appreciate that many modifications can be made to the embodiments without substantially departing from the novel teachings and advantages of the invention. Therefore, all such modifications are intended to be included within the scope of the invention as defined in the claims. It should be understood that the foregoing is illustrative of the various embodiments and should not be construed as limiting oneself to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A gate driver, the gate driver comprising multiple stages, wherein, At least one of the plurality of levels includes: The logic circuit is configured to generate an intermediate carry signal and a carry output signal by sampling a carry input signal based on a clock signal, and to generate an intermediate gate signal by performing logic operations on an output enable signal, the intermediate carry signal, and the carry output signal. A level shifting circuit is configured to generate a gate signal by shifting the voltage level of the intermediate gate signal; and A buffer circuit is configured to output the gate signal at the gate output node when the high impedance signal has a first level, and to float the gate output node when the high impedance signal has a second level.

2. The gate driver according to claim 1, wherein, While the high-impedance signal has the second level, the logic circuit performs a masking operation that converts the clock signal into a low power supply voltage.

3. The gate driver according to claim 1, wherein, The buffer circuit includes: The first PMOS transistor is configured to output a high gate voltage at the gate output node as the gate signal in response to the voltage of the first control node. The first NMOS transistor is configured to output a low gate voltage as the gate signal at the gate output node in response to the voltage of the second control node; A second PMOS transistor is configured to transmit the high gate voltage to the first control node in response to an inverted high-impedance signal; and The second NMOS transistor is configured to transmit the low gate voltage to the second control node in response to the high impedance signal.

4. The gate driver according to claim 3, wherein, The buffer circuit also includes: The first inverter is configured to generate an inverted gate signal by inverting the gate signal; A first transmission gate is configured to transmit the inverted gate signal to the first control node in response to the high-impedance signal and the inverted high-impedance signal; and The second transmission gate is configured to transmit the inverted gate signal to the second control node in response to the high-impedance signal and the inverted high-impedance signal.

5. The gate driver according to claim 1, wherein, The logic circuit includes: The first AND gate is configured to perform an AND operation on the clock signal and the inverted high-impedance signal; The first flip-flop is configured to output the intermediate carry signal by sampling the carry input signal at the rising edge of the output signal of the first AND gate; A second inverter is configured to invert the output signal of the first AND gate; The second flip-flop is configured to output the carry output signal by sampling the intermediate carry signal at the rising edge of the output signal of the second inverter; The second AND gate is configured to perform an AND operation on the output enable signal and the intermediate carry signal; and The NAND gate is configured to generate the intermediate gate signal by performing a NAND operation on the output signal of the second AND gate and the carry output signal.

6. The gate driver according to claim 1, wherein, The level shifting circuit includes: A first level shifter is configured to convert the high power supply voltage of the intermediate gate signal to a high gate voltage when the intermediate gate signal has a high power supply voltage; and A second level shifter is configured to convert the low power supply voltage of the intermediate gate signal to a low gate voltage when the intermediate gate signal has a low power supply voltage, and to output the gate signal having the high gate voltage or the low gate voltage.

7. The gate driver according to claim 6, wherein, The level shifting circuit also includes: The third inverter is configured to generate an inverted intermediate gate signal by inverting the intermediate gate signal. The first level shifter includes: The third NMOS transistor is configured to transmit the low power supply voltage to the first node in response to the intermediate gate signal; The fourth NMOS transistor is configured to transmit the low power supply voltage to the second node in response to the inverted intermediate gate signal; A third PMOS transistor is configured to transfer the high gate voltage to the first node in response to the voltage of the second node; A fourth PMOS transistor is configured to transfer the high gate voltage to the second node in response to the voltage of the first node; A fourth inverter is configured to invert the voltage at the first node; and A fifth inverter is configured to invert the voltage of the second node, and wherein the second level shifter includes: The fifth PMOS transistor is configured to transmit the high gate voltage to the third node in response to the output signal of the fourth inverter; The sixth PMOS transistor is configured to transmit the high gate voltage to the fourth node in response to the output signal of the fifth inverter; The fifth NMOS transistor is configured to transfer the low gate voltage to the third node in response to the voltage of the fourth node; The sixth NMOS transistor is configured to transfer the low gate voltage to the fourth node in response to the voltage of the third node; A sixth inverter is configured to generate a gate signal having either the high gate voltage or the low gate voltage by inverting the voltage at the third node; and The seventh inverter is configured to invert the voltage of the fourth node.

8. The gate driver according to claim 1, wherein, The buffer circuit includes: Multiple inverters, connected in series and configured to buffer the gate signal; and A transmission gate is configured to transmit the gate signal output from the plurality of inverters to the gate output node in response to the high-impedance signal and the inverted high-impedance signal.

9. An electronic device, wherein, The electronic device includes: The processor is configured to provide input image data; and A display device configured to receive input image data from the processor and display an image based on the input image data, the display device comprising: The display panel includes multiple gate lines and multiple pixels connected to the multiple gate lines; A data driver is configured to provide data signals to the plurality of pixels; A first gate driver is disposed on a first side of the plurality of pixels, and the first gate driver is configured to provide a plurality of gate signals to the plurality of pixels through the plurality of gate lines; A second gate driver is disposed on a second side of the plurality of pixels opposite to the first side, and the second gate driver is configured to provide the plurality of gate signals to the plurality of pixels through the plurality of gate lines; and The controller is configured to provide a start signal, a clock signal, an output enable signal, and a first high-impedance signal to the first gate driver, and to provide the start signal, the clock signal, the output enable signal, and a second high-impedance signal to the second gate driver. Wherein, the first gate driver includes a plurality of first stages, the second gate driver includes a plurality of second stages, and At least one of the plurality of first levels and the plurality of second levels includes: The logic circuit is configured to generate an intermediate carry signal and a carry output signal by sampling the carry input signal based on the clock signal, and to generate an intermediate gate signal by performing logic operations on the output enable signal, the intermediate carry signal and the carry output signal. A level shifting circuit is configured to generate a gate signal corresponding to one of the plurality of gate signals by shifting the voltage level of the intermediate gate signal; and A buffer circuit is configured to output the gate signal at the gate output node when the high impedance signal corresponding to one of the first high impedance signal and the second high impedance signal has a first level, and to float the gate output node when the high impedance signal has a second level.

10. An electronic device, wherein, The electronic device includes: The processor is configured to provide input image data; and A display device configured to receive input image data from the processor and display an image based on the input image data, the display device comprising: The display panel includes multiple write lines, multiple compensation lines, multiple first initialization lines, multiple second initialization lines, multiple anode initialization lines, multiple emission lines, and multiple pixels; A data driver is configured to provide data signals to the plurality of pixels; A left write driver and a right write driver are respectively arranged on the left and right sides of the plurality of pixels, and the left write driver and the right write driver are configured to provide write signals to the plurality of pixels through the plurality of write lines; A left compensation driver and a right compensation driver are respectively arranged on the left and right sides of the plurality of pixels, and the left compensation driver and the right compensation driver are configured to provide compensation signals to the plurality of pixels through the plurality of compensation lines; A left first initialization driver and a right first initialization driver are respectively arranged on the left and right sides of the plurality of pixels, and the left first initialization driver and the right first initialization driver are configured to provide a first initialization signal to the plurality of pixels through the plurality of first initialization lines; A left second initialization driver and a right second initialization driver are respectively arranged on the left and right sides of the plurality of pixels, and the left second initialization driver and the right second initialization driver are configured to provide a second initialization signal to the plurality of pixels through the plurality of second initialization lines; A left anode initialization driver and a right anode initialization driver are respectively arranged on the left and right sides of the plurality of pixels, and the left anode initialization driver and the right anode initialization driver are configured to provide an anode initialization signal to the plurality of pixels through the plurality of anode initialization lines; A left emitter driver and a right emitter driver are respectively arranged on the left and right sides of the plurality of pixels, and the left emitter driver and the right emitter driver are configured to provide emitter signals to the plurality of pixels through the plurality of emitter lines; and The controller is configured to provide the same clock signal to the left write driver and the right write driver, the left compensation driver and the right compensation driver, the left first initialization driver and the right first initialization driver, the left second initialization driver and the right second initialization driver, the left anode initialization driver and the right anode initialization driver, and the left transmit driver and the right transmit driver; to provide a left write high impedance signal and a right write high impedance signal to the left write driver and the right write driver respectively; to provide a left compensation high impedance signal and a right compensation high impedance signal to the left compensation driver and the right compensation driver respectively; to provide a left first initialization high impedance signal and a right first initialization high impedance signal to the left first initialization driver and the right first initialization driver respectively; to provide a left second initialization high impedance signal and a right second initialization high impedance signal to the left second initialization driver and the right second initialization driver respectively; to provide a left anode initialization high impedance signal and a right anode initialization high impedance signal to the left anode initialization driver and the right anode initialization driver respectively; and to provide a left transmit high impedance signal and a right transmit high impedance signal to the left transmit driver and the right transmit driver respectively. Each of the left write driver and the right write driver, the left compensation driver and the right compensation driver, the left first initialization driver and the right first initialization driver, the left second initialization driver and the right second initialization driver, the left anode initialization driver and the right anode initialization driver, and the left transmit driver and the right transmit driver comprises multiple stages, and Wherein, at least one of the plurality of levels includes: The logic circuit is configured to generate an intermediate carry signal and a carry output signal by sampling the carry input signal based on the clock signal, and to generate an intermediate gate signal by performing logic operations on the output enable signal, the intermediate carry signal and the carry output signal. A level shifting circuit is configured to generate a gate signal corresponding to one of the write signal, the compensation signal, the first initialization signal, the second initialization signal, the anode initialization signal, and the transmit signal by shifting the voltage level of the intermediate gate signal; and The buffer circuit is configured to output the gate signal at the gate output node when the high impedance signal corresponding to one of the left write high impedance signal and the right write high impedance signal, the left compensated high impedance signal and the right compensated high impedance signal, the left first initial high impedance signal and the right first initial high impedance signal, the left second initial high impedance signal and the right second initial high impedance signal, the left anode initial high impedance signal and the right anode initial high impedance signal, and the left transmit high impedance signal and the right transmit high impedance signal has a first level, and to float the gate output node when the high impedance signal has a second level.

Images