Multi-module energy storage converter multi-machine parallel system and carrier synchronization method thereof

Abstract

The invention discloses a multi-module energy storage converter multi-machine parallel system and a carrier synchronization method thereof, and belongs to the field of energy storage of a new energy power system. In order to overcome the defects of poor anti-interference capability, poor reliability and high maintenance cost when multiple existing multi-module energy storage converters are connected in parallel, the voltage of the same power grid connection point is sampled, and an initial synchronization signal is generated at a voltage zero crossing point; a unified carrier synchronization reference is calculated; the main FPGA of the PCS control board broadcasts and issues a unified synchronous reference signal to all the PCM modules through optical fibers; each PCM module receives an instruction to drive the DSP so as to realize the synchronous switching action of the PCM module; each PCM module continuously monitors the voltage of a power grid and feeds back zero crossing point information to the main FPGA; and the main FPGA compares the deviation between the instruction and the actual feedback, and if the deviation exceeds a preset range, the synchronization reference is adjusted to realize self-adaptive deviation correction in operation. The carrier synchronization method is mainly used for carrying out carrier synchronization on the multi-machine parallel energy storage converter.

Description

Technical Field

[0001] This invention belongs to the field of energy storage in new energy power systems, and particularly relates to a multi-module energy storage converter multi-machine parallel system and its carrier synchronization method. Background Technology

[0002] As the capacity of electrochemical energy storage systems continues to increase, the power of energy storage converters is also constantly growing. To achieve greater charging and discharging power, multiple energy storage converters are typically connected in parallel. While parallel operation increases the charging and discharging power of the energy storage converters, it also introduces problems such as circulating current and power imbalance, which are usually eliminated using carrier synchronization.

[0003] Carrier synchronization typically uses a synchronization signal line, where the master sends a synchronization signal and the slave receives the signal and performs carrier synchronization. However, using modular energy storage converters, especially when there are many of them, has the following disadvantages: 1. The number of parallel connections using fiber optic cables is easily limited by the number of synchronization signal interfaces on the host computer; the synchronization signal lines are susceptible to external electromagnetic interference, which can lead to a decrease in synchronization accuracy. 2. As the number of modules increases, the wiring complexity increases significantly, and the maintenance cost also rises accordingly; 3. Cable connections are prone to interference due to the large number of nodes; signal transmission delay may be exacerbated by the increase in line length and number of nodes, affecting the overall system performance.

[0004] Therefore, there is a need for a multi-module energy storage converter parallel system with strong anti-interference capability, high reliability, and low maintenance cost, as well as its carrier synchronization method. Summary of the Invention

[0005] In order to overcome the shortcomings of existing multi-module energy storage converters with poor anti-interference capability, poor reliability and high maintenance cost when multiple units are connected in parallel, this invention provides a multi-module energy storage converter parallel system with strong anti-interference capability, high reliability and low maintenance cost and its carrier synchronization method.

[0006] The carrier synchronization method for multi-module energy storage converters in parallel according to the present invention includes the following steps: S1. Uplink transmission process of carrier synchronization signal: After the power grid is powered on, the voltage of the same power grid connection point is sampled independently and in parallel, and an initial synchronization signal is generated at the voltage zero crossing point. S2. Downlink transmission process of carrier synchronization signal: The main FPGA of the PCS control board receives the initial synchronization signals of all PCM modules inside it and calculates a unified carrier synchronization reference. S3. DSP carrier synchronization during normal operation: The main FPGA of the PCS control board broadcasts a unified synchronization reference signal to all PCM modules through optical fiber; each PCM module receives the instruction, drives the DSP, and realizes the synchronous switching action of all PCM modules. S4. Each PCM module continuously monitors the grid voltage and feeds back the zero-crossing information to the main FPGA. The main FPGA compares the deviation between the instruction and the actual feedback. If the deviation exceeds the preset range, it adjusts the synchronization reference to achieve adaptive correction during operation.

[0007] Further: In S1, the specific process of generating the initial synchronization signal includes: S11. After the power grid is powered on, each PCM module starts to independently and in parallel acquire the power grid voltage signal through the DSP's AD sampling module. S12. When a zero-crossing point is detected in a certain phase of the grid voltage signal, a carrier synchronization initial signal is generated from the FPGA within the current PCM module. S13. Each PCM module transmits its initial synchronization signal generated by the FPGA to the PCS control board of the local energy storage converter via an optical fiber communication link.

[0008] Further: In S2, the calculation process of the carrier synchronization reference is as follows: S21. The main FPGA of the PCS control board receives the initial synchronization signal from the uplink of all n PCM modules under its jurisdiction. S22. The main FPGA determines whether the system meets the initialization conditions based on the number of initial signals received and the time difference between each signal. S23. If the conditions are met, the main FPGA will use all the received initial signals as the unified carrier synchronization reference initial value to complete the internal synchronization initialization of the PCS. Since all devices are based on the same power grid voltage source, their respective references will be naturally aligned at the system level.

[0009] Further: In S22, the initialization condition is: The initial synchronization signals of multiple PCMs, the time interval ΔT1 between the first signal and the last signal is set according to the time range T1 allowed by the hardware; The average time between the second signal and the (n-1)th signal is calculated, and the reference signal is generated at the average time. A reference carrier synchronization signal with a fixed period is output with the reference signal generation time as 0.

[0010] Further: In S3, the specific steps of carrier synchronization of the DSP are as follows: S31. When the system is running, the main FPGA of the PCS control board begins to periodically generate a unified carrier synchronization signal. S32. The generated periodic carrier synchronization signal is simultaneously broadcast and sent to the FPGA of each PCM module inside this PCS via optical fiber. S33. After receiving the downlink synchronization signal from the FPGA, each PCM module directly transmits it to the DSP on this board through the chip pins. Based on this synchronization signal, S34 and DSP generate a precisely synchronized PWM drive waveform to control the switching of power devices, thereby achieving carrier-synchronized operation of all converter modules.

[0011] Furthermore, in S4, the specific process of adaptive correction is as follows: S41. During operation, the main FPGA continuously monitors the time interval between the uplink feedback signal and the downlink synchronization signal; S42. If the current time interval is found to exceed the preset allowable error range, the main FPGA will actively adjust the corresponding carrier synchronization reference value and reissue the updated synchronization reference value to achieve adaptive correction during operation.

[0012] Furthermore: When multiple modules of the energy storage converter are connected in parallel, all the parallel energy storage converters (PCS) are connected to the same grid common connection point. Therefore, the zero-crossing point of the sampled grid voltage is the grid voltage at the same moment.

[0013] The present invention describes a multi-module energy storage converter parallel system for implementing a carrier synchronization method for multi-module energy storage converters in parallel, comprising m energy storage converters connected to the common connection of the power grid. Each energy storage converter includes a PCS control board and n energy storage converter modules. The PCS control board includes a master FPGA, and each energy storage converter module includes a PCM control board, wherein each PCM control board includes a DSP and a slave FPGA. The energy storage converter is connected to the grid's point of common coupling and has the same grid voltage. Each of the PCM modules communicates with the PCS control via optical fiber, eliminating the need for separate synchronization signal cables; The PCS control board has multiple fiber optic interfaces to meet the requirements of a single energy storage converter. The DSP within each of the PCM control boards is directly connected to the FPGA via multiple chip pins; Each of the DSPs has an AD sampling module for acquiring grid voltage.

[0014] The beneficial effects of this invention are: This invention effectively avoids the electromagnetic interference susceptibility of traditional synchronization signal cables by employing fiber optic communication links, significantly improving the system's anti-interference capability. Simultaneously, the combination of independent sampling and centralized processing among modules ensures high reliability during multi-unit parallel operation. Furthermore, the elimination of the need for complex additional synchronization signal cables significantly reduces installation and maintenance costs, while also minimizing potential failure points caused by line complexity. This method is suitable for large-scale energy storage scenarios, meeting the requirements of multi-module, multi-unit parallel operation, and providing strong support for the stable operation of new energy power systems. Attached Figure Description

[0015] Figure 1 A schematic diagram of multiple modules of energy storage converter connected in parallel; Figure 2 A schematic diagram of the initialization signal transmission for the carrier synchronization signal upon power-up; Figure 3 This is a schematic diagram of carrier synchronization signal transmission during normal operation. Figure 4 A flowchart illustrating the initialization and operation process of the carrier synchronization signal; In the diagram, 1 is the energy storage converter; 2 is the PCS control board; 3 is the energy storage converter module; and 4 is the PCM control board. Detailed Implementation

[0016] The following are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. The embodiments described below are only for explaining the present invention and should not be construed as limiting the present invention. The scope of protection of the present invention should be determined by the scope of the claims. The embodiments of the present invention are described in detail below. In order to facilitate the description of the present invention and simplify the description, the technical terms used in the specification of the present invention should be interpreted broadly, including but not limited to conventional alternatives not mentioned in this application, and including both direct and indirect implementation methods.

[0017] Example 1 Combination Figures 1-3 This embodiment describes a multi-module energy storage converter multi-machine parallel system, such as... Figure 1As shown, the system includes m energy storage converters 1 connected to the grid common connection. Each energy storage converter 1 includes a PCS control board 2 (Power Conversion System) and n energy storage converter modules 3. The PCS control board 2 includes a main FPGA, and each energy storage converter module 3 includes a PCM control board 4 (Pulse Code Modulation). Each PCM control board 4 includes a DSP (Digital Signal Processing) chip and a slave FPGA.

[0018] The energy storage converter is connected to the grid's point of common coupling and has the same grid voltage.

[0019] The PCM module communicates with the PCS control via optical fiber, eliminating the need for a separate synchronization signal cable.

[0020] The PCS control board has multiple fiber optic interfaces to meet the requirements of a single energy storage converter.

[0021] The PCM control board DSP and FPGA are directly connected through multiple chip pins.

[0022] The PCM control board DSP has an AD sampling module that can collect grid voltage.

[0023] Upon receiving the synchronization signal from the master FPGA, the slave FPGA of each energy storage converter module immediately decodes it and transmits the decoded signal to the DSP via its internal bus. The DSP, based on the received synchronization signal and its own computational logic, adjusts the initial value of its internal counter to ensure that the generated PWM waveform is completely consistent with that of other modules. Throughout this process, the fiber optic communication links between modules maintain high bandwidth and low latency, thus guaranteeing the real-time performance and accuracy of signal transmission.

[0024] Furthermore, when generating a unified carrier synchronization signal, the main FPGA comprehensively considers the real-time fluctuations of the power grid voltage and the operating status information fed back by each module. This dynamic adjustment mechanism enables the system to adapt to complex power grid environments, maintaining the synchronization performance of all modules even in the event of slight distortions or frequency shifts in the power grid voltage. This approach not only improves the system's robustness but also further reduces the risk of synchronization errors caused by power grid fluctuations.

[0025] To verify the system's synchronization accuracy, the PWM waveforms output by multiple energy storage converter modules were compared and analyzed using an oscilloscope. Experimental results show that under different load conditions, the PWM waveforms of each module remain highly consistent, with phase and amplitude deviations controlled within extremely small ranges. This characteristic provides a solid guarantee for the stable operation of the multi-module parallel system, while also significantly reducing the probability of circulating current phenomena and improving the overall system's energy conversion efficiency.

[0026] Example 2 In conjunction with Example 1, Figures 2-4 This embodiment describes a carrier synchronization method for a multi-module energy storage converter multi-machine parallel system as described in Embodiment 1, comprising the following steps: S1, as attached Figure 2 As shown, the uplink transmission process of the carrier synchronization signal is as follows: When the power grid is powered on, each PCM module starts to independently sample the grid voltage and flips the carrier synchronization initial signal uplink pin to output the signal from the FPGA when the grid voltage of phase A (or phase B, phase C) crosses zero. The FPGA then transmits the carrier synchronization initial signal to the main FPGA of the PCS control board through optical fiber.

[0027] The grid voltage zero-crossing point is sampled by multiple initial signals generated by each PCM control board. These multiple initial signals are then processed by the PCS control board to generate a carrier synchronization reference signal.

[0028] S11. After the power grid is powered on, each PCM module starts to independently and in parallel acquire the power grid voltage signal through the DSP's AD sampling module. S12. When a zero-crossing point is detected in a certain phase of the grid voltage signal, an initial carrier synchronization signal is generated from the FPGA within the current PCM module. S13. Each PCM module transmits its initial synchronization signal generated by the FPGA to the PCS control board of the local energy storage converter via an optical fiber communication link.

[0029] The PCM module's control board contains a DSP chip for sampling processing, and external sampling lines and conditioning circuits or voltage detection sensors are required for signal conversion.

[0030] Upon receiving the synchronization signal from the master FPGA, each PCM module's slave FPGA immediately decodes it and transmits the decoded signal to the DSP via its internal bus. The DSP, based on the received synchronization signal and its own computational logic, adjusts the initial value of its internal counter to ensure the generated PWM waveform is completely consistent with other modules. Throughout this process, the fiber optic communication links between modules maintain high bandwidth and low latency, guaranteeing real-time signal transmission and accuracy. Furthermore, when generating a unified carrier synchronization signal, the master FPGA comprehensively considers real-time fluctuations in the grid voltage and the operational status information fed back by each module. This dynamic adjustment mechanism allows the system to adapt to complex grid environments, maintaining synchronization performance across all modules even with slight grid voltage distortion or frequency shifts. This approach not only improves system robustness but also further reduces the risk of synchronization errors caused by grid fluctuations. To verify the system's synchronization accuracy, the PWM waveforms output by multiple energy storage converter modules can be compared and analyzed using an oscilloscope. Experimental results show that under different load conditions, the PWM waveforms of each module remain highly consistent, with phase and amplitude deviations controlled within minimal ranges. This characteristic provides a solid guarantee for the stable operation of multi-machine parallel systems, while also significantly reducing the probability of circulating current phenomena and improving the overall system's energy conversion efficiency.

[0031] S2, as attached Figure 3 As shown, the downlink transmission process of the carrier synchronization signal: After the main FPGA of the PCS control board completes the initial value setting, the main FPGA transmits the carrier synchronization downlink signal to the slave FPGA of each PCM module through optical fiber. The slave FPGA outputs to the DSP through pins, and the DSP performs PWM output according to the carrier synchronization signal.

[0032] In S2, the calculation process of the carrier synchronization reference is as follows: S21. The main FPGA of the PCS control board receives the initial synchronization signal from the uplink of all n PCM modules under its jurisdiction. S22. The main FPGA determines whether the system meets the initialization conditions based on the number of initial signals received and the time difference between each signal. The initialization conditions are: (1) The initial synchronization signal of multiple PCMs, the time interval ΔT1 between the first signal and the last signal is set according to the time range T1 allowed by the hardware; for example, ΔT1 needs to be within the time range T1 allowed by the hardware. (2) Calculate the average time between the second signal and the (n-1)th signal, and generate a reference signal at the average time; (3) Output a reference carrier synchronization signal with a fixed period, with the time when the reference signal is generated as 0.

[0033] S23. If the conditions are met, the main FPGA will use all the received initial signals as the unified carrier synchronization reference initial value to complete the internal synchronization initialization of the PCS. Since all devices are based on the same power grid voltage source, their respective references will be naturally aligned at the system level.

[0034] As attached Figure 4 The diagram below illustrates the initialization and operation workflow of the carrier synchronization signal. S3, PCS control board main FPGA carrier synchronization signal initialization and update; The main FPGA determines whether the initialization conditions are met based on the number of initial carrier synchronization signals received from the slave FPGA and the time difference. If the initialization conditions are met, it determines whether the main FPGA has completed the initial value setting of the carrier synchronization signal. If it has not been initialized, the main FPGA uses the midpoint of the slave FPGA as the initial value to complete the carrier synchronization initialization and enters the normal carrier synchronization information transmission. If the initialization has been completed, the main FPGA compares whether the time interval between the uplink synchronization signal and the downlink synchronization signal is within the allowable error range. If it exceeds the error range, it updates the initial value of the carrier synchronization of the main FPGA and enters the normal carrier synchronization signal transmission.

[0035] In S3, the specific steps of carrier synchronization of the DSP are as follows: S31. When the system is running, the main FPGA of the PCS control board begins to periodically generate a unified carrier synchronization signal. S32. The generated periodic carrier synchronization signal is simultaneously broadcast and sent to the FPGA of each PCM module inside this PCS via optical fiber. S33. After receiving the downlink synchronization signal from the FPGA, each PCM module directly transmits it to the DSP on this board through the chip pins. Based on this synchronization signal, S34 and DSP generate a precisely synchronized PWM drive waveform to control the switching of power devices, thereby achieving carrier-synchronized operation of all converter modules.

[0036] S4. DSP carrier synchronization during normal operation During normal operation, the FPGA on the PCS control board transmits carrier synchronization signals to the slave FPGA of each PCM module via optical fiber. The slave FPGA outputs the signals to the DSP via pins, and the DSP performs PWM output based on the carrier synchronization signals.

[0037] In S4, the specific process of adaptive correction is as follows: S41. During operation, the main FPGA continuously monitors the time interval between the uplink feedback signal and the downlink synchronization signal; S42. If the current time interval is found to exceed the preset allowable error range, the main FPGA will actively adjust the corresponding carrier synchronization reference value and reissue the updated synchronization reference value to achieve adaptive correction during operation.

Claims

1. A carrier synchronization method for multiple parallel multi-module energy storage converters, characterized in that, Includes the following steps: S1. Uplink transmission process of carrier synchronization signal: After the power grid is powered on, the voltage of the same power grid connection point is sampled independently and in parallel, and an initial synchronization signal is generated at the voltage zero crossing point. S2. Downlink transmission process of carrier synchronization signal: The main FPGA of the PCS control board receives the initial synchronization signals of all its internal PCM modules and calculates a unified carrier synchronization reference signal. S3. DSP carrier synchronization during normal operation: The main FPGA of the PCS control board broadcasts a unified synchronization reference signal to all PCM modules through optical fiber; each PCM module receives the instruction, drives the DSP, and realizes the synchronous switching action of all PCM modules. S4. Each PCM module continuously monitors the grid voltage and feeds back the zero-crossing information to the main FPGA. The main FPGA compares the deviation between the instruction and the actual feedback. If the deviation exceeds the preset range, it adjusts the synchronization reference to achieve adaptive correction during operation.

2. The carrier synchronization method for multi-module energy storage converters in parallel operation according to claim 1, characterized in that, In S1, the specific process of generating the initial synchronization signal includes: S11. After the power grid is powered on, each PCM module starts to independently and in parallel acquire the power grid voltage signal through the DSP's AD sampling module. S12. When a zero-crossing point is detected in a certain phase of the grid voltage signal, an initial carrier synchronization signal is generated from the FPGA within the current PCM module. S13. Each PCM module transmits its initial synchronization signal generated by the FPGA to the PCS control board of the local energy storage converter via an optical fiber communication link.

3. The carrier synchronization method for multi-module energy storage converters in parallel operation according to claim 1, characterized in that, In S2, the calculation process of the carrier synchronization reference is as follows: S21. The main FPGA of the PCS control board receives the initial synchronization signal from the uplink of all n PCM modules under its jurisdiction. S22. The main FPGA determines whether the system meets the initialization conditions based on the number of initial signals received and the time difference between each signal. S23. If the conditions are met, the main FPGA will use all the received initial signals as the unified carrier synchronization reference initial value to complete the internal synchronization initialization of the PCS. Since all devices are based on the same power grid voltage source, their respective references will be naturally aligned at the system level.

4. The carrier synchronization method for multi-module energy storage converters in parallel operation according to claim 1, characterized in that, In S22, the initialization condition is: The initial synchronization signals of multiple PCMs, the time interval ΔT1 between the first signal and the last signal is set according to the time range T1 allowed by the hardware; The average time between the second signal and the (n-1)th signal is calculated, and a reference signal is generated at the average time. A fixed-period reference carrier synchronization signal is output with the reference signal generation time as 0.

5. The carrier synchronization method for multi-module energy storage converters in parallel operation according to claim 1, characterized in that, In S3, the specific steps of carrier synchronization of the DSP are as follows: S31. When the system is running, the main FPGA of the PCS control board begins to periodically generate a unified carrier synchronization signal. S32. The generated periodic carrier synchronization signal is simultaneously broadcast and sent to the FPGA of each PCM module inside this PCS via optical fiber. S33. After receiving the downlink synchronization signal from the FPGA, each PCM module directly transmits it to the DSP on this board through the chip pins. Based on this synchronization signal, S34 and DSP generate a precisely synchronized PWM drive waveform to control the switching of power devices, thereby achieving carrier-synchronized operation of all converter modules.

6. The carrier synchronization method for multi-module energy storage converters in parallel operation according to claim 1, characterized in that, In S4, the specific process of adaptive correction is as follows: S41. During operation, the main FPGA continuously monitors the time interval between the uplink feedback signal and the downlink synchronization signal; S42. If the current time interval is found to exceed the preset allowable error range, the main FPGA will actively adjust the corresponding carrier synchronization reference value and reissue the updated synchronization reference value to achieve adaptive correction during operation.

7. The carrier synchronization method for multi-module energy storage converters in parallel operation according to claim 1, characterized in that, When multiple modules of the energy storage converter are connected in parallel, all the parallel energy storage converters (PCS) are connected to the same grid common connection point. Therefore, the zero-crossing point of the sampled grid voltage is the grid voltage at the same moment.

8. A multi-module energy storage converter parallel system for implementing a carrier synchronization method for multi-module energy storage converters in parallel as described in any one of claims 1-7, characterized in that, It includes m energy storage converters connected to the grid common connection. Each energy storage converter includes a PCS control board and n energy storage converter modules. The PCS control board includes a master FPGA, and each energy storage converter module includes a PCM control board, wherein each PCM control board includes a DSP and a slave FPGA. The energy storage converter is connected to the grid's point of common coupling and has the same grid voltage. Each of the PCM modules communicates with the PCS control via optical fiber. The PCS control board has multiple fiber optic interfaces to meet the requirements of a single energy storage converter. The DSP within each of the PCM control boards is directly connected to the FPGA via multiple chip pins; Each of the DSPs has an AD sampling module for acquiring grid voltage.

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