Self-rectification nonvolatile electrochemical memory and preparation method thereof

Abstract

The invention discloses a self-rectification nonvolatile electrochemical memory and a preparation method thereof. The memory comprises a substrate, and a source electrode, a rectification layer, a modification layer, a channel layer, a drain electrode, a grid electrode and an electrolyte layer which are arranged on the substrate, the source electrode is a bottom electrode, the drain electrode is a top electrode, the rectification layer, the modification layer and the channel layer are sequentially arranged between the source electrode and the drain electrode from bottom to top, and the source electrode, the rectification layer, the modification layer, the channel layer and the drain electrode form a sandwich structure; the grid electrode is arranged on one side of the sandwich structure, and a channel layer is arranged between the grid electrode and the substrate; the electrolyte layer covers the grid electrode and the sandwich structure from top to bottom. The vertical sandwich structure is adopted, on one hand, the depth-to-length ratio of a channel can be increased, potential distribution is flat, the ion containing capacity is improved, and therefore good nonvolatile storage performance is obtained; and on the other hand, the sandwich structure allows a rectification layer to be constructed below the channel layer to realize a one-way conduction mechanism similar to a p-n junction, so that the device has a self-rectification behavior, non-volatile storage and rectification performance are integrated in a single device, and single device integration of storage and self-rectification functions is realized.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to a self-rectified non-volatile electrochemical memory and its preparation method. Background Technology

[0002] The rapid iteration of artificial intelligence technology has placed higher demands on hardware computing power, especially the parallel processing and low-power characteristics of neuromorphic computing, which have become core directions for supporting advanced artificial intelligence applications. Currently, mainstream computing hardware is still based on von Neumann architecture. The von Neumann architecture, with its physically separated storage and data processing units, leads to significant latency and energy consumption during data retrieval and transmission. Furthermore, the need for sequential algorithm execution makes it difficult to match the parallel computing efficiency of the human brain's neural networks. This architectural bottleneck has become a key factor limiting the performance improvement of artificial intelligence hardware. To overcome this limitation, in-memory computing artificial neural network hardware has become a research focus. The core of such hardware lies in high-performance storage devices. Existing solutions mostly rely on two-terminal storage devices (such as resistive random access memory, bridged random access memory, and phase-change memory), but these devices generally suffer from drawbacks such as few effective conductance states, high write randomness, and insufficient linearity, which restrict computational accuracy and efficiency. While three-terminal storage devices, represented by floating-gate transistor memory, offer improved write accuracy, they suffer from high write voltage and high manufacturing complexity, making it difficult to meet the comprehensive storage performance requirements of in-memory computing hardware.

[0003] In high-density storage scenarios, storage devices are typically integrated in a cross-array configuration. While the traditional 1R cell structure, consisting of devices at both ends, can reduce cell area and increase storage density, it is prone to bypass current crosstalk: when some cells in the array are in a low-resistance state, the current reading from high-resistance cells will form a bypass path through surrounding low-resistance cells, leading to data misreading. Furthermore, this crosstalk can affect the signal accuracy of many surrounding cells. To address this issue, existing solutions often employ series rectifier devices (such as diodes, selectors, and transistors) within the storage cell, forming composite structures such as 1D1R, 1S1R, and 1T1R. However, these solutions add additional device manufacturing steps, increasing processing costs and significantly reducing array integration density, which contradicts the high-density and low-cost requirements of in-memory computing hardware. Therefore, the industry urgently needs an integrated device that can simultaneously achieve storage and rectification functions in a single device.

[0004] In summary, the current development of AI hardware requires not only higher-performance storage devices with multiple conductance states, low write randomness, high linearity, low power consumption, and low cost, but also solutions to the crosstalk problem of cross arrays without sacrificing integration. Existing technologies are unable to meet both of these core requirements simultaneously. Summary of the Invention

[0005] To overcome the problem that existing devices cannot simultaneously integrate storage and rectification functions, the present invention aims to provide a self-rectifying non-volatile electrochemical memory and its preparation method. By utilizing the interaction between ions and conductive polymer chain segments and interface modification to increase the potential barrier, a single device integrating multi-conductance state storage and self-rectification functions is achieved. The device features precise programming, simple process, and low processing cost.

[0006] To achieve the above objectives, the present invention provides the following technical solution: A non-volatile electrochemical memory with self-rectification characteristics includes a substrate, and a source electrode, a rectifier layer, a modification layer, a channel layer, a drain electrode, a gate electrode, and an electrolyte layer disposed on the substrate. The source electrode is the bottom electrode, and the drain electrode is the top electrode. A rectifier layer, a modification layer, and a channel layer are sequentially arranged between the source and the drain electrode from bottom to top. The source electrode, rectifier layer, modification layer, channel layer, and drain electrode form a sandwich structure. The source and drain electrodes are arranged perpendicularly in the sandwich structure. The gate electrode is arranged on one side of the sandwich structure, and a channel layer is arranged between the gate electrode and the substrate. The electrolyte layer covers the gate electrode and the sandwich structure from top to bottom and fills the gap between the gate electrode and the sandwich structure.

[0007] Furthermore, the substrate is silicon dioxide, silicon, or polyethylene terephthalate; The source is an indium tin oxide layer with a thickness of 40~200 nm; The rectifier layer is a zinc oxide layer with a thickness of 100~200 nm.

[0008] Furthermore, the modification layer is a 10-50 nm thick polyethyleneimine layer or an ethoxylated polyethyleneimine layer; The channel layer has a thickness of 100~300 nm, a width of 300~500 μm, and a height of 300~500 μm; the channel layer material is a P-type organic semiconductor.

[0009] Furthermore, the drain electrode is a gold layer with a thickness of 60~100 nm; The gate is a 60~100 nm thick gold layer; P-type organic semiconductors include P(g2T-T), P(g2T-TT), PTTBT, PTBT, or P(gBTTT).

[0010] A method for fabricating a self-rectifying non-volatile electrochemical memory includes the following steps: An indium tin oxide layer was deposited on the substrate using DC magnetron sputtering to prepare a patterned source electrode. Then, a rectifier layer was prepared on the substrate and the source electrode using a sol-gel spin coating process. After patterning the rectifier layer, a modification layer was prepared on the rectifier layer using a solution spin coating process. After a first annealing, the modification layer was patterned. A channel layer was prepared on the modification layer using a solution spin coating process. After a second annealing, a metal drain electrode and a metal gate electrode were prepared on the channel layer using a vacuum evaporation deposition process. The channel layer was patterned. Finally, an electrolyte layer was prepared on the sandwich structure and the gate electrode, and the gap between the gate electrode and the sandwich structure was filled with the electrolyte layer.

[0011] Furthermore, the annealing conditions are as follows: annealing at 80°C for 20 min in a nitrogen atmosphere; The secondary annealing conditions are as follows: when the material of the channel layer is p(g2T-T), annealing is carried out in a nitrogen atmosphere at a temperature of 120℃ for 60 min. When the channel layer material is P(g2T-TT), it is annealed in a nitrogen atmosphere at a temperature of 160℃ for 30 min. When the channel layer is made of PTTBT, it is annealed in a nitrogen atmosphere at a temperature of 180°C for 45 minutes.

[0012] Furthermore, the conditions for patterning the rectifier layer, the decoration layer, and the channel layer are as follows: etching is performed using argon gas at a power of 60~120 W for a time of 120~300 s. A patterned source electrode was fabricated by depositing an indium tin oxide layer on a substrate using a DC magnetron sputtering process, including: in a vacuum level below 5 × 10⁻⁶. -4 At Pa, a mixed gas of argon and oxygen in a volume ratio of 9:1 is introduced, the DC sputtering power is 90~120W, the target material is indium oxide and tin dioxide in a molar ratio of 9:1, and a source electrode with a thickness of 40~200 nm is deposited on the substrate using a stainless steel mask.

[0013] Furthermore, the preparation of the rectifier layer on the substrate and the source electrode using a sol-gel spin coating process includes: mixing zinc acetate and 2-hydroxyethylamine at a mass ratio of 3:1 to obtain a mixture; dissolving 1.2 g of the mixture in 10 ml of ethylene glycol monomethyl ether to prepare a zinc oxide precursor solution; then dropping the zinc oxide precursor solution onto the substrate, rotating the substrate at 2000~5000 rpm, and continuously spinning and drying for 30 s; and then reacting at 180~220℃ for 60 min to obtain the rectifier layer. The preparation of the modification layer on the rectifier layer using a solution spin coating process includes: dropping a branched polyethyleneimine solution onto the substrate, then rotating the substrate at 3000~5000 rpm and continuously spinning to dry it for 30 s; The preparation of the channel layer on the modification layer using a solution spin coating process includes: dissolving P(g2T-T) in chloroform to obtain a P(g2T-T) solution with a concentration of 12~18 g / L; dissolving P(g2T-TT) in chloroform to obtain a P(g2T-TT) solution with a concentration of 10~20 g / L; dissolving PTTBT in chloroform to obtain a PTTBT solution with a concentration of 5~10 g / L; dropping the P(g2T-T) solution, P(g2T-TT) solution, or PTTBT solution onto a substrate rotating at 1000~4000 rpm, and continuously spinning and spin-drying for 20 s.

[0014] Furthermore, a metal drain and a metal gate are fabricated on the channel layer using a vacuum evaporation deposition process, including: in a vacuum level lower than 6 × 10⁻⁶. -4 In the cavity of Pa, a stainless steel mask is used for patterning with a linewidth of 300~500 μm, and a film with a thickness of 60~100 nm is deposited at a rate of 0.1~0.2 nm / s to form a metal drain and a metal gate. The preparation process of the electrolyte layer includes the following steps: the gelling polymer, organic ionic liquid and solvent are mixed in a mass ratio of 1:2:5, and then dropped onto the gate and sandwich structure, and cured to form the electrolyte layer.

[0015] Furthermore, the gelling polymer is poly(vinylidene fluoride-co-hexafluoropropylene) or polymethyl methacrylate-polystyrene-polymethyl methacrylate block copolymer; The organic ionic liquid is 1-ethyl-3-methylimidazolium bis(trifluoromethanesulfonyl)imide, 1-butyl-3-methylimidazolium bis(trifluoromethanesulfonyl)imide, or 1-ethyl-3-methylimidazolium acetate; The solvent is N,N-dimethylformamide, acetonitrile, or acetone.

[0016] Compared with the prior art, the present invention has at least the following beneficial effects: The self-rectified non-volatile electrochemical memory of this invention employs a unique vertical sandwich structure. On one hand, it increases the channel depth-to-length ratio, flattens the potential distribution, and improves ion capacity, thereby achieving excellent non-volatile storage performance. On the other hand, the sandwich structure allows for the construction of a rectifier layer below the channel layer to achieve a unidirectional conduction mechanism similar to a pn junction, enabling the device to exhibit self-rectification behavior. This integrates non-volatile storage and rectification performance within a single device, achieving single-device integration of storage and self-rectification functions. Compared to traditional two-terminal memory devices (such as resistive random access memory and phase-change memory), it offers higher write accuracy, higher write linearity, significantly reduced randomness, and a greater number of effective storage states, enabling stable multi-analog state non-volatile storage. This device has a simple structure, low fabrication cost, and write accuracy and storage time comparable to current advanced three-terminal electrochemical memories, without requiring integration of the gate with other devices. Furthermore, the memory fabricated by this invention effectively suppresses bypass current crosstalk in cross-arrays without the need for additional series rectifier devices, effectively improving array integration and avoiding the increased process complexity caused by composite structures. These advantages enable the present invention to be efficiently adapted to the construction of high-performance in-memory computing hardware, especially suitable for artificial neural synapses as fully connected layers of neural networks and convolutional kernels of convolutional neural networks, providing reliable device support for performance breakthroughs in advanced artificial intelligence hardware.

[0017] Furthermore, the modification layer introduced between the rectifying layer and the channel layer, under optimized modification layer thickness and annealing conditions, can enhance interfacial bonding, effectively regulate interfacial energy levels, fill interfacial defects, and enhance self-rectification capability. Moreover, optimized channel annealing conditions can effectively increase the crystallinity of the channel layer, thereby raising the ion insertion / extraction barrier and enhancing non-volatile storage performance. Optimal channel layer and rectifying layer thicknesses can balance non-volatile storage performance and self-rectification performance. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of the self-rectified non-volatile electrochemical memory in Example 1 of the present invention; wherein, (a) is a front view and (b) is a top view; Figure 2 This is a flowchart of the fabrication process of the self-rectified non-volatile electrochemical memory of the present invention; wherein, (a) is the patterned deposition of source 2, (b) is the deposition of rectifier layer 3, (c) is the patterning of rectifier layer 3, (d) is the deposition of modification layer 4, (e) is the patterning of modification layer 4, (f) is the deposition of channel layer 5, (g) is the deposition of drain 6 and gate 7, (h) is the patterning of channel layer 5, and (i) is the deposition of electrolyte layer 8; Figure 3 This is a schematic diagram of the energy levels of the self-rectified non-volatile electrochemical memory in Example 1 of this invention; Figure 4The curves show the self-rectified output characteristics of the self-rectified non-volatile electrochemical memory in Example 1 of this invention; where (a) is the case where the vertical axis is logarithmic and (b) is the case where the vertical axis is linear. Figure 5 The images show the read performance of the self-rectified non-volatile electrochemical memory in Example 1 of this invention under forward read leakage voltage and reverse read leakage voltage, respectively. Figure 6 The curves show the state retention performance of the self-rectified non-volatile electrochemical memory in Example 1 of this invention in the high resistance state (HRS) and low resistance state (LRS), respectively; where (a) is the curve in the low resistance state and (b) is the curve in the high resistance state. Figure 7 This is the write / erase cycle stability curve (4096 storage states) of the self-rectifying non-volatile electrochemical memory of Example 1 in this invention. Figure 8 The linear relationship between the conductivity update amount and the write pulse width and write pulse amplitude of the self-rectified non-volatile electrochemical memory in Example 1 of the present invention is shown; wherein, (a) is the linear relationship between the conductivity update amount and the write pulse width, and (b) is the linear relationship between the conductivity update amount and the write pulse amplitude. Figure 9 This is a schematic diagram of the MNIST handwritten digit recognition task based on a two-layer fully connected neural network using a self-rectified non-volatile electrochemical memory in Embodiment 1 of the present invention; wherein, (a) is the sample preview of the MNIST dataset and the size of the training set and test set, (b) is the original image (28 pixels × 28 pixels) and the central cropped region (24 pixels × 24 pixels), (c) is the cropped and scaled feature image (16 pixels × 16 pixels), and (d) is the topology of the two-layer fully connected neural network; Figure 10 The comparison shows the classification accuracy and confusion matrix of the MNIST handwritten digit recognition task based on a two-layer fully connected neural network; where (a) is a comparison of classification accuracy under three conditions, (b) is the confusion matrix obtained by the memory cross array under the ideal condition of no crosstalk, (c) is the confusion matrix obtained by the cross array constructed using the self-rectified non-volatile electrochemical memory of the present invention, and (d) is the confusion matrix obtained by the cross array constructed using a memory without self-rectification capability. Detailed Implementation

[0019] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0020] See Figure 1 In (a) and (b), the present invention provides a non-volatile electrochemical memory with self-rectification characteristics, comprising a substrate 1, and a source electrode 2, a rectifying layer 3, a modification layer 4, a channel layer 5, a drain electrode 6, a gate electrode 7, and an electrolyte layer 8 disposed on the substrate 1; wherein the source electrode 2 is the bottom electrode, the drain electrode 6 is the top electrode, and the rectifying layer 3, the modification layer 4, and the channel layer 5 are sandwiched between the source electrode 2 and the drain electrode 6 from bottom to top, forming a sandwich structure, in which the source electrode 2 and the drain electrode 6 are arranged perpendicularly; the gate electrode 7 is disposed on one side of the sandwich structure, and a channel layer 5 is also disposed between the gate electrode 7 and the substrate 1; the electrolyte layer 8 covers the gate electrode 7 and the sandwich structure from top to bottom, and is in contact with the electrolyte layer 8, the gate electrode 7, and the sandwich structure, and fills the gap between the gate electrode 7 and the sandwich structure.

[0021] Preferably, substrate 1 can be a rigid substrate such as silicon dioxide or silicon, or a flexible substrate such as polyethylene terephthalate.

[0022] Preferably, the source electrode 2 is an indium tin oxide with a thickness of 40~200 nm and a linewidth of 100~200 μm.

[0023] Preferably, the gate 7 is a 60-100 nm thick polarizable electrode layer made of gold, platinum or tungsten, with a linewidth of 100-500 μm.

[0024] Preferably, the drain electrode 6 is a gold layer with a thickness of 60~100 nm and a linewidth of 300~500 μm.

[0025] Preferably, the rectifier layer 3 is a zinc oxide layer with a thickness of 100~200 nm, and its length and width are slightly larger than the linewidth of the source electrode 2.

[0026] The modification layer 4 is a 10-50 nm thick polyethyleneimine layer or an ethoxylated polyethyleneimine layer, with a length slightly greater than the length of the rectifier layer 3 and a width slightly greater than the width of the rectifier layer 3, so as to completely cover the rectifier layer 3.

[0027] Preferably, the channel length (i.e., the thickness of the channel layer 5) is 100~300 nm, the width is 300~500 μm, and the height is 300~500 μm, so as to completely cover the modification layer 4. The channel layer 5 material is a p-type organic semiconductor, including but not limited to P(g2T-T), P(g2T-TT), PTTBT, PTBT, or P(gBTTT).

[0028] See Figure 2In (a)-(i), a method for fabricating a self-rectifying non-volatile electrochemical memory according to the present invention includes the following steps: A patterned source electrode 2 is fabricated by depositing an indium tin oxide layer on a clean substrate 1 using a DC magnetron sputtering process. The rectifier layer 3 was prepared on the substrate 1 and the source electrode 2 using a sol-gel spin coating process. The rectifier layer 3 is patterned using an inert gas sputtering etching process; then, a modification layer 4 is prepared on the rectifier layer 3 using a solution spin coating process; the modification layer 4 is prepared on the rectifier layer 3 using a solution spin coating process, which is static coating, including: adding a branched polyethyleneimine solution or ethoxylated polyethyleneimine to an easily solvent ethylene glycol monomethyl ether or ethanol to obtain a branched polyethyleneimine solution or ethoxylated polyethyleneimine solution with a mass fraction of 0.5 wt%; dropping the branched polyethyleneimine solution or ethoxylated polyethyleneimine solution onto the substrate 1, and then rotating the substrate 1 at 3000~5000 rpm and continuously spinning and drying for 30 s.

[0029] The interfacial adhesion between the modification layer 4 and the rectification layer 3 is increased by an annealing process; the annealing process is annealing at 80°C for 20 minutes in a nitrogen atmosphere. The modification layer 4 was patterned using an inert gas sputtering etching process; The channel layer 5 was prepared on the modified layer 4 using a solution spin-coating process. Specifically, P(g2T-T) was dissolved in chloroform to obtain a P(g2T-T) solution with a concentration of 12–18 g / L; P(g2T-TT) was dissolved in chloroform to obtain a P(g2T-TT) solution with a concentration of 10–20 g / L; and PTTBT was dissolved in chloroform to obtain a PTTBT solution with a concentration of 5–10 g / L. The concentration of the solution was determined based on the molecular weight of P(g2T-T), P(g2T-TT), or PTTBT.

[0030] The channel layer 5 is prepared on the modification layer 4 by solution spin coating process. The process includes: dropping P(g2T-T) solution, P(g2T-TT) solution or PTTBT solution onto the substrate 1 which is rotating at 1000~4000 rpm and continuously spinning and drying for 20 s. The crystallinity of the channel layer 5 is further increased through an annealing process; the annealing process differs for different P-type organic semiconductors. When the P-type organic semiconductor used is P(g2T-T), annealing is carried out under a nitrogen atmosphere at a temperature of 120℃ for 60 min. The P-type organic semiconductor used is P(g2T-TT): annealing is carried out under a nitrogen atmosphere at a temperature of 160℃ for 30 min; When PTTBT is used as the P-type organic semiconductor, annealing is carried out under a nitrogen atmosphere at a temperature of 180°C for 45 minutes. Then, a metal drain 6 and a metal gate 7 are fabricated on the channel layer 5 using a vacuum evaporation deposition process; Using the metal drain 6 and the metal gate 7 as hard masks, the channel layer 5 is patterned by an inert gas sputtering etching process to separate the gate 7 and the sandwich structure. An electrolyte layer 8 is fabricated on the sandwich structure and the gate 7, and the gap between the gate 7 and the sandwich structure is also filled by the electrolyte layer 8, thus completing the fabrication of the self-rectified non-volatile electrochemical memory.

[0031] Preferably, the DC magnetron sputtering process is performed at a vacuum level below 5 × 10⁻⁶. -4 The process was carried out under a mixed gas atmosphere of argon and oxygen in a volume ratio of 9:1 at Pa. The DC sputtering power used was 90~120 W. A target material with a molar ratio of indium oxide and tin dioxide of 9:1 was used. A 40~200 nm thick indium tin oxide source electrode 2 was deposited on substrate 1 using a stainless steel mask. The linewidth was 100~200 μm, and the resistivity was controlled at 3×10⁻⁶. -4 Below Ω·cm.

[0032] Preferably, the sol-gel spin coating process includes the following steps: Zinc acetate and 2-hydroxyethylamine were mixed at a mass ratio of 3:1 to obtain a mixture. 1.2g of the mixture was dissolved in 10ml of ethylene glycol monomethyl ether and stirred at room temperature for 12h to prepare a zinc oxide precursor solution. The zinc oxide precursor solution was then dropped onto substrate 1, and substrate 1 was rotated at 2000~5000 rpm and continuously spun dry for 30s. The mixture was then reacted in air at 180~220℃ for 60min to form a film, thus obtaining the rectifying layer 3.

[0033] Preferably, the inert gas sputtering etching process uses a stainless steel mask or directly uses the top metal gate 7 and metal drain 6 as a hard mask for etching, and uses argon gas for etching, with a power of 60~120 W and a time of 120~300 s.

[0034] Preferably, the vacuum evaporation deposition process is performed at a vacuum level below 6 × 10⁻⁶. -4 Inside the cavity of Pa, a stainless steel mask is used for patterning with a linewidth of 300~500 μm. The output power is adjusted to control the deposition rate at 0.1~0.2 nm / s to deposit a film with a thickness of 60~100 nm, forming a metal drain 6 and a metal gate 7.

[0035] Preferably, the preparation process of the electrolyte layer 8 includes the following steps: The gelling polymer, organic ionic liquid and solvent are mixed in a mass ratio of 1:2:5; then the mixture is precisely applied to the gate 7 and the sandwich structure using a dispensing machine to ensure coverage and gap filling; then it is placed in a vacuum chamber for 60 min to allow the solvent to evaporate and solidify, forming the electrolyte layer 8.

[0036] The gelling polymers include poly(vinylidene fluoride-co-hexafluoropropylene) and polymethyl methacrylate-polystyrene-polymethyl methacrylate block copolymers.

[0037] The organic ionic liquid comprises 1-ethyl-3-methylimidazolium bis(trifluoromethanesulfonyl)imide, 1-butyl-3-methylimidazolium bis(trifluoromethanesulfonyl)imide, and 1-ethyl-3-methylimidazolium acetate.

[0038] The solvents include N,N-dimethylformamide, acetonitrile, and acetone.

[0039] The following are specific examples.

[0040] Example 1 The present invention discloses a method for fabricating a self-rectified non-volatile electrochemical memory, comprising the following steps: Step 1, Cleaning the silicon dioxide hard substrate: Place the substrate 1 in deionized water for ultrasonic cleaning for 45 min, then place it in acetone and ethanol for ultrasonic cleaning for 60 min each. After taking it out, blow it dry with nitrogen gas, and then place it in an ultraviolet-ozone cleaning device for 30 minutes of surface cleaning treatment.

[0041] Step 2, Depositing Indium Tin Oxide Source 2: Place the clean substrate 1 into a stainless steel mask, and then place it under a vacuum of less than 5 × 10⁻⁶. -4 In the chamber of Pa, a mixture of argon and oxygen in a volume ratio of 9:1 was introduced. A target material with an indium oxide and tin dioxide molar ratio of 9:1 was bombarded with a DC sputtering plasma of 100 W. A 200 nm thick indium tin oxide layer was deposited using DC magnetron sputtering, with the resistivity controlled at 3 × 10⁻⁶. -4 Below Ω·cm.

[0042] Step 3: Prepare zinc oxide rectifying layer 3 on substrate 1 and source electrode 2 using sol-gel spin coating process: Zinc acetate and 2-hydroxyethylamine are mixed at a mass ratio of 3:1 to obtain a mixture. Take 1.2g of the mixture and dissolve it in 10 ml of ethylene glycol monomethyl ether. Stir at room temperature for 12h to prepare a precursor solution for later use. Drop the precursor solution onto substrate 1, and then rotate substrate 1 at 4000 rpm and continue to spin dry for 30s. React in air at 200℃ for 60 min to form a uniform film, forming rectifying layer 3.

[0043] Step 4, Patterning of rectifier layer 3: Place the substrate 1 with rectifier layer 3 deposited on it into a stainless steel mask, and then place it under a vacuum of less than 6×10⁻⁶. -4 Argon gas was introduced into the chamber of Pa at a flow rate of 20 sccm, and etching was performed at a power of 100W for 270s.

[0044] Step 5, Deposition of modified layer 4: Branched polyethyleneimine is added to ethylene glycol monomethyl ether and stirred for 12 h to prepare a branched polyethyleneimine solution with a mass fraction of 0.5 wt% for later use; the prepared branched polyethyleneimine solution is dropped onto substrate 1, and substrate 1 is rotated at 5000 rpm and continuously rotated and spun dry for 30 s; annealing is carried out at 80 °C for 20 min in a nitrogen atmosphere.

[0045] Step 6, Patterning of the modification layer 4: Place the substrate 1, as completed in step 5, into a stainless steel mask, and then place it under a vacuum of less than 6×10⁻⁶. -4 Argon gas was introduced into the chamber of Pa at a flow rate of 20 sccm, and etching was performed at a power of 80W for 120s.

[0046] Step 7, Deposition of channel layer 5: Dissolve P(g2T-TT) in chloroform and stir for 12 hours to obtain a P-type organic semiconductor solution with a concentration of 15 g / L for later use; determine the concentration based on the molecular weight.

[0047] Step 8, Deposit gate 7 and drain 6: Place the substrate 1 after step 7 into a stainless steel mask, and then place it under a vacuum of less than 6 × 10⁻⁶. -4 In the chamber of Pa, the output power is controlled to deposit an 80 nm thick gold film at a rate of 0.1 nm / s to form the drain 6 and the gate 7.

[0048] Step 9, Patterning of Channel Layer 5: The substrate 1, after step 8, is directly placed in a vacuum with a vacuum level below 6×10⁻⁶. -4 In the chamber of Pa, using gate 7 and drain 6 as hard masks, argon gas is introduced at a flow rate of 20 sccm and etched for 120s at a power of 80W.

[0049] Step 10, Preparation of Electrolyte Layer 8: The gelling polymer, organic ionic liquid, and solvent are mixed sequentially at a mass ratio of 1:2:5; the mixture is precisely applied to the gate 7 and the sandwich structure using a dispensing machine to ensure coverage and gap filling; the mixture is then placed in a vacuum chamber for 60 min to allow the solvent to evaporate and solidify, resulting in electrolyte layer 8. The gelling polymer is poly(vinylidene fluoride-co-hexafluoropropylene). The organic ionic liquid is 1-ethyl-3-methylimidazolium bis(trifluoromethanesulfonyl)imide. The solvent is acetone.

[0050] from Figure 4As can be seen from (a) and (b), the self-rectified non-volatile electrochemical memory prepared by the present invention can read the drain current under the forward drain voltage, and the current under the reverse drain voltage is greatly suppressed, thus possessing unidirectional conduction capability, i.e., self-rectification performance, with a channel self-rectification ratio >1000.

[0051] from Figure 5 It can be seen that the self-rectified non-volatile electrochemical memory prepared by the present invention can read out the currently stored conductance state under the forward drain voltage, and the interference current under the reverse drain voltage is greatly suppressed.

[0052] from Figure 6 As can be seen from (a) and (b), the self-rectified non-volatile electrochemical memory prepared by the present invention has good storage state retention capability in both low-resistivity and high-resistivity states, and the conductivity drift coefficient γ < 0.002.

[0053] from Figure 7 It can be seen that the self-rectified non-volatile electrochemical memory prepared by the present invention can achieve precise and linear writing with a nonlinearity of <0.1 and a writing accuracy (ΔG / σ)2>200; it has a high number of storage states, capable of storing at least 4096 states; and it exhibits good cyclic write and erase stability, withstanding more than 200,000 write and erase operations without significant performance degradation.

[0054] from Figure 8 As can be seen from (a) and (b), the single conductivity update of the self-rectified non-volatile electrochemical memory prepared by the present invention has a good linear relationship with the pulse width and pulse amplitude, which facilitates precise conductivity modulation.

[0055] To illustrate the improvement effect of the self-rectifying characteristics of the self-rectifying non-volatile electrochemical memory of this invention on the accuracy degradation of neural networks caused by bypass current crosstalk in cross-arrays, a handwritten digit recognition task was constructed using the MNIST (Mixed National Institute of Standards and Technology) dataset for relevant evaluation. Figure 9As shown in (a)-(d), the MNIST dataset consists of 70,000 handwritten digit images of 28 pixels × 28 pixels, of which 60,000 constitute the training set and 10,000 constitute the test set. Each image sample in the dataset undergoes a preprocessing procedure: center-cropping to 24 pixels × 24 pixels, scaling to 16 pixels × 16 pixels, and flattening into a 256-dimensional input vector. The network architecture used is a two-layer fully connected neural network with 256 input nodes, a single hidden layer with 20 nodes, and 10 output nodes; the output of the first layer is activated using a linear rectified function, and cross-entropy is used as the loss function. Training is first performed on a computer: the batch size of the training set is 64, the optimizer is the Adam optimizer, the learning rate is 0.001, and training is conducted for 30 epochs until the loss function converges, yielding the parameter matrix. The parameter matrices were then downloaded into three simulated memory cross-arrays built using SPICE (Simulation Program with Integrated Circuit Emphasis) software. The size of each cross-array matched the size of the parameter matrix. The three simulated cross-arrays were: a memory cross-array under ideal conditions with no crosstalk, a cross-array built using the self-rectifying non-volatile electrochemical memory of this invention, and a cross-array built using a memory without self-rectification capability. Finally, the classification performance was evaluated on the test set to obtain the corresponding classification accuracy and confusion matrix. Figure 10 The classification results shown in (a)-(d) demonstrate that the self-rectified non-volatile electrochemical memory of the present invention can effectively suppress the bypass current crosstalk effect in the constructed cross array through its self-rectification performance, thereby significantly reducing the decrease in the computational accuracy of the neural network.

[0056] Example 2 The present invention discloses a method for fabricating a self-rectified non-volatile electrochemical memory, comprising the following steps: Step 1, Cleaning the silicon dioxide substrate: Place the substrate 1 in deionized water for ultrasonic cleaning for 45 min, then place it in acetone and ethanol for ultrasonic cleaning for 60 min each. After taking it out, blow it dry with nitrogen gas, and then place it in an ultraviolet-ozone cleaning device for 30 minutes of surface cleaning treatment.

[0057] Step 2, Depositing Indium Tin Oxide Source 2: Place the clean substrate 1 into a stainless steel mask, and then place it under a vacuum of less than 5 × 10⁻⁶. -4 In the chamber of Pa, a mixture of argon and oxygen in a volume ratio of 9:1 was introduced. A target material with an indium oxide and tin dioxide molar ratio of 9:1 was bombarded with a DC sputtering plasma of 90 W. A 40 nm thick indium tin oxide layer was deposited using DC magnetron sputtering, with the resistivity controlled at 3 × 10⁻⁶. -4 Below Ω·cm.

[0058] Step 3: Prepare zinc oxide rectifying layer 3 on substrate 1 and source electrode 2 using sol-gel spin coating process: Zinc acetate and 2-hydroxyethylamine are mixed at a mass ratio of 3:1 to obtain a mixture. Take 1.2g of the mixture and dissolve it in 10 ml of ethylene glycol monomethyl ether to prepare a precursor solution. Stir at room temperature for 12h for later use. Drop the precursor solution onto substrate 1, then rotate substrate 1 at 3000 rpm and continue to spin dry for 30s. React in air at 180℃ for 60 min to form a uniform film, forming rectifying layer 3.

[0059] Step 4, Patterning of rectifier layer 3: Place the substrate 1 with rectifier layer 3 deposited on it into a stainless steel mask, and then place it under a vacuum of less than 6×10⁻⁶. -4 Argon gas was introduced into the chamber of Pa at a flow rate of 20 sccm, and etching was performed at a power of 120W for 240s.

[0060] Step 5, Deposition of modified layer 4: Prepare a 0.5 wt% ethoxylated polyethyleneimine solution using ethylene glycol monomethyl ether as solvent, stir for 12 h, and set aside; add the prepared ethoxylated polyethyleneimine solution dropwise onto substrate 1, then rotate substrate 1 at 5000 rpm and continue to spin dry for 30 s; anneal at 80 °C for 20 min in a nitrogen atmosphere.

[0061] Step 6, Patterning of the modification layer 4: Place the substrate 1, as completed in step 5, into a stainless steel mask, and then place it under a vacuum of less than 6×10⁻⁶. -4 Argon gas was introduced into the chamber of Pa at a flow rate of 20 sccm, and etching was performed at a power of 90W for 180s.

[0062] Step 7, Deposition of channel layer 5: Dissolve P(g2T-TT) in chloroform and stir for 12 h to obtain a polymer semiconductor solution with a concentration of 10 g / l for later use; The polymer semiconductor solution was dropped onto substrate 1, which was rotating at 1000 rpm, and spun dry for 20 s; then annealed at 160 °C for 30 min in a nitrogen atmosphere.

[0063] Step 8, Deposit gate 7 and drain 6: Place the substrate 1 after step 7 into a stainless steel mask, and then place it under a vacuum of less than 6 × 10⁻⁶. -4 In the chamber of Pa, a 60 nm thick gold film is deposited at a rate of 0.1 nm / s to form the drain 6 and the gate 7.

[0064] Step 9, Patterning of Channel Layer 5: The substrate 1, after step 8, is directly placed in a vacuum with a vacuum level below 6×10⁻⁶. -4In the chamber of Pa, using gate 7 and drain 6 as hard masks, argon gas is introduced at a flow rate of 20 sccm and etched for 180s at a power of 80W.

[0065] Step 10, Preparation of Electrolyte Layer 8: The gelling polymer, organic ionic liquid, and solvent are mixed sequentially at a mass ratio of 1:2:5; the mixture is precisely applied to the gate 7 and the sandwich structure using a dispensing machine to ensure coverage and gap filling; the mixture is then placed in a vacuum chamber for 60 min to allow the solvent to evaporate and solidify, resulting in electrolyte layer 8. The gelling polymer is poly(vinylidene fluoride-co-hexafluoropropylene). The organic ionic liquid is 1-ethyl-3-methylimidazolium bis(trifluoromethanesulfonyl)imide. The solvent is N,N-dimethylformamide.

[0066] Example 3 The present invention discloses a method for fabricating a self-rectified non-volatile electrochemical memory, comprising the following steps: Step 1, cleaning the silicon substrate: Place the substrate 1 in deionized water for ultrasonic cleaning for 45 min, then place it in acetone and ethanol for ultrasonic cleaning for 60 min each. After taking it out, blow it dry with nitrogen gas, and then place it in an ultraviolet-ozone cleaning device for 30 minutes of surface cleaning treatment.

[0067] Step 2, Depositing Indium Tin Oxide Source 2: Place the clean substrate 1 into a stainless steel mask, and then place it under a vacuum of less than 5 × 10⁻⁶. -4 In the chamber of Pa, a mixture of argon and oxygen in a volume ratio of 9:1 was introduced. A target material with an indium oxide and tin dioxide molar ratio of 9:1 was bombarded with a DC sputtering plasma of 120 W. A 200 nm thick indium tin oxide layer was deposited using DC magnetron sputtering, with the resistivity controlled at 3 × 10⁻⁶. -4 Below Ω·cm.

[0068] Step 3: Prepare zinc oxide rectifying layer 3 on substrate 1 and source electrode 2 using sol-gel spin coating process: Zinc acetate and 2-hydroxyethylamine are mixed at a mass ratio of 3:1 to obtain a mixture. Take 1.2g of the mixture and dissolve it in 10 ml of ethylene glycol monomethyl ether to prepare a precursor solution. Stir at room temperature for 12h for later use. Drop the precursor solution onto substrate 1, then rotate substrate 1 at 5000 rpm and continue to spin dry for 30s. React in air at 200℃ for 60 min to form a uniform film, forming rectifying layer 3.

[0069] Step 4, Patterning of rectifier layer 3: Place the substrate 1 with rectifier layer 3 deposited on it into a stainless steel mask, and then place it under a vacuum of less than 6×10⁻⁶. -4 Argon gas was introduced into the chamber of Pa at a flow rate of 20 sccm, and etching was performed at a power of 100W for 300s.

[0070] Step 5, Deposition of modified layer 4: Prepare a branched polyethyleneimine solution with a mass fraction of 0.5 wt%, stir for 12 h, and set aside; drop the prepared branched polyethyleneimine solution onto substrate 1, then rotate substrate 1 at 3000 rpm and continue to spin dry for 30 s; anneal at 80 °C for 20 min in a nitrogen atmosphere.

[0071] Step 6, Patterning of the modification layer 4: Place the substrate 1, as completed in step 5, into a stainless steel mask, and then place it under a vacuum of less than 6×10⁻⁶. -4 Argon gas was introduced into the chamber of Pa at a flow rate of 20 sccm, and etching was performed at a power of 60W for 140s.

[0072] Step 7, Deposition of channel layer 5: Dissolve PTTBT in chloroform and stir for 12 hours to obtain a polymer semiconductor solution with a concentration of 10 g / L, for later use; The polymer semiconductor solution was dropped onto substrate 1, which was rotating at 3000 rpm, and spun dry for 20 s; then annealed at 180°C for 45 min in a nitrogen atmosphere.

[0073] Step 8, Deposit gate 7 and drain 6: Place the substrate 1 after step 7 into a stainless steel mask, and then place it under a vacuum of less than 6 × 10⁻⁶. -4 In the chamber of Pa, a 100 nm thick gold film is deposited at a rate of 0.2 nm / s to form the drain 6 and the gate 7, while controlling the output power.

[0074] Step 9, Patterning of Channel Layer 5: The substrate 1, after step 8, is directly placed in a vacuum with a vacuum level below 6×10⁻⁶. -4 In the chamber of Pa, using gate 7 and drain 6 as hard masks, argon gas is introduced at a flow rate of 20 sccm and etched for 140s at a power of 90W.

[0075] Step 10, Preparation of Electrolyte Layer 8: The gelling polymer, organic ionic liquid, and solvent are mixed sequentially at a mass ratio of 1:2:5; the mixture is precisely applied to the gate 7 and the sandwich structure using a dispensing machine to ensure coverage and gap filling; the mixture is then placed in a vacuum chamber for 60 min to allow the solvent to evaporate and solidify, resulting in electrolyte layer 8. The gelling polymer is a polymethyl methacrylate-polystyrene-polymethyl methacrylate block copolymer. The organic ionic liquid is 1-butyl-3-methylimidazolium bis(trifluoromethanesulfonyl)imide. The solvent is acetonitrile.

[0076] Example 4 The present invention discloses a method for fabricating a self-rectified non-volatile electrochemical memory, comprising the following steps: Step 1, Cleaning the polyethylene terephthalate substrate: Place the substrate 1 in deionized water for ultrasonic cleaning for 45 minutes, then place it in acetone and ethanol for ultrasonic cleaning for 60 minutes each. After taking it out, blow it dry with nitrogen gas, and then place it in an ultraviolet-ozone cleaning device for 30 minutes of surface cleaning treatment.

[0077] Step 2, Depositing Indium Tin Oxide Source 2: Place the clean substrate 1 into a stainless steel mask, and then place it under a vacuum of less than 5 × 10⁻⁶. -4 In the chamber of Pa, a mixture of argon and oxygen in a volume ratio of 9:1 was introduced. A target material with an indium oxide and tin dioxide molar ratio of 9:1 was bombarded with a DC sputtering plasma of 100 W. A 100 nm thick indium tin oxide layer was deposited using DC magnetron sputtering, with the resistivity controlled at 3 × 10⁻⁶. -4 Below Ω·cm.

[0078] Step 3: Prepare zinc oxide rectifier layer 3 on substrate 1 and source electrode 2 using sol-gel spin coating process: Zinc acetate and 2-hydroxyethylamine are mixed at a mass ratio of 3:1 to obtain a mixture. Take 1.2g of the mixture and dissolve it in 10 ml of ethylene glycol monomethyl ether to prepare a precursor solution. Stir at room temperature for 12h for later use. Drop the precursor solution onto substrate 1, then rotate substrate 1 at 4000 rpm and continue to spin dry for 30s. React in air at 220℃ for 60 min to form a uniform film, forming rectifier layer 3.

[0079] Step 4, Patterning of rectifier layer 3: Place the substrate 1 with rectifier layer 3 deposited on it into a stainless steel mask, and then place it under a vacuum of less than 6×10⁻⁶. -4 Argon gas was introduced into the chamber of Pa at a flow rate of 20 sccm, and etching was performed at a power of 110W for 260s.

[0080] Step 5, Deposition of modified layer 4: Prepare a branched polyethyleneimine solution with a mass fraction of 0.5 wt%, stir for 12 h, and set aside; drop the prepared branched polyethyleneimine solution onto substrate 1, then rotate substrate 1 at 4000 rpm and continue to spin dry for 30 s; anneal at 80 °C for 20 min in a nitrogen atmosphere.

[0081] Step 6, Patterning of the modification layer 4: Place the substrate 1, as completed in step 5, into a stainless steel mask, and then place it under a vacuum of less than 6×10⁻⁶. -4 Argon gas was introduced into the chamber of Pa at a flow rate of 20 sccm, and etching was performed at a power of 100W for 120s.

[0082] Step 7, Deposition of channel layer 5: Dissolve P(g2T-T) in chloroform and stir for 12 h to obtain a polymer semiconductor solution with a concentration of 12 g / l for later use; The polymer semiconductor solution was dropped onto substrate 1, which was rotating at 4000 rpm, and spun dry for 20 s; then annealed at 120°C for 60 min in a nitrogen atmosphere.

[0083] Step 8, Deposit gate 7 and drain 6: Place the substrate 1 after step 7 into a stainless steel mask, and then place it under a vacuum of less than 6 × 10⁻⁶. -4 In the chamber of Pa, a 90 nm thick gold film is deposited at a rate of 0.1 nm / s to form the drain 6 and the gate 7.

[0084] Step 9, Patterning of Channel Layer 5: The substrate 1, after step 8, is directly placed in a vacuum with a vacuum level below 6×10⁻⁶. -4 In the chamber of Pa, using gate 7 and drain 6 as hard masks, argon gas is introduced at a flow rate of 20 sccm, and etching is performed at a power of 100W for 120s.

[0085] Step 10, Preparation of Electrolyte Layer 8: The gelling polymer, organic ionic liquid, and solvent are mixed sequentially at a mass ratio of 1:2:5; the mixture is precisely applied to the gate 7 and the sandwich structure using a dispensing machine to ensure coverage and gap filling; the mixture is then placed in a vacuum chamber for 60 min to allow the solvent to evaporate and solidify, resulting in electrolyte layer 8. The gelling polymer is poly(vinylidene fluoride-co-hexafluoropropylene). The organic ionic liquid is 1-ethyl-3-methylimidazolium acetate. The solvent is acetone.

[0086] The programming and reading methods for the self-rectifying non-volatile electrochemical memory provided by this invention are as follows: An amplitude of 7 is applied to gate 7 2.4 ~ A single voltage pulse to ground with an amplitude of 0.75 V and a width of 1~100 ms or a voltage pulse with an amplitude of 1.2 ~ A single ground current pulse of 0.1 μA with a width of 1–100 ms can increase the device's conductivity, i.e., perform a "write" operation; applying a single ground voltage pulse of 1–2.6 V with a width of 1–100 ms or a single ground current pulse of 0.12–1.2 μA with a width of 1–100 ms to gate 7 can decrease the device's conductivity, i.e., perform an "erase" operation.

[0087] During reading, source 2 is grounded, and gate 7 can be disconnected or grounded. A read voltage of 0.1~0.5V to ground is applied to drain 6, and the source-drain current is measured simultaneously. The quotient of the source-drain current divided by the read voltage is the current stored conductance value of the device.

[0088] The working mechanism of the self-rectified non-volatile electrochemical memory provided in this invention is as follows: Non-volatile storage mechanism: When the applied pulse exceeds the threshold, ions in the solid electrolyte electromigrate and insert into the polymer crystalline phase region; after the gate voltage is removed, non-volatility is guaranteed by two conditions: first, the crystalline polymer chain segments are regular and compact, and the strong interaction between them and the ions raises the insertion / extraction barrier; second, the channel depth-to-length ratio is extremely large, making the channel potential distribution flat and the reverse electric field weak, which inhibits ion insertion / extraction and achieves non-volatile storage.

[0089] Self-rectification mechanism: Rectification behavior originates from the unidirectional conduction mechanism of a pn-junction-like structure formed by interface band alignment. The polyethyleneimine-modified zinc oxide surface forms a matched interface with the p-type polymer channel surface. Due to the Fermi level difference, a built-in electric field is generated from the n-type rectifier layer towards the p-type channel. See [link to relevant documentation]. Figure 3 When forward biased, the p-type side is connected to a positive voltage and the n-type side is grounded. The external electric field weakens the built-in electric field, lowering the barrier for p-type majority carrier holes to migrate to the cathode and electrons to migrate to the anode, allowing charge carriers to pass through smoothly. When reverse biased, the external and built-in electric fields are superimposed and enhanced, significantly raising the interface barrier, hindering majority carrier migration, minimizing minority carrier injection, and suppressing current. This unidirectional conduction characteristic that varies with the bias direction causes the device to exhibit rectification behavior.

[0090] The performance indicators and characteristics of a single self-rectified non-volatile electrochemical memory in this invention are as follows: Channel self-rectification ratio >10 3 Under forward read leakage voltage, the current storage state can be read normally, while under reverse read leakage voltage, the reverse interference current is significantly suppressed; the number of stored conductance states is >4096; the conductance modulation range is >100 times; the non-volatile storage time is >1000 s; the conductance drift coefficient γ <0.002, (t / t0). γ =R t / R0, R0 and R t These are the resistance values ​​at time t0 and time t, respectively; linear writing can be achieved using gate voltage pulses, with a non-linearity of <0.1 and a writing accuracy of (ΔG / σ). 2 >200, where ΔG is the mean of a single conductance update and σ is its corresponding standard deviation; the single conductance update has a good linear relationship with both pulse width and pulse amplitude, facilitating precise conductance modulation; it can withstand at least 200,000 write and erase operations without significant performance degradation; in the array simulation of the MNIST handwritten digit recognition task, it effectively alleviates the problem of decreased classification accuracy caused by crosstalk.

[0091] The above description is merely a preferred embodiment of the present invention and is not intended to limit the technical solution of the present invention in any way. Those skilled in the art should understand that, without departing from the spirit and principles of the present invention, the technical solution can be modified and replaced in several simple ways, and these modifications and replacements are all within the scope of protection covered by the claims.

Claims

1. A non-volatile electrochemical memory with self-rectifying characteristics, characterized in that, It includes a substrate (1), and a source electrode (2), a rectifier layer (3), a modification layer (4), a channel layer (5), a drain electrode (6), a gate electrode (7), and an electrolyte layer (8) disposed on the substrate (1). Among them, the source (2) is the bottom electrode and the drain (6) is the top electrode. A rectifier layer (3), a decoration layer (4) and a channel layer (5) are arranged sequentially from bottom to top between the source (2) and the drain (6). The source (2), the rectifier layer (3), the decoration layer (4), the channel layer (5) and the drain (6) form a sandwich structure. The source (2) and the drain (6) are arranged vertically in the sandwich structure. The gate (7) is arranged on one side of the sandwich structure. A channel layer (5) is arranged between the gate (7) and the substrate (1). The electrolyte layer (8) covers the gate (7) and the sandwich structure from top to bottom and fills the gap between the gate (7) and the sandwich structure.

2. The non-volatile electrochemical memory with self-rectifying characteristics according to claim 1, characterized in that, The substrate (1) is silicon dioxide, silicon or polyethylene terephthalate; The source electrode (2) is an indium tin oxide layer with a thickness of 40~200 nm; The rectifier layer (3) is a zinc oxide layer with a thickness of 100~200 nm.

3. The non-volatile electrochemical memory with self-rectifying characteristics according to claim 1, characterized in that, The modification layer (4) is a polyethyleneimine layer or an ethoxylated polyethyleneimine layer with a thickness of 10~50 nm; The channel layer (5) has a thickness of 100~300 nm, a width of 300~500 μm, and a height of 300~500 μm; the channel layer (5) is made of P-type organic semiconductor.

4. The non-volatile electrochemical memory with self-rectifying characteristics according to claim 3, characterized in that, The drain electrode (6) is a gold layer with a thickness of 60~100 nm; The gate (7) is a gold layer with a thickness of 60~100 nm; P-type organic semiconductors include P(g2T-T), P(g2T-TT), PTTBT, PTBT, or P(gBTTT).

5. A method for fabricating a self-rectifying non-volatile electrochemical memory as described in any one of claims 1-4, characterized in that, Includes the following steps: An indium tin oxide layer is deposited on the substrate (1) using a DC magnetron sputtering process to prepare a patterned source electrode (2); then a rectifier layer (3) is prepared on the substrate (1) and the source electrode (2) using a sol-gel spin coating process; after patterning the rectifier layer (3), a modification layer (4) is prepared on the rectifier layer (3) using a solution spin coating process; after a first annealing, the modification layer (4) is patterned; a channel layer (5) is prepared on the modification layer (4) using a solution spin coating process; after a second annealing, a metal drain electrode (6) and a metal gate electrode (7) are prepared on the channel layer (5) using a vacuum evaporation deposition process; the channel layer (5) is patterned; finally, an electrolyte layer (8) is prepared on the sandwich structure and the gate electrode (7), and the gap between the gate electrode (7) and the sandwich structure is filled with the electrolyte layer (8).

6. The method for fabricating a self-rectifying non-volatile electrochemical memory according to claim 5, characterized in that, The annealing conditions for one annealing step are: annealing at 80°C for 20 minutes in a nitrogen atmosphere; The secondary annealing conditions are as follows: when the material of the channel layer (5) is p(g2T-T), annealing is carried out in a nitrogen atmosphere, the annealing temperature is 120℃ and the time is 60 min; When the material of the channel layer (5) is P(g2T-TT), it is annealed in a nitrogen atmosphere at a temperature of 160℃ for 30 min. When the material of the channel layer (5) is PTTBT, it is annealed in a nitrogen atmosphere at a temperature of 180°C for 45 minutes.

7. The method for fabricating a self-rectifying non-volatile electrochemical memory according to claim 5, characterized in that, The conditions for patterning the rectifier layer (3), the decoration layer (4), and the channel layer (5) are: etching with argon gas, power of 60~120 W, and time of 120~300 s; A patterned source electrode (2) is fabricated by depositing an indium tin oxide layer on a substrate (1) using a DC magnetron sputtering process, including: in a vacuum degree lower than 5×10 -4 At Pa, a mixed gas of argon and oxygen in a volume ratio of 9:1 is introduced, the DC sputtering power is 90~120 W, the target material of indium oxide and tin dioxide in a molar ratio of 9:1 is used, and a source electrode (2) with a thickness of 40~200 nm is deposited on the substrate (1) using a stainless steel mask.

8. The method for fabricating a self-rectified non-volatile electrochemical memory according to claim 5, characterized in that, The preparation of the rectifier layer (3) on the substrate (1) and the source electrode (2) by sol-gel spin coating includes: mixing zinc acetate and 2-hydroxyethylamine at a mass ratio of 3:1 to obtain a mixture; dissolving 1.2g of the mixture in 10ml of ethylene glycol monomethyl ether to prepare a zinc oxide precursor solution; then dropping the zinc oxide precursor solution onto the substrate (1), rotating the substrate (1) at 2000~5000 rpm, and continuously spinning and drying for 30s; then reacting at 180~220℃ for 60 min to obtain the rectifier layer (3). The preparation of the modification layer (4) on the rectifier layer (3) by solution spin coating includes: dropping a branched polyethyleneimine solution onto the substrate (1), then rotating the substrate (1) at 3000~5000 rpm and continuously spinning and drying for 30 s; The preparation of the channel layer (5) on the modification layer (4) by solution spin coating includes: dissolving P(g2T-T) in chloroform to obtain a P(g2T-T) solution with a concentration of 12~18 g / l; dissolving P(g2T-TT) in chloroform to obtain a P(g2T-TT) solution with a concentration of 10~20 g / l; dissolving PTTBT in chloroform to obtain a PTTBT solution with a concentration of 5~10 g / l; dropping the P(g2T-T) solution, P(g2T-TT) solution or PTTBT solution onto the substrate (1) rotating at 1000~4000 rpm, and continuously spinning and drying for 20s.

9. The method for fabricating a self-rectified non-volatile electrochemical memory according to claim 5, characterized in that, A metal drain (6) and a metal gate (7) are fabricated on the channel layer (5) using a vacuum evaporation deposition process, including: in a vacuum degree lower than 6×10 -4 In the cavity of Pa, a stainless steel mask is used for patterning with a linewidth of 300~500 μm. A film with a thickness of 60~100 nm is deposited at a rate of 0.1~0.2 nm / s to form a metal drain (6) and a metal gate (7). The preparation process of the electrolyte layer (8) includes the following steps: the gelling polymer, organic ionic liquid and solvent are mixed in a mass ratio of 1:2:5, and then dropped onto the gate (7) and sandwich structure, and cured to form the electrolyte layer (8).

10. The method for fabricating a self-rectified non-volatile electrochemical memory according to claim 9, characterized in that, The gelling polymer is poly(vinylidene fluoride-co-hexafluoropropylene) or polymethyl methacrylate-polystyrene-polymethyl methacrylate block copolymer; The organic ionic liquid is 1-ethyl-3-methylimidazolium bis(trifluoromethanesulfonyl)imide, 1-butyl-3-methylimidazolium bis(trifluoromethanesulfonyl)imide, or 1-ethyl-3-methylimidazolium acetate; The solvent is N,N-dimethylformamide, acetonitrile, or acetone.

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