Data processing assembly and computer processor

Abstract

A data processing component includes a fault attack shielding and detection arrangement. Specifically, the data processing component comprises: a first layer comprising: a first data processing element configured to receive a control input and perform a predetermined operation on the control input to generate a control output; and a first comparator configured to compare the control output with an expected control output and generate a fault condition signal if the control output is different from the expected control output; and a second layer including a second data processing element identical to the first data processing element, configured to receive the first operation input and perform an identical predetermined operation on the first operation input to generate a first operation output. A computer processor may include the data processing component.

Description

Technical Field

[0001] The present invention relates to a data processing component including fault attack detection and shielding arrangement, and a computer processor including the data processing component. Background Technology

[0002] Moore's Law states that the number of transistors in an integrated circuit roughly doubles every two years. This is due to advancements in the semiconductor industry that have enabled the miniaturization of technologies used in integrated circuits. One development that has allowed for this miniaturization of integrated circuit components is the adoption of 3D packaging methods.

[0003] This method allows different chiplets or functional layers to be stacked within the same chip package, thus utilizing a third dimension, unlike traditional methods. This approach allows chip manufacturers to significantly increase the number of transistors per unit surface area, and therefore also the number of transistors per chip.

[0004] Vertical 3D die stacking (e.g., monolithic 3D chips) can employ hybrid bonding (wafer-to-wafer or wafer-to-die) and can provide a higher level of integration. This approach has been adopted by Intel®, which has announced a goal of achieving one trillion transistors on a single chip by 2030.

[0005] This application relates to protection against fault attacks, specifically against fault attacks that rely on applying electromagnetic radiation (typically laser) to components of a chip or other data processing components. In a fault attack, electromagnetic radiation is directed to the chip or a specific component to disrupt its operation, thereby causing a malfunction. The purpose of such actions is to prevent the chip or its components from performing their intended function or to introduce errors in the processing performed by the chip or component.

[0006] Known techniques for protecting data processing components, such as chips, from fault-finding attacks typically rely on detecting such attacks and making downstream processing decisions based on the detection. The most vulnerable parts of data processing components are those performing sensitive or critical operations, such as components processing security-critical information or implementing internal protection mechanisms. These are precisely the components most likely to be compromised by malicious actors.

[0007] Therefore, known techniques for detecting fault attacks rely on redundancy by providing more than one identical data processing element on a data processing component, each configured to perform a critical operation on the same input. The data processing component then includes a comparator configured to compare the outputs of the two redundant data processing elements. Because the redundant data processing elements perform the same operation on the same input, the expected outputs are the same. Therefore, if the comparator detects different outputs, it can be inferred that one of the redundant data processing elements has become a victim of a fault attack.

[0008] This is Figure 1 The diagram in the middle shows, Figure 1 A data processing component 100, such as a chip, is shown. The data processing component 100 includes multiple layers: a substrate 102, a logic layer 104, and a shielding layer 106. In the illustrated example, the logic layer 104 may be a central processing unit (CPU) layer or an arithmetic logic unit (ALU) layer. The shielding layer 106 may also serve as a power line. The logic layer 104 includes a first redundant data processing element 108 and a second redundant data processing element 110. The first redundant data processing element 108 and the second redundant data processing element 110 are each configured to receive the same input and perform the same operation on that input. Therefore, they are expected to generate the same output. The logic layer 104 also includes a comparator 112, which is configured to receive the outputs of the first redundant data processing element 108 and the second redundant data processing element 110 via traces 109 and 111, respectively. Figure 1 In the arrangement shown, the data processing component 100 is susceptible to fault attacks via the substrate 102, which may be a thinned substrate 102. This is because the shielding layer 106 protects the first redundant data processing element 108 and the second redundant data processing element 110 from such attacks by acting as a physical shield. The substrate 102 may be thinned to improve laser efficiency.

[0009] Figure 1 The text describes a first type of fault attack that the data processing component 100 can typically withstand. In this fault attack, a laser beam L1 is directed to a first redundant data processing element 108 located in logic layer 104. The laser beam L1 may cause a fault in the processing performed by the first redundant data processing element 108. This means that the output of the first redundant data processing element 108 will no longer be the same as the output of the second redundant data processing element 110. Therefore, when the comparator 112 compares the two outputs, it will detect that they are different and generate a signal indicating that a fault attack has been detected.

[0010] The complexity of fault attacks has increased. Figure 2 The second type of failure attack is described, which is more... Figure 1The first type of fault attack described in the text is more complex. Figure 2 Data processing component 100 and Figure 1 The data processing components 100 shown are identical, and the same reference numerals are used to represent the same features. Figure 2 In the fault attack illustrated, two lasers are used. Specifically, a first laser beam L1 is directed to a first redundant data processing element 108, and a second laser beam L2 is directed to a second redundant data processing element 110. Laser beams L1 and L2 can be controlled such that they induce the same error in both the first and second redundant data processing elements 108 and 110. Therefore, the output of the first redundant data processing element 108 will be identical to the output of the second redundant data processing element 110, even though both outputs will contain the same error. Because the outputs are identical, the comparator 112 will not detect the interference, and the fault attack will remain undetected.

[0011] Therefore, the structure of the data processing element 100 is insufficient for detection. Figure 2 The example illustrates a complex failure attack of this type. A typical approach to solving this problem generally involves adding more redundant data processing components, but this only linearly improves security.

[0012] The inventors have proposed a solution to this problem that utilizes a vertical stacking method, which is now more commonly used to increase the processing power of a single data processing element. Summary of the Invention

[0013] At a higher level, the present invention aims to address the problems outlined in the previous section of this patent application by providing a data processing element comprising a fault attack shielding and detection arrangement. More specifically, the data processing element includes a first data processing element in a first layer and a second data processing element in a second layer. The first data processing element in the first layer can act as a shield to prevent electromagnetic radiation from incident on the second data processing element in the second layer. The expected output of the first data processing element in the first layer can be compared with the actual output to detect interference in the form of a fault attack.

[0014] Therefore, a first aspect of the present invention provides a data processing assembly including a fault attack shielding and detection arrangement, the data processing assembly comprising: a first layer including: a first data processing element configured to receive a control input and perform a predetermined operation on the control input to generate a control output; and a first comparator configured to compare the control output with a expected control output, and generate a fault condition signal if the control output differs from the expected control output; and a second layer including: a second data processing element identical to the first data processing element, configured to receive a first operation input and perform the same predetermined operation on the first operation input to generate a first operation output.

[0015] The advantages provided by the data processing element of the first aspect of the invention are at least twofold. First, fault attacks can be detected based on a comparison of the control output with the expected control output. Second, the first layer and the first data processing element can act as a shield, either preventing the transmission of electromagnetic radiation to the second data processing element in the second layer or significantly attenuating electromagnetic radiation, and vice versa. Therefore, the data processing element according to the first aspect of the invention is more robust in detecting and defending against fault attacks.

[0016] Before describing the various optional features of the data processing component of the first aspect of the invention, we clarify some of the terms used above.

[0017] The term "data processing component" is widely used to refer to any electronic component capable of performing logical operations on incoming data. Therefore, a data processing component may include programming logic configured to perform those logical operations on incoming data. A data processing component may be a processor of a computer or computing device, or a component of a processor of a computer or computing device, such as a chip or other equivalent integrated circuit forming a submodule of the processor. In this case, the first layer, second layer, and other layers may be layers of a chip, rather than, for example, a separate integrated circuit or a separate chip. For example, a data processing component may be a submodule of a processor responsible for performing a subset of specific operations. A "data processing element" is a smaller entity contained within a data processing component and represents a subset of the data processing component configured to perform one or more specific operations (specifically, predetermined operations). Therefore, a data processing element may include a subset of the programming logic contained within the data processing component.

[0018] Two types of inputs are defined: "control inputs" and "operation inputs." Control inputs may differ from operation inputs. Control inputs can be randomly generated. Control inputs can be predetermined. In the context of this invention, a "control input" is an input generated solely for the purpose of testing the first data processing element. The expected control output resulting from performing a predetermined operation on the control input is preferably known or easily determined. The control input is preferably independent of the "real" data processed by the data processing element. This input is used because if a fault attack disrupts the operation of the first data processing element, it will not cause any problem because it is control data, or dummy data, whose processing is not essential to (and in fact completely irrelevant to) the "real" operation of the data processing component. In contrast, an "operation input" refers to the real data being processed by the data processing component (specifically, its second data processing element). An "operation output" is the output resulting from performing a predetermined operation on the operation input.

[0019] The term "comparator" is used to refer to an electronic component configured to receive two inputs and generate an output based on a comparison of those two inputs. Control outputs and operational outputs may contain electronic signals having voltage and / or current profiles. In these cases, the comparator may be configured to compare the voltage and / or current of the inputs. Specifically, in the context of this invention, if the comparator determines that the two inputs it receives are different, then it may be configured to generate a fault condition signal. The term "fault condition signal" is used to refer to any electronic signal indicating that a fault has been detected. Such a signal may alternatively be referred to as an alarm signal or a trigger signal. Alternatively, if the comparator determines that the two inputs it receives are the same, then it may be configured to generate a normal condition signal. The term "normal condition signal" is used to refer to any electronic signal indicating that no fault has been detected.

[0020] We now discuss various optional features of the data processing component of the first aspect of the invention. It should be emphasized that any, some, or all of the optional features listed below may be combined with any other feature unless such combination is obviously incompatible with the technology or the context otherwise requires.

[0021] We will first discuss the structure of the data processing component in more detail. The first layer can be mounted on a substrate, which can be a planar substrate. In this document, the term "substrate" is used to refer to any component having a mounting surface on which another component can be mounted. The substrate can be a passive component, meaning it may not form a processing layer such as a logic layer. The thickness of the substrate is preferably constant or substantially constant in the direction perpendicular to the plane of the substrate, and can be not less than 50 μm, not less than 75 μm, or not less than 100 μm. Similarly, the thickness of the substrate in the direction perpendicular to the plane of the substrate can not exceed 200 μm, not more than 250 μm, not more than 300 μm, not more than 400 μm, or not more than 500 μm. The substrate can be made of silicon or other materials such as diamond, or III-V or II-VI semiconductor materials.

[0022] In a direction perpendicular to the planar substrate, the second layer can be farther from the planar substrate than the first layer. In this way, the first layer can shield the second layer from electromagnetic radiation. This is advantageous because fault attacks are typically performed from the substrate side of the data processing assembly, and in this case, the first layer of the data processing assembly contains a first data processing element that only receives control input, i.e., it does not participate in the processing of any real data. This means that the layer that processes real data is shielded by a layer that only processes dummy or control data. Another advantage becomes apparent when viewed from the perspective of a malicious actor. In seeking to identify the data processing element in which to induce a fault, such a malicious actor would need to perform some kind of probing operation to locate such a data processing element. During such a probing operation, because the first data processing element is closer to the substrate than the second data processing element, it is more likely to be identified than the second data processing element. Therefore, a malicious actor is more likely to target the first data processing element. Obviously, this is desirable because the first data processing element only handles control input (i.e., no "real" data). Thus, the first data processing element acts as a honeypot, enticing malicious actors to perform fault attacks against it, thereby causing them to be detected and appropriate action taken.

[0023] In addition to the shielding provided by the first layer itself, the data processing elements can also provide a shielding effect. Specifically, the data processing elements may include metal traces implementing logic, which absorb and thus attenuate electromagnetic radiation. Therefore, additional shielding effects can be achieved by aligning the data processing elements in different layers. Thus, the first layer may be a first planar layer, and the second layer may be a second planar layer. The first planar layer may be parallel or substantially parallel to the second planar layer. The first and second planar layers may also be parallel to the planar substrate. Here, "parallel" is used to mean "parallel or substantially parallel." In this arrangement, when viewed in a direction perpendicular to the first planar layer, the second planar layer, or the planar substrate, the first data element may at least partially overlap with the second data processing element. In this way, the first data processing element can form at least partial shielding configured to reduce electromagnetic radiation transmitted through the first data processing element to the second data processing element. In other arrangements, the second data processing element can form at least partial shielding configured to reduce electromagnetic radiation transmitted through the second data processing element to the first data processing element.

[0024] To achieve a greater shielding effect, when viewed in a direction perpendicular to the first planar layer, the second planar layer, or the planar substrate, the first data processing element may completely overlap with the second data processing element to form a shield configured to prevent or reduce electromagnetic radiation transmitted through the first data processing element to the second data processing element. Alternatively, when viewed in a direction perpendicular to the first planar layer, the second planar layer, or the planar substrate, the second data processing element may completely overlap with the first data processing element to form a shield configured to reduce or prevent electromagnetic radiation transmitted through the second data processing element to the first data processing element. In this document, "complete overlap" should be understood as one data processing element completely obscuring another data processing element, such that when viewed in a direction perpendicular to the first planar layer, the second planar layer, or the planar substrate, if all layers are transparent, it would be impossible to see the data processing element located on the other side of the shielding data processing element.

[0025] The data processing component may also include a shielding layer, which may be a planar shielding layer. This shielding layer may be configured to prevent the transmission of electromagnetic radiation, or to significantly attenuate electromagnetic radiation to a level that prevents it from disrupting the operation of the data processing element. The shield may be metallic, and more specifically may include a material configured to prevent or reduce electromagnetic radiation transmitted from the green portion of the visible spectrum to the infrared portion of the electromagnetic spectrum. For example, the shield may be configured to prevent or reduce electromagnetic radiation transmitted at wavelengths of 300 nm to 1500 nm, or from 440 nm to 1200 nm, or from 530 nm to 1100 nm. In a direction perpendicular to the planar substrate, the shielding layer may be farther from the planar substrate than the first and second layers. In this way, the first and second layers may be sandwiched between the planar substrate and the shielding layer.

[0026] To further enhance the data processing component's ability to detect and respond to fault attacks, the second layer may also include a third data processing element identical to the first and second data processing elements. Therefore, the third data processing element can be configured to receive a second operational input identical to the first operational input and perform the same predetermined operation on the second operational input to generate a second operational output. The second layer may also include a second comparator configured to compare the first operational output with the second operational output, and generate a fault condition signal if the first operational input differs from the second operational output.

[0027] To demonstrate the advantages of this arrangement, consider a scenario where a carefully orchestrated fault attack is carried out, in which a laser beam is directed at a second and a third data processing element. This laser beam is deliberately generated to induce the same error in each of the second and third data processing elements. In this case, the first data processing element can act as a shield, reducing the amount of laser light transmitted to the second data processing element. This in itself may be sufficient to mean that the laser has different effects on the second and third data processing elements, meaning that the second comparator will record the difference between the second and third operational outputs. Furthermore, the laser incident on the first data processing element will induce an error when it processes the control input, meaning that its output will differ from the expected control output. Therefore, the first comparator will also record the difference. Thus, using this arrangement, a fault condition signal will be generated.

[0028] As discussed, a data processing component can be part of a computer processor, etc. Therefore, the data processing component includes several layers with different functions. The first layer can be a logic layer, and / or the second layer can be a logic layer. In this document, the term "logic layer" is used to refer to a layer in the data processing component that performs logical operations on incoming data. The types of operations that can be performed are discussed later in this patent application. Therefore, a logic layer can include various logic components such as logic gates. Data processing elements located in a logic layer can include multiple logic elements arranged to perform predetermined operations. A logic layer can be a CPU logic layer or an ALU logic layer.

[0029] In addition to the first and second layers, which respectively contain the first and second data processing elements, the data processing component may also include one or more intermediate layers located between the first and second layers. The intermediate layers may also be logical layers similar to the first and second layers. However, they may be other types of functional layers. For example, one or more intermediate layers may include one or more of the following: a memory layer, a sensor layer (e.g., an accelerometer, temperature sensor, pressure sensor, magnetic sensor, light sensor, humidity sensor, chemical sensor, or any other suitable sensor of any type, depending on the intended function of the data processing component), a power layer (e.g., which may include a voltage regulator or detector), or a tensor processing unit (which is an AI accelerometer ASIC) for implementations in which the data processing component is used to execute machine learning algorithms or models.

[0030] We will now discuss the nature of predetermined operations in more detail. Predetermined operations are preferably deterministic operations or algorithms. In this paper, "deterministic" means an algorithm where the same input will always produce the same output, and the underlying machine always passes through the same sequence of states. Hardware errors can cause the state of the machine (i.e., the data processing element) to change unexpectedly, leading to failure. It is for this reason that data processing elements configured to perform deterministic predetermined operations are secure against failure attacks. Predetermined operations that particularly deserve protection include those implementing security functions, cryptographic functions, authentication functions, or verification functions of the data processing component, especially those that rely on data that is typically kept confidential.

[0031] In one example, the predetermined operation can be an encryption operation. The control input can then include a control message to be encrypted, and the operation input can include an operation message to be encrypted. The first operation output can be a first encrypted message, the control output can be a second encrypted message, and the expected control output can be the expected encrypted message. Similarly, the predetermined operation can be a decryption operation. The control input can then include a control message to be decrypted, and the operation input can include an operation message to be decrypted. The first operation output can be a first decrypted message, the control output can be a second decrypted message, and the expected control output can be the expected decrypted message.

[0032] Another example of a pre-defined operation is an authentication operation. The output of such an algorithm can be binary (i.e., "authenticated" or "authenticated not," or equivalent) and can be referred to as an "authentication output." To clarify, performing an authentication operation on an input (i.e., a control or operational input) produces an authentication output. Thus, a control input can include the control input to be authenticated, and an operational input can include the operational input to be authenticated. A first operational output can be a first authentication output, a control output can be a second authentication output, and a pre-defined control output can be a pre-defined authentication output. The input can be a password, PIN, biometric input (e.g., fingerprint, retinal scan, Face ID, Voice ID, etc.), or any other suitable form of authentication input.

[0033] It is important to emphasize that the examples of predefined operations listed above are not an exhaustive list, but merely illustrative examples.

[0034] A data processing component (or a larger data processing component as part of it) may include a clock, wherein all processing stages occur at a frequency determined by the clock. Within the data processing component, a first data processing element, a second data processing element, and an optional third data processing element may be synchronized with each other. More specifically, the first data processing element, the second data processing element, and the optional third data processing element may be synchronized with the clock frequency. This ensures that the comparator compares "like for like," that is, compares the states of data processing elements that are in the same stage of a predetermined operation. Alternatively, the comparator may simply compare the outputs of the relevant data processing elements with each other.

[0035] The purpose of this invention is to detect fault attacks and limit side-channel attacks. We will now discuss what might happen if an attack is detected. As outlined elsewhere, if a first or second comparator detects a difference between its two inputs, a fault condition signal is generated. The fault condition signal indicates the presence of a fault and may be equivalently referred to as an “alarm signal” or a “trigger signal.” The first and / or second comparator may be configured to transmit the fault condition signal to a fault response module. The fault response module may be part of a first data processing element, a second data processing element, a third data processing element, a data processing component, or the data processing component itself as part of a larger processing component that is a subcomponent. In this document, the term “module” is used to refer to a functional module that can be implemented in software (e.g., a piece of code stored on a component) or hardware (e.g., a separate physical module). In response to receiving a fault condition signal, the fault response module may be configured to perform a shutdown operation. The severity of the shutdown operation depends on the urgency of the detected fault attack. For example, the shutdown operation may simply be the shutdown of a data processing component or a larger component that is a subcomponent. In other, more critical situations, a shutdown operation may also include erasing some or all of the data stored on the data processing component or a larger component that is a subcomponent of it. In even more critical situations, a shutdown operation may include permanently rendering the data processing component inoperable. In still more critical situations, a shutdown operation may include permanently rendering a larger component, in which the data processing component is a subcomponent of it, inoperable.

[0036] A first aspect of the invention relates to a data processing component. It has been frequently mentioned that the data processing component of the first aspect of the invention is a larger component or a larger processing component of its sub-components. Such a larger component may take the form of a computer processor. In this document, "computer processor" means the processor of any computing device, such as a desktop computer, laptop computer, smartphone, tablet computer, or any other computing device, including processors found in other devices / machines. Accordingly, a second aspect of the invention provides a computer processor according to the first aspect of the invention. This computer processor may include a clock generator configured to generate a clock signal, wherein a first data processing element, a second data processing element, and an optional third data processing element are each synchronized with the clock signal. The optional features listed above with respect to the first aspect of the invention also apply to the second aspect of the invention, unless there is a clear technical incompatibility or the context clearly provides otherwise.

[0037] In other words, the present invention includes combinations of the described aspects and preferred features, unless such combinations are obviously prohibited or explicitly avoided. Attached Figure Description

[0038] Embodiments of the present invention will now be described with reference to the accompanying drawings, in which:

[0039] Figure 1 This is a diagram of a known data processing component that is undergoing a fault attack.

[0040] Figure 2 This is a diagram of a known data processing component that is undergoing a more complex failure attack.

[0041] Figure 3 This is an embodiment of a data processing component undergoing a fault attack according to the first aspect of the present invention.

[0042] Figure 4 This is an implementation of a data processing component that is undergoing a more complex failure attack according to the first aspect of the invention. Detailed Implementation

[0043] Aspects and embodiments of the invention will now be discussed with reference to the accompanying drawings. Other aspects and embodiments will be apparent to those skilled in the art. All documents mentioned herein are incorporated by reference.

[0044] Figure 1 and Figure 2 A prior art data processing component 100 is shown and has been described in detail in the "Background" section of this patent application. This section begins... Figure 3 The description begins.

[0045] Figure 3 This is a schematic diagram of a data processing component 200 (or a portion thereof) according to a first aspect of the present invention, to illustrate a high-level implementation of the invention. The data processing component comprises three layers: a substrate layer 202, a first logic layer 204, and a second logic layer 206. In the data processing component 200, the substrate layer 202, the first logic layer 204, and the second logic layer are planar and parallel, but this is not mandatory. The first logic layer 204 is formed on the substrate layer 202, and the second logic layer 206 is formed on the first logic layer 204. However, it will be appreciated that this is not mandatory, and intermediate layers may exist between the substrate layer 202 and the first logic layer 204, and / or between the first logic layer 204 and the second logic layer 206. The relative thicknesses of the substrate layer 202, the first logic layer 204, and the second logic layer 206 are... Figure 3 The choice of terms is arbitrary and should not be construed as a restriction in any way.

[0046] The first logic layer includes a first data processing element 208 connected to a first comparator 210 via a trace 212. The first data processing element 208 is configured to perform a predetermined operation on incoming data. Specifically, within the data processing assembly 200, the first data processing element is configured to perform a predetermined operation on a control input (not shown). The control input is a fixed input, independent of the “real” data processed by the data processing assembly 200. The output of the predetermined operation on the control input, referred to herein as a first control output, is transmitted to the first comparator 210 via the trace 212. The first comparator 210 is then configured to compare the first control output with a desired control output, which is the expected output produced by performing the predetermined operation on the control input. The first comparator 210 may retrieve the desired control output from a memory or other suitable storage component, or may receive it from another component (not shown) within the first logic layer 204. If the first comparator 210 determines that the control output differs from the desired control output, then the first comparator 210 is configured to output a fault condition signal (e.g., in the form of a predetermined voltage signal). If the first comparator 210 does not detect a difference between the control output and the expected control output, then no fault condition signal is generated. In some cases, a normal condition signal can be generated and output.

[0047] The second logic layer 206 includes a second data processing element 214. The second data processing element 214 is identical to the first data processing element 208, and crucially, is configured to perform the same predetermined operation. The second data processing element 214 is configured to receive a first operation input (not shown) and perform a predetermined operation thereon to generate a first operation output. The first operation input differs from a control input in that it includes actual data; that is, the second data processing element 214 performs actual data processing on the data processing component 200.

[0048] The data processing components may optionally include power lines on both the front and back sides of the wafer.

[0049] Figure 3 A fault attack is illustrated, in which, for example, electromagnetic radiation in the form of a laser L1 of a selected wavelength is incident on the data processing component 200. The arrangement of the data processing component 200 provides at least two means of defending against fault attacks:

[0050] i. First, as Figure 3As shown, laser L1 is incident on the first data processing element 208. The incident laser L1 on the first data processing element 208 can alter the state of the logic components within the first data processing element 208. Therefore, it may cause errors in the execution of a predetermined operation. Consequently, as a result of a fault attack, the control output will mismatch with the expected control output, and the first comparator 210 will detect the difference between the control output and the expected control output. A fault condition signal will then be generated. Since the first data processing element 308 only receives control input, i.e., no actual data, the disruption of the execution of the predetermined operation is irrelevant.

[0051] ii. Secondly, even if the laser L1 might penetrate the substrate 202, the first data processing element 208 also includes metal components that enable logic components to perform predetermined operations. These metal components are capable of absorbing at least some of the laser L1. This either significantly attenuates or completely prevents the laser from incident on the second data processing element 214. Therefore, the presence of the first data processing element 208 at the location where it forms an electromagnetic radiation shield against the laser L1 for the second data processing element 214 also reduces the effectiveness of a fault attack on the data processing element 214, which performs predetermined operations on real data.

[0052] Figure 4 The illustration shows a schematic arrangement of components in data processing component 300 that provides effective protection against complex fault attacks in which a laser is directed to data processing component 300 to attempt to induce the same fault in two identical data processing components, making it impossible for comparators to detect the differences in their outputs and rendering the fault undetectable.

[0053] The data processing component comprises five layers: a substrate layer 302, a first logic layer 304, an intermediate layer 316, a second logic layer 306, and a shielding layer 318. In the data processing component 300, the substrate layer 302, the first logic layer 304, the intermediate layer 316, the second logic layer 306, and the shielding layer 318 are all planar and parallel, but this is not mandatory. The first logic layer 304 is formed on the substrate layer 302. The intermediate layer 316 (which can be a memory layer such as a RAM layer) is formed on the first logic layer 304. The second layer 306 is formed on the intermediate layer 316. The shielding layer 318 is formed on the second layer 306. Naturally, as... Figure 3 Similarly, it will be recognized that this specific configuration of layers is for illustrative purposes only, and additional intermediate layers, logic layers, or shielding layers may be present. The relative thicknesses of the substrate layer 302, the first logic layer 304, the intermediate layer 316, the second logic layer 306, and the shielding layer 318 are as follows: Figure 4 The choice of terms is arbitrary and should not be construed as a restriction in any way.

[0054] Like Figure 3 Similar to the data processing component 200, the first logic layer 304 includes a first data processing element 308. The first data processing element 308 is configured to perform a predetermined operation on incoming data. Specifically, in the data processing component 300, the first data processing element is configured to perform a predetermined operation on a control input (not shown). The control input is a fixed input that is independent of the “real” data processed by the data processing component 300. The output of the predetermined operation on the control input, referred to herein as a first control output, is transmitted via trace 312 to a first comparator 310. The first comparator 310 is then configured to compare the first control output with a desired control output, which is the expected output produced by performing the predetermined operation on the control input. The first comparator 310 may retrieve the desired control output from memory or other suitable storage components, or it may receive it from another component (not shown) within the first logic layer 304. If the first comparator 310 determines that the control output differs from the desired control output, then the first comparator 310 is configured to output a fault condition signal (e.g., in the form of a predetermined voltage signal). If the first comparator 310 does not detect a difference between the control output and the expected control output, then no fault condition signal is generated. In some cases, a normal condition signal can be generated and output.

[0055] The second logic layer 306 of data processing component 300 differs slightly from the second logic layer 206 of data processing component 200. The second logic layer 306 includes a second data processing element 314. The second data processing element 314 is identical to the first data processing element 308, and crucially, is configured to perform the same predetermined operation. The second data processing element 314 is configured to receive a first operation input (not shown) and perform a predetermined operation thereon to generate a first operation output. The first operation input differs from a control input in that it includes actual data, i.e., the second data processing element 314 uses to perform actual data processing on the data processing component 300. The second logic layer 306 also includes a third data processing element 320. The third data processing element 320 is identical to the first data processing element 308 and the second data processing element 314, and is configured to perform the same predetermined operation as both. The third data processing element 320 is configured to receive a second operation input (not shown) that is identical to the first operation input (e.g., from the same source) and perform a predetermined operation thereon to generate a second operation output. Just like the first operational output, the second operational input differs from the control input in that it contains real data, that is, the second data processing element 320 is also used to perform real data processing on the data processing component 300.

[0056] The second logic layer 306 also includes a second comparator 322, which is connected to the second data processing element 314 via a trace 326 and to the third data processing element 320 via a trace 324.

[0057] The second comparator 322 is then configured to compare the first operational output received from the second data processing element 314 with the second operational output received from the third data processing element 320. If the second comparator 322 determines that the control output differs from the second operational output, then the second comparator 322 is configured to output a fault condition signal (e.g., in the form of a predetermined voltage signal). If the second comparator 322 does not detect a difference between the first and second operational outputs, then no fault condition signal is generated. In some cases, a normal condition signal may be generated and output.

[0058] Figure 4 The illustration depicts a fault attack in which electromagnetic radiation (e.g., in the form of lasers L1 and L2 of selected wavelengths) is incident on data processing component 300. The arrangement of data processing component 300 provides at least two means of defending against fault attacks:

[0059] i. First, as Figure 4 As shown, laser L1 is incident on the first data processing element 308. The incident laser L1 on the first data processing element 308 can alter the state of the logic components within the first data processing element 308. Therefore, it may cause errors in the execution of a predetermined operation. Consequently, as a result of a fault attack, the control output will mismatch with the expected control output, and the first comparator 310 will detect the difference between the control output and the expected control output. A fault condition signal will then be generated. Since the first data processing element 308 only receives control input, i.e., no actual data, the disruption of the execution of the predetermined operation is irrelevant.

[0060] ii. Secondly, even if the laser L1 might penetrate the substrate 302, the first data processing element 308 also includes metal components that enable logic components to perform predetermined operations. These metal components are capable of absorbing at least some of the laser L1. This either significantly attenuates or completely prevents the laser from incident on the second data processing element 314. Therefore, the presence of the first data processing element 208 at the location where it forms an electromagnetic radiation shield against the laser L1 for the second data processing element 314 also reduces the effectiveness of a fault attack on the data processing element 314, which performs predetermined operations on real data.

[0061] iii. Third, even if the first data processing element 308 forms an insufficient shield against the laser L1, and its penetration is sufficient to have a destructive effect on the second data processing element 314 performing its intended operation (e.g., Figure 4 In the event of penetration by laser L1' (as shown), the presence of the third data processing component 320 and the second comparator 322 means that a fault attack can still be detected. Specifically, even though laser L1' can still irradiate the second data processing element 314, it is unlikely to cause the same damage as laser L2 incident on the third data processing element 320 because it is attenuated by the shielding provided by the first data processing element 308. Therefore, although errors may be triggered in the execution of the predetermined operations of the second data processing element 314 and the third data processing element 320, these errors are highly unlikely to be the same. Therefore, the first operation output from the second data processing element 314 and the second operation output from the third data processing element 320 will be different. This will be detected by the second comparator 322, and a fault condition signal will be generated, thereby warning the system of a fault attack, although the nature of the fault attack is more complex.

[0062] Therefore, the implementation of data processing components 200 and 300 enables the detection of fault attacks of varying complexity.

[0063] The features disclosed in the foregoing description, or in the subsequent claims, or in the accompanying drawings, expressed in their specific form or as means for performing the disclosed functions or as methods or processes for obtaining the disclosed results, may be suitably used individually or in any combination of these features to implement the invention in its different forms.

[0064] While the invention has been described in conjunction with the exemplary embodiments described above, many equivalent modifications and variations will be apparent to those skilled in the art when this disclosure is given. Therefore, the exemplary embodiments of the invention set forth above are to be considered illustrative and not restrictive. Various changes may be made to the described embodiments without departing from the spirit and scope of the invention.

[0065] To avoid any doubt, any theoretical explanations provided herein are intended to enhance the reader's understanding. The inventor does not wish to be bound by any of these theoretical explanations.

[0066] Any section headings used in this document are for organizational purposes only and should not be construed as limiting the subject matter described.

[0067] Throughout this specification, including in the following claims, unless the context otherwise requires, the words “comprise” and “include” and their variations such as “comprises”, “comprising” and “including” shall be understood to imply inclusion of the integers or steps or groups of steps stated therein, but do not exclude any other integers or steps or groups of steps.

[0068] It should be noted that, as used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly specifies otherwise. A range may be expressed herein as from “about” a particular value, and / or to “about” another particular value. When such a range is expressed, another embodiment includes from this particular value and / or to another particular value. Similarly, when a value is expressed as an approximation using the antecedent “about,” it should be understood that the particular value forms another embodiment. The term “about” in relation to numerical values ​​is optional and means, for example, + / - 10%.

Claims

1. A data processing component, comprising a fault attack shielding and detection arrangement, the data processing component comprising: The first layer includes: A first data processing element, configured to receive control input and perform a predetermined operation on the control input to generate a control output; and A first comparator is configured to compare the control output with a desired control output, and if the control output differs from the desired control output, then generate a fault condition signal; and The second layer includes: A second data processing element, identical to the first data processing element, is configured to receive a first operation input and perform the same predetermined operation on the first operation input to generate a first operation output.

2. The data processing component as described in claim 1, wherein: The control input is different from the operation input.

3. The data processing component as described in claim 1 or claim 2, wherein: The control input is predetermined or randomly generated.

4. The data processing component as described in any one of claims 1 to 3, wherein: The control input includes dummy data, used solely for testing the first data processing element.

5. The data processing component as described in any one of claims 1 to 4, wherein: The first layer is mounted on the planar substrate; and In a direction perpendicular to the planar substrate, the second layer is farther from the planar substrate than the first layer.

6. The data processing component as described in claim 5, wherein: The first layer is a first planar layer, and the second layer is a second planar layer, with the first planar layer parallel to the second planar layer; and When viewed in a direction perpendicular to the first and second planar layers, the first data processing element at least partially overlaps with the second data processing element to form at least a partial shield configured to reduce or prevent the transmission of electromagnetic radiation from the first data processing element to the second data processing element.

7. The data processing component as described in claim 6, wherein: When viewed in a direction perpendicular to the first planar layer, the first data processing element and the second data processing element completely overlap to form a shield configured to reduce or prevent the transmission of electromagnetic radiation from the first data processing element to the second data processing element.

8. The data processing component as described in any one of claims 5 to 7, further comprising: A shielding layer is configured to reduce or prevent the transmission of electromagnetic radiation to the first data processing element and the second data processing element; When viewed perpendicular to the planar substrate, the shielding layer is farther from the planar substrate than the first layer and the second layer.

9. The data processing component according to any one of claims 1 to 8, wherein: The second layer also includes: A third data processing element, identical to the first and second data processing elements, is configured to receive a second operation input identical to the first operation input and to perform the same predetermined operation on the second operation input to generate a second operation output; and A second comparator is configured to compare the first operational output with the second operational output, and if the first operational output differs from the second operational output, then generate a fault condition signal.

10. The data processing component according to any one of claims 1 to 9, wherein: The first layer is a logical layer; and / or The second layer is the logic layer.

11. The data processing component as described in any one of claims 1 to 10, further comprising: One or more intermediate layers located between the first layer and the second layer.

12. The data processing component as claimed in claim 9, wherein: The one or more intermediate layers include one or more of the following: a memory layer, a logic layer, a sensor layer, a power layer, or a tensor processing unit.

13. The data processing component according to any one of claims 1 to 10, wherein: The predetermined operation is a deterministic operation.

14. The data processing component of claim 13, wherein: The deterministic operation includes one or more of the following: encryption operation, decryption operation, and authentication operation.

15. The data processing component according to any one of claims 1 to 14, wherein: The first comparator and / or the second comparator are configured to transmit the fault condition signal to the fault response module, the fault response signal being configured to perform a shutdown operation in response to receiving the fault condition signal.

16. The data processing component as claimed in any one of claims 1 to 15, wherein the data processing component is a chip comprising the first layer and the second layer.

17. A computer processor comprising the data processing component as described in any one of claims 1 to 16.

18. The computer processor of claim 17, comprising: A clock generator configured to generate a clock signal, wherein the first data processing element, the second data processing element, and optionally the third data processing element are each synchronized with the clock signal.

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