Reference voltage source circuit and electronic equipment

Abstract

The invention relates to a reference voltage source circuit and electronic equipment. The reference voltage source circuit comprises a reference voltage generating circuit connected with a voltage source and used for outputting reference voltage; the current mirror circuit is connected with the reference voltage generating circuit; one end of the self-biasing circuit is connected with the reference voltage generation circuit, the other end of the self-biasing circuit is connected with the current mirror circuit, and the self-biasing circuit is used for adjusting the reference voltage output by the reference voltage generation circuit according to the balance state of the current mirror circuit. According to the reference voltage source circuit and the electronic equipment, the problem of reference voltage fluctuation caused by temperature drift, output noise and the like can be reduced, so that stable reference voltage is provided in various scenes.

Description

Technical Field

[0001] This disclosure relates to the field of electronic circuit technology, and in particular to a reference voltage source circuit and electronic device. Background Technology

[0002] In fields such as electric vehicles and home appliances (such as inverter air conditioners), most electronic devices require a reference voltage source. The reference voltage source can provide a reference voltage for power electronic systems. Summary of the Invention

[0003] To overcome the problem of unstable reference voltage sources in related technologies, this disclosure provides a reference voltage source circuit and electronic device that can reduce reference voltage fluctuations caused by temperature drift, output noise, etc., thereby providing a stable reference voltage in various scenarios.

[0004] According to a first aspect of the present disclosure, a reference voltage source circuit is provided, comprising: a reference voltage generation circuit connected to a voltage source for outputting a reference voltage; a current mirror circuit connected to the reference voltage generation circuit; and a self-biasing circuit, one end of which is connected to the reference voltage generation circuit and the other end of which is connected to the current mirror circuit, wherein the self-biasing circuit is used to adjust the reference voltage output by the reference voltage generation circuit according to the balance state of the current mirror circuit.

[0005] This reference voltage source circuit includes a reference voltage generation circuit, a current mirror circuit, and a self-biasing circuit. The current mirror circuit is connected to the reference voltage generation circuit, allowing its balance state to characterize the stability of the output reference voltage. Furthermore, by adjusting the output reference voltage based on the balance state of the current mirror circuit, the self-biasing circuit can resolve reference voltage instability issues caused by temperature drift, output noise, and other factors, effectively ensuring the stability of the reference voltage output by the reference voltage source circuit. Therefore, this reference voltage source circuit can reduce reference voltage fluctuations caused by temperature drift, output noise, and other factors, thus providing a stable reference voltage in various scenarios.

[0006] In some possible implementations, the reference voltage generation circuit includes: a common-source cascode structure, one end of which is connected to the voltage source to increase the output impedance of the reference voltage generation circuit; and a load circuit, one end of which is connected to the other end of the common-source cascode structure, the other end of which is grounded, and the load circuit is used to output a reference voltage.

[0007] The reference voltage generation circuit, which uses a common source and common gate structure and a load circuit, can improve the output impedance and reduce the impact of voltage source fluctuations on the reference voltage.

[0008] In some possible implementations, the common-source common-gate structure includes: at least one PMOS transistor and at least two NMOS transistors, wherein the drain of the at least one PMOS transistor and the gate of the at least two NMOS transistors are both connected to the same circuit node.

[0009] A common-source, common-gate structure consisting of at least one PMOS transistor and at least two NMOS transistors can effectively improve the output impedance and reduce the impact of voltage source fluctuations on the reference voltage.

[0010] In some possible implementations, the load circuit includes at least two NMOS transistors, with the gate and drain of each NMOS transistor shorted together.

[0011] A load circuit consisting of at least two NMOS transistors can be equivalent to a diode-connected load, so that the reference voltage generation circuit can provide a stable reference voltage.

[0012] In some possible implementations, the current mirror circuit includes at least two PMOS transistors and at least two NMOS transistors, wherein the drain of one of the PMOS transistors and the drain of one of the NMOS transistors are connected to the same circuit node, and the gates of the at least two NMOS transistors are connected to the same circuit node, forming a multi-level NMOS mirror structure.

[0013] A current mirror structure consisting of at least two PMOS transistors and at least two NMOS transistors can not only provide auxiliary bias and enhance the matching accuracy of the current mirror, but also suppress process deviations and temperature drift through multi-stage NMOS mirrors, thereby improving the stability of the reference voltage.

[0014] In some possible implementations, the self-biasing circuit includes: at least two PMOS transistors and at least two NMOS transistors; the gates of the at least two PMOS transistors and one of the at least two NMOS transistors are connected to a target circuit node, which is connected to the current mirror circuit; the self-biasing circuit is used to adjust the conduction state of the at least two PMOS transistors according to the voltage of the target circuit node, so as to adjust the reference voltage output by the reference voltage generation circuit.

[0015] By using a self-biasing circuit consisting of at least two PMOS transistors and at least two NMOS transistors, the reference voltage can be adjusted based on the voltage value of the target circuit node, thereby improving the stability of the reference voltage source circuit.

[0016] In some possible implementations, the reference voltage source circuit further includes a protection circuit connected to the reference voltage generation circuit and / or the self-biasing circuit, for protecting the reference voltage source circuit.

[0017] By incorporating a protection circuit into the reference voltage source circuit, the reference voltage source can be protected, thereby enhancing its safety.

[0018] In some possible implementations, the protection circuit includes a current-limiting resistor connected to the reference voltage generation circuit and / or the self-biasing circuit for limiting the input current of the reference voltage generation circuit and / or the self-biasing circuit.

[0019] By using a current-limiting resistor, the input current in the reference voltage source circuit can be effectively limited, avoiding excessive transient impacts and improving circuit stability.

[0020] In some possible implementations, the protection circuit includes a voltage divider resistor connected to the reference voltage generation circuit and / or the self-biasing circuit, for stabilizing the reference voltage output by the reference voltage generation circuit.

[0021] By using voltage divider resistors, the reference voltage output by the reference voltage generation circuit can be effectively stabilized, thereby improving the stability of the reference voltage source circuit.

[0022] According to a second aspect of the present disclosure, an electronic device is provided, comprising: a reference voltage source circuit as described in the first aspect of the present disclosure, the reference voltage source circuit being configured to provide a reference voltage for a load in the electronic device.

[0023] In some possible implementations, the electronic device further includes a power factor correction circuit and a protection circuit corresponding to the power factor correction circuit, wherein the reference voltage source circuit is further used to provide a reference voltage to the protection circuit corresponding to the power factor correction circuit.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0026] Figure 1 This is a block diagram illustrating a reference voltage source circuit according to an exemplary embodiment.

[0027] Figure 2 This is a block diagram illustrating a reference voltage generation circuit according to an exemplary embodiment.

[0028] Figure 3This is a schematic diagram of the circuit structure of a reference voltage source circuit according to an exemplary embodiment.

[0029] Figure 4 This is a schematic diagram illustrating the connection relationship between a reference voltage source circuit and a PFC protection circuit according to an exemplary embodiment.

[0030] Figure 5 This is an example circuit structure diagram of a current feedback amplifier according to an exemplary embodiment.

[0031] Figure 6 This is a schematic diagram of the circuit structure of a hysteresis comparator according to an exemplary embodiment. Detailed Implementation

[0032] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0033] It should be noted that all actions involving the acquisition of signals, information, or data in this disclosure are carried out in accordance with the relevant data protection laws and policies of the country where the location is situated, and with the authorization granted by the owner of the relevant device.

[0034] As mentioned in the background section, reference voltage sources are involved in fields such as electric vehicles and home appliances (such as inverter air conditioners). These reference voltage sources can provide a reference voltage for power electronic systems.

[0035] In related technologies, the design of reference voltage sources is relatively simple. For example, a reference voltage source circuit is constructed by using a voltage source and a voltage divider network. The role of the voltage divider network is to maximize the stability of the output reference voltage.

[0036] This type of reference voltage source circuit, limited by the design of the voltage divider network, cannot effectively guarantee the stability of the output reference voltage under various scenarios. For example, there may be temperature drift, output noise, etc., which may lead to unstable reference voltage output.

[0037] Based on this, the present disclosure provides a reference voltage source circuit, which includes a reference voltage generation circuit, a current mirror circuit, and a self-biasing circuit. The current mirror circuit is connected to the reference voltage generation circuit, so that the balance state of the current mirror circuit can characterize whether the output reference voltage is stable. Furthermore, by adjusting the output reference voltage based on the balance state of the current mirror circuit through the self-biasing circuit, the problem of reference voltage instability caused by temperature drift, output noise, etc. can be solved, effectively ensuring the stability of the reference voltage output by the reference voltage source circuit.

[0038] Therefore, this reference voltage source circuit can reduce reference voltage fluctuations caused by temperature drift, output noise, and other factors, thereby providing a stable reference voltage in various scenarios.

[0039] This reference voltage source circuit can be applied to fields such as electric vehicles and home appliances (such as inverter air conditioners), for example, it can provide a reference voltage for power electronic systems in these fields.

[0040] Figure 1 This is a block diagram illustrating a reference voltage source circuit 10 according to an exemplary embodiment, such as... Figure 1 As shown, the reference voltage source circuit 10 includes: a reference voltage generation circuit 11, a current mirror circuit 12, and a self-biasing circuit 13.

[0041] The reference voltage generation circuit 11 is connected to the voltage source, the current mirror circuit 12 is connected to the reference voltage generation circuit 11, one end of the self-biasing circuit 13 is connected to the reference voltage generation circuit 11, and the other end of the self-biasing circuit 13 is connected to the current mirror circuit 12.

[0042] Regarding the reference voltage generation circuit 11, it is used to output a reference voltage. The magnitude of the output reference voltage is determined by the corresponding power supply object and is not limited here.

[0043] Regarding the current mirror circuit 12, since it is connected to the reference voltage generation circuit 11, it can operate under the influence of the reference voltage. Therefore, the balance state of the current mirror circuit 12 can reflect the stability of the reference voltage.

[0044] The self-biasing circuit 13 is used to adjust the reference voltage output by the reference voltage generation circuit 11 according to the balance state of the current mirror circuit 12.

[0045] In one embodiment, the self-biasing circuit 13 adjusts the reference voltage output by the reference voltage generation circuit 11 with the goal of restoring the current mirror circuit 12 to a balanced state, so that the reference voltage also stabilizes after the current mirror circuit 12 is restored to a balanced state.

[0046] Figure 2This is a block diagram illustrating a reference voltage generation circuit 11 according to an exemplary embodiment, such as... Figure 2 As shown, the reference voltage generation circuit 11 includes a common source cascode structure 110 and a load circuit 112; wherein, one end of the common source cascode structure 110 is connected to a voltage source, one end of the load circuit 112 is connected to the other end of the common source cascode structure 110, and the other end of the load circuit 112 is grounded.

[0047] Regarding the common source cascode structure 110, it is used to increase the output impedance of the reference voltage generation circuit 11; regarding the load circuit 112, it is used to output the reference voltage.

[0048] The reference voltage generation circuit 11, which is composed of a common source and common gate structure 110 and a load circuit 112, can improve the output impedance and reduce the impact of voltage source fluctuations on the reference voltage.

[0049] In one implementation, for circuits, modules, systems, etc. that require a reference voltage input, they can be connected to the corresponding circuit node in the reference voltage generation circuit 11; or, the magnitude of the reference voltage finally output by the reference voltage source circuit 10 is equal to the voltage magnitude of the corresponding circuit node in the reference voltage generation circuit 11.

[0050] In one embodiment, the common-source common-gate structure 110 includes at least one PMOS transistor and at least two NMOS transistors, wherein the drain of the at least one PMOS transistor and the gate of the at least two NMOS transistors are both connected to the same circuit node.

[0051] Among them, MOS transistor stands for Metal Oxide Semiconductor Field Effect Transistor. PMOS transistor is a P-type transistor, and NMOS transistor is an N-type transistor.

[0052] The common-source, common-gate structure 110, consisting of at least one PMOS transistor and at least two NMOS transistors, can effectively improve the output impedance and reduce the impact of voltage source fluctuations on the reference voltage.

[0053] In one implementation, the number of PMOS transistors can be 1, and the number of NMOS transistors can be 2; there is no limitation on this.

[0054] In one embodiment, the same circuit node to which the drain of at least one PMOS transistor and the gates of at least two NMOS transistors are connected can be regarded as a reference voltage node, and the voltage at this circuit node is the reference voltage.

[0055] In one embodiment, the load circuit 112 includes at least two NMOS transistors, with the gate and drain of each NMOS transistor shorted together.

[0056] The load circuit 112, which consists of at least two NMOS transistors, can be equivalent to a diode-connected load, so that the reference voltage generation circuit 11 can provide a stable reference voltage.

[0057] In one implementation, the gate and drain of each NMOS transistor are shorted to the same circuit node, which may be the reference voltage node in the aforementioned embodiments.

[0058] In one embodiment, the common-source common-gate structure 110 and the load circuit 112 can share at least two NMOS transistors to reduce the number of circuit devices.

[0059] In one embodiment, the number of NMOS transistors in the load circuit 112 is 3, and the number of NMOS transistors in the cascode structure 110 is 2. Therefore, the two NMOS transistors in the cascode structure 110 can be used as part of the load circuit 112.

[0060] In one embodiment, the current mirror circuit 12 may include at least two PMOS transistors and at least two NMOS transistors.

[0061] In this configuration, the drain of one of the at least two PMOS transistors is connected to the drain of one of the at least two NMOS transistors, and the gates of the at least two NMOS transistors are connected to the same circuit node, forming a multi-level NMOS mirror structure.

[0062] A current mirror structure consisting of at least two PMOS transistors and at least two NMOS transistors can not only provide auxiliary bias and enhance the matching accuracy of the current mirror, but also suppress process deviations and temperature drift through multi-stage NMOS mirrors, thereby improving the stability of the reference voltage.

[0063] In one implementation, the number of PMOS transistors can be 2, and the number of NMOS transistors can be 3.

[0064] In one implementation, the same circuit node to which the drain of one of the at least two PMOS transistors and the drain of one of the at least two NMOS transistors are connected can be considered as a circuit node providing auxiliary bias to enhance the current mirror matching accuracy.

[0065] In one implementation, the same circuit node to which the gates of at least two NMOS transistors are connected can be regarded as a multi-level NMOS mirror node, used to suppress process deviations and temperature drift.

[0066] In one embodiment, since the current mirror circuit 12 has a temperature compensation function, it can also be called a current mirror and temperature compensation circuit, without limitation.

[0067] In one embodiment, the self-biasing circuit 13 includes at least two PMOS transistors and at least two NMOS transistors.

[0068] The gates of at least two PMOS transistors and one of the at least two NMOS transistors are connected to the target circuit node, which is connected to the current mirror circuit 12.

[0069] The self-biasing circuit 13 is used to adjust the conduction state of at least two PMOS transistors according to the voltage of the target circuit node, so as to adjust the reference voltage output by the reference voltage generation circuit 11.

[0070] The self-biasing circuit 13, consisting of at least two PMOS transistors and at least two NMOS transistors, can adjust the reference voltage based on the voltage value of the target circuit node, thereby improving the stability of the reference voltage source circuit 10.

[0071] In one implementation, at least two PMOS transistors and at least two NMOS transistors can form a self-biased current source. Through feedback from the target circuit node, the conduction state of at least two PMOS transistors is controlled, so that the current mirror enters a balanced state, thereby allowing the reference voltage to enter a steady state.

[0072] In one implementation, a stable operating point can be quickly established via the self-biasing circuit 13 when the voltage source is powered on. In subsequent processes, the balance of the current mirror can also be adjusted by considering the voltage value of the feedback node.

[0073] In one implementation, the number of PMOS transistors can be 2, and the number of NMOS transistors can also be 2; there is no limitation on this.

[0074] In one embodiment, the reference voltage source circuit 10 further includes a protection circuit, which is connected to the reference voltage generation circuit 11 and / or the self-biasing circuit 13, for protecting the reference voltage source circuit 10.

[0075] By setting a protection circuit in the reference voltage source circuit 10, the reference voltage source can be protected, and the safety of the reference voltage source circuit 10 can be improved.

[0076] In one implementation, the protection circuit may have filtering and noise suppression functions. Therefore, the protection circuit may be referred to as a filtering and noise suppression module / unit / circuit, without limitation.

[0077] In one implementation, the protection circuit can be flexibly set in the voltage source protection circuit, so its connection relationship with other circuits is not limited here.

[0078] In one embodiment, the protection circuit includes a current-limiting resistor connected to the reference voltage generation circuit 11 and / or the self-biasing circuit 13 for limiting the input current of the reference voltage generation circuit 11 and / or the self-biasing circuit 13.

[0079] By using a current-limiting resistor, the input current in the reference voltage source circuit 10 can be effectively limited, avoiding excessive transient impacts and improving circuit stability.

[0080] In one implementation, the current-limiting resistor can be one or more resistors with fixed resistance values, which is not limited here.

[0081] In one embodiment, the protection circuit includes a voltage divider resistor connected to the reference voltage generation circuit 11 and / or the self-biasing circuit 13, for stabilizing the reference voltage output by the reference voltage generation circuit 11.

[0082] By using voltage divider resistors, the reference voltage output by the reference voltage generation circuit 11 can be effectively stabilized, thereby improving the stability of the reference voltage source circuit 10.

[0083] In one embodiment, the voltage divider resistor can be one or more resistors with fixed resistance values, and this is not limited thereto.

[0084] Figure 3 This is a schematic diagram of the circuit structure of a reference voltage source circuit 10 according to an exemplary embodiment. As shown in the figure, the reference voltage source circuit 10 includes devices such as PM16, PM17, PM18, PM19, NM12, NM13, NM14, NM15, NM16, NM17, NM18, R7, and R8.

[0085] In this diagram, PM represents a PMOS transistor, with different serial numbers indicating different PMOS transistors; NM represents an NMOS transistor, with different serial numbers indicating different NMOS transistors; and R represents a resistor, with different serial numbers indicating different resistors.

[0086] The reference voltage source circuit 10 adopts a multi-stage current mirror and negative feedback structure. Through the coordinated operation of PMOS and NMOS, it can generate a stable reference voltage.

[0087] The reference voltage source circuit 10 incorporates a self-biasing structure, temperature compensation, and low-noise design. The self-biasing structure stabilizes the operating point through an internal feedback node, reducing dependence on voltage source fluctuations. Temperature compensation utilizes the threshold voltage characteristics of the MOSFET to partially offset the effects of temperature drift. The low-noise design reduces output noise through appropriate current mirror matching.

[0088] The self-biasing circuit 13 (start-up and biasing circuit) includes PM16, PM17, NM13 and NM14. These four MOS transistors form a self-biasing current source. The gate voltages of PM16 and PM17 are controlled by feedback from the X node to ensure that the circuit quickly establishes a stable operating point when VCC is powered on.

[0089] Regarding node X, it is a critical feedback point. Based on this feedback point, the conduction state of PM16 / 17 can be adjusted to bring the current mirror circuit 12 into balance.

[0090] The reference voltage generation circuit 11 includes PM16, NM12, NM13, and NM15. The drain of PM16 and the gates of NM12 and NM15 are connected to the VC (reference voltage source) node, forming a common source and common gate structure 110, which increases the output impedance and reduces the impact of VCC (voltage source) fluctuations on VC.

[0091] NM12, NM13, and NM15 form a diode-connected load by shorting their gate and drain (VC node), providing a stable reference voltage.

[0092] The current mirror circuit 12 (current mirror and temperature compensation) includes PM18, PM19, NM16, NM17, and NM18. In the current mirror circuit 12, the drains of PM18 and NM16 are connected to the Y node to provide auxiliary bias and enhance the current mirror matching accuracy; the gates of NM16, NM17, and NM18 are connected to the Z node, suppressing process deviations and temperature drift through multi-stage NMOS mirroring.

[0093] The protection circuit (filtering and noise suppression) includes R7 and R8. R7 is used to limit the source current of PM16 to avoid excessive transient impact. R8, together with NM14 and NM15, forms a voltage divider network to further stabilize the VC voltage.

[0094] When VCC is powered on, PM17, PM18, and PM19 are initially turned on, the voltage at node X is pulled down, PM16 and PM17 are gradually turned on, and the current mirror enters a balanced state.

[0095] When the reference voltage is generated, the VC voltage is determined by the threshold voltage (Vth) of NM12 and NM15 and the current of PM16, and the VC value is locked through negative feedback (X node).

[0096] When stability is maintained, if VC increases due to interference, NM12 and NM15 conduct more strongly, the voltage at node X increases, the current at PM16 and PM17 decreases, and VC drops back, and vice versa.

[0097] This disclosure also provides an electronic device that may include a reference voltage source circuit 10 for providing a reference voltage to a load in the electronic device.

[0098] In one embodiment, the electronic device further includes a power factor correction circuit and a corresponding protection circuit. The protection circuit corresponding to the power factor correction circuit can serve as one of the loads requiring a reference voltage; therefore, the reference voltage source circuit 10 is also used to provide a reference voltage to the protection circuit corresponding to the power factor correction circuit.

[0099] Therefore, the reference voltage source circuit 10 can also serve as part of the protection circuit corresponding to the power factor correction circuit.

[0100] The power factor correction circuit, also known as the PFC (Power Factor Correction) circuit, is commonly found in semiconductor high-voltage drive chips and can be applied in fields such as electric vehicles and home appliances (such as inverter air conditioners).

[0101] The protection circuit can provide overcurrent protection for the PFC circuit, thereby protecting the entire semiconductor high-voltage driver chip.

[0102] Figure 4 This is a schematic diagram illustrating the connection relationship between a reference voltage source circuit 10 and a PFC protection circuit according to an exemplary embodiment, as shown below. Figure 4 As shown, the reference voltage source circuit 10 can be directly connected to both ends of the PFC protection circuit, thereby providing the PFC protection circuit with VC voltage.

[0103] The PFC protection circuit may include two parts: a current feedback amplifier and a hysteresis comparator. The current feedback amplifier may be connected to the reference voltage source circuit 10.

[0104] Figure 5 This is an example circuit structure diagram of a current feedback amplifier according to an exemplary embodiment. Figure 5 In this circuit, the current feedback amplifier includes the following components: PM1, PM2, PM5, PM6, PM7, PM8, NM1, NM2, NM3, NM4, NM5, RM, CM, R1, R2, and R3.

[0105] In this diagram, PM represents a PMOS transistor, with different serial numbers indicating different PMOS transistors; NM represents an NMOS transistor, with different serial numbers indicating different NMOS transistors; R represents a resistor, with different serial numbers indicating different resistors; RM represents a damping resistor; and CM represents a Miller capacitor.

[0106] This circuit structure can form a high-precision, fully differential input current feedback amplifier to process the current sampling signal (VPFCTRIP) of the IGBT in the PFC circuit and convert it into a positive voltage signal (VPFCTRIP1) for output. Its core functions include: linear conversion from negative to positive voltage; high common-mode rejection ratio to suppress power supply and ground noise; and low temperature drift.

[0107] Furthermore, the circuit structure employs a symmetrical power supply and ground layout, and the entire circuit adopts a fully differential structure. The input, amplification, and output stages are all symmetrically designed. This symmetry allows the common-mode noise of the power supply (VCC) and ground (GND) to be canceled in the differential path.

[0108] The input stage (differential input stage) may include PM1, PM2, and NM1. PM1 and PM2 form a PMOS differential pair, with the sources of the two PMOS transistors connected to the tail current source NM1. Their gates receive the differential signals. Common-mode signals exhibit identical variations on both PMOS transistors and are suppressed by the tail current source, effectively suppressing common-mode noise. NM1, acting as a constant-current tail current source, provides a stable bias current, ensuring the differential pair maintains a constant current under common-mode signals, thus enhancing the common-mode rejection ratio.

[0109] Va is provided by NM1; IS1 can characterize the constant tail current; VC represents the voltage regulator, which can be provided by the reference voltage source circuit 10.

[0110] The inverting amplifier stage can include PM6 and PM7, forming a cascode structure to further improve the output impedance, enhance the suppression of common-mode signals, isolate the input stage from the output stage, and reduce the coupling of output stage noise to the input. Furthermore, since its operating point is set by a current source, it is insensitive to temperature-induced changes in device parameters.

[0111] The active load current mirror of the inverting amplifier stage may include NM4 and NM5, which serve as active load current mirrors, providing high gain while maintaining symmetry and helping to suppress common-mode gain.

[0112] The feedback network of the inverting amplifier stage can include R1, R2, and R3. Although the resistors themselves have a temperature coefficient, by using resistors of the same type and process (such as polysilicon resistors), their temperature coefficients are matched, resulting in high ratio stability. The gain of the inverting amplifier stage is A = -R1 / R2, which depends on the ratio of the resistors rather than their absolute values. Therefore, temperature-induced resistance changes are partially offset.

[0113] R1 can be used as a feedback resistor, R2 can be used as an input series resistor, and R3 can be used as a DC bias resistor.

[0114] Compensation networks, which may include CM and RM, can not only achieve frequency compensation and improve circuit stability, but also indirectly improve the common-mode rejection ratio by suppressing high-frequency noise, thereby suppressing power supply and ground noise.

[0115] Push-pull output structures, including PM8 and NM2, provide low impedance output, reduce feedback interference from the output stage to the input stage, and indirectly support high common-mode rejection ratio.

[0116] In this circuit structure, the path of the input current sampling signal is: VPFCTRIP → voltage divider R2 / R3 → gate of PM6 (inverting input). Differential amplification: PM6 / PM7 compares the inverting input signal with the non-inverting input signal (grounded), and outputs a differential current to NM4 / NM5. Feedback control: The output VPFCTRIP1 is fed back to the gate of PM6 through R1, forcing the voltage at the inverting input to 0V (virtual ground). Output drive: The push-pull stage (PM8+NM2) provides high current output.

[0117] It is understandable that in a high-gain amplifier with deep negative feedback, the voltage V- at the inverting input terminal will be automatically adjusted to be infinitely close to the voltage V+ at the non-inverting input terminal. Therefore, in this circuit, V+=0V, V-≈0V, thus achieving a "virtual ground".

[0118] In this circuit structure, the anti-interference capability is significantly improved through a fully differential input stage; and a fast dynamic response is achieved through a current negative feedback structure. Furthermore, the self-biasing technology allows the NM1 (VC bias) and PM5 / PM8 current mirrors to automatically stabilize their operating points without the need for an external reference.

[0119] Figure 6 This is a schematic diagram of a hysteresis comparator circuit structure according to an exemplary embodiment, such as... Figure 6 As shown, the hysteresis comparator includes the following devices: PM9, PM10, PM11, PM12, PM13, PM14, PM15, NM6, NM7, NM8, NM9, NM10, NM11, DZ1, R4, R5, and R6.

[0120] In this designation, PM represents a PMOS transistor (different serial numbers indicate different PMOS transistors), NM represents an NMOS transistor (different serial numbers indicate different NMOS transistors), R represents a resistor (different serial numbers indicate different resistors), and DZ1 represents a diode.

[0121] The function of this hysteresis comparator is to form a hysteresis window through positive feedback to prevent noise from triggering the overcurrent protection function.

[0122] The comparator can include two devices, PM11 and PM12, which can also be called the differential input stage.

[0123] The gate of PM11 is connected to the output stage of the current feedback amplifier as the inverting input, and is connected to the positive voltage signal VPFCTRIP1; the source of PM11 is connected to the IS2 node.

[0124] The gate of PM12 serves as the non-inverting input terminal, connected to the reference voltage signal VREF. The source of PM12 shares the IS2 node with PM11.

[0125] A differential signal can be generated by comparing a fixed threshold reference (VREF) with PM11 using a comparator.

[0126] The reference voltage generation module may include DZ1, R4, and R5. The cathode of DZ1 is connected to the drain of PM13, and the anode is grounded, providing a stable reference voltage (e.g., 3.3V). R4 and R5 form a voltage divider network to set the VREF voltage: VREF = Vz1 × R5 / (R4 + R5), where Vz1 represents the input voltage of the voltage divider network.

[0127] The function of the reference voltage generation module is to adjust the comparator trigger threshold to adapt to different overcurrent protection requirements.

[0128] The hysteresis feedback network includes NM9, PM15, and NM11. In the hysteresis feedback network, the gate of NM9 is controlled by VOUT (the drain of PM15 / NM11), and the drain is connected to the R5 / R6 node. When the output V0 changes, NM9 changes the voltage divider of R5 / R6, dynamically adjusting VREF to form a hysteresis window. For example: V0 goes high - VOUT goes low - NM9 turns off - VREF rises, increasing the threshold for triggering the next overcurrent protection.

[0129] Furthermore, PM15 and NM11 form an inverter to convert the V0 signal into VOUT, controlling the switching state of NM9.

[0130] The output circuit may include PM14 and NM10. PM14's gate is connected to Vb, and its drain, along with NM10, drives the output V0. NM10's gate is controlled by NM8, and its drain, along with PM14, forms a complementary output.

[0131] Through the output circuit, a protection signal (V0) with low impedance and high speed can be output, which can directly drive the protection pin of the PFC control chip.

[0132] Regarding the bias circuit, it includes: PM9, PM10, PM13 and NM6. Among them, the sources of PM9, PM10 and PM13 are connected to VCC, and the gates are connected to Vb (provided by the drain of NM6), forming a current mirror, whose function is to provide a constant bias current for the differential pair (PM11 / PM12).

[0133] In addition, the gate of NM6 is connected to VC (reference voltage source circuit 10), the source is grounded, and the drain generates Vb, whose function is to stabilize the bias voltage and suppress the influence of power supply fluctuations.

[0134] In this hysteresis comparator, the initial state is: VPFCTRIP1 < VREF. In this state, PM11 conducts weaker than PM12, NM8 is turned off, and V0 outputs a high level (≈VCC). VOUT (the drain of PM15 / NM11) is at a low level, NM9 is turned off, and VREF maintains its initial value.

[0135] The triggered overcurrent protection state is: VPFCTRIP1 > VREF. In this state, PM11 conducts stronger than PM12, NM8 conducts, V0 jumps to a low level (≈0V), VOUT becomes a high level, NM9 conducts, pulling down the voltage of the R5 / R6 node, and reducing VREF. At this time, it is necessary that VPFCTRIP1 < (VREF - AV) to return to the initial state, forming a hysteresis window AV. <​​​​​​​​​​​​​​​​The beneficial effects of using this circuit structure include at least the following:

[0140] High stability: The self-biased structure reduces dependence on VCC fluctuations and significantly improves the power supply rejection ratio.

[0141] Low temperature drift: The threshold voltage temperature coefficient of NMOS / PMOS is partially offset, and the VC drift range is better than the resistive voltage divider scheme of related technologies.

[0142] Strong anti-interference capability: The common source and common gate structure and current mirror design suppress high-frequency noise, making it suitable for high-noise environments.

[0143] Low power consumption: The quiescent current is controlled by resistors R7 and R8 and MOS size optimization, resulting in power consumption lower than that of a bandgap reference source.

[0144] It should be understood that, unless otherwise specifically indicated, features of various embodiments of this disclosure described herein can be combined with each other. As used herein, the term “and / or” includes any one of the relevant listed items and any combination of any two or more; similarly, “at least one of…” includes any one of the relevant listed items and any combination of any two or more.

[0145] It should be understood that, unless otherwise expressly specified and limited, the terms "joining," "attaching," "installing," "connecting," "linking," "fixing," etc., used in the embodiments of this disclosure should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms herein based on the specific circumstances.

[0146] Furthermore, the term “exemplary” is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “exemplary” is not necessarily to be construed as advantageous compared to other aspects or designs. Rather, the use of the term “exemplary” is intended to present the concept in a concrete manner. As used herein, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise specified or clear from the context, “X applies A or B” is intended to mean any of the natural inclusive arrangements. That is, “X applies A or B” satisfies any of the foregoing instances if X applies A; X applies B; or both X applies A and B. Additionally, unless otherwise specified or clear from the context to refer to the singular form, the articles “a” and “an” as used in this application and the appended claims are generally understood to mean “one or more.”

[0147] Similarly, although this disclosure has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. This disclosure includes all such modifications and variations and is limited only by the scope of the claims. In particular, with respect to the various functions performed by the components described above (e.g., elements, resources, etc.), unless otherwise indicated, the terminology used to describe such components is intended to correspond to any component (functionally equivalent) that performs the specific function of the described component, even if structurally not equivalent to the disclosed structure. Furthermore, although specific features of this disclosure may have been disclosed with respect to only one of several implementations, such features may be combined with one or more other features of other implementations, as may be desired and advantageous to any given or particular application. Moreover, with regard to the terms “comprising,” “owning,” “having,” “having,” or variations thereof as used in the detailed description or claims, such terms are intended to be inclusive in a manner similar to the term “including.”

[0148] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

[0149] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A reference voltage source circuit, characterized in that, include: A reference voltage generation circuit, connected to a voltage source, is used to output a reference voltage; A current mirror circuit is connected to the reference voltage generation circuit. A self-biasing circuit is provided, with one end connected to the reference voltage generation circuit and the other end connected to the current mirror circuit. The self-biasing circuit is used to adjust the reference voltage output by the reference voltage generation circuit according to the balance state of the current mirror circuit.

2. The reference voltage source circuit according to claim 1, characterized in that, The reference voltage generation circuit includes: A common source cascode structure, one end of which is connected to the voltage source, is used to increase the output impedance of the reference voltage generation circuit; A load circuit, one end of which is connected to the other end of the common source and common gate structure, and the other end of which is grounded, is used to output a reference voltage.

3. The reference voltage source circuit according to claim 2, characterized in that, The common-source, common-gate structure includes: at least one PMOS transistor and at least two NMOS transistors, wherein the drain of the at least one PMOS transistor and the gate of the at least two NMOS transistors are both connected to the same circuit node.

4. The reference voltage source circuit according to claim 2, characterized in that, The load circuit includes at least two NMOS transistors, with the gate and drain of each NMOS transistor shorted together.

5. The reference voltage source circuit according to claim 1, characterized in that, The current mirror circuit includes at least two PMOS transistors and at least two NMOS transistors. The drain of one of the PMOS transistors and the drain of one of the NMOS transistors are connected to the same circuit node, and the gates of the at least two NMOS transistors are connected to the same circuit node, forming a multi-level NMOS mirror structure.

6. The reference voltage source circuit according to claim 1, characterized in that, The self-biasing circuit includes: at least two PMOS transistors and at least two NMOS transistors; The gates of at least two PMOS transistors and one of the at least two NMOS transistors are connected to a target circuit node, which is connected to the current mirror circuit. The self-biasing circuit is used to adjust the conduction state of at least two PMOS transistors according to the voltage of the target circuit node, so as to adjust the reference voltage output by the reference voltage generation circuit.

7. The reference voltage source circuit according to any one of claims 1 to 6, characterized in that, The reference voltage source circuit further includes a protection circuit, which is connected to the reference voltage generation circuit and / or the self-biasing circuit, and is used to protect the reference voltage source circuit.

8. The reference voltage source circuit according to claim 7, characterized in that, The protection circuit includes a current-limiting resistor connected to the reference voltage generation circuit and / or the self-biasing circuit, used to limit the input current of the reference voltage generation circuit and / or the self-biasing circuit.

9. The reference voltage source circuit according to claim 7, characterized in that, The protection circuit includes a voltage divider resistor connected to the reference voltage generation circuit and / or the self-biasing circuit, for stabilizing the reference voltage output by the reference voltage generation circuit.

10. An electronic device, characterized in that, include: The reference voltage source circuit according to any one of claims 1 to 9, wherein the reference voltage source circuit is used to provide a reference voltage for the load in the electronic device.

11. The electronic device according to claim 10, characterized in that, The electronic device further includes a power factor correction circuit and a protection circuit corresponding to the power factor correction circuit. The reference voltage source circuit is also used to provide a reference voltage for the protection circuit corresponding to the power factor correction circuit.

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