Communication method and system based on IIC communication program, terminal and storage medium
By monitoring the changes in the SDA pin level in real time and configuring a timer delay strategy to mask interrupts, the problem of nested interrupts in IIC communication is solved, achieving IIC communication with high stability and high response performance, suitable for various MCU systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHUHAI DERUNTANG ELECTRONIC TECH CO LTD
- Filing Date
- 2025-12-30
- Publication Date
- 2026-04-21
AI Technical Summary
In existing technologies, IIC communication is susceptible to interrupt nesting interference in MCU multi-interrupt systems, resulting in poor communication stability, low response speed, and insufficient compatibility.
By monitoring the changes in the SDA pin level in real time, the IIC communication program is triggered, and a timer delay strategy is configured to shield non-critical interrupt signals. The core logic of IIC communication is executed, and the communication process is forcibly exited after the timer delay ends.
Completely eliminates nested interrupts during IIC communication, reduces bit error rate, improves communication stability and response performance, and has strong compatibility, adapting to various MCU systems.
Smart Images
Figure CN121901130A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of sensor communication technology, and in particular to a communication method, system, terminal and storage medium based on IIC communication program. Background Technology
[0002] Inter-chip communication (IIC) is a core protocol for data interaction between chips in embedded systems, widely used in communication scenarios between MCUs and sensors, memory chips, and peripheral interfaces. In MCU multi-interrupt systems, IIC communication relies on precise timing control. However, interrupt nesting (e.g., timer interrupts or UART interrupts preempting IIC communication timing) can cause abnormal SCL / SDA pin level transitions, leading to data transmission errors. Especially in scenarios with intensive real-time tasks, frequent interrupt nesting severely impacts the stability of IIC communication.
[0003] Existing solutions to IIC communication interruption interference mainly fall into two categories: disabling global interrupts and configuring interrupt priorities. While disabling global interrupts can avoid nesting, it will block other critical interrupts, thus affecting the overall real-time performance of the system. On the other hand, configuring interrupt priorities can only avoid preemption by low-priority interrupts, but cannot prevent interference from interrupts of the same or higher priority, and it does not have a protection mechanism designed for the special characteristics of IIC communication timing.
[0004] Therefore, the existing technology still suffers from problems such as low overall system response speed, poor communication stability, and insufficient compatibility, and the technology needs further improvement. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to provide a communication method, system, terminal and storage medium based on IIC communication program to address the shortcomings of the prior art, thereby solving the problems of low overall system response speed, poor communication stability and insufficient compatibility in the prior art.
[0006] The technical solution adopted by this invention to solve the technical problem is as follows: In a first aspect, the present invention provides a communication method based on an IIC communication program, comprising: The system monitors the level changes of the SDA pin in real time, and triggers the IIC communication program when a level change of the SDA pin is detected. Based on the IIC communication program, a timer delay strategy is configured, all non-critical interrupt signals are masked according to the timer delay strategy, and the core IIC communication logic is executed. When the timer delay policy expires, the communication process is forcibly terminated.
[0007] In one implementation, the real-time monitoring of the SDA pin's level change information, when a change in the SDA pin's level is detected, triggers an IIC communication program, including: Configure the signal mode corresponding to the SDA pin as a double-edge triggered interrupt mode; Real-time detection of the rising edge and falling edge level signals of the SDA pin; Based on the rising edge level signal and the falling edge level signal, determine whether the level of the SDA pin has changed; When the level of the SDA pin changes, an interrupt response is immediately triggered, and the process jumps to the IIC communication program.
[0008] In one implementation, configuring a timer delay strategy based on the IIC communication program, and masking all non-critical interrupt signals according to the timer delay strategy, includes: Based on the IIC communication program, the current system timer count is read, the target count after the target delay time is calculated, the timer comparison register information is updated, and the timer delay strategy is obtained. Based on the timer delay strategy, during the target delay time, all non-critical interrupt signals are masked by the MCU interrupt controller, while system fault interrupt signals are retained.
[0009] In one implementation, the step of shielding all non-critical interrupt signals by the MCU interrupt controller while retaining system fault interrupt signals includes: Record the system interrupt state before entering communication, and use the recorded system interrupt state as the system recovery state when exiting communication.
[0010] In one implementation, the execution of the IIC communication core logic includes: During the target delay time, the IIC communication core logic is executed; wherein, the execution of the IIC communication core logic includes: start signal generation, device address transmission, data read / write, response detection, and stop signal generation; A 64-byte data buffer is set up. During batch read and write operations, the data is buffered first and then transmitted continuously in sequence to ensure that regular data transmission is completed within the target delay time.
[0011] In one implementation, the step of forcibly exiting the communication process when the timer delay policy ends includes: The timer interrupt signal is used to monitor whether the current delay time has reached the target delay time; When the target delay time is reached, a timeout interrupt signal is triggered; Terminate the IIC communication process, stop the SCL / SDA pin level control, and restore the pins to their initial state.
[0012] In one implementation, terminating the IIC communication process, stopping the SCL / SDA pin level control, and restoring the pin to its initial state, then includes: Based on the recorded system interrupt status, enable all non-critical interrupt signals to ensure that other communication tasks in the system operate normally.
[0013] Secondly, the present invention provides a communication system based on an IIC communication program, comprising: The trigger detection module is used to monitor the level change information of the SDA pin in real time. When the level change of the SDA pin is detected, the IIC communication program is triggered. Interrupt protection module is used to configure timer delay strategy based on the IIC communication program and to block all non-critical interrupt signals according to the timer delay strategy; The communication execution module is used to execute the core logic of IIC communication; The timeout handling module is used to force the communication process to terminate when the timer delay strategy ends.
[0014] Thirdly, the present invention provides a terminal, comprising: a processor and a memory, wherein the memory stores a communication program based on an IIC communication program, and the communication program based on the IIC communication program, when executed by the processor, is used to implement the operation of the communication method based on the IIC communication program as described in the first aspect.
[0015] Fourthly, the present invention also provides a computer-readable storage medium storing a communication program based on an IIC communication program, which, when executed by a processor, is used to implement the operation of the communication method based on the IIC communication program as described in the first aspect.
[0016] The present invention, by employing the above technical solution, has the following effects: This invention completely eliminates nested interrupts during IIC communication by using SDA triggering and timer delay protection, thereby reducing the communication error rate and improving the stability of the communication system. It also avoids communication dead loops by using a forced exit mechanism, and only blocks non-critical interrupts during communication, thereby improving the response performance of the communication system. Furthermore, it can be ported without modifying the core logic, thus improving compatibility. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0018] Figure 1 This is a flowchart of the communication method based on the IIC communication program in this invention.
[0019] Figure 2 This is a functional schematic diagram of the terminal in one implementation of the present invention.
[0020] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0021] To make the objectives, technical solutions, and advantages of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
[0022] Exemplary methods Existing solutions to IIC communication interruption interference mainly fall into two categories: disabling global interrupts and configuring interrupt priorities. While disabling global interrupts can avoid nesting, it will block other critical interrupts, thus affecting the overall real-time performance of the system. On the other hand, configuring interrupt priorities can only avoid preemption by low-priority interrupts, but cannot prevent interference from interrupts of the same or higher priority, and it does not have a protection mechanism designed for the special characteristics of IIC communication timing.
[0023] Therefore, the disadvantages of existing technology are: 1) Interrupt nesting cannot be completely eliminated: Priority configuration alone cannot completely prevent critical interrupts from preempting IIC timing, leading to communication timing disorder; 2) Impaired system real-time performance: Disabling global interrupts will block other important tasks and affect the overall system response speed; 3) Poor communication fault tolerance: No forced exit mechanism is designed. If IIC communication gets stuck in an infinite loop due to an anomaly, it will lead to permanent communication blockage. 4) Poor adaptability: The solution is tied to the MCU interrupt controller, and different architecture MCUs need to be redesigned, resulting in insufficient compatibility.
[0024] To address the above technical problems, this invention provides a communication method based on an IIC communication program. The method includes: real-time monitoring of SDA pin level changes; triggering an IIC communication program when a level change is detected on the SDA pin; configuring a timer delay strategy based on the IIC communication program; blocking all non-critical interrupt signals according to the timer delay strategy; and executing the core IIC communication logic; forcibly exiting the communication process when the timer delay strategy ends. This invention, through SDA triggering and timer delay protection, completely eliminates interrupt nesting during IIC communication, reduces the communication error rate, and improves the stability of the communication system. Furthermore, the forced exit mechanism avoids communication deadlocks, blocks non-critical interrupts only during communication, improves the response performance of the communication system, and can be ported without modifying the core logic, thus improving compatibility.
[0025] like Figure 1 As shown, this embodiment of the invention provides a communication method based on an IIC communication program, comprising the following steps: Step S100: Monitor the level change information of the SDA pin in real time. When the level of the SDA pin changes, trigger the IIC communication program.
[0026] In this embodiment, a communication method based on an IIC communication program is proposed. This method is a highly reliable IIC communication implementation method that prevents nested interrupts. The core of this method is "SDA change triggering + timer delay protection + forced exit mechanism". When the SDA pin level changes (triggers a critical node in IIC communication), the dedicated IIC processing program is immediately entered, and the system timer is delayed by 50ms. During the 50ms delay, all non-critical interrupts are blocked to avoid nested interrupts interfering with IIC timing. After the 50ms delay ends, regardless of whether IIC communication is completed, the communication process is forcibly exited, and the system interrupt normal state is restored, ensuring that the communication process does not block the system and that IIC timing is not disturbed.
[0027] To implement the above method, this embodiment also provides a communication implementation architecture, which includes: a trigger detection layer, an interrupt protection layer, a communication execution layer, and a timeout handling layer. This four-layer collaboration achieves highly reliable IIC communication with anti-interruption nesting. The trigger detection layer is used to monitor changes in the SDA pin level in real time and trigger the IIC processing program; the interrupt protection layer is used to shield non-critical interrupts and avoid nesting by delaying for 50ms using a timer; the communication execution layer is used to execute the core IIC communication logic within the protection period (50ms); and the timeout handling layer is used to forcibly terminate communication and restore the system state after 50ms.
[0028] The overall architecture is based on "SDA triggering + delay protection" to balance communication stability and system real-time performance.
[0029] In this embodiment, based on the trigger detection layer described above, the level change information of the SDA pin is monitored in real time. When a change in the level of the SDA pin is detected, the IIC communication program is immediately triggered.
[0030] Specifically, in one implementation of this embodiment, step S100 includes the following steps: Step S101: Configure the signal mode corresponding to the SDA pin as a double-edge triggered interrupt mode; Step S102: Real-time detection of the rising edge level signal and falling edge level signal of the SDA pin; Step S103: Determine whether the level of the SDA pin has changed based on the rising edge level signal and the falling edge level signal; In step S104, when the level of the SDA pin changes, an interrupt response is immediately triggered, and the process jumps to the IIC communication program.
[0031] In this embodiment, the SDA level is monitored by configuring the SDA pin in a double-edge triggered interrupt mode to detect the rising and falling edges of the pin level in real time (corresponding to key nodes such as the start, stop, and data bit changes in IIC communication). The IIC communication program is triggered by immediately triggering an interrupt response when a change in the SDA level is detected, jumping to the dedicated IIC processing program to ensure the timing integrity of key communication nodes.
[0032] As an example, in a practical application scenario, this embodiment configures the SDA pin to a dual-edge triggered interrupt mode. The SDA pin is configured as follows: the SDA pin is set to input mode via the GPIO configuration register, and the dual-edge interrupt function is enabled. After configuring the SDA pin, a dedicated IIC interrupt handler is written to immediately trigger an interrupt response when a change in the SDA level is detected. Within the interrupt handler, the type of level change (rising edge or falling edge) is determined by reading the GPIO status register.
[0033] Specifically, in the interrupt handler, the corresponding IIC communication operation is performed according to the level change type, as shown below: 1) Rising edge: Handles IIC start conditions or data bit changes.
[0034] 2) Falling edge: Handles IIC stop conditions or data bit changes.
[0035] This embodiment manages the IIC communication status through a state mechanism to ensure timing integrity.
[0036] When writing the interrupt handlers described above, the interrupt response time must be less than the IIC communication timing requirements to ensure real-time detection of critical nodes.
[0037] Furthermore, error detection mechanisms can be added to the interrupt handler, such as triggering the error handling process when an abnormal level change is detected; and the status of key nodes can be recorded through logging to facilitate debugging and fault analysis. In addition to adding error detection mechanisms, hardware debouncing circuits can be used to reduce false triggers and improve the reliability of level change detection, thereby optimizing the interrupt handler logic, reducing resource consumption, and ensuring the normal operation of other system functions.
[0038] like Figure 1 As shown, this embodiment of the invention provides a communication method based on an IIC communication program, comprising the following steps: Step S200: Configure a timer delay strategy based on the IIC communication program, block all non-critical interrupt signals according to the timer delay strategy, and execute the IIC communication core logic.
[0039] In this embodiment, based on the above-mentioned interrupt protection layer, the IIC communication program is used to configure a timer delay strategy, which can block all non-critical interrupt signals according to the timer delay strategy to achieve the interrupt protection function; and based on the above-mentioned communication execution layer, the IIC communication core logic is executed to ensure that the normal data transmission is completed within the delay time.
[0040] Specifically, in one implementation of this embodiment, step S200 includes the following steps: Step S201: Based on the IIC communication program, read the current system timer count, calculate the target count after the target delay time, update the timer comparison register information, and obtain the timer delay strategy; Step S202: Based on the timer delay strategy, during the target delay time, all non-critical interrupt signals are shielded by the MCU interrupt controller, while system fault interrupt signals are retained; Step S203: Record the system interruption state before entering communication, and use the recorded system interruption state as the system recovery state when exiting communication.
[0041] In this embodiment, the timer delay is configured in the interrupt protection layer as follows: after entering the IIC processing program, the current system timer count is read, the target count after a 50ms delay is calculated, and the timer comparison register is updated to achieve a 50ms delay.
[0042] The interrupt masking logic is as follows: During the delay period, all non-critical interrupts (e.g., UART interrupts, SPI interrupts) are masked by the MCU interrupt controller, and only system fault interrupts (e.g., power failure interrupts) are retained, so as to avoid interrupt nesting from interfering with IIC timing.
[0043] The state latching method is to record the system interrupt state before entering communication, providing a basis for restoring the state upon exit.
[0044] In this embodiment, updating the timer compare register and setting the target count as the timer interrupt trigger point enables a precise 50ms delay, avoiding software delay accuracy issues. During the delay, all non-critical interrupts are masked by the MCU interrupt controller, retaining only system fault interrupts to prevent interrupt nesting from interfering with IIC timing and ensuring communication reliability. Furthermore, by recording the system interrupt state before entering communication and utilizing a state latching mechanism, interrupt configuration conflicts are avoided, improving system robustness.
[0045] In this embodiment, the delay is triggered by a timer interrupt to ensure accurate timing; during the interrupt masking period, the system clock remains stable to avoid timing jitter; after the delay ends, the system timing returns to normal to ensure the reliability of subsequent operations.
[0046] Specifically, in one implementation of this embodiment, step S200 further includes the following steps: Step S204: During the target delay time, execute the IIC communication core logic; wherein, the execution of the IIC communication core logic includes: start signal generation, device address transmission, data read / write, response detection, and stop signal generation; Step S205: Set up a 64-byte data buffer. During batch read and write operations, the data is buffered first and then transmitted continuously in sequence to ensure that regular data transmission is completed within the target delay time.
[0047] In this embodiment, the timing control method in the communication execution layer is as follows: within a 50ms protection period, the core IIC communication logic is executed. This core logic includes: start signal generation, device address transmission, data read / write, acknowledgment detection, and stop signal generation. During the execution of the core IIC communication logic, the IIC protocol timing is strictly followed. Simultaneously with timing control, data caching is implemented by setting a 64-byte data buffer. During batch read / write operations, data is cached first and then transmitted continuously according to the timing sequence, improving communication efficiency and ensuring that regular data transmission is completed within 50ms.
[0048] like Figure 1 As shown, this embodiment of the invention provides a communication method based on an IIC communication program, comprising the following steps: Step S300: When the timer delay strategy ends, the communication process is forcibly terminated.
[0049] In this embodiment, based on the timeout processing layer described above, the communication process can be forcibly terminated when the timer delay strategy ends, ensuring that other system tasks run normally.
[0050] Specifically, in one implementation of this embodiment, step S300 includes the following steps: Step S301: Monitor whether the current delay time has reached the target delay time through the timer interrupt signal; Step S302: When the target delay time is reached, a timeout interrupt signal is triggered; Step S303: Terminate the IIC communication process, stop the SCL / SDA pin level control, and restore the pin to its initial state; Step S304: Based on the recorded system interrupt status, restore the enabling of all non-critical interrupt signals to ensure the normal operation of other communication tasks in the system.
[0051] In this embodiment, the timeout detection method in the timeout processing layer is as follows: the timeout is monitored by a timer interrupt to see if the 50ms delay has ended. When the timer count reaches the target value, a timeout interrupt is triggered. The forced exit method is as follows: the IIC communication process is terminated immediately after the timeout, the SCL / SDA pin level control is stopped, and the pin initial state is restored. The system recovery method is as follows: based on the latched interrupt status, restore the enabling of all non-critical interrupts to ensure the normal operation of other system tasks.
[0052] In this embodiment, the current IIC communication process is terminated immediately after a timeout interrupt is triggered. By stopping the level control of the SDA pin, the pin can be set to the default input state. Furthermore, clearing the IIC controller status register and resetting the communication state machine releases control of the IIC bus and avoids bus lock-in.
[0053] This embodiment can restore the enable state of non-critical interrupts one by one according to the pre-latched interrupt states; by restoring peripheral interrupts such as UART, SPI, and ADC, it ensures the normal operation of other system tasks. It also clears the timeout flag to prepare for the next IIC communication. Recording timeout error logs facilitates system debugging and fault analysis.
[0054] As an example, in a practical application scenario, the interrupt recovery logic that can be adopted in this embodiment is as follows: 1) After the delay ends, restore the system interrupt status according to the state latch.
[0055] 2) Prioritize the recovery of critical interrupts (such as UART and SPI interrupts) to ensure normal system function.
[0056] 3) Finally, restore system fault interruptions (such as abnormal power interruptions) to ensure system safety.
[0057] In one implementation, the core process and code example of the technical solution provided in this embodiment are as follows: (1) Core communication process: S1, initialize the SDA pin as a double-edge triggered interrupt, and configure the system timer; S2 detects a change in the SDA level, triggers an interrupt, and enters the IIC processing routine; S3 records the current interrupt status, disables non-critical interrupts, and sets the timer delay to 50ms. S4 executes IIC communication logic (e.g., address transmission, data read / write, etc.). S5 checks if a timeout has occurred; if communication is completed within 50ms, actively exits and resumes interruption; if a timeout occurs, the timer triggers a forced exit and restores the system state.
[0058] (2) Core code example (SDA triggering and timer delay) / / SDA level change interrupt service function (triggers IIC handler) void SDA_IRQHandler(void) { if(SDA_LEVEL==0) / / Detect SDA level changing from high to low { IIC_Comm_Flag = 1; / / Set the communication flag Save_Interrupt_State(); / / Save the current interrupt state Disable_Non_Critical_Interrupts(); / / Disables non-critical interrupts / / Timer delay 50ms: Calculate the target count and update the timer. uint32_t current_cnt = TIM_GetCounter(TIM3); uint32_t target_cnt = current_cnt + (SystemCoreClock / 1000) * 50; / / 50ms delay TIM_SetCompare1(TIM3, target_cnt); TIM_EnableIT(TIM3, TIM_IT_CC1); / / Enable timer compare interrupt (timeout detection) IIC_Communication_Process(); / / Perform IIC communication processing } } This embodiment uses SDA level changes to trigger dedicated processing: using changes in SDA level as the trigger condition for IIC communication, it accurately captures key communication nodes and ensures the accuracy of timing startup.
[0059] This embodiment achieves effective protection through a 50ms timer delay: during communication, non-critical interrupts are shielded by a timer delay, thus avoiding interrupt nesting at the source and ensuring that the IIC timing is not disturbed.
[0060] This embodiment employs a forced exit mechanism, which forcibly terminates communication after a 50ms timeout to avoid system blockage caused by abnormalities and improve system fault tolerance.
[0061] This embodiment adopts a lossless recovery method for interrupted states, saving and restoring the system interrupted state before and after communication, thus balancing communication stability and system real-time performance.
[0062] Compared to existing technical solutions, this embodiment completely eliminates nested interrupts during IIC communication through SDA triggering and timer delay protection, resulting in a reduced communication error rate and a 100% improvement in stability. Furthermore, by employing a 50ms forced exit mechanism, it avoids communication dead loops, significantly enhancing system reliability. Moreover, the solution provided in this embodiment does not require disabling global interrupts; it only masks non-critical interrupts during communication, keeping the system's real-time performance loss to within 5%. Finally, the solution provided in this embodiment is compatible with mainstream 8-bit / 32-bit MCUs, allowing for portability without modifying core logic, thus enhancing compatibility. Furthermore, the communication rate remains consistent with traditional solutions, balancing reliability and efficiency.
[0063] It is worth mentioning that, based on the above technical solution, this embodiment can be improved as follows according to the actual application scenario: 1) Adaptive delay parameter: The timer delay time is dynamically adjusted according to the IIC communication rate and data length (e.g., 10ms~100ms is configurable) to adapt to different communication scenarios.
[0064] 2) Critical interrupt classification: System interrupts are classified into core level, critical level, and normal level. Only normal level interrupts are disabled, while core level and critical level interrupts are retained to further improve system real-time performance.
[0065] 3) Multi-master device adaptation: Extend the bus arbitration logic to realize multi-master device conflict detection and processing during the timer delay protection period, adapting to multi-master communication scenarios.
[0066] 4) Low power optimization: During the delay period, the MCU enters a shallow sleep mode, keeping only IIC communication and timer-related modules working, thereby reducing system power consumption.
[0067] 5) Communication breakpoint resume: Records the communication progress before forced exit, and resumes transmission from the breakpoint when triggered again, improving the efficiency of long data transmission.
[0068] In summary, the embodiments of this invention are suitable for scenarios with high requirements for IIC communication stability, such as industrial control, smart sensors, and smart homes, and are particularly suitable for MCU systems with multiple interrupts and high real-time requirements. Future development can further optimize the SDA level detection algorithm and introduce an anti-jitter mechanism to avoid false communication triggers due to level jitter. Simultaneously, a matching timing calibration tool can be developed to dynamically optimize timer delay parameters based on the clock characteristics and communication rates of different MCUs, further improving timing accuracy.
[0069] Furthermore, adaptation to high-speed IIC protocols (e.g., IIC Fast-mode Plus) can be explored to optimize the timing logic of the communication execution layer and achieve higher data transmission rates within a 50ms protection period. The method of this embodiment can also be combined with DMA transmission to reduce CPU involvement in data handling, improve communication efficiency, and reduce the impact of interrupt nesting on CPU usage, achieving a dual improvement in stability and efficiency.
[0070] This embodiment achieves the following technical effects through the above technical solution: This embodiment completely eliminates nested interrupts during IIC communication through SDA triggering and timer delay protection, reducing the communication error rate and improving the stability of the communication system; and avoids communication dead loops through a forced exit mechanism, only blocking non-critical interrupts during communication, improving the response performance of the communication system, and can be ported without modifying the core logic, thus improving compatibility.
[0071] Exemplary device Based on the above embodiments, the present invention also provides a communication system based on an IIC communication program, comprising: The trigger detection module is used to monitor the level change information of the SDA pin in real time. When the level change of the SDA pin is detected, the IIC communication program is triggered. Interrupt protection module is used to configure timer delay strategy based on the IIC communication program and to block all non-critical interrupt signals according to the timer delay strategy; The communication execution module is used to execute the core logic of IIC communication; The timeout handling module is used to force the communication process to terminate when the timer delay strategy ends.
[0072] This embodiment achieves the following technical effects through the above technical solution: This embodiment completely eliminates nested interrupts during IIC communication through SDA triggering and timer delay protection, reducing the communication error rate and improving the stability of the communication system; and avoids communication dead loops through a forced exit mechanism, only blocking non-critical interrupts during communication, improving the response performance of the communication system, and can be ported without modifying the core logic, thus improving compatibility.
[0073] Based on the above embodiments, the present invention also provides a terminal, the principle block diagram of which can be as follows: Figure 2 As shown.
[0074] The terminal includes: a processor, a memory, an interface, a display screen, and a communication module connected via a system bus; wherein, the processor of the terminal provides computing and control capabilities; the memory of the terminal includes a computer-readable storage medium and internal memory; the computer-readable storage medium stores an operating system and computer programs; the internal memory provides an environment for the operation of the operating system and computer programs in the computer-readable storage medium; the interface is used to connect to external devices; the display screen is used to display relevant information; and the communication module is used to communicate with a cloud server or other devices.
[0075] When executed by the processor, this computer program is used to implement the communication method based on the IIC communication program.
[0076] It will be understood by those skilled in the art that Figure 2 The schematic diagram shown is only a partial structural diagram related to the present invention and does not constitute a limitation on the terminal to which the present invention is applied. A specific terminal may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.
[0077] In one embodiment, a terminal is provided, comprising: a processor and a memory, the memory storing a communication program based on an IIC communication program, which, when executed by the processor, is used to implement the above-described communication method based on the IIC communication program.
[0078] In one embodiment, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a communication program based on an IIC communication program, which, when executed by a processor, is used to implement the operation of the communication method based on the IIC communication program as described above.
[0079] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, database, or other media used in the embodiments provided by this invention can include both non-volatile and volatile memory.
[0080] In summary, this invention provides a communication method, system, terminal, and storage medium based on an IIC communication program, comprising: real-time monitoring of the level change information of the SDA pin; triggering the IIC communication program when a level change of the SDA pin is detected; configuring a timer delay strategy based on the IIC communication program; shielding all non-critical interrupt signals according to the timer delay strategy; and executing the core IIC communication logic; and forcibly exiting the communication process when the timer delay strategy ends. This invention, through SDA triggering and timer delay protection, completely eliminates interrupt nesting during IIC communication, reduces the communication error rate, and improves the stability of the communication system; and avoids communication deadlocks through the forced exit mechanism, shielding non-critical interrupts only during communication, improving the response performance of the communication system, and can be ported without modifying the core logic, thus improving compatibility.
[0081] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.
Claims
1. A communication method based on an IIC communication program, characterized in that, include: The system monitors the level changes of the SDA pin in real time, and triggers the IIC communication program when a level change of the SDA pin is detected. Based on the IIC communication program, a timer delay strategy is configured, all non-critical interrupt signals are masked according to the timer delay strategy, and the core IIC communication logic is executed. When the timer delay policy expires, the communication process is forcibly terminated.
2. The communication method based on the IIC communication program according to claim 1, characterized in that, The real-time monitoring of SDA pin level changes triggers an IIC communication program when a level change is detected, including: Configure the signal mode corresponding to the SDA pin as a double-edge triggered interrupt mode; Real-time detection of the rising edge and falling edge level signals of the SDA pin; Based on the rising edge level signal and the falling edge level signal, determine whether the level of the SDA pin has changed; When the level of the SDA pin changes, an interrupt response is immediately triggered, and the process jumps to the IIC communication program.
3. The communication method based on the IIC communication program according to claim 1, characterized in that, The configuration of the timer delay strategy based on the IIC communication program, and the blocking of all non-critical interrupt signals according to the timer delay strategy, includes: Based on the IIC communication program, the current system timer count is read, the target count after the target delay time is calculated, the timer comparison register information is updated, and the timer delay strategy is obtained. Based on the timer delay strategy, during the target delay time, all non-critical interrupt signals are masked by the MCU interrupt controller, while system fault interrupt signals are retained.
4. The communication method based on the IIC communication program according to claim 3, characterized in that, The process involves shielding all non-critical interrupt signals through the MCU interrupt controller, while retaining system fault interrupt signals, and then includes: Record the system interrupt state before entering communication, and use the recorded system interrupt state as the system recovery state when exiting communication.
5. The communication method based on the IIC communication program according to claim 3, characterized in that, The execution of the IIC communication core logic includes: During the target delay time, the IIC communication core logic is executed; wherein, the execution of the IIC communication core logic includes: start signal generation, device address transmission, data read / write, response detection, and stop signal generation; A 64-byte data buffer is set up. During batch read and write operations, the data is buffered first and then transmitted continuously in sequence to ensure that regular data transmission is completed within the target delay time.
6. The communication method based on the IIC communication program according to claim 1, characterized in that, The step of forcibly exiting the communication process when the timer delay policy ends includes: The timer interrupt signal is used to monitor whether the current delay time has reached the target delay time; When the target delay time is reached, a timeout interrupt signal is triggered; Terminate the IIC communication process, stop the SCL / SDA pin level control, and restore the pins to their initial state.
7. The communication method based on the IIC communication program according to claim 6, characterized in that, The termination of the IIC communication process, stopping the SCL / SDA pin level control, and restoring the pins to their initial state, then includes: Based on the recorded system interrupt status, enable all non-critical interrupt signals to ensure that other communication tasks in the system operate normally.
8. A communication system based on the IIC communication program, characterized in that, include: The trigger detection module is used to monitor the level change information of the SDA pin in real time. When the level change of the SDA pin is detected, the IIC communication program is triggered. The interrupt protection module is used to configure a timer delay strategy based on the IIC communication program and to block all non-critical interrupt signals according to the timer delay strategy. The communication execution module is used to execute the core logic of IIC communication; The timeout handling module is used to force the communication process to terminate when the timer delay strategy ends.
9. A terminal, characterized in that, include: The processor and the memory, wherein the memory stores a communication program based on the IIC communication program, which, when executed by the processor, is used to implement the operation of the communication method based on the IIC communication program as described in any one of claims 1-7.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a communication program based on an IIC communication program, which, when executed by a processor, is used to implement the operation of the communication method based on an IIC communication program as described in any one of claims 1-7.