Memory device, memory device, and operating method of

Abstract

The invention relates to a memory device, a storage device, and an operating method of the storage device. A memory device includes: a plurality of blocks, each block including memory cells; and a control circuit configured to enable a blind erase option and perform a blind erase operation on a target block among the plurality of blocks. During the blind erase operation, the control circuit is configured to perform an erase pulse application operation on the target block without performing an erase verify operation on the target block.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Application No. 10-2024-0144338, filed on October 21, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to memory devices and storage devices including the memory devices. Background Technology

[0004] A storage device can store data provided by an external device in response to a write request from that external device. Furthermore, a storage device can provide data stored therein to an external device in response to a read request from that external device. External devices, as electronic devices capable of processing data, can include computers, digital cameras, or mobile phones. Storage devices can be embedded in and operate within external devices, or they can be operated by being manufactured in a detachable form and coupled to an external device. Storage devices can include memory devices for storing data.

[0005] Memory devices may require erase operations to erase data and make room for new data. For example, because non-volatile memory devices such as flash memory cannot overwrite data, the original data must be erased before new data can be written. The time spent performing erase operations has a significant impact on the operational performance of the storage device, and frequent erase operations can also affect the lifespan of the memory device. When a memory device performs erase operations efficiently, its operational performance can be maximized. Summary of the Invention

[0006] A memory device according to an embodiment of the present disclosure may include: a plurality of blocks, each block including memory cells; and control circuitry configured to enable a blind erase option and perform a blind erase operation on a target block among the plurality of blocks. During the blind erase operation, the control circuitry may apply an erase pulse to the target block without performing an erase verification operation on the target block.

[0007] A storage device according to an embodiment of the present disclosure may include: a memory device including a plurality of blocks, each block including memory cells; and a controller configured to control the memory device to perform a blind erase operation on a target block among the plurality of blocks, and to perform a fast erase operation on the target block in response to determining that a new open block is needed. During the blind erase operation, the memory device may perform an erase pulse application operation on the target block without performing an erase verification operation on the target block.

[0008] An operation method of a storage device including a memory device and a controller according to an embodiment of the present disclosure may include: the controller controlling the memory device to perform a blind erase operation on a target block; and the controller controlling the memory device to perform a fast erase operation on the target block in response to determining that a new open block is needed. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0010] Figure 2 This is a circuit diagram illustrating a memory block according to an embodiment of the present disclosure.

[0011] Figure 3 This is a diagram illustrating the process of specifying and using new open blocks through a normal erase operation according to an embodiment of the present disclosure.

[0012] Figure 4 This is a diagram illustrating the process of specifying and using new open blocks through a blind erase operation and a fast erase operation, according to an embodiment of the present disclosure.

[0013] Figures 5A to 5C This is a diagram illustrating a set of commands sent from a controller to a memory device according to an embodiment of the present disclosure.

[0014] Figure 6 This is a flowchart illustrating the operation of a controller according to an embodiment of the present disclosure.

[0015] Figure 7 This is a flowchart illustrating the operation of a controller according to an embodiment of the present disclosure.

[0016] Figure 8 This is a flowchart illustrating the operation of a controller according to an embodiment of the present disclosure.

[0017] Figure 9 This is a flowchart illustrating the operation of a controller according to an embodiment of the present disclosure.

[0018] Figure 10 This is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0019] In the following description, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0020] Figure 1 This is a block diagram illustrating a storage device 100 according to an embodiment of the present disclosure.

[0021] Storage device 100 can store data received from a host device (e.g., an external device) in response to a write request from that host device (not shown). Furthermore, storage device 100 can send the data stored therein to the host device in response to a read request from that host device.

[0022] Storage device 100 may include controller 110 and memory device 120.

[0023] Controller 110 can control the operation of storage device 100. Controller 110 can control storage device 120 according to requests from host device. For example, controller 110 can store data sent from host device to storage device 120 according to write requests from host device. Furthermore, controller 110 can read data from storage device 120 and send the data to host device according to read requests from host device.

[0024] Furthermore, independent of the host device, i.e., even without receiving requests from the host device, controller 110 can control memory device 120 to perform internally required management operations. Management operations may include wear leveling, deduplication, and garbage collection. Depending on the embodiment, controller 110 may also perform management operations based on requests from the host device. Controller 110 can perform management operations in the background or in the foreground.

[0025] An open block can be one of the blocks BK1 to BKi of the memory device 120 that is designated for performing programming operations on the memory device 120. When there is no more free space in the currently designated open block, the controller 110 can designate a free block as a new open block.

[0026] The controller 110 can control the memory device 120 to perform a normal erase operation to generate a blank block. The normal erase operation can be performed by repeating the erase pulse application operation and the erase verification operation one or more times. Depending on the result of performing the previous erase verification operation, the normal erase operation may also include additional erase pulse application operations and additional erase verification operations. In the normal erase operation, the erase pulse application operation and the erase verification operation can be linked or paired. The erase pulse application operation can be an operation that erases data stored in the memory cell by applying an erase pulse with a high voltage level to the channel of the memory cell. The erase verification operation can be an operation that verifies whether the data stored in the memory cell has been erased by reading the data stored in the memory cell.

[0027] The memory device 120 can perform read operations, program operations, erase operations, etc., under the control of the controller 110. The memory device 120 may include a control circuit 121 and multiple blocks BK1 to BKi. The control circuit 121 can control the overall operation of the memory device 120 under the control of the controller 110. Each block of BK1 to BKi can be a unit in which the memory device 120 performs an erase operation under the control of the controller 110. Each block of BK1 to BKi may include multiple memory cells in which data is stored.

[0028] According to one embodiment, the memory device 120 may include one or more planes. Each plane may be a group of blocks BK1 to BKi sharing bit lines. Each block BK1 to BKi may consist of one or more memory blocks included in each of the one or more planes.

[0029] The controller 110 can control the memory device 120 to perform a blind erase operation on a target block among a plurality of blocks BK1 to BKi, and in response to determining that a new open block is needed, control the memory device 120 to perform a fast erase operation on the target block.

[0030] During a blind erase operation, an erase pulse can be applied to the target block. During the blind erase operation, the control circuit 121 may not perform an erase verification operation on the target block after the erase pulse application operation. The blind erase operation may not include an erase verification operation to verify whether the target block has been completely erased.

[0031] The fast erase operation may include a pre-erase verification operation performed first without any erase pulse application. During the fast erase operation, control circuitry 121 may not apply an erase pulse to the target block before performing the pre-erase verification operation. Control circuitry 121 may perform a normal erase operation on the target block in response to determining that the result of the pre-erase verification operation is "failure".

[0032] In one embodiment, controller 110 may control memory device 120 to perform a blind erase operation in response to determining that memory device 120 is idle. In another embodiment, controller 110 may control memory device 120 to perform a blind erase operation in response to determining that there are no pending operations for memory device 120.

[0033] In one embodiment, controller 110 can control memory device 120 to perform a blind erase operation by enabling a blind erase option in memory device 120 and then sending an erase command set to memory device 120. Controller 110 can sequentially send a setup command set and an erase command set to memory device 120, the setup command set being used to enable the blind erase option. The erase command set can be sent after the setup command set for enabling the blind erase option, thereby instructing memory device 120 to perform a blind erase operation.

[0034] In one embodiment, controller 110 can control memory device 120 to perform a fast erase operation by enabling a pre-erase verification option in memory device 120 and then sending an erase command set to memory device 120. Controller 110 can sequentially send a setup command set and an erase command set to memory device 120, the setup command set being used to enable the pre-erase verification option. The erase command set can be sent after the setup command set for enabling the pre-erase verification option, thereby instructing memory device 120 to perform a fast erase operation.

[0035] In one embodiment, controller 110 can control memory device 120 to perform a normal erase operation by sending only an erase command set without sending a set of setup commands to memory device 120.

[0036] In one embodiment, controller 110 may select a target block from an invalid block pool for a blind erase operation. The invalid block pool may consist of blocks containing only invalid data. Controller 110 may register target blocks that have already undergone a blind erase operation in a free block pool. The free block pool may consist of blocks that have already undergone a blind erase operation. After a blind erase operation has been performed, a target block may be registered in the free block pool, regardless of whether the target block has been completely erased. Controller 110 may select a target block from the free block pool in response to determining that a new open block is needed.

[0037] In one embodiment, controller 110 may determine whether a new open block is needed in response to a write request received from a host device. In response to determining that a new open block is needed, controller 110 may control memory device 120 to perform a fast erase operation on the target block. After the fast erase operation is performed, controller 110 may designate the target block as a new open block and control memory device 120 to perform a programming operation on the target block.

[0038] Control circuit 121 can enable the blind erase option and perform a blind erase operation on the target block under the control of controller 110. Control circuit 121 can enable the blind erase option in response to a set of setting commands for enabling the blind erase option, and perform a blind erase operation in response to a set of erase commands that are consecutive to the set of setting commands.

[0039] Control circuit 121 can enable the pre-erase verification option and perform a fast erase operation on the target block under the control of controller 110. Control circuit 121 can enable the pre-erase verification option in response to a set of setting commands for enabling the pre-erase verification option, and perform a fast erase operation in response to a set of erase commands that are consecutive to the set of setting commands.

[0040] Although not shown, control circuitry 121 may include: a decoder for selecting a target block among a plurality of blocks BK1 to BKi; a voltage generation circuit for supplying the target block with the voltage required for erase pulse application operation, erase verification operation, and programming operation; and an option setting circuit for enabling / disabling blind erase option and pre-erase verification option.

[0041] In one embodiment, storage device 100 may include a PCMCIA card, a smart media card, a memory stick, various multimedia cards (such as MMC, eMMC, RS-MMC, and MMC-micro), a secure digital card (such as SD, Mini-SD, and Micro-SD), universal flash storage (UFS), or a solid-state drive (SSD).

[0042] In one embodiment, the memory device 120 may include NAND flash memory, 3D NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), and spin-transfer torque random access memory (STT-RAM).

[0043] Figure 2 This is a circuit diagram illustrating a memory block MB according to an embodiment of the present disclosure. Figure 1 Each of blocks BK1 to BKi may include blocks with Figure 2 One or more memory blocks are configured similarly to memory blocks MB.

[0044] refer to Figure 2 The memory block MB can be coupled to the control circuit 121 via the selection lines DSL1, DSL2, SSL1 and SSL2, word lines WL1 to WLn, bit lines BL1 to BLm and source line SL.

[0045] A memory block MB can include strings ST11 to ST1m and ST21 to ST2m. Each string in ST11 to ST1m and ST21 to ST2m can extend in the vertical direction (i.e., the Z direction). Within the memory block MB, m strings can be arranged in the row direction (i.e., the X direction). Although Figure 2The illustration shows two strings arranged in the column direction (i.e., the Y direction), but this is for ease of description, and three or more strings can be arranged in the column direction (i.e., the Y direction).

[0046] Serial lines ST11 to ST1m and ST21 to ST2m can be configured in the same manner. For example, serial line ST11 may include source select transistors SST, memory cells MC1 to MCn, and drain select transistors DST, which are coupled in series between source line SL and bit line BL1. The source of source select transistor SST may be coupled to source line SL, and the drain of drain select transistor DST may be coupled to bit line BL1. Memory cells MC1 to MCn may be coupled in series between source select transistor SST and drain select transistor DST. In one embodiment, multiple source select transistors may be coupled in series between source line SL and memory cell MC1. In one embodiment, multiple drain select transistors may be coupled in series between bit line BL1 and memory cell MCn.

[0047] Source selection transistors located at the same position in the vertical direction can be configured as follows. Specifically, the gates of source selection transistors arranged in strings in the same row can be coupled to the same source selection line. For example, the gates of source selection transistors arranged in strings ST11 to ST1m in the first row can be coupled to source selection line SSL1. For example, the gates of source selection transistors arranged in strings ST21 to ST2m in the second row can be coupled to source selection line SSL2.

[0048] In one embodiment, the source select transistors in strings arranged in two or more rows can be commonly coupled to a single source select line. For example, the source select transistors in strings ST11 to ST1m and ST21 to ST2m arranged in the first and second rows can be commonly coupled to a single source select line, and the source select transistors in strings arranged in the third and fourth rows can be commonly coupled to a single source select line.

[0049] Drain select transistors located at the same position in the vertical direction can be configured as follows. Specifically, the gates of drain select transistors arranged in strings in the same row can be coupled to the same drain select line. For example, the gates of drain select transistors arranged in strings ST11 to ST1m in the first row can be coupled to drain select line DSL1. For example, the gates of drain select transistors arranged in strings ST21 to ST2m in the second row can be coupled to drain select line DSL2.

[0050] Strings arranged in the same column can be coupled to the same bit line. For example, strings ST11 and ST21 arranged in the first column can be coupled to bit line BL1. For example, strings ST1m and ST2m arranged in the m-th column can be coupled to bit line BLm.

[0051] The gates of memory cells located at the same position in the vertical direction can be coupled to the same word line. For example, memory cells in strings ST11 to ST1m and ST21 to ST2m located at the same position in the vertical direction as memory cell MC1 can be coupled to word line WL1.

[0052] Within a memory cell, memory cells in the same row coupled to the same word line can constitute a memory region. For example, memory cells in the first row coupled to word line WL1 can constitute a memory region MR11. For example, memory cells in the second row coupled to word line WL1 can constitute a memory region MR12. For example, memory cells in the first row coupled to word line WL2 can constitute a memory region MR21. Depending on the number of rows, each word line can be coupled to multiple memory regions. Memory cells constituting a memory region can be accessed simultaneously.

[0053] In one embodiment, the memory block MB may also be coupled to one or more dummy word lines other than word lines WL1 to WLn. In this case, the memory block MB may also include dummy memory cells coupled to the dummy word lines.

[0054] Figure 3 This is a diagram illustrating the process by which a storage device 100, according to an embodiment of the present disclosure, specifies and uses new open blocks through a normal erase operation.

[0055] refer to Figure 3 In operation S1, controller 110 can select blocks BK1 to BK3 as sacrificial blocks VBK. This can be described as an example where the number of sacrificial blocks VBK is 3. Each valid data in valid data VD1, VD2, and VD3 can be stored in a different sacrificial block within sacrificial block VBK. Data in sacrificial block VBK other than valid data VD1, VD2, and VD3 can be invalid.

[0056] In operation S2, controller 110 can select a target block TBK for garbage collection. In one embodiment, controller 110 can select the target block TBK for garbage collection from an invalid block pool 201 consisting of blocks containing only invalid data, and control memory device 120 to perform a normal erase operation on the target block TBK. In another embodiment, controller 110 can select a blank block that has already been erased as the target block TBK.

[0057] In operation S3, controller 110 can store the valid data VD1, VD2 and VD3 stored in the sacrificial block VBK in the target block TBK.

[0058] In operation S4, controller 110 may invalidate valid data VD1, VD2, and VD3 stored in the sacrificial block VBK. In one embodiment, controller 110 may invalidate valid data VD1, VD2, and VD3, and then register the sacrificial block VBK in the invalidation block pool 201.

[0059] In operation S5, the controller 110 can select block BK1 from the invalid block pool 201 and control the memory device 120 to perform a normal erase operation on block BK1.

[0060] In operation S6, the controller 110 can designate block BK1 as a new open block and control the memory device 120 to perform a first programming operation on the blank block BK1.

[0061] In operation S7, controller 110 can continue to use block BK1 as an open block until there is no more free space in block BK1. When all memory regions of block BK1 have been programmed, controller 110 can designate a new open block to replace block BK1.

[0062] According to the reference Figure 3 The described process involves linking or pairing the normal erase operation for block BK1 in operation S5 and the first programming operation for block BK1 in operation S6. When a new open block is selected from the invalid block pool 201, the normal erase operation for block BK1 cannot be skipped before the first programming operation for block BK1 is executed. Therefore, spending a significant amount of time on operations S5 and S6 until the first programming operation for block BK1 is fully executed can potentially degrade the performance of the storage device 100.

[0063] Figure 4 This is a diagram illustrating the process by which a storage device 100, according to an embodiment of the present disclosure, designates and uses new open blocks through blind erase operations and fast erase operations.

[0064] refer to Figure 4 In operation S11, the controller 110 can select blocks BK1 to BK3 as the sacrificial block VBK.

[0065] In operation S12, controller 110 can select a target block TBK for garbage collection operations. In one embodiment, controller 110 can select the target block TBK from a free block pool 301 consisting of blocks that have already undergone blind erase operations. When the target block TBK is selected from the free block pool 301, controller 110 can control memory device 120 to perform a fast erase operation on the target block TBK. In one embodiment, controller 110 can select a blank block that has already been erased as the target block TBK.

[0066] In operation S13, controller 110 can store the valid data VD1, VD2 and VD3 stored in the sacrificial block VBK in the target block TBK.

[0067] In operation S14, controller 110 can invalidate valid data VD1, VD2, and VD3 stored in the sacrificial block VBK. After invalidating valid data VD1, VD2, and VD3, controller 110 can register the sacrificial block VBK in the invalidation block pool 201.

[0068] In operation S15, controller 110 can select block BK1 from invalid block pool 201 and control memory device 120 to perform a blind erase operation on block BK1. After performing the blind erase operation, block BK1 can be removed from invalid block pool 201 and registered in free block pool 301.

[0069] After performing operation S15, controller 110 may perform operations S16 and S17 in response to determining that a new open block is needed for programming operations.

[0070] In operation S16, the controller 110 can select block BK1 from the free block pool 301 and control the memory device 120 to perform a fast erase operation on block BK1.

[0071] In operation S17, controller 110 can designate block BK1 as a new open block and control memory device 120 to perform a first programming operation on block BK1.

[0072] In operation S18, controller 110 may continue to use block BK1 as an open block until there is no more free space in block BK1. When all memory regions of block BK1 have been programmed, controller 110 may designate a new open block to replace block BK1.

[0073] According to the reference Figure 4The described process involves linking or pairing the fast erase operation for block BK1 in operation S16 and the first programming operation for block BK1 in operation S17. However, because the blind erase operation for block BK1 has already been pre-executed in operation S15, the fast erase operation can be performed quickly by starting from the pre-erase verification operation without performing an erase pulse application operation. Therefore, less time is spent on operations S16 and S17 until the first programming operation for block BK1 is fully executed, and thus the performance of the storage device 100 can be improved.

[0074] Figures 5A to 5C This is a diagram illustrating a set of commands sent from controller 110 to memory device 120 according to an embodiment of the present disclosure.

[0075] refer to Figure 5A The setting command set SC1 can be used to enable the blind erase option in the memory device 120. The setting command set SC1 may include a setting command EFh, an address A7h, and first setting values ​​P0 to fourth setting values ​​P3. The setting command EFh can be a command used to set an option, function, or mode of the memory device 120. The address A7h may indicate whether the option to be set is the blind erase option or the pre-erase verification option. The first setting value P0 to fourth setting value P3 may indicate whether the blind erase option or the pre-erase verification option is enabled or disabled.

[0076] refer to Figure 5C Table TB1 illustrates the usage of the first setting value P0 to the fourth setting value P3 for address A7h of the setting command EFh. The zeroth bit of the first setting value P0 (i.e., P0...) <0> This can be used to enable or disable the blind erase option. The first value of the first setting P0 (i.e., P0) <1> This can be used to enable or disable the pre-erasure verification option.

[0077] Return to reference Figure 5A The setting command set SC1 used to enable the blind erase option can be in the zeroth position of the first setting value P0 (i.e., P0 <0> The state is enabled and is in the first position of the first setting value P0 (i.e., P0). <1> The memory device 120 is in a disabled state. It can enable the blind erase option in response to the set command set SC1.

[0078] After setting the configuration command set SC1 to enable the blind erase option, the erase command set EC1 can be sent to the memory device 120. The erase command set EC1 may include an erase command 60h, an address ADD, and a confirmation command D0h. When the blind erase option is enabled, the erase command 60h instructs the memory device 120 to perform a blind erase operation. When the blind erase option is enabled, the address ADD indicates the target block to be blindly erased. The confirmation command D0h confirms that the erase command set EC1 has been successfully sent. When the blind erase option is enabled, the memory device 120 can perform a blind erase operation in response to the erase command set EC1.

[0079] While the conditions for performing a blind erase operation are met, the controller 110 can repeatedly perform blind erase operations on multiple target blocks by repeatedly sending the set command set SC1 and the erase command set EC1 to the memory device 120.

[0080] refer to Figure 5B The setting command set SC2 can be used to enable the pre-erase verification option in the memory device 120. The setting command set SC2 can include the setting command EFh, the address A7h, and first setting values ​​P0 to fourth setting values ​​P3. The setting command set SC2 for enabling the pre-erase verification option can be at the zeroth bit of the first setting value P0 (i.e., P0...). <0> The state is disabled and is in the first position of the first setting value P0 (i.e., P0). <1> The memory device 120 can enable the pre-erase verification option in response to the set command set SC2.

[0081] After setting the configuration command set SC2 to enable the pre-erase verification option, the erase command set EC2 can be sent to the memory device 120. The erase command set EC2 may include an erase command 60h, an address ADD, and a confirmation command D0h. When the pre-erase verification option is enabled, the erase command 60h instructs the memory device 120 to perform a fast erase operation. When the pre-erase verification option is enabled, the address ADD indicates the target block to be fast erased. The confirmation command D0h confirms that the erase command set EC2 has been sent correctly. When the pre-erase verification option is enabled, the memory device 120 can perform a fast erase operation in response to the erase command set EC2. The fast erase operation can be started from the pre-erase verification operation without an erase pulse application operation.

[0082] When the result of the fast erase operation is "pass," a programming command set PC can be sent to the memory device 120. The programming command set PC may include a programming command 80h, an address ADD, data, and a confirmation command 10h. The programming command 80h may be a command instructing a programming operation. The address ADD may indicate the page in the open block to which the programming operation is to be performed. The data may be the data to be programmed. The confirmation command 10h may be a command confirming that the programming command set PC has been successfully sent. The memory device 120 can perform a programming operation in response to the programming command set PC.

[0083] The erase command set used to indicate a normal erase operation can have the same configuration as the erase command set EC1 used to indicate a blind erase operation and the erase command set EC2 used to indicate a fast erase operation. Depending on whether the blind erase option and the pre-erase verification option are enabled, the memory device 120 can determine whether the erase command set indicates a blind erase operation, a pre-erase verification operation, or a normal erase operation.

[0084] Figure 6 This is a flowchart illustrating the operation of a controller 110 according to an embodiment of the present disclosure.

[0085] refer to Figure 6 In operation S110, the controller 110 can control the memory device 120 to perform a blind erase operation on the target block. Specifically, the controller 110 can control the memory device 120 to perform a blind erase operation on the target block by enabling the blind erase option in the memory device 120 and sending the erase command set EC1 for the target block to the memory device 120.

[0086] In operation S120, controller 110 can control memory device 120 to perform a fast erase operation on the target block in response to determining that a new open block is needed. Specifically, controller 110 can control memory device 120 to perform a fast erase operation on the target block by enabling the pre-erase verification option in memory device 120 and sending the erase command set EC2 for the target block to memory device 120.

[0087] Figure 7 This is a flowchart illustrating the operation of a controller 110 according to an embodiment of the present disclosure.

[0088] refer to Figure 7In operation S210, controller 110 can determine whether the performance conditions for the blind erase operation are met. For example, when it is determined that storage device 100 is in an idle state, controller 110 can determine that the performance conditions for the blind erase operation are met. For example, even while controller 110 is controlling operations for another memory device (not shown) included in storage device 100, when it is determined that there are no pending operations for memory device 120, controller 110 can also determine that the performance conditions for the blind erase operation are met for memory device 120. When it is determined that the performance conditions for the blind erase operation are met, operation S220 can be performed. When it is determined that the performance conditions for the blind erase operation are not met, the operation can be terminated.

[0089] In operation S220, the controller 110 can determine whether the memory device 120 is in an emergency state. An emergency state can be a state of shortage of blank blocks in the memory device 120. When it is determined that the memory device 120 is in an emergency state (i.e., "yes" in operation S220), operation S230 can be performed. When it is determined that the memory device 120 is not in an emergency state (i.e., "no" in operation S220), operation S240 can be performed.

[0090] In operation S230, controller 110 can determine whether to perform a blind erase operation in the foreground.

[0091] In operation S240, controller 110 can determine whether to perform a blind erase operation in the background.

[0092] In operation S250, the controller 110 can select the target block from the invalid block pool 201 to perform a blind erase operation.

[0093] In operation S260, the controller 110 can control the memory device 120 to perform a blind erase operation on the target block.

[0094] In operation S270, the controller 110 can register the target block that has undergone a blind erase operation in the free block pool 301.

[0095] According to embodiments of this disclosure, a free block pool 301 can be ensured through a blind erase operation, which makes it possible to improve the performance of the storage device 100 in the event of over-provisioning.

[0096] Figure 8 This is a flowchart illustrating the operation of a controller 110 according to an embodiment of the present disclosure.

[0097] refer to Figure 8In operation S310, controller 110 can determine whether the performance conditions for garbage collection are met. For example, when it is determined that storage device 100 is in an idle state, controller 110 can determine that the performance conditions for garbage collection are met. For example, when it is determined that a write request has been received from the host device, controller 110 can determine that the performance conditions for garbage collection are met. When it is determined that the performance conditions for garbage collection are met (i.e., "yes" in operation S310), operation S320 can be performed. When it is determined that the performance conditions for garbage collection are not met (i.e., "no" in operation S310), the operation can be terminated.

[0098] In operation S320, controller 110 can determine whether memory device 120 is in an emergency state. An emergency state can be a state of shortage of blank blocks in memory device 120. When it is determined that memory device 120 is in an emergency state (i.e., "yes" in operation S320), operation S330 can be performed. When it is determined that memory device 120 is not in an emergency state (i.e., "no" in operation S320), operation S340 can be performed.

[0099] In operation S330, controller 110 can determine whether to perform a garbage collection operation in the foreground.

[0100] In operation S340, controller 110 can determine whether to perform garbage collection in the background.

[0101] In operation S350, controller 110 can determine whether a new open block is needed to move valid data from one or more sacrificial blocks VBK of the garbage collection operation. When it is determined that a new open block is needed, operation S360 can be performed. When it is determined that a new open block is not needed, operation S390 can be performed.

[0102] In operation S360, controller 110 can select the target block from the free block pool 301 to perform a fast erase operation.

[0103] In operation S370, controller 110 can control memory device 120 to perform a fast erase operation on the target block.

[0104] In operation S380, controller 110 can designate the target block as a new open block.

[0105] In operation S390, controller 110 may perform garbage collection operations on open blocks. The garbage collection operations may include controlling memory device 120 to store valid data stored in one or more sacrificial blocks VBK in open blocks, invalidating valid data stored in one or more sacrificial blocks VBK, and registering one or more sacrificial blocks VBK in invalid block pool 201.

[0106] Figure 9 This is a flowchart illustrating the operation of a controller 110 according to an embodiment of the present disclosure.

[0107] refer to Figure 9 In operation S410, controller 110 can receive write requests from host device.

[0108] In operation S420, controller 110 can determine whether a new open block is needed to store the data corresponding to the write request. When it is determined that a new open block is needed (i.e., "yes" in operation S420), operation S430 can be performed. When it is determined that a new open block is not needed (i.e., "no" in operation S420), operation S460 can be performed.

[0109] In operation S430, controller 110 can select the target block from the free block pool 301 to perform a fast erase operation.

[0110] In operation S440, controller 110 can control memory device 120 to perform a fast erase operation on the target block.

[0111] In operation S450, controller 110 can designate the target block as a new open block.

[0112] In operation S460, controller 110 can control memory device 120 to perform programming operations on the open block. The data stored in the open block may include data corresponding to write requests.

[0113] Figure 10 This is a flowchart illustrating the operation of a memory device 120 according to an embodiment of the present disclosure.

[0114] refer to Figure 10 In operation S510, the memory device 120 can receive an erase command for the target block.

[0115] In operation S520, the memory device 120 can determine whether the blind erase option is enabled. When it is determined that the blind erase option is enabled (i.e., "yes" in operation S520), operation S560 can be performed to execute the blind erase operation. When it is determined that the blind erase option is disabled (i.e., "no" in operation S520), operation S530 can be performed.

[0116] In operation S530, the memory device 120 can determine whether the pre-erase verification option is enabled. When it is determined that the pre-erase verification option is enabled (i.e., "yes" in operation S530), operation S540 can be performed to cause a fast erase operation. When it is determined that the pre-erase verification option is disabled (i.e., "no" in operation S530), operation S560 can be performed to cause a normal erase operation.

[0117] In operation S540, memory device 120 can perform a pre-erase verification operation on the target block.

[0118] In operation S550, the memory device 120 can determine whether the result of the pre-erase verification operation is "pass". When the result of the pre-erase verification operation is determined to be "pass" (i.e., "yes" in operation S550), the operation can be terminated. When the result of the pre-erase verification operation is determined to be "fail" (i.e., "no" in operation S550), operation S560 can be performed to execute a normal erase operation.

[0119] In operation S560, memory device 120 can perform an erase pulse application operation on the target block.

[0120] In operation S570, the memory device 120 can determine whether the blind erase option is enabled. When it is determined that the blind erase option is enabled (i.e., "yes" in operation S570), the operation can be terminated. When it is determined that the blind erase option is disabled (i.e., "no" in operation S570), operation S580 can be performed.

[0121] In operation S580, memory device 120 can perform an erase verification operation on the target block.

[0122] In operation S590, the memory device 120 can determine whether the result of the erase verification operation is "pass". When the result of the erase verification operation is determined to be "pass" (i.e., "yes" in operation S590), the operation can be terminated. When the result of the erase verification operation is determined to be "fail" (i.e., "no" in operation S590), operation S600 can be performed.

[0123] In operation S600, the memory device 120 can determine whether the maximum number of times the erase pulse application operation has been performed has been reached. When it is determined that the maximum number of times the erase pulse application operation has been performed (i.e., "yes" in operation S600), the operation can be terminated. When it is determined that the maximum number of times the erase pulse application operation has not been performed (i.e., "no" in operation S600), operation S610 can be performed.

[0124] In operation S610, the memory device 120 can increase the voltage level of the erase pulse. Subsequently, the erase pulse application operation and the erase verification operation can be repeatedly performed (i.e., operation S560).

[0125] According to embodiments of the present disclosure, the memory device, storage device, and method of operating the storage device can improve the over-provisioning performance and write operation performance of the storage device by efficiently performing erase operations.

[0126] While embodiments of this disclosure have been described for illustrative purposes, those skilled in the art will recognize that various modifications and changes are possible without departing from the essential features of this disclosure. Therefore, the embodiments disclosed herein are not intended to limit the technical spirit of this disclosure, but rather to illustrate it, and the scope of the technical spirit of this disclosure is not limited by the embodiments. The scope of protection of this disclosure should be interpreted based on the following appended claims, and should be construed as including all technical details within the same or equivalent scope as the claims. Furthermore, embodiments may be combined to form additional embodiments.

Claims

1. A memory device, comprising: Multiple blocks, each block comprising memory units; as well as The control circuitry is configured to enable the blind erase option and perform a blind erase operation on a target block among the plurality of blocks. During the blind erase operation, the control circuit is configured to apply an erase pulse to the target block without performing an erase verification operation on the target block.

2. The memory device of claim 1, wherein during the blind erase operation, an erase pulse is applied to the target block.

3. The memory device according to claim 1, The control circuitry is configured to enable the blind erase option in response to a set of setting commands for enabling the blind erase option, and to perform the blind erase operation in response to a set of erase commands for the target block. The erase command set and the set of settings command are consecutive.

4. The memory device of claim 1, wherein the control circuitry is configured to enable a pre-erase verification option and perform a fast erase operation on the target block.

5. The memory device according to claim 4, The control circuitry is configured to enable the pre-erase verification option in response to a set of setting commands for enabling the pre-erase verification option, and to perform the fast erase operation in response to a set of erase commands for the target block. The erase command set and the set of settings command are consecutive.

6. The memory device of claim 5, wherein during the fast erase operation, the control circuitry is configured not to apply an erase pulse to the target block before performing a pre-erase verification operation on the target block.

7. The memory device of claim 6, wherein during the fast erase operation, the control circuitry is configured to perform a normal erase operation on the target block in response to determining that the pre-erase verification operation has failed.

8. A storage device, comprising: A memory device comprising multiple blocks, each block comprising memory cells; as well as A controller, configured to control the memory device to: Perform a blind erase operation on the target block among the plurality of blocks, and In response to the determination that a new open block is needed, a fast erase operation is performed on the target block. During the blind erase operation, the memory device applies an erase pulse to the target block without performing an erase verification operation on the target block.

9. The storage device of claim 8, wherein during the blind erase operation, an erase pulse is applied to the target block.

10. The storage device of claim 8, wherein the controller is configured to control the storage device to perform the blind erase operation in response to determining that the storage device is in an idle state.

11. The storage device of claim 8, wherein the controller controls the storage device to perform the blind erase operation in response to determining that there is no pending operation for the storage device.

12. The storage device of claim 8, wherein the controller is configured to enable a blind erase option in the storage device and send a set of erase commands for the target block to the storage device to control the storage device to perform the blind erase operation.

13. The storage device of claim 12, wherein the controller is configured to sequentially send a set of setup commands for enabling the blind erase option and the set of erase commands to the storage device.

14. The storage device of claim 8, wherein the controller is configured to enable a pre-erase verification option in the storage device and send a set of erase commands for the target block to the storage device to control the storage device to perform the fast erase operation.

15. The storage device of claim 14, wherein the controller is configured to sequentially send a set of setup commands for enabling the pre-erase verification option and the set of erase commands to the storage device.

16. The storage device of claim 14, wherein during the fast erase operation, the storage device is configured not to apply an erase pulse to the target block before performing a pre-erase verification operation on the target block.

17. The storage device according to claim 16, During the fast erase operation, the memory device is configured to perform a normal erase operation on the target block in response to determining that the pre-erase verification operation has failed, and During the normal erasure operation, one or more erasure pulses are applied to the target block.

18. The storage device of claim 8, wherein the controller is configured to select the target block from an invalid block pool to perform the blind erase operation.

19. The storage device of claim 8, wherein the controller is configured to register the target block for performing the blind erase operation in a free block pool.

20. The storage device of claim 19, wherein the controller is configured to select the target block from the free block pool in response to determining that the new open block is needed.

21. The storage device of claim 8, wherein the controller is configured to determine whether the new open block is needed in response to a write request received from an external source.

22. The storage device of claim 8, wherein the controller is configured to designate the target block as the new open block after the fast erase operation is performed, and to control the storage device to perform a programming operation on the target block.

23. A method of operating a storage device, the storage device comprising a memory device and a controller, the method comprising: The controller controls the memory device to perform a blind erase operation on the target block; as well as In response to the determination that a new open block is needed, the controller controls the memory device to perform a fast erase operation on the target block.

24. The method of operation according to claim 23, wherein during the blind erasure operation, a pulse is applied to the target block.

25. The method of operation according to claim 23, wherein controlling the memory device to perform the blind erase operation comprises: In response to determining that the storage device is in an idle state, the controller controls the storage device to perform the blind erase operation.

26. The method of operation according to claim 23, wherein controlling the memory device to perform the blind erase operation comprises: In response to determining that there are no pending operations for the memory device, the controller controls the memory device to perform the blind erase operation.

27. The method of operation according to claim 23, wherein controlling the memory device to perform the blind erase operation comprises: The controller enables the blind erase option in the memory device; as well as The controller sends a set of erase commands for the target block to the memory device.

28. The operating method according to claim 27, further comprising: The memory device performs the blind erase operation by applying an erase pulse to the target block in response to the erase command set without performing an erase verification operation on the target block.

29. The method of operation according to claim 23, wherein controlling the memory device to perform the fast erase operation comprises: The controller enables the pre-erase verification option in the memory device; as well as The controller sends a set of erase commands for the target block to the memory device.

30. The operating method according to claim 29, further comprising: The memory device performs the pre-erase verification operation in response to the erase command set without applying an erase pulse to the target block, thereby performing the fast erase operation.

31. The operating method according to claim 30, further comprising: During the fast erase operation, in response to determining that the pre-erasure verification operation has failed, the memory device performs a normal erase operation on the target block. During the normal erasure operation, one or more erasure pulses are applied to the target block.

32. The operating method according to claim 23 further includes: The controller selects the target block from the invalid block pool to perform the blind erase operation.

33. The operating method according to claim 23 further includes: The controller registers the target block for which the blind erase operation will be performed in the free block pool.

34. The operating method according to claim 33 further includes: The controller selects the target block from the free block pool in response to determining that the new open block is needed.

35. The operating method according to claim 23, further comprising: The controller determines whether the new open block is needed in response to a write request received from an external source.

36. The operating method according to claim 23 further includes: After performing the fast erase operation, the controller designates the target block as the new open block; as well as The controller controls the memory device to perform programming operations on the target block.

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