Storage device

Abstract

The invention discloses a storage device. The storage device comprises a storage array, a burning storage circuit, a command decoder and a processing circuit, the processing circuit is coupled with the burning storage circuit, the command decoder and the storage array, and damaged word line addresses stored in the burning storage circuit comprise at least three types of damaged word line addresses. Each type of damaged word line address corresponds to one type of redundant word line group, and the numbers of redundant word lines in various types of redundant word line groups are different, so that the processing circuit responds to the word line addressing address and is matched with one damaged word line address; and generating a corresponding redundant word line enable signal to drive the redundant word line mapping in the group of redundant word lines corresponding to the matched damaged word line address to replace the group of common word lines corresponding to the word line addressing address. According to the invention, the memory chip repairing efficiency and flexibility are improved.

Description

Technical Field

[0001] The disclosed embodiments of this application relate to the field of semiconductor memory technology, and more specifically, to a memory device. Background Technology

[0002] If a Dynamic Random Access Memory (DRAM) has damaged word lines (WLs) or bit lines (BLs) (e.g., short circuits or open circuits), these WLs and BLs need to be replaced with redundant WLs / BLs. Those skilled in the art will understand that, due to manufacturing process factors, when one word line (WL) is damaged, one or more adjacent word lines (WLs) are also highly likely to be damaged. Therefore, for replacement efficiency, manufacturers typically replace multiple adjacent word lines (WLs) simultaneously, such as replacing 8 WLs, 4 WLs, or 2 WLs simultaneously, etc., when performing redundant replacement of word lines (WLs). However, existing simultaneous replacement methods require pre-setting the number of word lines (WLs) to be replaced simultaneously, and then performing the pre-set number of word lines (WLs) for simultaneous replacement. Once the number of word lines (WLs) to be replaced simultaneously is set, it is difficult to modify later. Therefore, this simultaneous replacement method is very inflexible and has many problems. Summary of the Invention

[0003] According to embodiments of this application, this application proposes a storage device to solve the problem of the single word line replacement method mentioned above, and to improve the efficiency and flexibility of chip repair.

[0004] The first aspect of this application discloses a storage device, comprising: a storage array including a general-purpose storage array and a redundant storage array, wherein redundant word lines in the redundant storage array are used to map and replace general-purpose word lines in the general-purpose storage array, such that redundant storage cells in the redundant storage array map and replace damaged general-purpose storage cells in the general-purpose storage array; a programming storage circuit configured to store at least one damaged word line address, wherein each damaged word line address corresponds to a redundant word line of a redundant word line group; a command decoder configured to generate a corresponding word line addressing address in response to a user instruction; and a processing circuit coupled to the programming storage circuit and the command decoder. The processing circuit is configured to receive the word line addressing address and the damaged word line address; in response to the word line addressing address matching a damaged word line address, generate a corresponding redundant word line enable signal to drive the redundant word lines in a set of redundant word lines corresponding to the matched damaged word line address to map and replace a set of ordinary word lines corresponding to the word line addressing address; wherein the damaged word line address stored in the programming memory circuit may include at least three types of damaged word line addresses, each type of damaged word line address corresponding to a type of redundant word line set, and the number of redundant word lines in the various types of redundant word line sets is different.

[0005] In some embodiments, the damaged word line addresses stored in the programming memory circuit may include at least one type of damaged word line address among a first type of damaged word line address, a second type of damaged word line address, and a third type of damaged word line address. Each first type of damaged word line address corresponds to a first type of redundant word line group containing X redundant word lines, each second type of damaged word line address corresponds to a second type of redundant word line group containing Y redundant word lines, and each third type of damaged word line address corresponds to a third type of redundant word line group containing Z redundant word lines. X, Y, and Z are natural numbers.

[0006] In some embodiments, the processing circuit includes an address matching circuit coupled to the programming memory circuit and the command decoder, wherein the address matching circuit is configured to cache the corrupted word line address from the programming memory circuit, receive the word line addressing address from the command decoder, and compare the word line addressing address with the corrupted word line address to determine whether the word line addressing address matches at least one of the corrupted word line addresses.

[0007] In some embodiments, the processing circuit includes: a redundant word line decoding circuit coupled to the address matching circuit, responding to the address matching circuit determining that the word line addressing address matches at least one of the damaged word line addresses, the redundant word line decoding circuit being configured to receive at least one type of enable signal, receive the matched damaged word line address from the address matching circuit, generate a corresponding redundant word line enable signal based on the matched damaged word line address, and drive the redundant word lines in a set of redundant word lines corresponding to the matched damaged word line address to map and replace a set of ordinary word lines corresponding to the word line address.

[0008] In some embodiments, the at least one type of enable signal includes a first type of enable signal and a second type of enable signal; in response to the redundant word line decoding circuit being configured to receive the first type of enable signal, it blocks word line substitution of the second type of word line and word line substitution of the third type of word line to perform word line substitution of the first type of word line; in response to the redundant word line decoding circuit being configured to receive the second type of enable signal, it blocks word line substitution of the first type of word line and word line substitution of the third type of word line to perform word line substitution of the second type of word line; in response to the redundant word line decoding circuit being configured not to receive the first type of enable signal and the second type of enable signal, it blocks word line substitution of the first type of word line and word line substitution of the second type of word line to perform word line substitution of the third type of word line.

[0009] In some embodiments, in response to the redundant word line decoding circuit being configured to receive a first type enable signal, wherein the word line addressing address matches a first type damaged word line address, and the address matching circuit outputs the matched first type damaged word line address to the redundant word line decoding circuit; the redundant word line decoding circuit generates a corresponding redundant word line enable signal based on the matched first type damaged word line address to drive X redundant word lines in the first type redundant word line group corresponding to the matched first type damaged word line address to map and replace a group of ordinary word lines corresponding to the word line addressing address; or in response to the redundant word line decoding circuit being configured to receive a second word line type signal, wherein the word line addressing address matches a second type damaged word line address, and the address matching circuit outputs the matched second type damaged word line address to the redundant word line decoding circuit; the redundant word line decoding circuit... Based on the matched second-type damaged word line address, the circuit generates a corresponding redundant word line enable signal to drive Y redundant word lines in the second-type redundant word line group corresponding to the matched second-type damaged word line address to map and replace a group of ordinary word lines corresponding to the word line addressing address; or in response to the redundant word line decoding circuit being configured not to receive the first type enable signal and the second type enable signal, wherein the word line addressing address matches a third-type damaged word line address, and the address matching circuit outputs the matched third-type damaged word line address to the redundant word line decoding circuit; the redundant word line decoding circuit generates a corresponding redundant word line enable signal based on the matched third-type damaged word line address to drive Z redundant word lines in the third-type redundant word line group corresponding to the matched third-type damaged word line address to map and replace a group of ordinary word lines corresponding to the word line addressing address.

[0010] In some embodiments, the word line addressing address includes an a-bit address signal; the first type of damaged word line address includes an (ab)-bit high-order address signal and a first identification signal, wherein each first type of damaged word line address corresponds to a first type of redundant word line group, and the first type of redundant word line group includes X=2 bThe redundant word lines, wherein the first identification signal indicates whether a group of redundant word lines corresponding to the first type of damaged word line address is damaged; in response to the high-order address signal of the a-bit address signal of the word line address being consistent with the high-order address signal of the (ab) bits in a first type of damaged word line address, the word line address is matched with the first type of damaged word line address; the second type of damaged word line address includes a (ac)-bit high-order address signal and a second identification signal, wherein each second type of damaged word line address corresponds to a second type of redundant word line group, and the second type of redundant word line group includes Y=2 c The redundant word lines, wherein the second identification signal characterizes whether a group of redundant word lines corresponding to the address of the second type of damaged word line is damaged; in response to the c-th to (a-1)-th high-order address signal in the a-bit address signal of the word line addressing address being consistent with the (ac)-th high-order address signal in a group of redundant word lines of the second type of damaged word line address, the word line addressing address matches the address of the second type of damaged word line address; the third type of damaged word line address includes (ad)-th high-order address signal and a third identification signal, wherein each of the third type of damaged word line addresses corresponds to a group of redundant word lines of the third type, and the group of redundant word lines of the third type includes Z=2 d The redundant word lines, the third identification signal characterizes whether a group of redundant word lines corresponding to the third type of damaged word line address is damaged; in response to the high-order address signal of the a-bit address signal of the word line addressing address being consistent with the high-order address signal of the (ad) bit in the third type of damaged word line address, the word line addressing address matches the third type of damaged word line address.

[0011] In some embodiments, the first type of redundant word line group corresponding to the first type of damaged word line address includes 8 redundant word lines, where X = 8; the second type of redundant word line group corresponding to the second type of damaged word line address includes 4 redundant word lines, where Y = 4; the second type of redundant word line group corresponding to the second type of damaged word line address includes 2 redundant word lines, where Z = 2; the word line addressing address includes a 15-bit address signal, defined as ra<14:0>, where a = 15; the first type of damaged word line address includes a 12-bit high-order address signal <14:3> and a first label The first type of corrupted word line address is defined as efsadd<14:3,flag>, where b=3; the second type of corrupted word line address includes a 13-bit high-order address signal<14:2> and a second flag signal, defined as efsadd<14:2,flag>, where c=2; the third type of corrupted word line address includes a 14-bit high-order address signal<14:1> and a third flag signal, defined as efsadd<14:1,flag>, where d=1.

[0012] In some embodiments, the processing circuit further includes: a redundant word line decoding circuit, wherein the redundant word line decoding circuit includes a first type of redundant word line decoding circuit, a second type of redundant word line decoding circuit, and a third type of redundant word line decoding circuit, wherein the first type of redundant word line decoding circuit, the second type of redundant word line decoding circuit, and the third type of redundant word line decoding circuit are logic gate circuits; in response to the word line addressing address matching the first type of damaged word line address, the first type of redundant word line decoding circuit drives X redundant word lines in the first type of redundant word line group corresponding to the matched first type of damaged word line address; in response to the word line addressing address matching the second type of damaged word line address, the second type of redundant word line decoding circuit drives Y redundant word lines in the second type of redundant word line group corresponding to the matched second type of damaged word line address; in response to the word line addressing address matching the third type of damaged word line address, the third type of redundant word line decoding circuit drives Z redundant word lines in the third type of redundant word line group corresponding to the matched third type of damaged word line address.

[0013] In some embodiments, the redundant word line decoding circuit further includes: X first latch units corresponding to the first type of redundant word line decoding circuit, used to latch X bits of the first type of damaged word line address from the programming memory circuit; Y second latch units corresponding to the second type of redundant word line decoding circuit, used to latch Y bits of the second type of damaged word line address from the programming memory circuit; and Z third latch units corresponding to the third type of redundant word line decoding circuit, used to latch Z bits of the third type of damaged word line address from the programming memory circuit.

[0014] In some embodiments, the address matching circuit includes a first address matching circuit, a second address matching circuit, and a third address matching circuit. The first address matching circuit determines whether the address signals of the b-th to (a-1)-th bits of the high-order address signal in the a-bit address of the word line addressing address are consistent with the high-order address signal of the (ab)-th bit in the first type of damaged word line addressing address. The second address matching circuit determines whether the address signals of the c-th to (a-1)-th bits of the high-order address signal in the a-bit address of the word line addressing address are consistent with the high-order address signal of the (ac)-th bit in the second type of damaged word line addressing address. The third address matching circuit determines whether the address signals of the d-th to (a-1)-th bits of the high-order address signal in the a-bit address of the word line addressing address are consistent with the high-order address signal of the (ad)-th bit in the third type of damaged word line addressing address.

[0015] The beneficial effects of this application are as follows: A storage device. The storage device includes a storage array, a programming storage circuit, a command decoder, and a processing circuit. The processing circuit is coupled to the programming storage circuit, the command decoder, and the storage array. The damaged word line addresses stored in the programming storage circuit include at least two types of damaged word line addresses. Each type of damaged word line address corresponds to a type of redundant word line group, and the number of redundant word lines in each type of redundant word line group is different. The processing circuit, in response to a word line address matching a damaged word line address, generates a corresponding redundant word line enable signal to drive the redundant word lines in the redundant word line group corresponding to the matched damaged word line address to map and replace the set of ordinary word lines corresponding to the word line address, thereby improving the efficiency and flexibility of storage chip repair. Attached Figure Description

[0016] The present application will be further described below with reference to the accompanying drawings and embodiments. In the drawings:

[0017] Figure 1 This is a schematic diagram of the structure of a storage device according to an embodiment of this application;

[0018] Figure 2 This is a schematic diagram of a storage device according to yet another embodiment of this application;

[0019] Figure 3 This is a schematic diagram of a storage device according to yet another embodiment of this application;

[0020] Figure 4 This is a schematic diagram of a storage device according to yet another embodiment of this application;

[0021] Figure 5 This is a schematic diagram of a storage device according to yet another embodiment of this application;

[0022] Figure 6 This is a schematic diagram of a storage device according to another embodiment of this application. Detailed Implementation

[0023] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0024] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Additionally, the character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, "many" in this application means two or more. Moreover, the term "at least one" in this application means any combination of at least two of any one or more of a plurality of objects. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C. Furthermore, the terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0025] To enable those skilled in the art to better understand the technical solution of this application, the technical solution of this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] Please see Figure 1 , Figure 1This is a schematic diagram of the structure of a storage device according to an embodiment of this application. The storage device 10 includes a storage array 11, a programming storage circuit 12, a command decoder 13, and a processing circuit 14. The storage device 10 may be a dynamic random access memory (DRAM). The storage device 10 can be applied to electronic devices including storage systems, graphics systems, computing systems, or mobile systems. For example, the electronic device may include a data storage device, a memory controller, a cache memory, etc.

[0027] Specifically, the storage array 11 includes a general storage array 111 and a redundant storage array 112. The general storage array 111 includes multiple general word lines WL, multiple general bit lines BL, and multiple general storage cells. By performing row addressing operations on the general word lines WL and / or column addressing operations on the general bit lines BL, the corresponding general storage cell is selected to perform memory operations, such as read, write, and erase operations.

[0028] The redundant storage array 112 includes multiple redundant word lines and multiple redundant storage cells. The redundant word lines in the redundant storage array 112 can be used to map and replace ordinary word lines in the ordinary storage array 111, so that the redundant storage cells in the redundant storage array 112 can replace damaged ordinary storage cells in the ordinary storage array 111. In other words, when a damaged ordinary word line appears in the ordinary storage array 111, the redundant word lines in the redundant storage array 112 can be used for redundant replacement.

[0029] The programming memory circuit 12 is configured to store at least one damaged word line address, Efsadd, where each damaged word line address, Efsadd, corresponds to a redundant word line in a redundant word line group. The programming memory circuit 12 stores at least one damaged word line address, Efsadd, which can be the address of a faulty word line discovered during pre-shipment testing of the DRAM. Each damaged word line address, Efsadd, can correspond to a redundant word line in a redundant word line group. Simultaneous mapping and replacement of multiple redundant word lines in its corresponding redundant word line group is performed through the damaged word line address, Efsadd. For example, if a damaged word line address, Efsadd, corresponds to a redundant word line group containing 8 redundant word lines, then when that damaged word line address, Efsadd, is selected, the 8 redundant word lines in its corresponding redundant word line group are simultaneously mapped and replaced with 8 ordinary word lines.

[0030] Command decoder 13 is configured to generate a corresponding word line address in response to a user instruction. Specifically, when a user issues a user instruction, command decoder 13 can generate a corresponding word line address RA and a word line addressing operation trigger signal Act_en. The word line addressing operation trigger signal Act_en is used to trigger the back-end circuitry (e.g., the back-end processing circuitry 14) to perform a word line addressing operation. The word line address RA can be the word line address that the user wants to access.

[0031] Processing circuit 14 is coupled to programming and storage circuit 12, command decoder 13, and storage array 11. Processing circuit 14 is configured to receive word line addressing address RA and damaged word line address Efsadd, and to receive word line addressing operation trigger signal Act_en sent by command decoder 13. In response to word line addressing address RA matching a damaged word line address Efsadd, processing circuit 14 determines whether the word line addressing address is a faulty word line address. Further, if word line addressing address RA matches a damaged word line address Efsadd, a corresponding redundant word line enable signal is generated to drive the redundant word lines in the redundant word line group corresponding to the matched damaged word line address Efsadd to map and replace the group of ordinary word lines corresponding to word line address RA. In other words, when the processing circuit 14 matches a damaged word line address Efsadd according to the word line addressing address RA, it means that the set of ordinary word lines WL corresponding to the word line addressing address RA is faulty or damaged, and the set of ordinary word lines WL corresponding to the word line addressing address RA needs to be replaced. The replacement object is the redundant word line in the set of redundant word lines corresponding to the matched damaged word line address Efsadd.

[0032] In this application, the damaged word line address Efsadd stored in the programming memory circuit 12 may include at least two types of damaged word line addresses, such as two damaged word line addresses, four damaged word line addresses, eight damaged word line addresses, etc., wherein a two damaged word line address can be understood as a damaged word line address in which two word lines are replaced together, a four damaged word line address can be understood as a damaged word line address in which four word lines are replaced together, and an eight damaged word line address can be understood as a damaged word line address in which eight word lines are replaced together.

[0033] The number of redundant word lines in the redundant word line group corresponding to each type of damaged word line address is different from the number of redundant word lines in the redundant word line group corresponding to other types of damaged word line addresses. For example, the number of redundant word lines in the redundant word line group corresponding to two damaged word line addresses is 2, the number of redundant word lines in the redundant word line group corresponding to four damaged word line addresses is 4, and the number of redundant word lines in the redundant word line group corresponding to eight damaged word line addresses is 8. The number of redundant word lines in the redundant word line groups corresponding to them is not the same.

[0034] In some embodiments, such as Figure 1 As shown, the processing circuit 14 includes an address matching circuit 141, which is coupled to the programming and storage circuit 12 and the command decoder 13.

[0035] The address matching circuit 141 is configured to cache the corrupted word line address Efsadd from the programming memory circuit 12, receive the word line addressing address RA from the command decoder 13, and compare the word line addressing address RA with the corrupted word line address Efsadd to determine whether the word line addressing address RA matches at least one of the corrupted word line addresses Efsadd.

[0036] Specifically, the address matching circuit 141 may also include a latch unit for buffering or temporarily storing the damaged word line address Efsadd from the programming memory circuit 12, so as to compare it one by one with the word line addressing address RA corresponding to the user instruction to determine whether word line redundancy replacement is required. Furthermore, the address matching circuit 141 also receives the word line addressing address RA and the word line addressing operation trigger signal Act_en from the command decoder 13, and performs a word line addressing operation based on the word line addressing operation trigger signal Act_en; wherein, the word line addressing operation first compares the word line addressing address RA and the damaged word line address Efsadd to determine whether word line redundancy replacement is required. In response to a match between at least one of the word line addressing address RA and the damaged word line address Efsadd, it is determined that word line redundancy replacement is required.

[0037] Furthermore, such as Figure 1 As shown, in some embodiments, the processing circuit 14 further includes a redundant word line decoding circuit 142, which is coupled to an address matching circuit 141.

[0038] In this circuit, the address matching circuit 141 determines that the word line addressing address RA matches a damaged word line address Efsadd, meaning that the address matching circuit 141 determines that word line redundancy replacement is required. Therefore, the redundant word line decoding circuit 142 is configured to receive at least one type of enable signal, which includes a first type enable signal and a second type enable signal. For example, the first type enable signal is enable signal En1 to enable word line replacement of the first type of word line, and the second type enable signal is enable signal En2 to enable word line replacement of the second type of word line. Based on the damaged word line address Efsadd that matches the word line addressing address RA, the redundant word line decoding circuit 142 generates a corresponding redundant word line enable signal RWL_en to drive the redundant word lines in the set of redundant word lines corresponding to the matched damaged word line address Efsadd to map and replace the set of ordinary word lines corresponding to the word line addressing address RA. In other words, when the address matching circuit 141 determines that the word line addressing address RA matches a damaged word line address Efsadd, then a set of word lines corresponding to the word line addressing address RA is faulty or damaged and needs to be replaced redundantly. The redundant word line decoding circuit 142 generates a corresponding redundant word line enable signal RWL_en and replaces a set of normal word lines corresponding to the word line addressing address RA. The replacement object is the redundant word line in the set of redundant word lines corresponding to the damaged word line address Efsadd that matches the word line addressing address RA.

[0039] In some embodiments, such as Figure 1 As shown, the processing circuit 14 also includes a common word line decoding circuit 143, which is coupled to an address matching circuit 141.

[0040] In response to the address matching circuit 141 determining that neither the word line addressing address RA nor the damaged word line address Efsadd matches, that is, when word line redundancy replacement is not required, the ordinary word line decoding circuit 143 is selected and receives the word line addressing address RA from the command decoder 13. Based on the word line addressing address RA, it generates a corresponding ordinary word line enable signal WL_en to drive the ordinary word line corresponding to the word line addressing address RA and complete the relevant operations of ordinary word line addressing.

[0041] In other words, in this application, the address matching circuit 141 issues a selection signal Select based on the matching result between the word line addressing address RA and the damaged word line address Efsadd, thereby selecting either the normal word line decoding circuit 143 or the redundant word line decoding circuit 142. When the address matching circuit 141 determines that the word line addressing address RA matches at least one of the damaged word line addresses Efsadd, the address matching circuit 141 selects the redundant word line decoding circuit 142 to perform redundant mapping replacement of the word line based on the damaged word line address Efsadd; when the address matching circuit 141 determines that neither the word line addressing address RA nor the damaged word line address Efsadd matches, the address matching circuit 141 selects the normal word line decoding circuit 143 to perform normal word line addressing operation based on the word line addressing address RA.

[0042] In summary, in this application, since the damaged word line addresses Efsadd stored in the programming memory circuit 12 include at least three types of damaged word line addresses, and the number of redundant word lines in the redundant word line group corresponding to each type of damaged word line address is different from the number of redundant word lines in the redundant word line group corresponding to other types of damaged word line addresses, when the word line addressing address RA matches a type of damaged word line address Efsadd (e.g., 8 damaged word line address, 4 damaged word line address, 2 damaged word line address, etc.), the corresponding word line can be simultaneously redundantly replaced. Therefore, the memory device 10 of this application has great flexibility when performing word line redundancy replacement operations. It can flexibly configure the type of damaged word line address to perform different types of word line redundancy replacement according to actual needs, which can not only provide repair efficiency but also avoid wasting word line and redundant word line resources.

[0043] For ease of understanding, such as Figure 2-6 As shown, Figure 2-6 This is a schematic diagram of a storage device according to another embodiment of this application. In this embodiment, the application is specifically explained by way of example.

[0044] In this embodiment, the working principle of this application is described using the example that the corrupted word line address Efsadd stored in the programming memory circuit 12 includes at least two types of corrupted word line addresses. Of course, those skilled in the art will understand that the corrupted word line address Efsadd stored in the programming memory circuit 12 in this application is not limited to three types of corrupted word line addresses, but may also include four types of corrupted word line addresses, five types of corrupted word line addresses, etc. This application does not limit this, as long as it conforms to the working principle described in this application.

[0045] Specifically, the corrupted word line address Efsadd stored in the programming and storage circuit 12 may include at least one type of corrupted word line address among the first type of corrupted word line address, the second type of corrupted word line address, and the third type of corrupted word line address. The first type of corrupted word line address corresponds to a first type of redundant word line group containing X redundant word lines, the second type of corrupted word line address corresponds to a second type of redundant word line group containing Y redundant word lines, and the second type of corrupted word line address corresponds to a second type of redundant word line group containing Z redundant word lines. X, Y, and Z are natural numbers. In this embodiment, X=8, Y=2, Z=2. The first type of redundant word line group corresponding to the first type of damaged word line address includes 8 redundant word lines, that is, 8 redundant word lines constitute a damaged word line address corresponding to a redundant word line group. The second type of redundant word line group corresponding to the second type of damaged word line address includes 4 redundant word lines, that is, 4 redundant word lines constitute a damaged word line address corresponding to a redundant word line group. The third type of redundant word line group corresponding to the third type of damaged word line address includes 2 redundant word lines, that is, 2 redundant word lines constitute a damaged word line address corresponding to a redundant word line group. It can be understood that in other embodiments, only the first type of damaged word line address and the third type of damaged word line address, the second type of damaged word line address and the third type of damaged word line address, etc., may be included.

[0046] Understandably, in response to the redundant word line decoding circuit 142 being configured to receive a first type of enable signal, such as the enable signal En1 (as described below) Figure 4 As shown), the word line replacement of the second type of word line and the word line replacement of the third type of word line are blocked in order to perform the word line replacement of the first type of word line. That is, the word line replacement corresponding to a redundant word line group of 4 redundant word lines and the word line replacement corresponding to a redundant word line group of 2 redundant word lines are blocked in order to perform the word line replacement corresponding to a redundant word line group of 8 redundant word lines.

[0047] In response to the redundant word line decoding circuit being configured to receive a second type of enable signal, such as enable signal En2 (as follows) Figure 4 As shown), the word line replacement of the first type of word line and the word line replacement of the third type of word line are blocked in order to perform the word line replacement of the second type of word line. That is, the word line replacement corresponding to a redundant word line group of 8 redundant word lines and the word line replacement corresponding to a redundant word line group of 2 redundant word lines are blocked in order to perform the word line replacement corresponding to a redundant word line group of 4 redundant word lines.

[0048] In response to the redundant word line decoding circuit being configured not to receive the first type enable signal and the second type enable signal, for example, not receiving enable signal En1 and enable signal En2, word line replacement of the first type word line and word line replacement of the second type word line are blocked to perform word line replacement of the third type word line. That is, word line replacement corresponding to a redundant word line group of 8 redundant word lines and word line replacement corresponding to a redundant word line group of 4 redundant word lines are blocked to perform word line replacement corresponding to a redundant word line group of 2 redundant word lines.

[0049] like Figure 3 As shown, the address matching circuit 141 includes a first address matching circuit 1411, a second address matching circuit 1412, and a third address matching circuit 1413. The first address matching circuit 1411 can be used to match a first type of address, i.e., a first type address matching circuit; the second address matching circuit 1412 is used to match a second type of address, i.e., a second type address matching circuit; and the third address matching circuit 1413 is used to match a third type of address, i.e., a third type address matching circuit. The redundant word line decoding circuit 142 includes a first redundant word line decoding circuit 1421, a second redundant word line decoding circuit 1422, and a third redundant word line decoding circuit 1423. The first redundant word line decoding circuit 1421 can be a first type of redundant word line decoding circuit; the second redundant word line decoding circuit 1422 can be a second type of redundant word line decoding circuit; and the third redundant word line decoding circuit 1423 can be a third type of redundant word line decoding circuit. The first type of redundant word line decoding circuit, the second type of redundant word line decoding circuit, and the third type of redundant word line decoding circuit are all logic gate circuits.

[0050] Address matching circuit 141 receives word line addressing address RA<14:0> transmitted from command decoder 13 and determines whether word line addressing address RA<14:0> matches a cached corrupted word line address. Specifically, when address matching circuit 1411 determines that word line addressing address RA matches a first type of corrupted word line address Efsadd, first redundant word line decoding circuit 1421 receives a first type enable signal to perform redundant mapping replacement of word lines based on the first type of corrupted word line address Efsadd. When address matching circuit 1412 determines that word line addressing address RA matches a second type of corrupted word line address Efsadd, second redundant word line decoding circuit 1422 receives a second type enable signal to perform redundant mapping replacement of word lines based on the second type of corrupted word line address Efsadd. When the address matching circuit 1413 determines that the word line addressing address RA matches the third type damaged word line address Efsadd, the third redundant word line decoding circuit 1423 does not receive the first type enable signal and the second type enable signal, and then performs redundant mapping replacement of the word line based on the third type damaged word line address Efsadd.

[0051] like Figure 4 As shown, the programming and storage circuit 12 includes a first programming unit 121, a second programming unit 122, and a third programming unit 123. The first programming unit 121 programs a first type of corrupted word line address (e.g., ...). Figure 4 Efsadd shown <RA<14:3> The second programming unit 122 contains the address of the second type of damaged word line (e.g., flag>), Figure 4 Efsadd shown <RA<14:2> The third programming unit 123 contains the address of the third type of damaged word line (e.g., flag>), Figure 4 Efsadd shown <RA<14:1> (,flag>).

[0052] Correspondingly, the redundant word line decoding circuit 142 includes, in addition to, Figure 3 The embodiment includes a first redundant word line decoding circuit 1421, a second redundant word line decoding circuit 1422, and a third redundant word line decoding circuit 1423. The redundant word line decoding circuit 142 further includes multiple first latch units 14211, multiple second latch units 14221, and multiple third latch units 14231, as shown below. Figure 4 As shown.

[0053] The redundant word line decoding circuit 142 further includes multiple first latching units 14211 corresponding to the first redundant word line decoding circuit 1421, for example, X first latching units 14211, used to latch the first type of damaged word line address Efsadd transmitted from the burning and storing circuit 12. <RA<14:3> ,flag>, wherein each first latch unit 14211 latches the first type of corrupted word line address Efsadd <RA<14:3> The address of the corresponding bit in the flag>; the first redundant word line decoding circuit 1421 further receives the first type of corrupted word line address latched by the first latch unit 14211. <RA<14:3> The function `flag>` receives the word line addressing address `RA` and the first type enable signal `En1` to perform a comparison operation for word line replacement of the first type word line. The address data (e.g., `RA<14:3>`) on the corresponding bits of the word line addressing address `RA` is compared with the first type corrupted word line address `Efsadd`. <RA<14:3> If they are the same, then perform word line replacement for the first type of word line, generating the corresponding redundant word line enable signal RWL_en to drive the matching first type of corrupted word line address Efsadd. <RA<14:3> The eight redundant word lines in the corresponding first-type redundant word line group are mapped to replace the set of ordinary word lines corresponding to the word line addressing address RA<14:3>.

[0054] Similarly, the redundant word line decoding circuit 142 also includes a plurality of second latching units 14221 corresponding to the second redundant word line decoding circuit 1422, for example, Y second latching units 14221, used to latch the second type of damaged word line address Efsadd transmitted from the programming memory circuit 12. <RA<14:2> ,flag>, where each second latch unit 14221 latches the second type of corrupted word line address Efsadd respectively. <RA<14:2> The address of the corresponding bit in the flag>; the second redundant word line decoding circuit 1422 further receives the second type of corrupted word line address latched by the second latch unit 14221. <RA<14:2> The function `flag>` receives the word line addressing address `RA` and the second type enable signal `En2` to perform a comparison operation for word line replacement of the second type word line. The address data (e.g., `RA<14:2>`) on the corresponding bits of the word line addressing address `RA` is compared with the second type corrupted word line address `Efsadd`. <RA<14:2> If they are the same, then perform word line replacement for the second type of word line, generating the corresponding redundant word line enable signal RWL_en to drive the matching second type corrupted word line address Efsadd. <RA<14:2> The four redundant word lines in the corresponding second-type redundant word line group are mapped to replace the set of ordinary word lines corresponding to the word line addressing address RA<14:2>.

[0055] Similarly, the redundant word line decoding circuit 142 also includes multiple third latch units 14231 corresponding to the third redundant word line decoding circuit 1421, such as Z third latch units 14231, used to latch the third type of damaged word line address Efsadd transmitted from the programming memory circuit 12. <RA<14:1> ,flag>, where each third latch unit 14231 latches the third type of corrupted word line address Efsadd respectively. <RA<14:1> The address of the corresponding bit in the flag>; the third redundant word line decoding circuit 1423 further receives the third type corrupted word line address latched by the third latch unit 14231. The third type corrupted word line address Efsadd <RA<14:1> The flag is used to perform a comparison operation for word line replacement of type 3 word lines. This is in response to the address data (e.g., RA<14:1>) on the corresponding bit of the word line addressing address RA and the type 3 corrupted word line address Efsadd. <RA<14:1> If they are the same, then perform word line replacement for the third type of word line, generating the corresponding redundant word line enable signal RWL_en to drive the matching third type corrupted word line address Efsadd. <RA<14:1> The two redundant word lines in the corresponding third type of redundant word line group are mapped to replace the set of ordinary word lines corresponding to the word line addressing address RA<14:1>.

[0056] Those skilled in the art will understand that a word-line addressed address is composed of multiple address signals. For example, in this application, a word-line addressed address may include a-bit address signals, which can be denoted as RA. <a-1:0>This refers to the address signal from bit 0 to bit a-1, where a is a preset value. In this embodiment, a = 15, so the word line addressing signal can be recorded as RA<(15-1=14):0>, that is, RA<14:0>.

[0057] The corrupted word line address Efsadd also includes multiple address signals and identifier signals. The number of bits in its address signals is less than that of the word line address, and it corresponds to the word line address RA. <a-1:0>The high-order address signal of the same number of bits. For example, the first type of corrupted word line address includes (ab) bits of high-order address signal and a first flag signal, which can be recorded as Efsadd. <RA <a-1:b>,flag>, where RA <a-1:b>Corresponding word line address RA <a-1:0>The high-order address signal (bits b to a-1, totaling ab bits) is used to characterize whether the current first-type redundant word line group, sequentially assigned to the first-type damaged word line address, is damaged. The second-type damaged word line address includes (ac) bits of high-order address signal and the second-identification signal flag, which can be recorded as Efsadd. <RA <a-1:c>,flag>, where RA <a-1:c>Corresponding word line address RA <a-1:0>The high-order address signal (ab bits in total) from bit c to bit a-1 in the middle, the second flag signal is used to indicate whether the current second-type redundant word line group corresponding to the second-type damaged word line address is damaged; the third-type damaged word line address includes the (ad) high-order address signal and the third flag signal, which can be recorded as Efsadd <RA <a-1:d>,flag>, where RA <a-1:d>Corresponding word line address RA <a-1:0>The high-order address signals from bit d to bit a-1 (a total of ab bits), for example a=15, b=3, c=2, d=1.

[0058] Furthermore, based on the word line addressing address RA<14:0> and the first type of corrupted word line address Efsadd <RA<14:3> The matching result of ,flag> is used to perform redundant replacement of the word line; based on the word line addressing address RA<14:0> and the second type of damaged word line address Efsadd <RA<14:2> The matching result of ,flag> is used to perform redundant replacement of 4 word lines; based on the word line addressing address RA<14:0> and the third type of damaged word line address Efsadd <RA<14:1> If the match result of ,flag> is used, then redundant replacement of the 2-character line is performed.

[0059] For example, when the address matching circuit 141 performs a matching judgment, if the first type of damaged word line address Efsadd... <RA<14:3> If the high-order address signal RA<14:3> in the flag> matches the word line addressing signal RA<14:0>, then the word line addressing signal RA<14:3> is considered to match the first type of damaged word line address Efsadd. <RA<14:3> Match the flag to select the first redundant word line decoder circuit 1421; if the second type of damaged word line address Efsadd <RA<14:2> If the high-order address signal RA<14:2> in the flag> is consistent with the word line addressing signal RA<14:0>, then the word line addressing signal RA<14:0> is considered to be consistent with the second type of damaged word line address Efsadd. <RA<14:2> Match ,flag> to select the second redundant word line decoder circuit 1422; if the third type of damaged word line address Efsadd <RA<14:1> The high-order address signal RA in the flag> <a-1:d>AND word line addressing signal RA <a-1:0>If they are consistent, then the word line addressing signal RA is considered to be consistent. <a-1:0>With the third type of damaged word line address Efsadd <RA <a-1:d>Match the flag to select the third redundant word line decoder circuit 1423.

[0060] At this point, we will take the replacement of the first type of character line as an example for explanation, such as... Figure 5 As shown, the redundant storage array area can be the size of a Bank. A Bank is divided into two regions, P0 and P1, and horizontally into m sections. n sections are grouped together, with a preset number of redundant word lines. When the first redundant word line decoding circuit 1421 receives a first-type enable signal (En1), it performs word line replacement for the first-type word lines and masks word line replacement for the second and third types. Using the logic gates of the first redundant word line decoding circuit 1421, the word line addressing address RA<14:3> is latched with the second-type damaged word line address Efsadd, which is latched by multiple first latch units 14211. <RA<14:3> > Match one by one, and based on the first type of corrupted word line address Efsadd of the match. <RA<14:3> The location of the first latch unit 14211 generates eight redundant word line enable signals RWL_en, namely RWL0_en to RWL7_en, to drive the matching first type of corrupted word line address Efsadd. <RA<14:3> The eight redundant word lines in the first type of redundant word line group are mapped to replace a set of ordinary word lines corresponding to the word line addressing address RA<14:3>. For example, RDN WL 0 to RDN WL 7 in partitions P0 and P1 in the figure can be replaced simultaneously.

[0061] Furthermore, let's take the replacement of character lines in the second type of character line as an example for explanation, such as... Figure 6 As shown, the second redundant word line decoding circuit 1422 receives a second type of enable signal, which includes enable signal En2a and enable signal En2b. These two signals cooperate to perform word line replacement for the second type of word line and mask word line replacement for the first and third types of word lines. Using the various logic gates of the second redundant word line decoding circuit 1422, the word line addressing address RA<14:2> is latched with the second type of damaged word line address Efsadd, which is latched by multiple second latch units 14221. <RA<14:2> >Match one by one, and based on the matched second type corrupted word line address Efsadd <RA<14:2> The location of the second latch unit 14221 generates four corresponding redundant word line enable signals RWL_en, namely RWL0_en to RWL3_en, or RWL4_en to RWL7_en, to drive the matching second-type corrupted word line address Efsadd. <RA<14:2> The four redundant word lines in the corresponding second-type redundant word line group are mapped to replace a set of ordinary word lines corresponding to the word line addressing address RA<14:2>. For example, they can simultaneously replace RDN WL 0 to RDN WL 3 in partitions P0 and P1 of the diagram, or in partitions P0 and P1, for example, if the address decoding RA is 0, it replaces RDN WL 0 to RDN WL 3 in partitions P0 and P1 of the diagram, and if the address decoding RA is 1, it replaces RDN WL 4 to RDN WL 7 in partitions P0 and P1 of the diagram. In addition, in some embodiments, such as Figure 4 As shown, the programming and storage circuit 12 further includes a bit line programming unit 124, wherein at least one bit line mapped address Efsadd (e.g., ...) is programmed in the bit line programming unit 124. Figure 4 Efsadd shown <CA<9:3> The bit line mapping address Efsadd can be the address of a faulty bit line found during testing before the DRAM leaves the factory. Each bit line mapping address Efsadd can correspond to a redundant bit line in a redundant bit line group. By using the bit line mapping address Efsadd, the simultaneous mapping and replacement of multiple redundant bit lines in its corresponding redundant bit line group can be performed.

[0062] Correspondingly, the processing circuit 14 also includes a bit line latch unit 144, which is used to cache the bit line mapping address programmed by the bit line programming unit 124. Furthermore, the bit line latch unit 144 also receives the bit line addressing address CA<9:3> transmitted from the command decoder 13, and compares the bit line addressing address CA<9:3> with the bit line mapping address Efsadd. <CA<9:3> The flag determines whether the bit-line addressing address CA<9:3> matches the cached bit-line mapping address Efsadd. <CA<9:3> The flag> match, where the bit-line address CA can be the bit-line address that the user wants to access, and determines the bit-line address CA<9:3> and the cached bit-line mapping address Efsadd. <CA<9:3> Match the flag and generate the corresponding redundant bit line enable signal RBL_en.

[0063] In summary, the storage device 10 of this application includes a storage array 11, a programming storage circuit 12, a command decoder 13, and a processing circuit 14. The processing circuit 14 is coupled to the programming storage circuit 12, the command decoder 13, and the storage array 11. The damaged word line addresses stored in the programming storage circuit 12 include at least two types of damaged word line addresses. Each type of damaged word line address corresponds to a type of redundant word line group, and the number of redundant word lines in each type of redundant word line group is different. Therefore, the processing circuit 14 can generate a corresponding redundant word line enable signal in response to the word line address matching at least one damaged word line address to drive the redundant word lines in the at least one redundant word line group corresponding to the matched at least one damaged word line address to map and replace a group of ordinary word lines corresponding to the word line address. Thus, this application improves the efficiency and flexibility of memory chip repair.

[0064] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0065] In the several embodiments provided in this application, it should be understood that the disclosed methods and related devices can be implemented in other ways. For example, the related device implementations described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication disconnection shown or discussed may be indirect coupling or communication disconnection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0066] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0067] Those skilled in the art will readily recognize that numerous modifications and variations can be made to the apparatus and method while maintaining the teachings of this application. Therefore, the above disclosure should be considered limited only by the scope of the appended claims.

Claims

1. A storage device, characterized in that, include: The storage array includes a normal storage array and a redundant storage array, wherein the redundant word lines in the redundant storage array are used to map and replace the normal word lines in the normal storage array, so that the redundant storage cells in the redundant storage array map and replace the damaged normal storage cells in the normal storage array. The programming and storage circuit is configured to store at least one corrupted word line address, wherein each corrupted word line address corresponds to a redundant word line of a redundant word line group; The command decoder is configured to generate corresponding word-line addressing addresses in response to user commands. A processing circuit is coupled to the programming and storage circuit, the command decoder, and the storage array; wherein the processing circuit is configured to receive the word line addressing address and the damaged word line address; in response to the word line addressing address matching a damaged word line address, generate a corresponding redundant word line enable signal to drive the redundant word lines in a set of redundant word lines corresponding to the matched damaged word line address to map and replace a set of ordinary word lines corresponding to the word line addressing address; The damaged word line addresses stored in the programming and storage circuit may include at least three types of damaged word line addresses. Each type of damaged word line address corresponds to a type of redundant word line group, and the number of redundant word lines in the various types of redundant word line groups is different.

2. The storage device according to claim 1, characterized in that, The damaged word line addresses stored in the programming and storage circuit may include at least one type of damaged word line address, a first type of damaged word line address, a second type of damaged word line address, and a third type of damaged word line address. Each first type of damaged word line address corresponds to a first type of redundant word line group, which includes X redundant word lines. Each second type of damaged word line address corresponds to a second type of redundant word line group, which includes Y redundant word lines. Each third type of damaged word line address corresponds to a third type of redundant word line group, which includes Z redundant word lines. X, Y, and Z are natural numbers.

3. The storage device according to claim 2, characterized in that, The processing circuit includes: An address matching circuit is coupled to the programming memory circuit and the command decoder, wherein the address matching circuit is configured to cache the corrupted word line address from the programming memory circuit, receive the word line addressing address from the command decoder, and compare the word line addressing address with the corrupted word line address to determine whether the word line addressing address matches at least one of the corrupted word line addresses.

4. The storage device according to claim 2, characterized in that, The processing circuit includes: A redundant word line decoding circuit, coupled to the address matching circuit, responds to the address matching circuit in determining that the word line addressing address matches at least one of the damaged word line addresses. The redundant word line decoding circuit is configured to receive at least one type of enable signal, receive the matched damaged word line address from the address matching circuit, generate a corresponding redundant word line enable signal based on the matched damaged word line address, and drive the redundant word lines in a set of redundant word lines corresponding to the matched damaged word line address to map and replace a set of ordinary word lines corresponding to the word line address.

5. The storage device according to claim 4, characterized in that, The at least one type of enable signal includes a first type of enable signal and a second type of enable signal; In response to the redundant word line decoding circuit being configured to receive the first type enable signal, the word line replacement of the second type of word line and the word line replacement of the third type of word line are blocked in order to perform the word line replacement of the first type of word line; In response to the redundant word line decoding circuit being configured to receive the second type enable signal, word line replacement of the first type of word line and word line replacement of the third type of word line are blocked in order to perform word line replacement of the second type of word line; In response to the redundant word line decoding circuit being configured not to receive the first type enable signal and the second type enable signal, word line replacement of the first type word line and word line replacement of the second type word line are masked in order to perform word line replacement of the third type word line.

6. The storage device according to claim 5, characterized in that, In response to the redundant word line decoding circuit being configured to receive the first type enable signal, wherein the word line addressing address matches a first type damaged word line address, the address matching circuit outputs the matched first type damaged word line address to the redundant word line decoding circuit; the redundant word line decoding circuit generates a corresponding redundant word line enable signal based on the matched first type damaged word line address, to drive X redundant word lines in the first type redundant word line group corresponding to the matched first type damaged word line address to map and replace a group of ordinary word lines corresponding to the word line addressing address; or In response to the redundant word line decoding circuit being configured to receive a second word line type signal, wherein the word line addressing address matches a second type corrupted word line address, the address matching circuit outputs the matched second type corrupted word line address to the redundant word line decoding circuit; the redundant word line decoding circuit generates a corresponding redundant word line enable signal based on the matched second type corrupted word line address, to drive Y redundant word lines in the second type redundant word line group corresponding to the matched second type corrupted word line address to map and replace a group of ordinary word lines corresponding to the word line addressing address; or In response to the redundant word line decoding circuit being configured not to receive the first type enable signal and the second type enable signal, wherein the word line addressing address matches a third type damaged word line address, the address matching circuit outputs the matched third type damaged word line address to the redundant word line decoding circuit; the redundant word line decoding circuit generates a corresponding redundant word line enable signal based on the matched third type damaged word line address, so as to drive Z redundant word lines in the third type redundant word line group corresponding to the matched third type damaged word line address to map and replace a group of ordinary word lines corresponding to the word line addressing address.

7. The storage device according to claim 4, characterized in that, The word line addressing address includes a bit address signal; The first type of damaged word line address includes (ab) bits of high-order address signal and a first identifier signal, wherein each first type of damaged word line address corresponds to a first type of redundant word line group, and the first type of redundant word line group includes X=2 b The redundant word lines, wherein the first identification signal indicates whether a group of redundant word lines of the first type corresponding to the first type of damaged word line address is damaged; in response to the address signal of the a-bit address signal of the word line addressing address being consistent with the high-bit address signal of the (ab) bits of a first type of damaged word line address, the word line addressing address is matched with the first type of damaged word line address. The second type of corrupted word line address includes a (ac)-bit high-order address signal and a second identifier signal, wherein each second type of corrupted word line address corresponds to a second type of redundant word line group, and the second type of redundant word line group includes Y=2 c The redundant word lines, the second identification signal characterizes whether a group of redundant word lines of the second type corresponding to the second type of damaged word line address is damaged; in response to the c-th to (a-1)-th high-order address signal in the a-bit address signal of the word line addressing address being consistent with the high-order address signal in the (ac)-th bit of a second type of damaged word line address, the word line addressing address matches the second type of damaged word line address; The third type of corrupted word line address includes an (ad)-bit high-order address signal and a third identifier signal, wherein each third type of corrupted word line address corresponds to a third type of redundant word line group, and the third type of redundant word line group includes Z=2 d The redundant word lines, the third identification signal characterizes whether a group of redundant word lines corresponding to the third type of damaged word line address is damaged; in response to the high-order address signal of the a-bit address signal of the word line addressing address being consistent with the high-order address signal of the (ad) bit in the third type of damaged word line address, the word line addressing address matches the third type of damaged word line address.

8. The storage device according to claim 7, characterized in that, The first type of redundant word line group corresponding to the first type of damaged word line address includes 8 redundant word lines, where X = 8; The second type of redundant word line group corresponding to the second type of damaged word line address includes 4 redundant word lines, where Y = 4; The second type of redundant word line group corresponding to the second type of damaged word line address includes 2 redundant word lines, where Z = 2; The word line addressing address includes a 15-bit address signal, defined as ra<14:0>, where a = 15; The first type of corrupted word line address includes a 12-bit high-order address signal <14:3> and a first flag signal. The first type of corrupted word line address is defined as efsadd<14:3,flag>, where b=3; The second type of corrupted word line address includes a 13-bit high-order address signal <14:2> and a second flag signal. The second type of corrupted word line address is defined as efsadd<14:2,flag>, where c=2; The third type of corrupted word line address includes a 14-bit high-order address signal <14:1> and a third identifier signal flag. The third type of corrupted word line address is defined as efsadd<14:1, flag>, where d=1.

9. The storage device according to claim 7, characterized in that, The processing circuit further includes: A redundant word line decoding circuit, wherein the redundant word line decoding circuit includes a first type of redundant word line decoding circuit, a second type of redundant word line decoding circuit, and a third type of redundant word line decoding circuit, wherein the first type of redundant word line decoding circuit, the second type of redundant word line decoding circuit, and the third type of redundant word line decoding circuit are logic gate circuits. In response to the word line addressing address matching the first type of damaged word line address, the first type of redundant word line decoding circuit drives X redundant word lines in the first type of redundant word line group corresponding to the matched first type of damaged word line address; In response to the word line addressing address matching the second type of damaged word line address, the second type of redundant word line decoding circuit drives Y of the redundant word lines in the second type of redundant word line group corresponding to the matched second type of damaged word line address; In response to the word line addressing address matching the third type of damaged word line address, the third type of redundant word line decoding circuit drives Z of the redundant word lines in the third type of redundant word line group corresponding to the matched third type of damaged word line address.

10. The storage device according to claim 9, characterized in that, The redundant word line decoding circuit further includes: X first latch units corresponding to the first type of redundant word line decoding circuit, used to latch X bits of the first type of damaged word line address from the programming memory circuit; Y second latch units corresponding to the second type of redundant word line decoding circuit, used to latch Y bits of the second type of damaged word line address from the programming memory circuit; and Z third latch units corresponding to the third type of redundant word line decoding circuit, used to latch Z bits of the third type of damaged word line address from the programming memory circuit.

11. The storage device according to claim 9, characterized in that, The address matching circuit includes a first address matching circuit, a second address matching circuit, and a third address matching circuit, wherein, The first address matching circuit determines whether the address signals of the higher bits (bits b to (bit-1)) of the a-bit address signal of the word line addressing address are consistent with the higher bits (bits ab) of the (bits ab) address signal in the first type of damaged word line address. The second address matching circuit determines whether the address signal of the high-order bits from the c-th to the (a-1)-th bits in the a-bit address signal of the word line addressing address is consistent with the high-order address signal of the (ac)-th bit in the second type of damaged word line address; The third address matching circuit determines whether the address signals of the higher bits from the d-th to the (a-1)-th bits in the a-bit address signal of the word line addressing address are consistent with the higher bits of the (ad)-th bit address signal in the third type of damaged word line address.

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