3d computing circuit with high density z-axis interconnects

Abstract

Some embodiments of the present invention provide a 3D computing circuit with high density Z-axis interconnects, the circuit comprising a first integrated circuit (IC) die comprising a first processor core; and a second IC die vertically mounted on the first IC die, the IC die including a first cache for the first processor core, where the first cache vertically overlaps at least a portion of the first processor core at an overlap region, and the first IC die is communicatively coupled with the second IC die by a hybrid bond, where the first cache vertically overlaps at least a portion of the first processor core at the overlap region. The hybrid bond includes a plurality of directly bonded metal contact pads and a directly bonded non-conductive region, and wherein the first processor core is electrically connected to the first cache through at least one metal contact pad of the plurality of directly bonded metal contact pads disposed within the overlap region.

Description

Related application citation

[0001] This application is a divisional application of the invention patent application with international application number PCT / US2018 / 056559, international application date of October 18, 2018, entry into the Chinese national phase date of June 18, 2020, Chinese national application number 201880082142.3, and invention title "3D computing circuit with high-density Z-axis interconnection". Background Technology

[0002] Electronic circuits are typically fabricated on wafers of semiconductor materials such as silicon. Wafers containing such electronic circuits are usually diced into multiple dies, each called an integrated circuit (IC). Each die is housed in an IC casing and is commonly referred to as a microchip, "chip," or IC chip. According to Moore's Law (first proposed by Gordon Moore), the number of transistors that can be defined on an IC die roughly doubles every two years. This law has held true for the past 50 years thanks to advancements in semiconductor manufacturing processes. However, in recent years, as we have reached the maximum number of transistors that can be defined on a semiconductor substrate, the end of Moore's Law has been foreseen. Therefore, further advancements in the field are needed to allow for the definition of even more transistors in IC chips. Summary of the Invention

[0003] Some embodiments of the present invention provide a three-dimensional (3D) circuit formed by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In this arrangement, several circuit blocks (1) defined on each die overlap with other circuit blocks defined on one or more other dies, and (2) are electrically connected to these other circuit blocks via connections that pass through one or more bonding layers that bond one or more pairs of dies. In some embodiments, the 3D circuit can be any type of circuit, such as: a processor, such as a CPU (Central Processing Unit), GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), etc.; or other types of circuits, such as an FPGA (Field Programmable Gate Array), AI (Artificial Intelligence) neural network chip, encryption / decryption chip, etc.

[0004] In some embodiments, the connections pass through one or more bonding layers in a direction perpendicular to the bonding surface. In some embodiments, overlapping, connected circuit block pairs include compute block pairs and compute and memory block pairs. Connections that pass through the bonding layers to electrically connect circuit blocks on different dies are hereinafter referred to as z-axis wiring or connections. This is because these connections traverse entirely or primarily along the z-axis of the 3D circuit, while the x and y axes of the 3D circuit define the planes of the IC die substrate or interconnect layers. These connections are also referred to as vertical connections to distinguish them from horizontal plane connections along the interconnect layers of the IC die.

[0005] The foregoing summary is intended as a brief introduction to some embodiments of the invention. It is not intended to be a description or overview of all inventive subjects disclosed in this document. The following detailed description and the accompanying drawings referenced in the detailed description will further describe the embodiments described in the summary and other embodiments. Therefore, a full review of the summary, detailed description, drawings, and claims is necessary to understand all the embodiments described in this document. Attached Figure Description

[0006] The novel features of this invention are set forth in the appended claims. However, for illustrative purposes, several embodiments of the invention are illustrated in the following drawings.

[0007] Figure 1 3D circuits of some embodiments of the present invention are shown.

[0008] Figure 2 An example of a high-performance 3D processor is shown, which has a multi-core processor on one die and embedded memory on another die.

[0009] Figure 3 This demonstrates how prevalent multi-core processors are in many devices today.

[0010] Figure 4 An example of a 3D processor formed by vertically stacking three bare dies is shown.

[0011] Figure 5 Three vertically stacked dies are shown, wherein the back side of the second die is thinned by a thinning process after the first and second dies are joined face-to-face but before the third die is mounted face-to-face to the second die.

[0012] Figure 6-9 Other 3D processors are shown in some embodiments.

[0013] Figure 10 Some embodiments are shown where two computing circuits performing sequential computations are placed on different stacked dies.

[0014] Figure 11 An example of a high-performance 3D processor with overlapping processor cores on different dies is shown.

[0015] Figure 12 This illustrates another example of a high-performance 3D processor with a processor core on one die and a cache on another die.

[0016] Figure 13An example of a 3D processor with different portions of the processor core on two dies mounted face-to-face is shown.

[0017] Figure 14 The computing circuitry on the first die is shown overlapping with the memory circuitry on the second die, which is vertically stacked on the first die.

[0018] Figure 15 This illustrates two overlapping computational circuits on two vertically stacked dies.

[0019] Figure 16 An array of computing circuitry on a first die is shown overlapping with an array of memory on a second die, which is mounted face-to-face with the first die via a direct bonding interconnect (DBI) bonding process.

[0020] Figure 17 This illustrates a traditional approach of interleaving memory arrays with compute arrays.

[0021] Figure 18 and 19 Two examples are shown that illustrate how high-density DBI connections can be used to reduce the size of the arrangement of computational circuits consisting of several consecutive circuit stages, each performing computations that produce results through to the next stage of the circuit until the final stage of the circuit is reached.

[0022] Figure 20 A computational circuit is presented that performs calculations (such as addition or multiplication) on sixteen-bit input values ​​on two face-to-face mounted dies.

[0023] Figure 21 A device using 3D ICs is shown.

[0024] Figure 22 An example of a 3D chip is provided, which is formed by two IC dies mounted face-to-face on a ball grid array.

[0025] Figure 23 The manufacturing process of some embodiments used to produce 3D chips is shown.

[0026] Figure 24-27 It shows that it is in Figure 23 Two wafers at different stages of the manufacturing process.

[0027] Figure 28 An example of a 3D chip with three stacked IC dies is shown.

[0028] Figure 29 An example of a 3D chip with four stacked IC dies is shown.

[0029] Figure 30The diagram illustrates a 3D chip formed by mounting three smaller dies face-to-face on a larger die. Detailed Implementation

[0030] In the following detailed description of the invention, numerous details, examples, and embodiments of the invention are set forth and described. However, it will be apparent to those skilled in the art that the invention is not limited to the described embodiments, and that the invention can be practiced without certain specific details and examples discussed.

[0031] Some embodiments of the present invention provide three-dimensional (3D) circuits formed by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In this arrangement, several circuit blocks (1) defined on each die overlap with other circuit blocks defined on one or more other dies, and (2) are electrically connected to these other circuit blocks by connections spanning one or more bonding layers that bond one or more pairs of dies. In some embodiments, the overlapping, connected pairs of circuit blocks include computation block pairs and computation and memory block pairs.

[0032] In the following discussion, connections that pass through bonding layers to electrically connect circuit blocks on different dies are referred to hereinafter as z-axis wiring or connections. This is because these connections traverse entirely or mostly along the z-axis of the 3D circuitry (e.g., because in some embodiments, these connections pass through bonding layers(s) in a direction perpendicular to or nearly perpendicular to the bonding surface), where the x and y axes of the 3D circuitry define the surfaces of the IC die substrate or interconnect layers. These connections are also referred to as vertical connections to distinguish them from horizontal plane connections along the interconnect layers of the IC die.

[0033] The discussion above and below concerns different circuit blocks on different dies that overlap each other. As shown in the figures below, two circuit blocks on two vertically stacked dies overlap vertically in their horizontal cross-sections (i.e., their horizontal coverage areas) (i.e., they overlap in the vertical direction).

[0034] Figure 1 An example of such a 3D circuit is shown. Specifically, a 3D circuit 100 is shown, which is formed by vertically stacking two IC dies 105 and 110 such that each (1) of several circuit blocks on one die overlaps with at least one other circuit block on the other die, and (2) is partially electronically connected to the overlapping dies by a z-axis connection 150 passing through a bonding layer that bonds the two IC dies. In this example, the two dies 105 and 110 are mounted face-to-face, as further described below. Moreover, although not in Figure 1As shown, however, in some embodiments, the stacked first and second dies are packaged into an integrated circuit package by encapsulating epoxy resin and / or a die box.

[0035] As shown in the figure, the first die 105 includes a first semiconductor substrate 120 and a first interconnect layer assembly 125 defined above the first semiconductor substrate 120. Similarly, the second IC die 110 includes a second semiconductor substrate 130 and a second interconnect layer assembly 135 defined below the second semiconductor substrate 130. In some embodiments, a plurality of electronic components (e.g., active components such as transistors and diodes; or passive components such as resistors and capacitors) are defined on the first semiconductor substrate 120 and the second semiconductor substrate 130.

[0036] Electronic components on the first substrate 120 are interconnected with each other via interconnect wiring on the first interconnect layer set 125 to form numerous microcircuits (e.g., Boolean gates, such as AND gates, OR gates, etc.) and / or larger circuit blocks (e.g., functional blocks, such as memory, decoder, logic unit, multiplier, adder, etc.). Similarly, electronic components on the second substrate 130 are interconnected with each other via interconnect wiring on the second interconnect layer set 135 to form additional microcircuits and / or larger circuit blocks.

[0037] In some embodiments, a portion of the interconnect wiring required to define a circuit block on the substrate of one die (e.g., substrate 120 of the first die 105) is provided by one or more interconnect layers (e.g., second interconnect layer set 135) of another die (e.g., the second die 110). In other words, in some embodiments, electronic components on the substrate of one die (e.g., the first substrate 120 of the first die 105) are also connected to other electronic components on the same substrate (e.g., substrate 120) via interconnect wiring on the interconnect layer set of the other die (e.g., the second interconnect layer set 135 of the second die 110) to form a circuit block on the first die.

[0038] Thus, in some embodiments, the interconnect layer of one die can be shared by electronic components and circuitry of another die. As described in U.S. Patent Application 15 / 976,815, filed May 10, 2018, which is incorporated herein by reference, the interconnect layer of one die can also be used to deliver power, clock, and data signals to electronic components and circuitry of another die. In the following discussion, the interconnect layer shared between two dies will be referred to as a shared interconnect layer.

[0039] Each interconnect layer of an IC die typically has a preferred routing orientation (also known as a routing direction). Furthermore, in some embodiments, the preferred routing orientations of consecutive interconnect layers of the IC die are orthogonal to each other. For example, although several routing architectures employing 45-degree and 60-degree offsets between the preferred routing orientations of consecutive interconnect layers have been introduced, the preferred routing orientations of an IC die typically alternate between horizontal and vertical preferred routing orientations. Alternating routing orientations between consecutive interconnect layers of an IC die has several advantages, such as providing better signal routing and avoiding capacitive coupling between long parallel segments on adjacent interconnect layers.

[0040] In order to form Figure 1 In the 3D circuit 100, a first die and a second die are stacked face-to-face, such that a first interconnect layer assembly 125 and a second interconnect layer assembly 135 face each other. The top interconnect layers 160 and 165 are bonded to each other via a direct bonding process that establishes a direct contact metal-to-metal bond, oxide bond, or fusion bond between the two interconnect layer assemblies. An example of such a bond is a copper-copper (Cu-Cu) metal bond between two directly contacting copper conductors. In some embodiments, the direct bonding is provided using hybrid bonding technologies such as DBI® (Direct Bond Interconnect) technology and other metal bonding technologies, such as those offered by Invensas Bonding Technologies, Inc. of Xperi Corporation, San Jose, California. In some embodiments, the DBI connection spans both silicon oxide and silicon nitride surfaces.

[0041] The DBI process is further described in U.S. Patents 6,962,835 and 7,485,968, both of which are incorporated herein by reference. The process is also described in U.S. Patent Application 15 / 725,030, which is also incorporated herein by reference. As described in U.S. Patent Application 15 / 725,030, a direct bonding connection between two face-to-face mounted IC dies is a native interconnect that allows signals to cross two different dies without a standard interface and without an input / output protocol at the cross-die boundary. In other words, a direct bonding interconnect allows native signals from one die to be directly passed to another die without modification or negligible modification of the native signals, thus abandoning standard interface connections and adopting federated input / output protocols.

[0042] Direct bonding interconnects allow circuitry to be formed across the die boundaries of two face-to-face mounted dies and / or accessed through the die boundaries of two face-to-face mounted dies. Examples of such circuitry are further described in U.S. Patent Application 15 / 725,030. Combined U.S. Patents 6,962,835, 7,485,968, and 15 / 725,030 also describe manufacturing techniques for fabricating two face-to-face mounted dies.

[0043] The DBI connection between two dies terminates at an electrical contact (referred to as a pad in this document) on the top interconnect layer of each die. Through interconnects and / or vias on each die, the DBI connection pads on each die electrically connect the DBI connection to circuit nodes on the die that need to provide signals to or receive signals from the DBI connection. For example, the DBI connection pads connect to interconnect segments on the top interconnect layer of the die, and then the signals are transported to circuit blocks on the die substrate through a series of vias and interconnects. Vias are z-axis structures on each die that transport signals between interconnect layers of the die and between the IC die substrate and the interconnect layer of the die.

[0044] like Figure 1 As shown, the direct bonding technique in some embodiments allows for the establishment of a large number of direct connections 150 between the top interconnect layer 165 of the second die 110 and the top interconnect layer 160 of the first die 105. In some embodiments, to allow these signals to traverse to other interconnect layers of the first die 105 or the substrate 120 of the first die 105, the first die uses other IC structures (e.g., vias) to transport these signals from its top interconnect layer to these other layers and / or the substrate. In some embodiments, more than 1,000 connections / mm can be established between the top interconnect layers 160 and 165 of the first die 105 and the second die 110. 2 10,000 connections / mm 2 100,000 connections / mm 2 1,000,000 connections / mm 2 Or smaller, etc., to allow signals to cross between the first IC die and the second IC die.

[0045] The length of the direct bonding connection 150 between the first and second dies is very short. For example, based on current manufacturing technology, the range of direct bonding connections can be from a fraction of a micrometer to a single or lower two-digit micrometer (e.g., 2-10 micrometers). As further described below, the short length of these connections allows signals to quickly reach their destination across these connections while experiencing little or no capacitive load from nearby planar wiring and nearby direct bonding vertical connections. Planar wiring connections are referred to as xy-wiring or connections because such wiring largely remains within the plane defined by the xy-axis of the 3D circuit. On the other hand, vertical connections between two dies or between two interconnect layers are referred to as z-axis wiring or connections because such wiring typically traverses the z-axis of the 3D circuit. The use of "vertical" when referring to z-axis connections should not be confused with planar wiring in the preferred horizontal or vertical direction that traverses a single interconnect layer.

[0046] In some embodiments, the spacing (distance) between two adjacent direct bonding connections 150 can be very small, for example, between 0.5 μm and 15 μm. This close proximity allows for a large number and high density of such connections between the top interconnect layers 160 and 165 of the first die 105 and the second die 110. Furthermore, the close proximity of these connections does not introduce too much capacitive load between two adjacent z-axis connections because of their short length and small interconnect pad size. For example, in some embodiments, the length of the direct bonding connection is less than 1 or 2 μm (e.g., 0.1 to 0.5 μm), and even considering the via length on each die, it facilitates short z-axis connections (e.g., 1 to 10 μm in length) between two different locations on the two dies. In summary, the direct vertical connections between the two dies provide a short and fast path between different locations on these dies.

[0047] Electrical nodes in the overlapping portions of circuit blocks on the first and second dies can be electrically connected via z-axis connections 150 (e.g., DBI connections). These electrical nodes can be on the IC die substrate (e.g., on the substrate portion containing the electronic component nodes of the circuit blocks) or on the IC die interconnect layers (e.g., on the interconnect wiring forming the circuit blocks). When these electrical nodes are not on the top interconnect layer connected via the z-axis connection, vias can be used to transport signals to or from the z-axis connection to these nodes. On each IC die, vias are z-axis structures for transporting signals between interconnect layers and between the IC die substrate and the interconnect layers.

[0048] Figure 1A plurality of z-axis connections 150 are shown between overlapping regions 181-185 in top interconnect layers 160 and 165. Each of these regions corresponds to a circuit block 171-175 defined on one of IC die substrates 120 and 130. Moreover, each region on the top interconnect layer of one die is connected to one or more overlapping regions in the top interconnect layer of another die via a plurality of z-axis connections. Specifically, as shown, the z-axis connections connect overlapping regions 181 and 184, regions 182 and 184, and regions 183 and 185. Vias are used to provide signals from the IC die substrate and interconnect layers to these z-axis connections. Similarly, vias are also used to carry signals from the z-axis connections when electrical nodes that need to receive these signals are located on the die substrate or an interconnect layer below the top layer.

[0049] When the z-axis connection is a DBI connection, the connection density between overlapping connection areas can reach 1,000 connections / mm. 2 Up to 1,000,000 connections / mm 2 Within this range. Furthermore, the spacing between two adjacent direct bonding connections 150 can be very small, for example, between 0.5 μm and 15 μm. Additionally, these connections can be very short, for example, in the range from fractions of a micrometer to low single-digit micrometers. Even considering interconnect vias and wires, these short DBI connections will allow for very short signal paths (e.g., single-digit or low double-digit micrometers, such as 2-20 micrometers) between the circuit nodes of two electrically connected circuits on the two substrates of the IC dies 105 and 110.

[0050] exist Figure 1 In the example shown, each top interconnect layer region 181-185 corresponds to a circuit block region 171-175 on the IC die substrate 120 or 130. Those skilled in the art will recognize that the corresponding top interconnect layer region of a circuit block (i.e., the region used to establish the z-axis connection of that circuit block) does not necessarily completely overlap with the circuit block region on the IC substrate. Furthermore, in some embodiments, all z-axis connections used to connect two overlapping circuit blocks in two different dies do not connect a continuous region in the top interconnect layer of one die to another continuous region in the top interconnect layer of the other die.

[0051] Similarly, in some embodiments, z-axis connections connect non-overlapping circuits on two dies (i.e., preventing any horizontal cross-sections from vertically overlapping). However, it is advantageous to use z-axis connections to electrically connect overlapping circuits (e.g., circuit blocks 173 and 175, circuit blocks 171 and 174, etc.) on two dies 105 and 110 (e.g., circuits with vertically overlapping horizontal cross-sections) because such overlap significantly increases the number of candidate locations for connecting the two circuits. When two circuits are placed adjacent to each other on a substrate, the number of connections that can be established between them is limited by the number of connections that can be established through their perimeters on one or more interconnect layers. However, by placing two circuits in two overlapping regions on two vertically stacked dies, the connections between the two circuits are not limited to peripheral connections through the circuit perimeters, but also include z-axis connections (e.g., DBI connections and connections via) available through the region of the overlapping region.

[0052] In many cases, stacked IC dies allow for significantly shorter wiring for signal transmission because stacking provides more candidate locations for shorter connections between overlapping circuit blocks that need to be interconnected to receive these signals. For example, in Figure 1 In this circuit, circuit blocks 173 and 175 on dies 105 and 110 share a data bus 190 on the top interconnect layer of the second die 110. This data bus carries data signals to these two circuits.

[0053] Direct-attached connections are used to transport signals from the data bus 190 to circuit block 175 on the first die 105. These direct-attached connections are much shorter than connections that route data bus signals across approximately several functional blocks on the first die to reach circuit block 175 from the periphery of those blocks. Data signals traversing these short direct-attached connections reach circuit 175 on the first die very quickly (e.g., within one or two clock cycles) because they do not require routing from the periphery of the destination block. On less congested shared interconnect layers, data bus lines can be placed above or near the destination circuit on the first die to ensure that data bus signals on this line can be provided to the destination circuit via short-attached connections.

[0054] Z-axis connectivity and the ability to share interconnect layers across multiple dies reduce congestion and routing limitations that are more restrictive on one die than on another. Stacking IC dies also reduces the total number of interconnect layers between two dies because it allows two dies to share some of the higher-level interconnect layers for easier signal distribution. Reducing higher-level interconnect layers is beneficial because wiring on these layers typically takes up more space due to its thicker, wider, and coarser arrangement.

[0055] Even in Figure 1In this embodiment, two dies are mounted face-to-face. Those skilled in the art will recognize that in other embodiments, the two dies are stacked vertically in other arrangements. For example, in some embodiments, the two dies are stacked face-to-face (i.e., the interconnect layer assembly of one die is mounted near the back side of the semiconductor substrate of the other die) or stacked back-to-back (i.e., the back side of the semiconductor substrate of one die is mounted adjacent to the back side of the semiconductor substrate of the other die).

[0056] In other embodiments, a third die (e.g., an interposer die) is placed between the first and second dies, with the first and second dies stacked face-to-face, face-to-back (where the third die is located between the back side of the substrate of one die and the interconnect layer assembly of the other die), or back-to-back (where the third die is located between the back sides of the substrates of the first and second dies). Furthermore, as referenced... Figure 4 Further described, in some embodiments, the vertical stacking of dies includes three or more IC dies in a stack. While some embodiments use direct bonding techniques to establish connections between the top interconnect layers of two face-to-face stacked dies, other embodiments use alternative connection schemes (such as through-silicon vias (TSVs), through-oxide vias (TOVs), or through-glass vias (TGVs)) to establish connections between back-to-back dies and between back-to-back dies.

[0057] exist Figure 1 In different embodiments, the overlapping circuit blocks 171-175 on the two dies 105 and 110 are blocks of different types. In some embodiments, examples of such blocks include memory blocks for storing data, computation blocks for performing calculations on the data, and I / O blocks for receiving and outputting data from the 3D circuit 100. To provide a more specific example of the overlapping circuit blocks, Figure 2 , 4 Figures 6 and 7 illustrate several different overlapping memory block, compute block, and / or I / O block architectures in some embodiments. Some of these examples illustrate high-performance 3D multi-core processors. Then, Figure 10-11 Several examples of overlapping computing modules are shown, including different cores of a multi-core processor placed on different IC dies. Figure 13 An example of overlapping functional blocks of a processor core is shown.

[0058] Figure 2An example of a high-performance 3D processor 200 is shown, which has a multi-core processor 250 on one die 205 and an embedded memory 255 on another die 210. As shown in the figure, the horizontal cross-section of the multi-core processor and the horizontal cross-section of the embedded memory overlap substantially perpendicularly. Similarly, in this example, the two dies 205 and 210 are mounted face-to-face via a direct bonding process such as the DBI process. In other embodiments, the two dies may be mounted face-to-back or back-to-back.

[0059] like Figure 2 As shown, numerous z-axis connections 150 pass through a direct bonding layer that bonds the two IC dies 205 and 210 together to establish numerous signal paths between the multi-core processor 250 and the embedded memory 255. When using the DBI process to bond the two dies 205 and 210, the z-axis connections can reach 1,000 connections / mm. 2 Up to 1,000,000 connections / mm 2 Within this range. Thus, the DBI z-axis connection allows for defining a wide variety of signal paths between the multi-core processor 250 and the embedded memory 255.

[0060] The DBI z-axis connection 150 also supports very fast signal paths because DBI connections are typically very short (e.g., 0.2µm to 2µm). The total length of the signal path is also typically short because the signal path is mostly vertical. The signal path typically relies on interconnects (on the interconnect layers) and vias (between the interconnect layers) to connect the nodes of processor 250 and embedded memory 255. However, the signal paths are typically vertical because they often connect nodes 250 in the same approximate Z-shaped cross section. Assuming the DBI connection is very short, the length of the vertical signal path primarily considers the height of the interconnect layers of die 205 and 210, typically in the single to low double digits of micrometers (e.g., the length of the vertical signal path is typically between 10-20µm).

[0061] Because the z-axis connections provide short, fast, and abundant connectivity between the multi-core processor 250 and the embedded memory 255, they allow the embedded memory 255 to replace many of the external memories commonly used in devices employing multi-core processors today. In other words, the robust z-axis connections between vertically stacked IC dies enable next-generation system-on-a-chip (SoC) architectures to combine the computing power of the fastest multi-core processors with large embedded memories that can replace external memory.

[0062] To better illustrate this point, Figure 3This illustrates how multi-core processors are commonly used in many devices today. As shown, the multi-core processor 350 in device 305 typically communicates with multiple external memories 310 of device 305 via an external I / O interface 355, such as a Double Data Rate (DDR) interface. As further shown, the multi-core processor has multiple general-purpose processing cores 352 and one or more graphics processing cores 354 forming a graphics processing unit 356 of processor 350.

[0063] Each processing core has its own Level 1 (L1) cache 362 to store data. Furthermore, multiple Level 2 (L2) caches 364 are used to allow different processing cores to store their data for access by themselves and other cores. One or more Level 3 (L3) caches 366 are also used to store data retrieved from external memory 310 and to provide data to external memory 310. Different cores access the L2 and L3 caches via an arbitrator 368. As shown, an I / O interface 355 is used to retrieve data from the L3 cache 366 and processing cores 352 and 354. L1 caches typically have faster access times than L2 caches, and L2 caches, in turn, typically have faster access times than L3 caches.

[0064] I / O interfaces consume significant power and have limited I / O functionality. Typically, I / O interfaces must serialize and deserialize input and output data, which not only consumes power but also limits the input / output capabilities of multi-core processors. Similarly, Figure 3 The architecture shown requires sufficient wiring to route signals between the various components and I / O interfaces of the multi-core processor.

[0065] By replacing external memory with one or more embedded memories 255 vertically stacked with the multi-core processor 250 in the same IC package, power consumption, wiring, and processor I / O bottlenecks can be significantly improved. This arrangement greatly reduces the bottlenecks in the multi-core processor 250 and its external memory (in... Figure 2 The length of the wires required to transport signals between embedded memories (255) is now measured in micrometers instead of millimeters. This is an improvement of 100-1000 times in wire length.

[0066] The reduction in line length allows Figure 2 The 3D processor 200 has more than Figure 3The stacked design of the 3D processor consumes significantly less power than modern designs. It also consumes less power because it uses numerous short z-axis connections between the embedded memory 255 and the multi-core processor 250, foregoing the low-throughput, high-power I / O interface between the external memory 310 and the multi-core processor 350. The 3D processor 200 still requires an I / O interface on one of its dies (e.g., the first die 205, the second die 210, or another stacked die, not shown), but the processor 200 does not need to rely on it excessively for data input, as large amounts of data (e.g., greater than 200MB, 500MB, 1GB, etc.) can be stored in the embedded memory 255.

[0067] Figure 2 The stacked design of the 3D processor 200 also reduces the size of the multi-core processor by requiring less I / O interface circuitry and placing the I / O interface circuitry 257 on the second die 210. In other embodiments, the I / O interface circuitry 257 is on the first die 205, but with even less and / or smaller circuitry. In yet another embodiment, the I / O interface circuitry is placed on a third die stacked with the first and second dies, as further described below.

[0068] The stacked design of the 3D processor 200 also frees up space in devices using multi-core processors because it moves some external memory into the same IC die housing as the multi-core processor. Examples of memory that can be embedded memory 255 stacked with the multi-core processor 250 include any type of memory such as SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), MRAM (Magnetoresistive Random Access Memory), TCAM (Tri-State Content Addressable Random Access Memory), NAND flash memory, NOR flash memory, RRAM (Resistive Random Access Memory), PCRAM (Phase Change Random Access Memory), etc.

[0069] even though Figure 2 An embedded memory is shown on a second die 210. In some embodiments, multiple embedded memories are defined on the second die 210, while multiple embedded memories are defined on two or more dies vertically stacked with a first die 205 containing a multi-core processor 250. In some embodiments using multiple different embedded memories, the different embedded memories are of the same type, while in other embodiments, the different embedded memories are of different types (e.g., some are SRAM, while others are NAND / NOR flash memory). In some embodiments, the different embedded memories are defined on the same IC die, while in other embodiments, the different embedded memories are defined on different IC dies.

[0070] Figure 2As shown in some embodiments, the multi-core processor 250 has similar components (e.g., multiple general-purpose processing cores 270, L1, L2, and L3 caches 272, 274, and 276, cache arbitrators 278 and 280, graphics processing core 282, etc.) like other multi-processor cores. However, as described above, in the 3D processor 200, the I / O interface circuitry 257 for the multi-core processor 250 is placed on the second die 205.

[0071] I / O circuitry 257 writes data to and reads data from external devices and memory to embedded memory 255 for use with external devices and memory. In some embodiments, I / O circuitry 255 can also retrieve data from external devices and memory for use with L3 cache, or receive data from L3 cache for use with external devices and memory, without requiring the data to first pass through embedded memory 255. Some of these embodiments have a direct vertical (z-axis) bus between L3 cache and I / O circuitry 257. In these or other embodiments, first die 205 also includes I / O circuitry as an interface between I / O circuitry 255 and L3 cache 276, or as an interface between L3 cache 276 and external devices / memory.

[0072] Instead of placing the I / O circuitry on a different die than the rest of the multi-core processor, or combining this with placing the I / O circuitry on a different die than the rest of the multi-core processor, some embodiments place other components of the multi-core processor on different IC dies in a vertically stacked manner. For example Figure 4 An example of a 3D processor 400 formed by vertically stacking three dies 405, 410, and 415 is shown, wherein the first die 405 includes multiple processor cores 422 and 424 of a multi-core processor, the second die 410 includes L1-L3 caches 426, 428, and 430 for processing the cores, and the third die 415 includes I / O circuitry 435. In this example, the first die 405 and the second die 410 are mounted face-to-face (e.g., via a direct bonding process, such as a DBI process), while the second die 410 and the third die 415 are mounted back-to-back.

[0073] In this example, the processor cores are located in two quad-core sets 432 and 434. As shown, each core on the first die 405 (1) overlaps with the L1 cache 426 of the core on the second die 410, (2) overlaps with an L2 cache 428 on the second die 410, which is shared by three other cores in the same quad-core set 432 or 434, and (3) overlaps with the L3 cache 430 on the second die 410. In some embodiments, a number of z-axis connections (e.g., DBI connections) establish a number of signal paths between each core and each L1, L2, or L3 cache that overlaps with it. These signal paths are also established by interconnect segments on the interconnect layers of the first and second dies and vias between the interconnect layers.

[0074] In some embodiments, some or all of the cache memories (e.g., L2 and L3 cache memories 428 and 430) are multi-port memories that can be accessed simultaneously by different cores. In some embodiments, one or more of the cache memories include cache arbitrator circuitry that simultaneously arbitrates (e.g., controls and regulates) and sometimes arbitrates access to the memory by different processing cores. As shown, the 3D processor 400 also includes an L2 cache memory 436 on a first die 405 between the two quad-core sets 432 and 434 to allow data to be shared between these processor core sets. In some embodiments, the L2 cache memory 436 includes cache arbitrator circuitry (not shown). In other embodiments, the 3D processor 400 does not include the L2 cache memory 436. In some of these embodiments, different processor core sets 432 and 434 share data via the L3 cache 430.

[0075] L3 cache 430 stores data for access by all processing cores 422 and 424. Some of this data is retrieved from external memory (i.e., memory outside the 3D processor 400) via I / O circuitry 435 defined on the third die 415. In some embodiments, the third die 415 is mounted face-to-back with the second die. To establish this mounting, TSVs 460 are defined by the substrate of the second die, and these TSVs are electrically connected (either directly or via interconnect segments defined on the back side of the second die) to a direct bonding connection that connects the back side of the second die to the front side of the third die (i.e., to the top interconnect layer on the front side of the third die). Figure 5As shown, after the first and second dies are bonded face-to-face, but before the third die is mounted face-to-face to the second die, the back side of the second die is thinned through a thinning process. This thinning allows for shorter TSVs that penetrate the second die substrate. The shorter length of the TSVs, in turn, allows for smaller cross-sections and smaller spacing (i.e., smaller center-to-center distances to adjacent TSVs), thereby improving their density.

[0076] Most signal paths between the second die 410 and the third die 415 are very short (e.g., typically in the range of 10-20 μm in length) because they mostly traverse vertically through the substrate of the thinned second die and the interconnect layer of the third die, having a relatively short height. In some embodiments, a large number of short vertical signal paths are defined between the L3 cache 430 on the second die 410 and the I / O circuitry 435 on the third die 415. These signal paths utilize (1) a direct bonding connection between the top interconnect layer of the third die 415 and the back side of the second die 410, (2) a TSV 460 through the substrate of the second die, and (3) vias between the interconnect layers of the second and third dies and interconnect segments on the interconnect layers. The number and short length of these signal paths allow the I / O circuitry to quickly write to and read from the L3 cache.

[0077] The signal paths between the first die 405 and the second die 410 utilize (1) a direct bonding connection between the top interconnect layers of the first die 405 and the second die 410, and (2) interconnect segments between the interconnect layers of the first die 405 and the second die 410 and the interconnect layers. Most of these signal paths between the first die 405 and the second die 410 are also very short (e.g., typically in the range of 10-20 μm in length) because they mostly traverse the interconnect layers of the first and second dies in a vertical direction and have a relatively short height. In some embodiments, a large number of short vertical signal paths are defined between the processing core on the first die 405 and its associated L1-L3 cache.

[0078] In some embodiments, processor cores use these fast and abundant signal paths to perform very fast writing of large sets of data bits to L1-L3 caches and very fast reading of large sets of data bits from L1-L3 caches. The processor cores then perform their operations (e.g., their instruction fetch, instruction decode, arithmetic logic, and data write-back operations) based on these larger sets of data, which in turn allows them to execute more complex sets of instructions and / or execute smaller sets of instructions much faster.

[0079] Figure 6 Another 3D processor 600 is shown in some embodiments. This processor 600 will... Figure 2 Features of the 3D processor 200 Figure 4 The 3D processor 600 combines features of the processor 400. Specifically, like the processor 400, the processor 600 places multiple processor cores 422 and 424 on a first die 605, L1-L3 caches 426, 428, and 430 on a second die 610, and I / O circuitry 435 on a third die 615. However, like the processor 200, the processor 600 also has a die with embedded memory 622. This embedded memory is confined to a fourth die 620 placed between the second and third dies 610 and 615.

[0080] exist Figure 6 In this configuration, the first die 605 and the second die 610 are mounted face-to-face (e.g., via a direct bonding process, such as a DBI process), the fourth die 620 and the second die 610 are mounted back-to-face, and the third die 615 and the fourth die 620 are mounted back-to-face. To establish the back-to-face mounting, a TSV 460 is defined through a substrate passing through the second and third dies. The TSV is electrically connected to the direct bonding connection via the second die 610 (directly or via interconnect segments defined on the back side of the second die), which connects the back side of the second die 610 to the front side of the fourth die 620. Simultaneously, the TSV is electrically connected to the direct bonding connection via the fourth die 620 (directly or via interconnect segments defined on the back side of the second die), which connects the back side of the fourth die 620 to the front side of the third die 615.

[0081] To allow for shorter TSVs, the back side of the second die is thinned through a thinning process after the first and second dies are bonded face-to-face, but before the fourth die 620 is mounted face-to-back to the second die 610. Similarly, the back side of the fourth die 620 is thinned through a thinning process after the fourth and second dies 620 and 610 are mounted face-to-back, but before the third die 615 is mounted face-to-back to the fourth die 620. Furthermore, the shorter length of the TSVs allows for smaller cross-sections and smaller spacing (i.e., smaller center-to-center distance to adjacent TSVs), thereby improving their density.

[0082] like Figure 4 The same as in the middle, Figure 6 The L3 cache 430 stores data accessible to all processing cores 422 and 424. However, in Figure 6In this design, the L3 cache is not connected to the I / O circuit 435, but instead to the embedded memory 622 on the fourth die via a vertical signal path. The embedded memory 622 is connected to the I / O circuit 435 on the third die 615 via a vertical signal path. In some embodiments, the vertical signal paths between the second and fourth dies 610 and 620, and between the fourth and third dies 620 and 615, are established by z-axis direct bonding connections and vias (TSVs) and interconnect segments on the interconnect layers and between interconnect layers. Most of these signal paths are very short (e.g., typically in the range of 10-20 µm) because they are mostly vertical, and the height of the thinned substrate and its associated interconnect layers is also relatively short.

[0083] Similar to Figure 2 The embedded memory 255, in some embodiments, is a large memory (e.g., greater than 200MB, 500MB, 1GB, etc.). Thus, in some embodiments, the embedded memory can replace one or more external memories typically used in devices employing multi-core processors today. Examples of embedded memory 622 include SRAM, DRAM, MRAM, NAND flash memory, NOR flash memory, RRAM, PCRAM, etc. In some embodiments, two or more different types of embedded memory are defined on one or more dies in a die stack, the die stack including one or more dies defining a multi-core processor thereon.

[0084] Embedded memory 622 receives and provides data to I / O circuitry 435 via a series of short vertical signal paths. Through these signal paths, I / O circuitry 435 writes data from external devices and memories to embedded memory 622 and reads data from embedded memory 622 for use by external devices and memories. In some embodiments, I / O circuitry 435 can also retrieve data from external devices and memories for use in the L3 cache, or receive data from the L3 cache for use in external devices and memories, without requiring the data to first pass through embedded memory 622. Some of these embodiments have a direct vertical (z-axis) bus between the L3 cache and I / O circuitry 435. In these or other embodiments, second die 610 and / or fourth die 620 also include I / O circuitry as an interface between I / O circuitry 435 and L3 cache 430, or as an interface between L3 cache 430 and external devices / memory.

[0085] Figure 7 Another 3D processor 700 is shown in some embodiments. This processor 700 is related to… Figure 6The processor 600 is identical to the first die 705, except that it has only two layers of cache, L1 and L2, on the second die 710, which is mounted face-to-face on the first die 705, which has eight processor cores 722. As shown, each L1 cache 726 overlaps with only one core 722. Unlike the L1 cache 726, the L2 cache 728 is shared among all cores 722 and overlaps with each core 722. In some embodiments, each core is connected to each L1 or L2 cache, which overlaps through: (1) multiple z-axis DBI connections connecting the top interconnect layers of dies 705 and 721, and (2) interconnects and vias that carry signals from these DBI connections to other metals and substrates of dies 705 and 721. In some embodiments, the DBI connections allow the data bus between the cache and the core to be wider and faster than the conventional data bus between the cache and the core.

[0086] In some embodiments, the L1 cache is formed from memory that can be accessed faster (i.e., has faster read or write times) compared to the memory used to form the L2 cache. In some embodiments, each L1 cache 726 consists of only one set of memory, while in other embodiments it consists of several sets of memory. Similarly, in some embodiments, the L2 cache 728 consists of only one set of memory, while in other embodiments it consists of several sets of memory. Furthermore, in some embodiments, the L1 cache 726 and / or the L2 cache 728 are denser than conventional L1 and L2 caches because they use z-axis DBI connections to provide and receive signals to and from the overlapping core 722. In some embodiments, the L1 and L2 caches 726 and 728 are much larger than conventional L1 and L2 caches because they are defined on another die rather than on a die on which the core is defined, and therefore they face fewer space constraints in their layout and the amount of space consumed on the chip.

[0087] Other embodiments still use other architectures for the 3D processor. For example, instead of using only one L2 cache 728, some embodiments use two or four L2 caches with four overlapping cores (e.g., four left cores 726 and four right cores 726) or two cores (e.g., one pair of four pairs of vertically aligned cores 722). Figure 8 Another 3D processor 800 is shown in some embodiments. This processor 800 is related to… Figure 7 The processor 900 is the same as the processor 700, except that it does not have an L2 cache 728. Instead of the L2 cache, the processor 900 has a network on-chip (NOC) 8028 on a die 810, which is mounted face-to-face to the die 705 via a DBI bonding process.

[0088] In some embodiments, NOC 828 is an interface through which core 722 communicates. This interface includes one or more buses and associated bus circuitry. In some embodiments, NOC 828 also communicatively connects each core to an L1 cache overlapping with other cores. Through this NOC, a first core can access data stored by a second core in an L1 cache overlapping with the second core. Furthermore, through this NOC, in some embodiments, the first core can store data in an L1 cache overlapping with the second core. In some embodiments, L1 and L2 caches overlap with each core 722, and NOC 828 connects the core to the L2 caches of other cores, but not to the L1 caches of those cores. In other embodiments, NOC 828 connects the core to both the L1 and L2 caches overlapping with other cores, as well as other cores.

[0089] Figure 9 Another 3D processor 900 is shown in some embodiments. This processor 900 is related to… Figure 4 The processor 400 is identical to the processor 900, except that it has only one L1 cache 932 on die 910 for each of the six CPU (Central Processing Unit) cores 922, and one L1 cache 934 for each of the two GPU (Graphics Processing Unit) cores 924, which are defined on die 905 mounted face-to-face to die 910 via a DBI bonding process. The processor 900 does not use Level 2 and Level 3 caches because it uses large L1 caches for both CPU and GPU cores. L1 caches can be larger than conventional L1 caches because they are defined on a separate die rather than on a die that defines the cores, thus facing fewer space constraints in terms of their layout and the amount of space they consume on the chip.

[0090] exist Figure 9 In one embodiment, processor 900 has an I / O interface defined on a third die 415 mounted face-to-face on die 910. In other embodiments, processor 900 does not include the third die 415, but only includes first and second dies 905 and 910. In some of these embodiments, the I / O interface of processor 900 is defined in the first and second dies 905 and 910. Moreover, in other embodiments, an L1 cache 932 is shared across multiple CPU cores 922 and / or multiple GPU cores 924.

[0091] Figure 10 Some embodiments are shown where two computing circuits performing sequential computations are placed on two different stacked dies. A computing circuit is one that receives multi-bit values ​​as input and computes multi-bit values ​​as outputs based on the received inputs. Figure 10In this configuration, a computing circuit 1015 is defined on a first die 1005, while another computing circuit 1020 is defined on a second die 1010.

[0092] The first and second dies are mounted face-to-face via a direct bonding process (e.g., DBI process). This mounting defines a number of z-axis connections between the two dies 1005 and 1010. Together with the interconnects on the interconnect layers in the two dies and the vias between the interconnect layers, the z-axis connections define a number of vertical signal paths between the two computing circuits 1015 and 1020. These vertical signal paths are short because they mostly traverse relatively short die interconnect layers in a vertical direction. Due to their very short length, these vertical signal paths are very fast parallel paths connecting the two computing circuits 1015 and 1020.

[0093] exist Figure 10 In this circuit, the first computing circuit 1015 receives a multi-bit input value 1030 and calculates a multi-bit output value 1040 based on the input value. In some embodiments, the multi-bit input value 1030 and / or the output value 1040 are large-bit values, such as 32-bit, 64-bit, 128-bit, 256-bit, 512-bit, 1024-bit, etc. Through a vertical signal path between the two computing circuits, the first computing circuit 1015 provides its multi-bit output value 1040 as an input value to the computing circuit 1020. Based on this value, the computing circuit 1020 calculates another multi-bit output value 1045.

[0094] Given a large number of vertical signal paths between the first computing circuit 1015 and the second computing circuit 1020, a large number of bits can be transferred between these two circuits 1015 and 1020 without the need for serialization and deserialization circuitry. The number of vertical signal paths and the size of the exchanged data also allow for more computation to be performed per clock cycle. Due to the short length of these vertical signal paths, the two circuits 1015 and 1020 can exchange data within one clock cycle. When two computing circuits are placed on a single die, due to the distance and / or congestion between the two circuits, it can sometimes take eight or more clock cycles to provide a signal from one circuit to the other.

[0095] In some embodiments, the two overlapping computing circuits on the two dies 1005 and 1010 are different cores of a multi-core processor. Figure 11 An example of a high-performance 3D processor 1100 with overlapping processor cores on different dies is shown. In this example, two dies 1105 and 1110 are mounted face-to-face via a direct bonding process (e.g., a DBI process). The first die 1105 includes a first processor core 1112, while the second die 1110 includes a second processor core 1114.

[0096] The first die 1105 also includes an L1 cache 1116 for the second core 1114 on the second die 1110, and L2 and L3 caches 1122 and 1126 for the two cores 1112 and 1114. Similarly, the second die 1110 also includes an L1 cache 1118 for the first core 1112 on the first die 1105, and L2 and L3 caches 1124 and 1128 for the two cores 1112 and 1114. As shown, each core completely overlaps its corresponding L1 cache and is connected to its L1 cache via a number of vertical signal paths defined by z-axis connections between the top two interconnect layers of dies 1105 and 1110. As described above, such vertical signal paths are also defined by (1) vias between interconnect layers of each die and / or (3) interconnect segments on the interconnect layers of each die.

[0097] Each core on one die also overlaps with an L2 cache and an L3 cache on another die, and is located near another L2 cache and another L3 cache on its own die. Each L2 and L3 cache 1122-826 can be accessed by each core 1112 or 1114. Each core accesses the overlapping L2 or L3 cache via a number of vertical signal paths, which are partially defined by the z-axis connection between the top two interconnect layers of dies 1105 and 1110, and by the following: (1) vias between interconnect layers of each die, and / or (3) interconnect segments on the interconnect layers of each die.

[0098] Each core can also access L2 or L3 caches on its own die via signal paths defined by vias between interconnect layers of its own die and interconnect segments on the interconnect layers. In some embodiments, when an additional signal path is required between each core and its own L2 or L3 cache, each core is also connected to such L2 or L3 cache via signal paths defined not only by vias between interconnect layers of its own die and interconnect segments on the interconnect layers of its own die, but also by vias between interconnect layers of other dies and interconnect segments on the interconnect layers.

[0099] However, other embodiments do not use signal paths traversing interconnect layers of other dies to connect the core to its own on-die L2 or L3 cache because such signal paths may have different latency (i.e., greater latency) compared to signal paths between the core and caches using only the interconnect layers of the core's own die. On the other hand, given a very short z-axis connection length, when the difference in signal path latency is very small (e.g., compared to the speed of signal paths using only the interconnect layers of the core die), other embodiments will use signal paths defined by interconnect layers of other dies (e.g., through their top interconnect layers).

[0100] Figure 11 The illustrated 3D architecture significantly increases the number of connections (via vertical signal paths) between each core 1112 or 1114 and its corresponding L1, L2, and L3 caches. With this increase, each core 1112 or 1114 retrieves a larger set of data bits and utilizes this larger set of data bits to execute more complex operations faster. In some embodiments, each core uses a wider instruction and data bus in its pipeline because it can retrieve a wider range of instructions and data from the overlapping memory. In these or other embodiments, each core has a pipeline that executes more operations in parallel because the core can retrieve more instructions and data bits from the overlapping memory.

[0101] In some embodiments, each core on a die uses only the L2 or L3 cache on another die (i.e., only the L2 or L3 cache vertically overlapping with the core) to utilize the numerous vertical signal paths between it and the overlapping L2 cache. In some embodiments of these embodiments, each core stores a redundant copy of each piece of data in its own overlapping cache (e.g., its own overlapping L2 cache) within a corresponding cache (e.g., another L2 cache) defined on its own die, making the data available to the other core as well. In some embodiments of these embodiments, each core reaches its own on-die cache via signal paths defined not only by interconnects and vias on the core's die but also by interconnects and vias on another die.

[0102] Figure 12Another example of a high-performance 3D processor 1200 is shown, which has a processor core on one die that overlaps with a cache on another die. In this example, two dies 1205 and 1210 are mounted face-to-face using a direct-bond process (e.g., DBI process). The first die 1205 includes a first processor core 1212, while the second die 1210 includes a second processor core 1214. The first die 1205 includes an L1 cache 1216 for the second processor core 1214 defined on the second die 1210, while the second die 1210 includes an L1 cache 1218 for the first processor core 1212 defined on the first die 1205.

[0103] In this example, the cross-section of each L1 cache on one die completely overlaps with the cross-section of the corresponding core on another die. This ensures that the maximum area of ​​z-axis connections (e.g., DBI connections) is defined within the overlapping region of each core and its corresponding L1 cache. These z-axis connections are very short, thus allowing for the definition of a very fast bus between each core and its corresponding L1 cache. Similarly, when using high-density z-axis bonding (e.g., when using DBI), this z-axis bus can be wide and can be completely defined within the xy cross-section of the core and its L1 cache, as described below. By being completely contained within this cross-section, the z-axis bus does not consume routing resources around the core and its L1 cache. Likewise, the speed and width of this bus allow for high throughput bandwidth, perfectly complementing the high speed of the L1 cache.

[0104] like Figure 12 As shown, the 3D processor 1200 defines an L2 cache for each core on the same die on which the cores are defined. In some embodiments, each core can access the L2 cache of another core via a z-axis connection established by face-to-face bonding of the two IC dies. Furthermore, due to the size of the L1 cache, the 3D processor 1200 does not use an L3 cache in some embodiments.

[0105] In some embodiments, different components of a multi-processor core are placed on different dies. Figure 13 An example of a 3D processor 1300 is shown, which has different portions of the processor core on two face-to-face mounted dies 1305 and 1310. In this example, the first die 1305 includes multiple pipelines 1390, each pipeline having an instruction fetch (IF) unit 1312, an instruction decode unit 1314, an execution unit 1316, and a write-back unit 1318. The second die includes an instruction memory 1322, as well as data registers and memory 1324.

[0106] As shown in the figure, the instruction memory 1322 on the second die overlaps with the IF cell 1312 on the first die 1305. Furthermore, the data register and memory 1324 on the second die overlap with the execution unit 1316 and the write-back unit. Numerous vertical signal paths are defined between the overlapping core components via the z-axis connection between the top two interconnect layers of dies 1305 and 1310, and via: (1) vias between the interconnect layers of each die 1305 or 1310, and / or (2) interconnect segments on the interconnect layers of each die.

[0107] Through the vertical signal path, each IF unit 1312 fetches instructions from the instruction memory and provides the fetched instructions to its instruction decoding unit 1314. The decoding unit decodes each received instruction and provides the decoded instructions to its execution unit for execution. Through the vertical signal path, each execution unit receives operands required to execute the received instructions from the data register and memory 1324 and provides the execution result to its write-back unit 1318. Through the vertical signal path, each write-back unit 1318 stores the execution result in the data register and memory 1324. Other embodiments use different architectures to partition processor cores between two different dies. For example, some embodiments place instruction decoding and execution units 1314 and 1316 on a different layer than instruction fetch and write-back units 1312 and 1318. Other embodiments use other arrangements to partition processor cores between different dies. These or other embodiments place different ALUs of the processor core or different portions of the same ALU on different vertically stacked dies (e.g., on two dies mounted face-to-face using a DBI bonding process).

[0108] As mentioned above, it is advantageous to use DBI connections to connect overlapping connection areas on two vertically stacked dies because DBI allows for a higher connection density than other z-axis connection schemes. Figure 14 An example illustrating this is given. The figure shows computing circuitry 1415 on a first die 1405, which overlaps with memory circuitry 1420 on a second die 1410, which is vertically stacked on the first die 1405. The computing circuitry can be any type of computing circuitry (e.g., processor core, processor pipeline computing unit, neural network neuron, logic gate, adder, multiplier, etc.) and the memory circuitry can be any type of memory circuitry (e.g., SRAM, DRAM, non-volatile memory, cache, etc.).

[0109] In this example, the two circuits 1415 and 1420 occupy a 250 × 250 micrometer square area on their respective dies 1405 and 1410 (only in... Figure 14The substrate surface is shown in the figure. Moreover, in this example, a 100-bit z-axis bus 1425 is defined between these circuits, where in this example, the term bus refers to the data and control signals exchanged between the two circuits 1415 and 1420 (in other examples, the bus may only include data signals). Figure 14 The diagram shows that when a TSV is used to define the z-axis bus 1425, the bus will consume an area 1435 on each die, which is at least 2.5 times the size of any circuitry on that die. This is because the TSV has a 40-micron pitch. For TSV connections, two dies 1405 and 1410 will be mounted face-to-back, with the TSV passing through the substrate of one of the dies.

[0110] On the other hand, when two dies are joined face-to-face by mounting and a 100-bit z-axis bus 1425 is defined using DBI connections, the cross-section 1430 of the DBI bus can be contained within the footprint (i.e., substrate area) of the two circuits 1415 and 1420 on their respective dies. Specifically, assuming the DBI connections have a 2-micrometer pitch, 100 DBI connections can be fitted in a size as small as 20 × 20 micrometers square, as the 100 connections can be defined as a 10 × 10 array, each connection having a minimum center-to-center distance of 2 micrometers from adjacent connections. By being contained within the footprint of circuits 1415 and 1420, the DBI connections generally will not consume any valuable routing space on dies 1405 and 1410 beyond the portions already consumed by the circuitry. In some embodiments, the DBI connections can have a pitch ranging from less than 1 micrometer (e.g., 0.2 or 0.5 micrometers) to 5 micrometers.

[0111] As the number of bits in the 1425 bus increases, the difference in space consumption between TSV connections and DBI connections becomes more pronounced. For example, when swapping 3600 bits between two circuits, 1415 and 1420, a 60x60 TSV array would require a minimum area of ​​2400x2400 micrometers (with a 40-micrometer DBI pitch), while a 60x60-60 DBI array would require a minimum area of ​​120x120 micrometers (with a 2-micrometer DBI pitch). In other words, the coverage area of ​​a TSV is at least 400 times that of a DBI connection. It is common to swap large numbers of bits between memory and compute circuits when performing computations (e.g., dot product calculations) in certain computing environments (e.g., machine-trained neural networks). Furthermore, the density of DBI connections allows for very large bandwidths (e.g., in the high GB or TB range) between overlapping compute and memory circuits.

[0112] The density of DBI connections is also advantageous when connecting overlapping circuit regions on two vertically stacked dies. Figure 15An example illustrating this is given. The figure shows two overlapping computing circuits 1515 and 1520 on two vertically stacked dies 1505 and 1510. Each circuit occupies a 250 × 250 micrometer square on the substrate of its corresponding die and can be any type of computing circuit (e.g., processor core, processor pipeline computing unit, neural network neuron, logic gate, adder, multiplier, etc.).

[0113] Similar to Figure 14 Examples in, Figure 15 The example shows that when using a DBI connection (i.e., when two dies 1505 and 1510 are mounted face-to-face via DBI), and the DBI connection spacing is 2 micrometers, the 100-bit bus 1525 between the two circuits 1515 and 1520 can be contained within a 20×20 micrometer square area 1530, which can be entirely included in the circuit's coverage area. On the other hand, when using a TSV connection (e.g., when two dies are mounted face-to-back and connected using TSV), the 100-bit bus 1525 will consume at least a 400x400 micrometer square area 1535, which is larger than the coverage area of ​​the circuits 1515 and 1520. This larger coverage area will consume additional routing space and is not as beneficial as the smaller coverage area that can be achieved with a DBI connection.

[0114] High-density DBI connections can also be used to reduce the size of circuits composed of numerous computing circuits and their associated memory. DBI connections can also provide very high bandwidth between the computing circuits and their associated memory for this smaller circuit. Figure 16 Examples illustrating these benefits are given. Specifically, it shows a reduction in the size of an array 1600 of computing circuitry 1615 on a first die 1605 by moving memory 1620 for these circuits to a second die 1610, which is mounted face-to-face with the first die 1605 via a DBI bonding process. In this example, a 6x10 array of computing circuitry is shown, but in other examples, the array could have a much larger number of circuits (e.g., more than 100 circuits, more than 1000 circuits). Moreover, in other embodiments, the computing circuitry and its associated memory circuitry can be organized in arrangements other than arrays.

[0115] The computing circuitry 1615 and memory circuitry 1620 can be any type of computing processing circuitry and memory circuitry. For example, in some embodiments, the circuit array 1600 is part of an FPGA having an array of logic circuits (e.g., logic gates and / or lookup tables, LUTs) and an array of memory circuits, wherein each memory in the memory array corresponds to a logic circuit in the circuit array. In other embodiments, the computing circuitry 1615 is a neuron of a neural network or a multiplier-accumulator (MAC) circuit of a neuron. In these embodiments, the memory circuitry 1620 stores the weights and / or input / output data of the neuron or MAC circuit. In other embodiments, the computing circuitry 1615 is the processing circuitry of a GPU, and the memory circuitry stores input / output data from these processing circuits.

[0116] like Figure 17 As shown, in most single-die implementations today, memory arrays are typically interleaved with circuit arrays. Figure 17 In the example, the total length of the two interleaved arrays is X micrometers. To connect two circuits in the same column of the arrays, the wiring must be at least X micrometers. However, as... Figure 16 As shown, by moving the memory circuitry onto the second die 1610, two circuits in the same column can be connected with a minimum wiring length of X / 2 micrometers.

[0117] Furthermore, each memory circuit can have a higher memory cell density because less space is consumed to define shared peripheral channels for output signals to the circuit, since these output signals can now traverse along the z-axis. Moreover, by moving the memory circuits onto the second IC die 1610, more routing space is available in the open channels 1650 (between the substrate and the metal house) between the computing circuits in the computing array 1600 on the first die 1605 and between the memory circuits in the memory array 1602 on the second die 1610. This additional routing space makes it easier to connect the outputs of the computing circuits. In many cases, this additional routing space allows for shorter wire lengths for these interconnects. In some embodiments, this also makes it easier for the computing circuits to read data from or write data to the memory circuits of other computing circuits. In some embodiments, the DBI connection is also used to route signals through the metal layer of the second die 1610 to define signal paths (i.e., routing) for connection to the computing circuit 1615 defined on the first die 1605.

[0118] Higher-density DBI connections also allow for a greater number of z-axis connections between corresponding memory and compute circuits, which are entirely contained within the occupied area of ​​a pair of corresponding memory and compute circuits (i.e., the substrate area occupied by them). As previously mentioned, these DBI connections link the top interconnect layers of one wafer to the top interconnect layers of another wafer, while the remaining connections between a pair of memory and compute circuits are established through interconnects and vias on these wafers. This approach is also highly advantageous when compute circuits require wide buses (e.g., 128-bit, 256-bit, 512-bit, 1000-bit, 4000-bit, etc.) to their corresponding memory circuits. One such example is when the compute circuit array is a neural array that needs to access large amounts of data from its corresponding memory circuits.

[0119] Figure 18 and 19 Two examples are shown illustrating how high-density DBI connections can be used to reduce the size of an arrangement of computational circuits formed by several consecutive stages of circuitry, each stage performing a computation that produces a result, which is then passed to another stage of the circuit until the final stage is reached. In some embodiments, such an arrangement of computational circuitry can be an adder tree, where each computational circuit in the tree is an adder. In other embodiments, the circuitry in the arrangement is a multiply-accumulate (MAC) circuit, such as those used to compute dot products in neural networks.

[0120] Figure 18 and 19 The examples illustrate one implementation of circuit 1800, which performs calculations (e.g., addition or multiplication) based on eight input values. In some embodiments, each input value is a multi-bit value (e.g., a 32-bit value). Circuit 1800 has three stages: a first stage 1802 with four calculation circuits A and D, a second stage 1804 with two calculation circuits E and F, and a third stage 1806 with a calculation circuit G. Each calculation circuit in the first stage 1802 performs an operation based on two input values. In the second stage 1804, calculation circuit E performs calculations based on the outputs of calculation circuits A and B, while calculation circuit F performs calculations based on the outputs of calculation circuits C and D. Finally, calculation circuit Gn in the third stage 1806 performs calculations based on the outputs of calculation circuits E and F.

[0121] Figure 18A prior art implementation of circuit 1800 on an IC die 1805 is shown. In this implementation, computational circuits AG are arranged in a row in the following order: A, E, B, G, C, F, and D. As shown, the first-stage computational circuit AD (1) receives its input from circuits (e.g., memory circuits or other circuits) above and below in the y-axis direction of the plane, and (2) provides its result to computational circuit E or F. Computational circuits E and F provide their computation results to computational circuit G in the middle of the row. The signal paths from computational circuits E and F are relatively long and consume nearby routing resources. As the size of the circuit layout (e.g., adders or multiplication trees) increases, the length of interconnects and congestion become worse. For example, to implement an adder tree that adds 100 or 1000 input values, multiple adders are required in multiple stages, which quickly leads to the need for long, large data buses to transfer computation results between subsequent stages of the adders.

[0122] Figure 19 A novel implementation of circuit 1800 is shown, which significantly reduces the size of the connections required to provide the outputs of computing circuits E and F to computing circuit G. As shown, this implementation defines computing circuits A, B, E, and G on a first die 1910, while defining computing circuits C, D, and F on a second die 1905, which is mounted face-to-face on the first die 1905 using a DBI bonding process. Computing circuits A, B, E, and G are defined in areas on the first die 1910 that overlap with areas on the second die 1905 that define computing circuits C, D, and F.

[0123] In this implementation, computing circuit G is located below computing circuit E in the y-plane direction. At this location, computing circuit G receives the output of computing circuit E via a short data bus defined on chip 1910, and simultaneously receives the output of computing circuit F via: (1) the z-axis DBI connection at overlapping positions 1950 and 1952 on the top interconnect layer connecting dies 1905 and 1910, and (2) the interconnects and vias on these dies that bring the output of circuit F to the input of circuit G. In this implementation, the interconnects providing the input to computing circuit G are very short. Computing circuits E and G are adjacent to each other, so the signal path only includes the short interconnect and via length between circuits E and G. Furthermore, the length of the interconnects, vias, and z-axis DBI connection required to provide the output of computing circuit F to computing circuit G is very small.

[0124] Therefore, by breaking down the arrangement of circuit 1800 between the two dies 1905 and 1910, successive computing circuits can be placed close to each other (because an additional dimension, namely the z-axis, can now be used to place the circuits close to each other), which in turn allows for shorter interconnections to be defined between computing circuits in successive stages. Similarly, the high density of DBI connections makes it easier to define a greater number of z-axis connections within the cross-section of the area used to define successive computing circuits (which is necessary for larger z-axis data buses).

[0125] The computational circuit layout can have more than three levels. For example, a large adder or a MAC tree can have more levels (e.g., 8 levels, 10 levels, 12 levels, etc.). To achieve such a circuit layout, some embodiments (1) divide the computational circuit into two or more groups, which are then defined on two or more vertically stacked dies, and (2) arrange different groups of circuits on these dies to minimize the interconnect length required to connect the computational circuits in consecutive levels.

[0126] Figure 20 An example is presented to illustrate this point. This example shows an implementation of a computational circuit 2000 that performs calculations (such as addition or multiplication) on sixteen-bit multi-bit input values. The circuit includes... Figure 18 and 19 The computational circuit 1800 has two versions, 2012 and 2014. The computational circuit in the second version is labeled circuit HN. Each of these versions has three stages. As shown in the figure, the outputs of these two versions are provided to a fourth-stage computational circuit O, which performs calculations based on these outputs.

[0127] To implement the four-level circuit 2000, versions 2012 and 2014 have an inverted layout. This is because the computing circuits A, B, and E (operating on the first four inputs of the first version 2012) are defined on IC die 2010, while the computing circuits H, I, and L (operating on the first four inputs of the second version) are defined on IC die 2005. Similarly, the computing circuits C, D, and F (operating on the second four inputs of the first version 2012) are defined on IC die 2005, while the computing circuits J, K, and M (operating on the second four inputs of the second version) are defined on IC die 2010. Furthermore, the third-level circuit G of the first version is defined on IC die 2010, while the third-level circuit N is defined on IC die 2005. The fourth-level aggregation circuit O is also defined on IC die 2010. Finally, the second version 2014 is located to the right of the first version in the x-axis direction.

[0128] The overall inverted arrangement of Version 2 (2014) compared to Version 1 ensures that the interconnect lengths required to supply the outputs of the third-level computing circuits G and N to the fourth-level computing circuit O are very short. This is because, like computing circuits E, F, and G, computing circuits L, M, and N are placed near and / or overlapped, allowing these three circuits L, M, and N to be connected via short DBI connections, and the vertical signal paths are largely facilitated by small planar interconnects and a few via connections. This arrangement also places computing circuits G, N, and O near and / or overlapped, which again allows them to be connected via short DBI connections, and the vertical signal paths are largely facilitated by small planar interconnects and a few via connections.

[0129] Figure 21 Device 2102 using a 3D IC 2100 (similar to any of 3D ICs 210, 200, 400, 600-900) is shown. In this example, the 3D IC 2100 is formed from two IC dies 2105 and 2110 mounted face-to-face, with a plurality of direct bonding connections 2115 between them. In other examples, the 3D IC 2100 includes three or more vertically stacked IC dies. As shown, the 3D IC die 2100 includes a cover 2150 that encapsulates the die within a secure housing 2125. On the back side of the die 2110, one or more TSVs and / or interconnect layers 2106 are defined to connect the 3D IC to a ballgrid array 2120 (e.g., a microbump array), which allows these to be mounted onto a printed circuit board 2130 of device 2102. Device 2102 includes other components (not shown). In some embodiments, examples of such components include one or more memory storage devices (e.g., semiconductor or disk storage), input / output interface circuitry, one or more processors, etc.

[0130] In some embodiments, the first die 2105 and the second die 2110 are Figure 1-2 The first and second dies are shown in any one of 4, 6-16, and 19-20. In some of these embodiments, the second die 2110 receives data signals via a ball grid array and routes the received signals to I / O circuitry on the first and second dies via interconnects on the interconnect layers and vias between the interconnect layers. When such data signals need to cross to the first die, these signals cross the z-axis connection of the face-to-face adhesive layers.

[0131] Figure 22Another example of a 3D chip 2200 is provided, which is formed by two face-to-face mounted IC dies 2205 and 2210 mounted on a ball grid array 2240. In this example, the first die 2205 and the second die 2210 are face-to-face connected via a direct-bond connection (e.g., a DBI connection). As shown, several TSVs 2222 are defined by the second die 2210. These TSVs are electrically connected to interconnect / pads on the back side of the second die 2210, on which a multilayer interconnect is defined.

[0132] In some embodiments, interconnects on the back side of the second die 2210 create signal paths for defining one or more system-level circuits for the 3D chip 2200 (i.e., circuitry for the first die 2205 and the second die 2210). Examples of system-level circuits are power circuits, clock circuits, data I / O signals, test circuits, etc. In some embodiments, circuit components (e.g., power circuits, etc.) that are part of the system-level circuitry are defined on the front side of the second die 2210. Circuit components may include active components (e.g., transistors, diodes, etc.) or passive / analog components (e.g., resistors, capacitors (e.g., decoupling capacitors), inductors, filters, etc.).

[0133] In some embodiments, some or all of the wiring used to interconnect these circuit components to form system-level circuitry is defined on an interconnect layer on the back side of the second die 2210. Using these back-side interconnect layers to implement the system-level circuitry of the 3D chip 2200 frees up one or more interconnect layers on the front side of the second die 2210 to share other types of interconnects with the first die 2205. In some embodiments, the back-side interconnect layers are also used to define certain circuit components (e.g., decoupling capacitors, etc.). As further described below, in some embodiments, the back side of the second die 2210 may also be connected to the front or back side of a third die.

[0134] In some embodiments, one or more layers on the back side of the second die 2210 are also used to mount the die to the ball grid array 2240, which allows the 3D chip 2100 to be mounted on a printed circuit board. In some embodiments, system circuitry receives some or all of system-level signals (e.g., power signals, clock signals, data I / O signals, test signals, etc.) via the ball grid array 2240 connected to the back side of the third die.

[0135] Figure 23 Some embodiments are shown for generating Figure 22 The manufacturing process of the 3D chip 2200 is shown in Figure 2300. This figure will be referenced. Figure 24-27 To explain, Figure 24-27Two wafers, 2405 and 2410, are shown at different stages of the process. Once diced, the two wafers produce two stacked dies, such as dies 2205 and 2210. Even Figure 23 In process 2300, the wafer is diced into dies after it has been mounted and processed. In other embodiments, the manufacturing process still performs dicing operations at different stages of at least one wafer. Specifically, some embodiments diced a first wafer 2405 into several first dies, each of which was mounted on a second wafer before the second wafer was diced into individual second dies.

[0136] As shown in the figure, process 2300 begins by defining components (e.g., transistors) on substrates of a first wafer 2405 and a second wafer 2410, and defining a plurality of interconnect layers over each substrate to define interconnects for forming microcircuits (e.g., gates) on each die (e.g., starting at 2305). In order to define these components and interconnects on each wafer, in some embodiments, process 2300 performs a plurality of IC manufacturing operations (e.g., film deposition, patterning, doping, etc.) for each wafer. Figure 24 The first and second wafers 2405 and 2410 are shown after several manufacturing operations that have defined components and interconnects on these wafers. As shown, the manufacturing operations of the second wafer 2410 defined a plurality of TSVs 2412 that pass through the interconnect layer of the second wafer 2410 and penetrate a portion of the wafer substrate 2416.

[0137] After the first and second wafers are processed to define their components and interconnections, process 2300 mounts the first and second wafers 2205 and 2210 face-to-face (at 2310) through a direct bonding process such as the DBI process. Figure 25 The diagram shows the first wafer 2405 and the second wafer 2410 after they have been face-to-face mounted via a DBI process. As shown, the DBI process creates a plurality of direct bonding connections 2426 between the first and second wafers 2405 and 2410.

[0138] Next, at 2315, process 2300 performs a thinning operation on the back side of the second wafer 2410 to remove a portion of the substrate layer of the wafer. As... Figure 26 As shown, the thinning operation exposes TSV2412 on the back side of the second wafer 2410. After the thinning operation, process 2300 defines (at 2320) one or more interconnect layers 2430 on the back side of the second wafer. Figure 27 The first wafer 2405 and the second wafer 2410 are shown after an interconnect layer has been defined on the back side of the second wafer.

[0139] These interconnect layers 2430 include one or more layers that allow 3D chip stacking for electrical connection to a ball grid array. In some embodiments, interconnects / pads on the back side of the third wafer also create one or more redistribution layers (RDL layers) that allow signals to be redistributed to different locations on the back side. In some embodiments, the interconnect layers 2430 on the back side of the second die also create signal paths for the circuitry of the first and second dies to define one or more system-level circuits (e.g., power circuitry, clock circuitry, data I / O signals, test circuitry, etc.). In some embodiments, the system-level circuitry is defined by circuit components (e.g., transistors, etc.) defined on the front side of the second die. In some embodiments, process 2300 does not define interconnect layers on the back side of the second wafer to create signal paths for system-level circuitry because it only uses the interconnect layers of the first and second dies between the two sides of the first and second dies to establish system-level signal paths.

[0140] After defining an interconnect layer on the back side of the second wafer 2410, the process dices (at 2325) the stacked wafers into individual chip stacks, each chip stack comprising two stacked IC dies 2205 and 2210. The process then mounts each chip stack (at 2330) onto a ball grid array and encapsulates the chip stack within a chip housing (e.g., using a chip cartridge). The process then concludes.

[0141] In some embodiments, three or more IC dies are stacked to form a 3D chip. Figure 28 An example of a 3D chip 2800 with three stacked IC dies 2805, 2810, and 2815 is shown. In this example, the first die 2805 and the second die 2810 are face-to-face connected via a direct bonding connection (e.g., a DBI connection), while the third and second dies 2815 and 2810 are face-to-back connected (e.g., the face of the third die 2815 is mounted on the back of the second die 2810). In some embodiments, the first and second dies 2805 and 2810 are... Figure 1-2 , Figure 4 , Figure 6-16 and Figures 19-20 The first and second bare plates shown in either of them.

[0142] exist Figure 28In this design, several TSVs 2822 are defined by a second die 2810. These TSVs are electrically connected to interconnect / pads on the back side of the second die 2810, which in turn connect to interconnect / pads on the top interconnect layer of a third die 2815. The third die 2815 also has multiple TSVs that connect signals on the front side of the die to interconnect / pads on the back side of the die. The back side of the third die is connected to a ball grid array 2840 via interconnect / pads, which allows the 3D chip 2800 to be mounted on a printed circuit board.

[0143] In some embodiments, the third die 2815 includes system circuitry, such as power circuitry, clock circuitry, data I / O circuitry, test circuitry, etc. In some embodiments, the system circuitry of the third die 2815 provides system-level signals (e.g., power signals, clock signals, data I / O signals, test signals, etc.) to the circuitry of the first and second dies 2805 and 2810. In some embodiments, the system circuitry receives some or all of the system-level signals via a ball grid array 2840 connected to the back side of the third die.

[0144] Figure 29 Another example of a 3D chip 2900 having two or more stacked IC dies is shown. In this example, the 3D chip 2900 has four IC dies 2905, 2910, 2915, and 2920. In this example, the first die 2905 and the second die 2910 are face-to-face connected via a direct bonding connection (e.g., a DBI connection), while the third and second dies 2915 and 2910 are face-to-back connected (e.g., the face of the third die 2915 is mounted on the back of the second die 2910), and the fourth and third dies 2920 and 2915 are face-to-back connected (e.g., the face of the fourth die 2920 is mounted on the back of the third die 2915). In some embodiments, the first and second dies 2905 and 2910 are... Figure 1-2 , Figure 4 , Figure 6-16 and Figures 19-20 The first and second bare plates shown in either of them.

[0145] exist Figure 29 In the chip, multiple TSVs 2922 are defined by second, third, and fourth dies 2910, 2915, and 2920. These TSVs are electrically connected to interconnect / pads on the back of these dies, which are connected to interconnects and pads on the top or bottom interconnect layers of the underlying dies. Signals from outside the chip are received from the ball grid array 2940 via the interconnects / pads and TSVs.

[0146] Other embodiments use different 3D chip stacking architectures. For example, instead of Figure 29In one embodiment, fourth and third dies 2920 and 2915 are mounted face-to-face, while in another embodiment, the 3D chip stack has these two dies mounted face-to-face, and second and third dies 2910 and 2915 mounted back-to-back. This arrangement allows the third and fourth dies 2915 and 2920 to share a more densely packed set of interconnect layers on their front sides.

[0147] Although the invention has been described with reference to many specific details, those skilled in the art will recognize that it may be practiced in other specific forms without departing from the spirit of the invention. For example, in Figure 1-2 In the examples shown in 4, 6-16, and 19-20, the first IC die is shown mounted face-to-face with the second IC die. In other embodiments, the first IC die is mounted face-to-face with a passive interposer that electrically connects the die to circuitry outside the 3D chip, or to other dies mounted face-to-face or face-to-back on the interposer. Some embodiments place the passive interposer between two faces of the two dies. Some embodiments use an interposer to allow a smaller die to be connected to a larger die.

[0148] Furthermore, several embodiments of 3D circuits and ICs have been described with reference to several 3D structures having vertically aligned IC dies. However, other embodiments are implemented with numerous other 3D structures. For example, in some embodiments, 3D circuits are formed using multiple smaller dies placed on a larger die or wafer. Figure 30 An example of this is shown. Specifically, it illustrates a 3D chip 3000 formed by mounting three smaller dies 3010a-c face-to-face on a larger die 3005. All four dies are housed in a single chip 3000 by encapsulating one side of the chip with a cover 3020 and mounting the other side on a microbump array 3025, wherein the microbump array 3025 is connected to a board 3030 of device 1935. Some embodiments are implemented in a 3D structure formed by vertically stacking two sets of vertically stacked multi-die structures.

Claims

1. A three-dimensional (3D) processor circuit, comprising: The first integrated circuit (IC) die includes a first processor core; as well as A second IC die is vertically mounted on the first IC die, and the second IC die includes a first cache for the first processor core. Wherein, the first cache overlaps vertically with at least a portion of the first processor core in the overlapping region, and, The first IC die is communicatively coupled to the second IC die via a hybrid bonding process. This hybrid bonding includes multiple directly bonded metal contact pads and directly bonded non-conductive regions. The first processor core is electrically connected to the first cache via at least one of the plurality of directly coupled metal contact pads disposed in the overlapping region.

2. The 3D processor circuit according to claim 1 further includes a plurality of z-axis connections between the first processor core and the first cache.

3. The 3D processor circuit of claim 2, wherein the plurality of z-axis connections include a z-axis bus, the z-axis bus being completely defined within the overlapping region.

4. The 3D processor circuit according to claim 2, wherein at least two of the plurality of z-axis connections have a center-to-center distance of less than 5 micrometers.

5. The 3D processor circuit of claim 2, wherein the plurality of z-axis connections include an interconnect layer, the interconnect layer interconnecting the first processor core and the first cache through the hybrid connection.

6. The 3D processor circuit according to claim 1, wherein the first IC die and the second IC die are mounted face-to-face.

7. The 3D processor circuit according to claim 1, wherein: The second IC die also includes a second processor core; The first IC die also includes a second cache; The second cache is used for the second processor core; and The second processor core overlaps vertically with the second cache.

8. The 3D processor circuit according to claim 1, wherein the first cache is an L1 cache.

9. The 3D processor circuit according to claim 8, wherein the first cache completely overlaps with the first processor core.

10. The 3D processor circuit according to claim 8 further includes a second cache located on the first IC die for the first processor core.

11. The 3D processor circuit according to claim 10, wherein the second cache is an L2 cache.

12. The 3D processor circuit according to claim 1, wherein the 3D processor circuit does not include an L3 cache.

13. The 3D processor circuit according to claim 1, wherein the 3D processor circuit is a graphics processing unit.

14. The 3D processor circuit according to claim 1, wherein the 3D processor circuit is a central processing unit.

15. An electronic device comprising: A 3D processor circuit, the 3D processor circuit comprising: The first integrated circuit (IC) die includes a first processor core; A second IC die is vertically mounted on the first IC die, and the second IC die includes a first cache for the first processor core. The first IC die is communicatively coupled to the second IC die via a hybrid bonding process, wherein the hybrid bonding includes multiple directly bonded metal contact pads and directly bonded non-conductive regions. The first cache overlaps vertically with at least a portion of the first processor core in the overlapping region, and The first processor core is electrically connected to the first cache via at least one of the plurality of directly bonded metal contact pads disposed in the overlapping region; and A substrate on which the 3D processor circuit is mounted.

16. The electronic device of claim 15, further comprising a plurality of z-axis connections between the first processor core and the first cache.

17. The electronic device of claim 16, wherein the plurality of z-axis connections include a z-axis bus, the z-axis bus being completely defined within the overlapping region.

18. The electronic device of claim 16, wherein the plurality of z-axis connections include an interconnect layer that interconnects the first processor core with the first cache via the hybrid connection.

19. The electronic device of claim 15, wherein the first IC die and the second IC die are mounted face-to-face.

20. The electronic device according to claim 15, wherein: The second IC die also includes a second processor core; The first IC die also includes a second cache; The second cache is used for the second processor core; and The second processor core overlaps vertically with at least a portion of the second cache.

21. A three-dimensional (3D) processor circuit, comprising: The first integrated circuit (IC) die includes a processor core; A second IC die is vertically stacked on top of the first integrated circuit die, and the second IC die includes a cache for the processor core; as well as An interconnect layer interconnects the first IC die and the second IC die through a hybrid bonding process, wherein the hybrid bonding includes multiple directly bonded metal contact pads and directly bonded non-conductive regions. The processor core is electrically connected to the cache via at least one of the plurality of directly bonded metal contact pads located in the region defined by the overlapping circuit blocks on the first IC die and the second IC die.

22. The 3D processor circuit according to claim 21, wherein the cache is a first cache, and the first IC die further includes a second cache.

23. The 3D processor circuit of claim 21, wherein the spacing between adjacent metal contact pads is 0.5 micrometers to 15 micrometers.

24. The 3D processor circuit of claim 21, wherein the first IC die and the second IC die are mounted back-to-back.

25. The 3D processor circuit according to claim 21, wherein: At least one of the first IC die and the second IC die includes a through-silicon via (TSV); and The signal path that communicatively couples the processor core to the cache also includes at least one of the TSVs.

26. The 3D processor circuit of claim 21, wherein the overlapping circuit block includes a first circuit block and a second circuit block, the first circuit block including at least a portion of the processor core, and the second circuit block including at least a portion of the cache.

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