TFT device and preparation method thereof
By using nanoimprinting technology and magnetron sputtering to fabricate TFT devices, the high cost and environmental risks of traditional photolithography processes have been solved, enabling low-cost and high-efficiency TFT device production.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- UNIV OF ELECTRONICS SCI & TECH OF CHINA
- Filing Date
- 2026-01-26
- Publication Date
- 2026-04-21
AI Technical Summary
Traditional photolithography processes for fabricating TFT devices are costly, involve complicated steps, pose significant environmental risks, and do not align with the trend of green manufacturing.
Nanoimprint technology is used to replace photolithography. Micron-scale ripple structures are formed on PMMA layers by magnetron sputtering and nanoimprint templates. The active layer of metal oxide semiconductor is prepared by combining magnetron sputtering, eliminating the need for coating, exposure, development and etching.
It reduces equipment investment costs, simplifies production processes, improves production efficiency, reduces energy consumption and environmental pollution, and meets the requirements of green manufacturing.
Smart Images
Figure CN121908597A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of electronic devices, and particularly to a TFT device and a preparation method thereof. Background Art
[0002] At present, with the rapid development of display technology, a high on-off ratio is the core goal for creating low-power and highly reliable TFT devices. In the prior art, lithography technology has been used to construct a corrugated heterojunction structure, which can improve device performance through a charge regulation mechanism at the nanoscale vertical interface: in the off state, a negative gate voltage repels electrons to the interface between IGZO and ITZO, and the thin ITZO region widens the energy band gap due to the quantum well effect, suppressing the accumulation of two-dimensional electron gas (2DEG) and forming an "electron barrier" to reduce leakage current; in the on state, a positive gate voltage destroys the interface potential well, promoting the migration of 2DEG to the ITZO channel and increasing the conduction current.
[0003] However, there are many limitations in preparing a TFT device with a corrugated structure by traditional lithography technology: the equipment cost of core equipment such as EUV lithography machines is extremely high, and the purchase and operation and maintenance costs of such equipment impose a heavy burden on enterprises; the process steps are cumbersome, and it is necessary to go through multiple links such as spin coating, exposure, development, etching, and stripping, and each step has strict parameter requirements, which will lead to a significant decrease in production efficiency; the materials such as photoresist and developer used in the process contain difficult-to-degrade organic substances and heavy metal ions, and even after treatment, there is still an environmental protection risk of trace amounts of harmful substances remaining. Moreover, the light source system and cooling equipment supporting EUV lithography machines consume huge amounts of energy, which does not conform to the trend of green manufacturing.
[0004] Therefore, it is necessary to develop a TFT device and a preparation method thereof to solve the above problems. Summary of the Invention
[0005] The purpose of the present invention is to design a TFT device and a preparation method thereof to solve the above problems.
[0006] The present invention achieves the above purpose through the following technical solutions: A TFT device includes a substrate, a gate electrode, a PMMA layer, a first metal oxide semiconductor active layer, and a second metal oxide semiconductor active layer, which are sequentially connected and arranged from bottom to top, and a source electrode and a drain electrode are arranged on the second metal oxide semiconductor active layer; Among them, the PMMA layer serves as both a dielectric layer and a corrugated structure layer, and its surface has a micron-scale corrugated structure; the first metal oxide semiconductor active layer is deposited on the corrugated structure surface of the PMMA layer, and the surface of the first metal oxide semiconductor active layer (4) has a micron-scale corrugated structure, and the second metal oxide semiconductor active layer (5) is deposited on the corrugated structure surface of the first metal oxide semiconductor active layer (4).
[0007] Specifically, the substrate includes a flexible substrate and a rigid substrate; the flexible substrate is any one of the polymers PET, PEN, PI, PE, PES and PDMS; the rigid substrate is glass with a thickness of 100 to 600 μm.
[0008] Preferably, the raw material for preparing the gate is any one of ITO, gold, silver, aluminum, and copper, and the raw material is a thin film structure with a thickness of 10 to 40 μm.
[0009] Specifically, the first and second active layers of the metal oxide semiconductor have different energy bands, forming a two-dimensional electron gas.
[0010] A method for fabricating a TFT device includes the following steps: Step S1: Clean and dry the substrate: Clean the substrate with acetone solution, deionized water and isoacetone, and then dry it with nitrogen gas. Step S2: Fabricate the gate on the surface of the substrate by magnetron sputtering or evaporation; Step S3: Spin-coat PMMA material onto the gate surface to form a PMMA layer. Use a nanoimprint template to imprint the PMMA layer. After demolding, a corrugated structure is formed. Step S4: The first metal oxide semiconductor active layer and the second metal oxide semiconductor active layer are obtained by sequential sputtering using a DC magnetron sputtering device. Step S5: The source and drain electrodes are fabricated on the second metal-oxide-semiconductor active layer by DC magnetron sputtering; Step S6: Perform annealing treatment at a temperature of 200-300℃.
[0011] Specifically, step S3 is as follows: Step S31: Prepare a PMMA solution with a concentration of 5%-15%; Step S32: Place the sputtered gate substrate on the rotating stage of the spin coater and fix it by vacuum adsorption; Step S33: Use a pipette to draw 3-5 mL of PMMA solution and drop it onto the center of the gate surface. Start the spin coater, set the rotation speed to 2000-4000 r / min, and the spin coating time to 30-60 s. Step S34: After spin coating, place it in an oven and dry it at 80-120℃ for 10-30 minutes to form a PMMA layer with a thickness of 100-300nm. Step S35: Place the device with the PMMA layer into the nanoimprint apparatus, align the customized nanoimprint template, and ensure that the template is parallel and aligned with the surface of the PMMA layer. Step S36: Set the imprinting temperature to 150-180℃, the pressure to 5-15MPa, and the imprinting time to 30-120s, and perform the imprinting operation; Step S37: After the temperature cools down to below 60°C, demold the material to form a corrugated structure with a period of 500nm-5um and an amplitude of 5nm-20nm on the surface of the PMMA layer.
[0012] The beneficial effects of this invention are: This invention reduces costs; by using nanoimprint technology to replace traditional photolithography, it avoids dependence on photolithography machines and other equipment, reducing equipment investment costs. It eliminates the cumbersome steps of photolithography, such as coating, exposure, development, etching, and resist removal, shortening the production process and improving efficiency. The nanoimprint process has low energy consumption, and PMMA materials are highly compatible with the process, further reducing energy consumption and environmental pollution, aligning with the trend of green manufacturing. Attached Figure Description
[0013] Figure 1 This is a schematic diagram of the structure of the present invention.
[0014] The markings in the diagram are: 1-substrate, 2-gate, 3-PMMA layer, 4-metal oxide semiconductor active layer one, 5-metal oxide semiconductor active layer two, 6-source electrode, 7-drain electrode. Detailed Implementation
[0015] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0016] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0017] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0018] In the description of this invention, it should be understood that the terms "upper," "lower," "inner," "outer," "left," "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are only used to facilitate the description of this invention and to simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0019] Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.
[0020] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, terms such as "set" and "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0021] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0022] like Figure 1 As shown, a TFT device includes a substrate 1, a gate 2, a PMMA layer 3, a metal oxide semiconductor active layer 4, and a metal oxide semiconductor active layer 5, which are connected sequentially from bottom to top. An active electrode 6 and a drain electrode 7 are disposed on the metal oxide semiconductor active layer 5. In this process, PMMA layer 3 serves as both a dielectric layer and a corrugated structure layer, with a micron-level corrugated structure on its surface. Metal oxide semiconductor active layer 4 is deposited on the corrugated structure surface of PMMA layer 3, and the surface of metal oxide semiconductor active layer 4 has a micron-level corrugated structure. Metal oxide semiconductor active layer 2 (5) is deposited on the corrugated structure surface of metal oxide semiconductor active layer 4. Metal oxide semiconductor active layer 4 and PMMA layer 3 together form a corrugated heterojunction. PMMA3 nanoimprinting adopts the nanothermal imprinting technology T-NIL, which utilizes the thermoplasticity of PMMA to achieve high-precision replication of nanoscale patterns. After cooling and solidification, a low-defect corrugated structure is formed.
[0023] Substrate 1 includes a flexible substrate and a rigid substrate; the flexible substrate is any one of the polymers PET, PEN, PI, PE, PES and PDMS; the rigid substrate is glass with a thickness of 100 to 600 μm.
[0024] The raw material for preparing gate 2 is any one of ITO, gold, silver, aluminum, and copper, and the raw material is a thin film structure with a thickness of 10 to 40 μm.
[0025] The metal-oxide-semiconductor active layer 4 and the metal-oxide-semiconductor active layer 5 have different energy bands, forming a two-dimensional electron gas. The metal-oxide-semiconductor active layer 4 and the metal-oxide-semiconductor active layer 5 can be selected as IGZO and ITZO, IGZO and IZO, etc.
[0026] A method for fabricating a TFT device includes the following steps: Step S1: Clean and dry the substrate (1): Clean the substrate (1) with acetone solution, deionized water and isoacetone, and then dry it with nitrogen gas. Step S2: The gate (2) is fabricated on the surface of the substrate (1) by magnetron sputtering or vapor deposition; Step S3: Spin-coat PMMA material onto the surface of the gate (2) to form a PMMA layer (3), and use a nanoimprint template to imprint the PMMA layer (3). After demolding, a corrugated structure is formed. Step S4: The first metal oxide semiconductor active layer (4) and the second metal oxide semiconductor active layer (5) are obtained by sequential sputtering using a DC magnetron sputtering device; Step S5: The source electrode 6 and drain electrode 7 are fabricated on the metal oxide semiconductor active layer 2 (5) by DC magnetron sputtering; Step S6: Perform annealing treatment at a temperature of 200-300℃.
[0027] Step S3 is as follows: Step S31: Prepare a PMMA solution with a concentration of 5%-15%; Step S32: Place the sputtered gate 2 substrate on the rotating stage of the spin coater and fix it by vacuum adsorption; Step S33: Use a pipette to draw 3-5 mL of PMMA solution and drop it onto the center of the gate surface. Start the spin coater, set the rotation speed to 2000-4000 r / min, and the spin coating time to 30-60 s. Step S34: After spin coating, place it in an oven and dry it at 80-120℃ for 10-30 minutes to form a PMMA layer 3 with a thickness of 100-300nm; Step S35: Place the device with PMMA layer 3 into the nanoimprint apparatus, align the customized nanoimprint template, and ensure that the template is parallel and aligned with the surface of the PMMA layer. Step S36: Set the imprinting temperature to 150-180℃, the pressure to 5-15MPa, and the imprinting time to 30-120s, and perform the imprinting operation; Step S37: After the temperature cools down to below 60°C, demolding is performed to form a corrugated structure with a period of 500nm-5um and an amplitude of 5nm-20nm on the surface of PMMA layer 2.
[0028] In some embodiments, in a TFT device, the substrate is glass, the gate is ITO (150nm), the gate insulating layer material is PMMA, the first metal oxide semiconductor active layer material is ITZO, and the second metal oxide semiconductor active layer material is IGZO.
[0029] In some embodiments, a method for fabricating a TFT device includes the following steps: Step S1: Clean the glass substrate 1 sequentially with deionized water, acetone solution, deionized water and isoacetone for 15 minutes each. Place the cleaned substrate in an ultraviolet ozone (UVO3) cleaner for 15 minutes and finally dry it with nitrogen.
[0030] Step S2: ITO gate 2 is fabricated on the surface of glass substrate 1 by magnetron sputtering. The sputtering power is 100W, the sputtering time is 1000s, the Ar flow rate is set to 30sccm, and the pressure inside the cavity is maintained at 2mTorr.
[0031] Step S3: Prepare PMMA gate insulating layer 3. First, prepare a PMMA solution with a concentration of 120 mg / mL. Use spin coating method, set the rotation speed to 3000 rpm and the spin coating time to 60 s. Then bake in an oven at 80℃ for 10 min and anneal at 135℃ for 1 h to produce a PMMA gate insulating layer 3 with a thickness of 400 nm.
[0032] Step S4: Perform hot embossing on the PMMA gate insulating layer 3. The embossing uses a corrugated template with a template period of 1nm and an amplitude of 10nm. The embossing is performed at a temperature of 150℃ and a pressure of 10MPA for 60s to ensure that the PMMA completely fills the template texture.
[0033] Step S5: ITZO metal-oxide-semiconductor active layer 4 and IGZO metal-oxide-semiconductor active layer 5 are fabricated using DC magnetron sputtering. The ITZO target is magnetron sputtered to a thickness of 10 nm, with an oxygen-argon flow ratio of O2 / (Ar+O2) = 2%, where the Ar flow rate is set to 100 sccm, the O2 flow rate is set to 2 sccm, the sputtering power is 180 W, the sputtering time is 600 s, and the chamber pressure is maintained at 3 mTorr. The IGZO target is magnetron sputtered to a thickness of 20 nm, with an oxygen-argon flow ratio of O2 / (Ar+O2) = 2%, where the Ar flow rate is set to 100 sccm, the O2 flow rate is set to 2 sccm, the sputtering power is 180 W, the sputtering time is 600 s, and the chamber pressure is maintained at 3 mTorr.
[0034] Step S6: Source and drain electrodes are fabricated on the active layer using DC magnetron sputtering. The oxygen-argon flow ratio O2 / (Ar+O2) = 0%, where the Ar flow rate is set to 100 sccm and the O2 flow rate is set to 0 sccm. The sputtering power is 180 W, the sputtering time is 300 s, and the chamber pressure is maintained at 3 mTorr. The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A TFT device, characterized in that, The structure includes a substrate (1), a gate (2), a PMMA layer (3), a metal oxide semiconductor active layer one (4), and a metal oxide semiconductor active layer two (5) connected sequentially from bottom to top. An active electrode (6) and a drain electrode (7) are provided on the metal oxide semiconductor active layer two (5). Among them, the PMMA layer (3) serves as both a dielectric layer and a corrugated structure layer, and its surface has a micron-level corrugated structure; the first metal oxide semiconductor active layer (4) is deposited on the corrugated structure surface of the PMMA layer (3), the surface of the first metal oxide semiconductor active layer (4) has a micron-level corrugated structure, and the second metal oxide semiconductor active layer (5) is deposited on the corrugated structure surface of the first metal oxide semiconductor active layer (4).
2. The TFT device according to claim 1, characterized in that, The substrate (1) includes a flexible substrate and a rigid substrate; the flexible substrate is any one of the polymers PET, PEN, PI, PE, PES and PDMS; the rigid substrate is glass with a thickness of 100 to 600 μm.
3. A TFT device according to claim 2, characterized in that, The raw material for preparing the gate (2) is any one of ITO, gold, silver, aluminum and copper. The raw material is a thin film structure with a thickness of 10 to 40 μm.
4. A TFT device according to claim 1, characterized in that, The active layers of the metal oxide semiconductor (MOS) layer 1 (4) and the active layers of the metal oxide semiconductor (MOS) layer 2 (5) have different energy bands, forming a two-dimensional electron gas.
5. A method for fabricating a TFT device according to any one of claims 1-4, characterized in that, Includes the following steps: Step S1: Clean and dry the substrate (1): Clean the substrate (1) with acetone solution, deionized water and isoacetone, and then dry it with nitrogen gas. Step S2: The gate (2) is fabricated on the surface of the substrate (1) by magnetron sputtering or vapor deposition; Step S3: Spin-coat PMMA material onto the surface of the gate (2) to form a PMMA layer (3), and use a nanoimprint template to imprint the PMMA layer (3). After demolding, a corrugated structure is formed. Step S4: The first metal oxide semiconductor active layer (4) and the second metal oxide semiconductor active layer (5) are obtained by sequential sputtering using a DC magnetron sputtering device; Step S5: The source (6) and drain (7) are fabricated on the metal oxide semiconductor active layer 2 (5) by DC magnetron sputtering. Step S6: Perform annealing treatment at a temperature of 200-300℃.
6. The method for fabricating a TFT device according to claim 5, characterized in that, Step S3 is as follows: Step S31: Prepare a PMMA solution with a concentration of 5%-15%; Step S32: Place the substrate with the sputtered gate (2) on the rotating stage of the spin coater and fix it by vacuum adsorption; Step S33: Use a pipette to draw 3-5 mL of PMMA solution and drop it onto the center of the gate surface. Start the spin coater, set the rotation speed to 2000-4000 r / min, and the spin coating time to 30-60 s. Step S34: After spin coating, place it in an oven and dry it at 80-120℃ for 10-30 minutes to form a PMMA layer with a thickness of 100-300nm (3). Step S35: Place the device with the PMMA layer (3) into the nanoimprint apparatus, align the customized nanoimprint template, and ensure that the template is parallel and aligned with the surface of the PMMA layer. Step S36: Set the imprinting temperature to 150-180℃, the pressure to 5-15MPa, and the imprinting time to 30-120s, and perform the imprinting operation; Step S37: After the temperature cools down to below 60°C, demolding is performed to form a corrugated structure with a period of 500nm-5um and an amplitude of 5nm-20nm on the surface of the PMMA layer (2).