Multicolor adjustable LED chip and preparation method thereof
By constructing isolated light-emitting units on the same substrate and independently controlling the current, the problems of light mixing uniformity and process complexity of multicolor LED chips are solved, and efficient fabrication of multicolor tunable LED chips is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANCHANG UNIV
- Filing Date
- 2025-12-26
- Publication Date
- 2026-04-21
AI Technical Summary
Existing technologies for multi-color tunable LED chips suffer from issues such as uniform light mixing and complex fabrication processes. In particular, it is difficult to achieve uniform light mixing in large-size dual-chip or multi-chip combinations. Furthermore, existing methods cannot achieve individual controllability of each wavelength and have a limited range of wavelength variations.
By constructing isolated first and second light-emitting units on the same substrate, using independent pads to control the magnitude of different LED input currents, and by arranging multiple light-emitting layers around each other, the light color space distance is shortened, thus achieving chip-level dual-color mixing.
This invention enables the creation of a monolithic integrated multicolor tunable LED chip with a simple fabrication process and uniform light mixing, significantly improving the light mixing efficiency of dual-color light and the output control of color temperature light.
Smart Images
Figure CN121908710A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of LED chip technology, and in particular to a multi-color tunable LED chip and its preparation method. Background Technology
[0002] With the increasing demand for multifunctional and high-performance LEDs in fields such as visible light communication, smart and health lighting, agricultural photobiological lighting, and full-color displays, LED technology is evolving towards miniaturization. From the initial hundreds of micrometers of traditional LEDs to the micrometers of Micro-LEDs, and further miniaturized to the nanometer level of Nano-LEDs, the change in LED size has brought new progress. However, regardless of the size of the LED, breaking through its inherent physical limitations and realizing multi-color tunable LEDs with high luminous efficiency and wide color gamut has become a key development direction for the next generation of optoelectronic devices, containing huge market potential and social value.
[0003] In order to realize multi-color tunable LEDs, existing technologies often require the fabrication of LED chips from wafers with different wavelengths, and then the integration of LED chips with different emission wavelengths through complex packaging processes. However, regardless of the combination and arrangement of multi-color LED chips, the spatial light distribution symmetry and light mixing uniformity have always been problems. It is necessary to use optical components such as microlens arrays and prism structures to achieve uniform light mixing. This multi-process and multi-component fabrication method not only significantly increases production costs, but also increases the difficulty of process control.
[0004] On the other hand, existing technologies for achieving multi-color tunable LEDs often employ monolithic integration, directly growing wafers with epitaxial layers of different wavelengths on the same substrate. One method involves adjusting the current to change the emission wavelength; however, current control cannot achieve individual control over each wavelength, and the range of wavelength variation is limited. Another method relies on etching to fabricate independently controllable multi-color LED chips. However, this method primarily produces micro-LEDs for full-color displays, with multi-color LED chip arrangements similar to traditional backlight displays, failing to consider light mixing issues. For large-size dual-chip or multi-chip combinations, the issue of light mixing uniformity needs to be addressed.
[0005] In existing technologies, to solve the light mixing problem, two independent epitaxial light-emitting units are integrated on the same epitaxial wafer, with the second epitaxial light-emitting unit arranged around the first epitaxial light-emitting unit, achieving chip-level dual-color light mixing. However, its LED chip has a vertical structure. This structure emphasizes the dual-color tunable LED chip, and the fabrication process requires transfer and bonding, substrate removal, N-side roughening, and precise N-side etching, resulting in complex fabrication processes and a small window size. Summary of the Invention
[0006] Based on this, the purpose of this invention is to provide a multi-color tunable LED chip and its fabrication method, which can realize a monolithic integrated multi-color tunable LED chip with simple fabrication process and uniform light mixing.
[0007] This invention provides a multi-color adjustable LED chip, comprising: A substrate is obtained, and a buffer layer and a plurality of light-emitting stacks are sequentially grown on the substrate. The plurality of light-emitting stacks include a first light-emitting stack and a second light-emitting stack from bottom to top. The first light-emitting stack includes a first N-type layer, a first light-emitting layer and a first P-type layer; the second light-emitting stack includes a second N-type layer, a second light-emitting layer and a second P-type layer. The middle region of the second light-emitting stack is etched to expose the first P-type layer to obtain a window. Then, the first light-emitting stack is etched along the surrounding area until a portion of the first N-type layer is etched, and the second light-emitting stack is etched until a portion of the second N-type layer is etched to expose the first N-type layer and the second N-type layer to form an isolated first light-emitting unit and a second light-emitting unit. The first N-type layer in the trench region is etched until the substrate is exposed; a sidewall passivation layer is prepared to cover the exposed substrate and the first and second light-emitting units; and the sidewall passivation layer is etched to form vias to expose the first N-type layer, the first P-type layer, the second N-type layer, and the second P-type layer. A first P-electrode and a second P-electrode are fabricated on the exposed first P-type layer and the second P-type layer, respectively; a first N-electrode and a second N-electrode are fabricated on the exposed first N-type layer and the second N-type layer, respectively; and a first P-electrode current extension and metal pad layer and a second P-electrode current extension and metal pad layer are fabricated on the first P-electrode and the second P-electrode, respectively. A surface passivation layer is prepared and vias are etched to expose the first N electrode, the second N electrode, the first P electrode current extension and metal pad layer, and the pads of the second P electrode current extension and metal pad layer to prepare a multi-color tunable LED chip.
[0008] In addition, the multi-color adjustable LED chip according to the present invention may also have the following additional technical features: Furthermore, in the step of etching the middle region of the second light-emitting stack to expose the first P-type layer to obtain a window, the method further includes: Etching damage repair is performed on the first P-type layer in the first light-emitting stack; The repair methods include: The first P-type layer in the first light-emitting stack is etched using a low-power etching process, wherein a damage layer is generated on the surface of the first P-type layer after etching. The damaged layer was repaired by high-temperature gas annealing and removed by wet etching. Then, a P-type layer is regrown on the surface after the damaged layer is removed to replace the damaged layer and repair the original first P-type layer.
[0009] Further, the steps of fabricating the first P-electrode and the second P-electrode on the exposed first P-type layer and second P-type layer respectively include: The first P-type layer and the second P-type layer are activated by high-temperature annealing at 500℃-900℃ in an N2 or O2 atmosphere. The first P-electrode and the second P-electrode are simultaneously fabricated by electron beam evaporation or magnetron sputtering of the first P-type layer and the second P-type layer after activation. The first P electrode and the second P electrode are annealed in an N2 or O2 atmosphere at a temperature of 200℃-600℃. Then, windows are made on the surface of the first P electrode and the second P electrode using a standard photolithography process. The first P electrode and the second P electrode are then prepared by wet etching.
[0010] Further, the steps of fabricating a first N-electrode and a second N-electrode on the exposed first N-type layer and second N-type layer, respectively; and fabricating a first P-electrode current spread and metal pad layer and a second P-electrode current spread and metal pad layer on the first P-electrode and second P-electrode, respectively, include: The first N electrode, the second N electrode, the current spread and metal pad layer of the first P electrode, and the current spread and metal pad layer of the second P electrode are all independently controlled so that the first light-emitting unit and the second light-emitting unit can be independently controlled.
[0011] Further, the steps of fabricating a first N-electrode and a second N-electrode on the exposed first N-type layer and second N-type layer, respectively; and fabricating a first P-electrode current spread and metal pad layer and a second P-electrode current spread and metal pad layer on the first P-electrode and second P-electrode, respectively, include: The first P-electrode current extension and metal pad layer are interconnected with the second P-electrode current extension and metal pad layer to construct a common P-electrode pad. The first N electrode and the second N electrode are controlled independently so that the first light-emitting unit and the second light-emitting unit can be controlled independently. or: The first N electrode and the second N electrode are interconnected to form a common N electrode pad; The first P-electrode current extension and metal pad layer are independently controlled with the second P-electrode current extension and metal pad layer so that the first light-emitting unit and the second light-emitting unit can be independently controlled.
[0012] Furthermore, in the steps of etching the first light-emitting stack along the surrounding area until a portion of the first N-type layer is etched, and etching the second light-emitting stack until a portion of the second N-type layer is etched to expose the first N-type layer and the second N-type layer to form isolated first light-emitting units and second light-emitting units: The thickness difference between the first light-emitting layer, the first P-type layer, the second light-emitting layer, and the second P-type layer is not greater than a preset difference, so that the first N-type layer and the second N-type layer can be exposed simultaneously in one etching.
[0013] Furthermore, in the steps of etching the first light-emitting stack along the surrounding area until a portion of the first N-type layer is etched, and etching the second light-emitting stack until a portion of the second N-type layer is etched to expose the first N-type layer and the second N-type layer to form isolated first light-emitting units and second light-emitting units: When the thickness difference between the first light-emitting layer, the first P-type layer, the second light-emitting layer, and the second P-type layer is greater than a preset difference, the method includes: First, etch along the surrounding area down to the first light-emitting stack until part of the first N-type layer is etched; Then etch along the surrounding area to the second light-emitting stack until part of the second N-type layer is etched.
[0014] Furthermore, the plurality of light-emitting stacks, from bottom to top, include a first light-emitting stack, a second light-emitting stack, a third light-emitting stack, and a fourth light-emitting stack, to construct a first light-emitting unit, a second light-emitting unit, a third light-emitting unit, and a fourth light-emitting unit based on the first light-emitting stack, the second light-emitting stack, the third light-emitting stack, and the fourth light-emitting stack, wherein: The second, third, and fourth light-emitting units are arranged around the first light-emitting unit in sequence, with the first light-emitting unit as the central region. The peak wavelength gradually increases from the first light-emitting unit to the fourth light-emitting unit.
[0015] This application also provides a multi-color tunable LED chip, which is fabricated using the above-described multi-color tunable LED chip fabrication method.
[0016] The aforementioned multi-color tunable LED chip and its fabrication method achieve different color temperature light outputs by constructing isolated first and second light-emitting units on the epitaxial layer and controlling the input current of different LEDs with independent pads. Secondly, multiple light-emitting layers are arranged in a surrounding configuration to obtain multiple surrounding light-emitting units, thereby shortening the spatial distance between different light colors and fundamentally improving the mixing efficiency of dual-color light. Specifically, chip-level dual-color mixing is achieved by constructing cyan and orange light-emitting units on the epitaxial layer. The orange light-emitting unit is arranged around the cyan light-emitting unit, significantly shortening the spatial distance between the two light colors and fundamentally improving the mixing efficiency of cyan and orange light. By controlling the input current of the cyan and orange LEDs with independent pads, different color temperature light outputs can be achieved. This results in a simple fabrication process and a monolithically integrated multi-color tunable LED chip with uniform light mixing. Attached Figure Description
[0017] Figure 1This is a cross-sectional schematic diagram of the epitaxial growth of dual-wavelength LEDs on the same substrate in an embodiment of this application.
[0018] Figure 2 This is a schematic cross-sectional view of the etching to the first P-type layer in an embodiment of this application.
[0019] Figure 3 This is a schematic cross-sectional view of the etching to the first N-type layer and the second N-type layer in an embodiment of this application. Figure 4 This is a schematic cross-sectional view of the chip after etching and isolation in an embodiment of this application.
[0020] Figure 5 This is a schematic cross-sectional view of the sidewall passivation layer after it has been prepared in an embodiment of this application.
[0021] Figure 6 This is a cross-sectional schematic diagram of the first P electrode and the second P electrode after they were fabricated in the embodiments of this application.
[0022] Figure 7 This is a cross-sectional schematic diagram of the independent first N electrode, second N electrode, first P electrode current extension and metal pad layer, and second P electrode current extension and metal pad layer in the embodiments of this application.
[0023] Figure 8 This is a cross-sectional schematic diagram showing the fabrication of independent first N-electrodes and second N-electrodes, and the interconnection of first P-electrode current extension and metal pad layer, and second P-electrode current extension and metal pad layer in the embodiments of this application.
[0024] Figure 9 This is a cross-sectional schematic diagram showing the fabrication of interconnected first N-electrodes and second N-electrodes, independent first P-electrode current extension and metal pad layer, and second P-electrode current extension and metal pad layer in the embodiments of this application.
[0025] Figure 10 This is a schematic cross-sectional view of the surface passivation layer after it has been prepared in an embodiment of this application.
[0026] Figure 11 This is a bird's-eye view of a multi-emitting-unit LED chip prepared according to an embodiment of this application.
[0027] Figure 12 This is a cross-sectional schematic diagram of a multi-emitting unit LED chip prepared according to an embodiment of this application.
[0028] Explanation of key component symbols:
[0029] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation
[0030] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0031] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.
[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0033] To achieve a monolithically integrated multi-color tunable LED chip with a simple fabrication process and uniform light mixing, this application provides a multi-color tunable LED chip and its fabrication method. Specifically, it provides a monolithically integrated multi-color tunable LED chip and its fabrication method. By constructing isolated first and second light-emitting units on the epitaxial layer, and controlling the magnitude of different LED input currents with independent pads, different color temperature light outputs can be achieved. Secondly, multiple light-emitting layers are arranged in a surrounding configuration to obtain multiple surrounding light-emitting units, thereby shortening the spatial distance between different light colors and fundamentally improving the light mixing efficiency of dual-color light. Specifically: by constructing cyan and orange light-emitting units on the epitaxial layer to achieve chip-level dual-color light mixing, with the orange light-emitting unit arranged around the cyan light-emitting unit, the spatial distance between the two light colors is significantly shortened, fundamentally improving the light mixing efficiency of cyan and orange light. By controlling the magnitude of the input current to the cyan and orange LEDs with independent pads, different color temperature light outputs can be achieved. This results in a monolithically integrated multi-color tunable LED chip with a simple fabrication process and uniform light mixing. This application provides a method for fabricating a multi-color tunable LED chip, including steps S11-S18: S11. Obtain a substrate, and sequentially grow a buffer layer and a plurality of light-emitting stacks on the substrate, wherein the plurality of light-emitting stacks include a first light-emitting stack and a second light-emitting stack from bottom to top.
[0034] Each light-emitting stack, from bottom to top, includes an N-type layer, a light-emitting layer, and a P-type layer. The first light-emitting stack includes a first N-type layer, a first light-emitting layer, and a first P-type layer; the second light-emitting stack includes a second N-type layer, a second light-emitting layer, and a second P-type layer. In some optional embodiments, the multiple light-emitting stacks may further include a first light-emitting stack, a second light-emitting stack, a third light-emitting stack, and a fourth light-emitting stack from bottom to top, to construct a first light-emitting unit, a second light-emitting unit, a third light-emitting unit, and a fourth light-emitting unit based on the first light-emitting stack, the second light-emitting stack, the third light-emitting stack, and the fourth light-emitting stack, wherein: the second light-emitting unit, the third light-emitting unit, and the fourth light-emitting unit are sequentially arranged around the first light-emitting unit with the first light-emitting unit as the central region, and the peak wavelength gradually increases from the first light-emitting unit to the fourth light-emitting unit.
[0035] S12. Etch the middle region of the second light-emitting stack to expose the first P-type layer to obtain a window.
[0036] In some alternative embodiments, in the step of etching the middle region of the second light-emitting stack to expose the first P-type layer to obtain a window, the method further includes: repairing the etching damage of the first P-type layer in the first light-emitting stack; wherein the repair method includes: etching the first P-type layer in the first light-emitting stack using a low-power etching process, wherein a damaged layer is generated on the surface of the etched first P-type layer; repairing by high-temperature gas annealing and removing the damaged layer by wet etching; and then regrowing a P-type layer on the surface after removing the damaged layer to replace the damaged layer to repair the original first P-type layer.
[0037] S13. Etch the first light-emitting stack along the surrounding area until a portion of the first N-type layer is etched, and etch the second light-emitting stack until a portion of the second N-type layer is etched to expose the first N-type layer and the second N-type layer to form isolated first light-emitting units and second light-emitting units.
[0038] In some optional embodiments, when the thickness difference between the first light-emitting layer, the first P-type layer, the second light-emitting layer, and the second P-type layer is not greater than a preset difference, that is, when the thicknesses of the first light-emitting layer, the first P-type layer, the second light-emitting layer, and the second P-type layer remain similar, a single etching operation can simultaneously expose the first N-type layer and the second N-type layer. When the thickness difference between the first light-emitting layer, the first P-type layer, the second light-emitting layer, and the second P-type layer is greater than a preset difference, that is, when the thicknesses of the first light-emitting layer, the first P-type layer, the second light-emitting layer, and the second P-type layer differ significantly, the etching operation needs to be divided into two steps. Specifically, the first etching step involves etching along the surrounding area down to the first light-emitting stack until a portion of the first N-type layer is etched; the second etching step involves etching along the surrounding area down to the second light-emitting stack until a portion of the second N-type layer is etched.
[0039] S14, etch the first N-type layer in the trench region until the substrate is exposed.
[0040] The first N-type layer in the etched trench region is etched until the substrate is exposed to completely isolate the chips and form independent multi-color chip units.
[0041] S15. Prepare a sidewall passivation layer to cover the exposed substrate and the first light-emitting unit and the second light-emitting unit, and etch through holes in the sidewall passivation layer to expose the first N-type layer, the first P-type layer, the second N-type layer and the second P-type layer.
[0042] S16. A first P electrode and a second P electrode are fabricated on the exposed first P-type layer and second P-type layer, respectively.
[0043] In some alternative embodiments, the first P-type layer and the second P-type layer are subjected to high-temperature annealing in an N2 or O2 atmosphere at a temperature of 500°C-900°C to activate the first P-type layer and the second P-type layer; the activated first P-type layer and the second P-type layer are then used to simultaneously prepare the first P-electrode and the second P-electrode; the first P-electrode and the second P-electrode are then annealed in an N2 or O2 atmosphere at a temperature of 200°C-600°C, and then windows are made on the surface of the first P-electrode and the second P-electrode using a standard photolithography process, and the first P-electrode and the second P-electrode are prepared by wet etching.
[0044] S17. A first N-electrode and a second N-electrode are fabricated on the exposed first N-type layer and second N-type layer, respectively; at the same time, a first P-electrode current extension and metal pad layer and a second P-electrode current extension and metal pad layer are fabricated on the first P-electrode and the second P-electrode, respectively.
[0045] In some alternative embodiments, when fabricating the first N electrode, the second N electrode, the first P electrode current extension and metal pad layer, and the second P electrode current extension and metal pad layer, on the one hand, the first N electrode, the second N electrode, the first P electrode current extension and metal pad layer, and the second P electrode current extension and metal pad layer can be fabricated independently to achieve independent control of the first light-emitting unit and the second light-emitting unit; on the other hand, the first P electrode current extension and metal pad layer and the second P electrode current extension and metal pad layer can be interconnected, and only one P electrode pad is fabricated; independent control of the first light-emitting unit and the second light-emitting unit is achieved through the independent first N electrode and the second N electrode. Furthermore, the first N electrode and the second N electrode can also be interconnected, and only one N electrode pad is fabricated; independent control of the first light-emitting unit and the second light-emitting unit is achieved through the independent first P electrode current extension and metal pad layer and the second P electrode current extension and metal pad layer.
[0046] S18. Prepare a surface passivation layer and etch through holes to expose the first N electrode, the second N electrode, the first P electrode current extension and metal pad layer, and the pad of the second P electrode current extension and metal pad layer to prepare a multi-color tunable LED chip.
[0047] This application also provides a multi-color tunable LED chip, which is fabricated using the above-described multi-color tunable LED chip fabrication method.
[0048] To facilitate understanding of the present invention, several embodiments are given below. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention will be more thorough and complete.
[0049] Example 1 The method for fabricating a multi-color tunable LED chip in the first embodiment of the present invention is specifically used to fabricate a dual-color tunable same-side LED chip structure, the method comprising: S101. Obtain a substrate, and grow a buffer layer and multiple light-emitting stacks sequentially on the substrate. The multiple light-emitting stacks include a first light-emitting stack and a second light-emitting stack from bottom to top.
[0050] In this embodiment, a substrate 1 is provided, on which a growth buffer layer 2, a first N-type layer 11, a first light-emitting layer 12, and a first P-type layer 13 of a first light-emitting stack 111, and a second N-type layer 21, a second light-emitting layer 22, and a second P-type layer 23 of a second light-emitting stack 112 are sequentially grown. The epitaxial structure after growth is as follows: Figure 1 As shown.
[0051] In this design, substrate 1 is sapphire, buffer layer 2 is made of AlN, the first N-type layer 11 and the second N-type layer 21 are both made of N-type GaN, the first P-type layer 13 and the second P-type layer 23 are both made of P-type GaN, the first light-emitting layer 12 is a cyan InGaN / GaN quantum well, and the second light-emitting layer 22 is an orange InGaN / GaN quantum well. The thickness of buffer layer 2 is 200 nm, the thickness of the first N-type layer 11 is 1600 nm, the thickness of the first light-emitting layer 12 is 100 nm, the thickness of the first P-type layer 13 is 220 nm, the thickness of the second N-type layer 21 is 600 nm, the thickness of the second light-emitting layer 22 is 100 nm, and the thickness of the second P-type layer 23 is 220 nm.
[0052] S102, Etch the middle region of the second light-emitting stack to expose the first P-type layer to obtain a window.
[0053] As a specific example, the second N-type layer 21, the second light-emitting layer 22, and the second P-type layer 23 of the second light-emitting stack 112 are etched away to expose the first P-type layer 13 of the first light-emitting stack 111. The structure after etching is as follows: Figure 2 As shown.
[0054] Specifically, after creating a window on the surface of the second P-type layer 23 using standard photolithography, mesa etching of the epitaxial layer is performed using inductively coupled plasma dry etching (ICP). The etching gas used in ICP is a mixture of Cl2 and BCl3 with a flow rate ratio of Cl2:BCl3 = 100:20 (sccm). The chamber pressure is 4 mtorr, the upper and lower electrode bias voltages are 120 W / 90 W, the DC bias voltage is 120 V, the etching rate is 20 A / s, and the etching time is 460 s. Mesa etching can also be performed using electron cyclotron resonance plasma etching (ECR) or reactive ion etching (RIE). In step S102, during the etching of the first P-type layer 13 of the first light-emitting stack 111, N-type nitrogen vacancy defects are generated on the surface of the first P-type layer 13, causing etching damage. This leads to a decrease in the electrical properties of the Mg-doped P-type layer. Repair is needed to reduce or eliminate these etching damages and restore the high-quality surface and the electrical properties of the material itself. Specifically, plasma-enhanced chemical vapor deposition (PECVD) is used to oxidize the P-type GaN damaged layer at 220°C in an N2O atmosphere for 10 minutes. After oxidation, hydrochloric acid is used to remove the oxidized P-type GaN damaged layer. Then, metal-organic chemical vapor deposition (MOCVD) is used to regenerate a whole layer of P-type GaN on the repaired surface. The thickness of the whole layer of P-type GaN is 100 nm.
[0055] S103. Etch the first light-emitting stack along the surrounding area until a portion of the first N-type layer is etched, and etch the second light-emitting stack until a portion of the second N-type layer is etched to expose the first N-type layer and the second N-type layer to form an isolated first light-emitting unit and a second light-emitting unit.
[0056] As a specific example, the first light-emitting layer 12, the first P-type layer 13, and part of the first N-type layer 11 of the first light-emitting stack 111, and the second light-emitting layer 22, the second P-type layer 23, and part of the second N-type layer 21 of the second light-emitting stack 112 are etched away, exposing the first N-type layer 11 of the first light-emitting stack 111 and the second N-type layer 21 of the second light-emitting stack 112, forming isolated first light-emitting units and second light-emitting units. The structure after etching is as follows: Figure 3 As shown. In the first light-emitting stack 111, the first light-emitting layer 12 and the first P-type layer 13 have a thickness of 320 nm, and the second light-emitting layer 22 and the second P-type layer 23 of the second light-emitting stack 112 have a thickness of 320 nm, and the thicknesses of the two are the same.
[0057] Specifically, after creating windows on the surfaces of the first N-type layer 11 and the second N-type layer 21 using standard photolithography, mesa etching of the epitaxial layer is performed using inductively coupled plasma dry etching (ICP). The etching gas for ICP is a mixture of Cl2 and BCl3, with a gas flow rate ratio of Cl2:BCl3=100:20 (sccm). The chamber pressure is 4 mtorr, the upper and lower electrode bias voltages are 330W / 180W, the DC bias voltage is 180V, the etching rate is 35A / s, and the etching time is 150s. Mesa etching can also be performed using electron cyclotron resonance plasma etching (ECR) or reactive ion etching (RIE).
[0058] S104, etch the first N-type layer in the trench region until the substrate is exposed.
[0059] In this embodiment, the first N-type layer 11 of the first light-emitting stack 111 in the trench region is etched away until the underlying substrate 1 is exposed, achieving complete isolation between chips and forming independent multi-color chip units. The structure after etching is as follows: Figure 4 As shown.
[0060] Specifically, after creating a window on the surface of the first N-type layer 11 using standard photolithography, mesa etching of the epitaxial layer is performed using inductively coupled plasma dry etching (ICP). The etching gas for ICP is a mixture of Cl2 and BCl3 with a gas flow ratio of Cl2:BCl3=100:20 (sccm). The chamber pressure is 4 mtorr, the upper and lower electrode bias voltages are 330W / 180W, the DC bias voltage is 180V, and the etching rate is 35A / s. Mesa etching can also be performed using electron cyclotron resonance plasma etching (ECR) or reactive ion etching (RIE).
[0061] S105. Prepare a sidewall passivation layer to cover the exposed substrate and the first light-emitting unit and the second light-emitting unit, and etch through holes in the sidewall passivation layer to expose the first N-type layer, the first P-type layer, the second N-type layer and the second P-type layer.
[0062] Specifically, a 300nm passivation layer 3 is first deposited and grown on the wafer surface using plasma-enhanced chemical deposition (PECVD). Then, using standard photolithography, windows are created on the surfaces of the first N-type layer 11 and the first P-type layer 13 of the first light-emitting stack 111, and the second N-type layer 21 and the second P-type layer 23 of the second light-emitting stack 112. Finally, BOE etching is used for 50 seconds until the surfaces of the first N-type layer 11 and the first P-type layer 13 of the first light-emitting stack 111, and the second N-type layer 21 and the second P-type layer 23 of the second light-emitting stack 112 at the window locations are exposed. The resulting structure is shown below. Figure 5 As shown.
[0063] S106. A first P electrode and a second P electrode are fabricated on the exposed first P-type layer and second P-type layer, respectively.
[0064] Specifically, a first P-electrode is fabricated on the first P-type layer of the exposed first light-emitting stack, and a second P-electrode is fabricated on the surface of the second P-type layer of the second light-emitting stack. Before fabricating the P-electrodes, a rapid annealing furnace (RTA) is used to anneal the first P-type layer 13 and the second P-type layer 23 at 550°C for 10 minutes in a mixed atmosphere of N2 and O2. This process removes the passivation effect of hydrogen atoms on the magnesium (Mg) acceptor impurities doped in the P-type GaN, thereby releasing holes and achieving P-type conductivity. This step is performed after the etching damage repair of the first P-type layer 13, serving a certain role in repairing the etching damage.
[0065] After annealing and activating p-type GaN, an indium tin oxide (ITO) thin film was magnetron sputtered onto the wafer surface using RF sputtering at a power of 60W and a chamber pressure of 1*10. -4 The evaporation atmosphere was an Ar / O2 mixture. Windows were then created on the surfaces of the first P-electrode 4 and the second P-electrode 5 using standard photolithography. The window areas were etched using ITO etching solution to fabricate the patterns of the first P-electrode 4 and the second P-electrode 5. The resulting structure is shown below. Figure 6 As shown, after the ITO thin film is prepared, it is annealed in a rapid annealing furnace at 550°C in a N2 atmosphere for 3 minutes to make the molecular structure in the film layer more stable, improve its conductivity, and enhance its light transmittance. This process removes missing elements in the film layer and re-matches the crystal lattice, thus eliminating film layer stress.
[0066] S107. A first N-electrode and a second N-electrode are fabricated on the exposed first N-type layer and second N-type layer, respectively; at the same time, a first P-electrode current extension and metal pad layer and a second P-electrode current extension and metal pad layer are fabricated on the first P-electrode and the second P-electrode, respectively.
[0067] Specifically, a first N-electrode is fabricated on the surface of the first N-type layer of the first light-emitting stack, and a second N-electrode is fabricated on the surface of the second N-type layer of the second light-emitting stack. Simultaneously, a first P-electrode current extension and metal pad layer is fabricated on the surface of the first P-type layer of the first light-emitting stack, and a second P-electrode current extension and metal pad layer is fabricated on the surface of the second P-type layer of the second light-emitting stack. To fabricate the N-electrode, P-electrode current extension layer, and metal pad layer, standard photolithography is first used to create electrical connection windows on the surfaces of the first N-type layer 11, the second N-type layer 21, the first P-electrode 4, and the second P-electrode 5. Then, an electron beam evaporation process is used to evaporate a 1.5 μm CrPtAu metal layer onto the wafer surface. Finally, a lift-off process is used to fabricate the first N-electrode 6, the second N-electrode 7, the first P-electrode current extension and metal pad layer 9, and the second P-electrode current extension and metal pad layer 8. The resulting structure is shown below. Figure 9As shown.
[0068] S108. Prepare a surface passivation layer and etch through holes to expose the first N electrode, the second N electrode, the first P electrode current extension and metal pad layer, and the pad of the second P electrode current extension and metal pad layer to prepare a dual-color tunable LED chip.
[0069] Specifically, a 300nm passivation layer is first deposited and grown on the wafer surface using plasma-enhanced chemical deposition (PECVD). Then, windows are created on the surface of the first N electrode 4, the second N electrode 5, the first P electrode current extension and metal pad 9, and the second P electrode current extension and metal pad layer 9 using standard photolithography. Finally, BOE etching is used for 50 seconds until the electrical connection pads at the window locations are exposed. The resulting structure is shown below. Figure 10 As shown, a dual-color tunable same-side LED chip structure was fabricated.
[0070] In summary, the multi-color tunable LED chip in the above embodiments of the present invention achieves different color temperature light outputs by constructing isolated first and second light-emitting units on the epitaxial layer and controlling the magnitude of different LED input currents with independent pads. Secondly, multiple light-emitting layers are arranged in a surrounding configuration to obtain multiple surrounding light-emitting units, thereby shortening the spatial distance between different light colors and fundamentally improving the mixing efficiency of dual-color light. Specifically, chip-level dual-color mixing is achieved by constructing cyan and orange light-emitting units on the epitaxial layer. The orange light-emitting unit is arranged around the cyan light-emitting unit, significantly shortening the spatial distance between the two light colors and fundamentally improving the mixing efficiency of cyan and orange light. By controlling the input current of the cyan and orange LEDs with independent pads, different color temperature light outputs can be achieved. This results in a monolithically integrated multi-color tunable LED chip with a simple fabrication process and uniform light mixing.
[0071] Example 2 The method for fabricating a multi-color tunable LED chip in the second embodiment of the present invention is specifically used to fabricate a four-color tunable LED chip structure on the same side, the method comprising: S201. Obtain a substrate, and grow a buffer layer and multiple light-emitting stacks sequentially on the substrate. The multiple light-emitting stacks include a first light-emitting stack, a second light-emitting stack, a third light-emitting stack, and a fourth light-emitting stack from bottom to top.
[0072] A substrate 1 is provided, on which a growth buffer layer 2, a first N-type layer 11, a first light-emitting layer 12, and a first P-type layer 13 of a first light-emitting stack 111, a second N-type layer 21, a second light-emitting layer 22, and a second P-type layer 23 of a second light-emitting stack 112, a third N-type layer 31, a third light-emitting layer 32, and a third P-type layer 33 of a third light-emitting stack 113, and a fourth N-type layer 41, a fourth light-emitting layer 42, and a fourth P-type layer 43 of a fourth light-emitting stack 114 are sequentially grown.
[0073] In this design, substrate 1 is sapphire, buffer layer 2 is made of AlN, the first N-type layer 11, the second N-type layer 21, the third N-type layer 31, and the fourth N-type layer 41 are all made of N-type GaN, the first P-type layer 13, the second P-type layer 23, the third P-type layer 33, and the fourth P-type layer 43 are all made of P-type GaN, the first light-emitting layer 12 is a blue InGaN / GaN quantum well, the second light-emitting layer 22 is a green InGaN / GaN quantum well, the third light-emitting layer 32 is a yellow InGaN / GaN quantum well, and the fourth light-emitting layer 42 is a red InGaN / GaN quantum well.
[0074] S202. The fourth light-emitting stack, the third light-emitting stack, and the second light-emitting stack are sequentially etched along the middle region to expose the third P-type layer, the second P-type layer, and the first P-type layer.
[0075] Specifically, the fourth light-emitting stack 114 is etched away to expose the third P-type layer 33 of the third light-emitting stack 113; the fourth light-emitting stack 114 and the third light-emitting stack 113 are etched away to expose the second P-type layer 23 of the second light-emitting stack 112; the fourth light-emitting stack 114, the third light-emitting stack 113 and the second light-emitting stack 112 are etched away to expose the first P-type layer 13 of the first light-emitting stack 111.
[0076] Specifically, after creating a window on the surface of the P-type GaN layer using standard photolithography, mesa etching of the epitaxial layer is performed using inductively coupled plasma dry etching (ICP). The etching gas in ICP is a mixture of Cl2 and BCl3 with a flow rate ratio of Cl2:BCl3 = 100:20 (sccm). The chamber pressure is 4 mtorr, the upper and lower electrode bias voltages are 120 W / 90 W, the DC bias voltage is 120 V, and the etching rate is 20 A / s. Electron cyclotron resonance plasma etching (ECR) or reactive ion etching (RIE) can also be used to complete the mesa etching.
[0077] Since etching of the P-type layer in step S202 generates N-type nitrogen vacancy defects on the P-type layer surface, causing etching damage, this leads to a decrease in the electrical properties of the Mg-doped P-type layer. Repair is needed to reduce or eliminate this etching damage and restore the high-quality surface and the material's inherent electrical properties. Specifically, plasma-enhanced chemical vapor deposition (PECVD) is used to oxidize the P-type GaN damaged layer at 220 °C in an N₂O atmosphere for 10 min. After oxidation, hydrochloric acid is used to remove the oxidized P-type GaN damaged layer. Then, metal-organic chemical vapor deposition (MOCVD) is used to regenerate a full layer of P-type GaN on the repaired surface, with a thickness of 100 nm.
[0078] S203. Etch the first light-emitting stack along the surrounding area until a portion of the first N-type layer is etched, etch the second light-emitting stack until a portion of the second N-type layer is etched, etch the third light-emitting stack until a portion of the third N-type layer is etched, and etch the fourth light-emitting stack until a portion of the fourth N-type layer is etched to expose the first N-type layer, the second N-type layer, the third N-type layer, and the fourth N-type layer to form isolated first light-emitting units, second light-emitting units, and second light-emitting units.
[0079] The first light-emitting layer 12, the first P-type layer 13, and part of the first N-type layer 11 of the first light-emitting stack 111, the second light-emitting layer 22, the second P-type layer 23, and part of the second N-type layer 21 of the second light-emitting stack 112, the third light-emitting layer 32, the third P-type layer 33, and part of the third N-type layer 31 of the third light-emitting stack 113, and the fourth light-emitting layer 42, the fourth P-type layer 43, and part of the fourth N-type layer 41 of the fourth light-emitting stack 114 are etched away to expose the N-type layer, thereby forming the first light-emitting unit, the second light-emitting unit, the third light-emitting unit, and the fourth light-emitting unit.
[0080] Specifically, after creating a window on the N-type layer surface using standard photolithography, mesa etching of the epitaxial layer is performed using inductively coupled plasma dry etching (ICP). The etching gas for ICP is a mixture of Cl2 and BCl3 with a gas flow ratio of Cl2:BCl3 = 100:20 (sccm). The chamber pressure is 4 mtorr, the upper and lower electrode bias voltages are 330 W / 180 W, the DC bias voltage is 180 V, and the etching rate is 35 A / s. Mesa etching can also be performed using electron cyclotron resonance plasma etching (ECR) or reactive ion etching (RIE).
[0081] S204, etch the first N-type layer in the trench region until the substrate is exposed.
[0082] The first N-type layer 11 of the first light-emitting stack 111 in the trench region is etched away until the underlying substrate 1 is exposed, thereby achieving complete isolation between chips and forming independent multi-color chip units.
[0083] Specifically, after creating a window on the surface of the first N-type layer using standard photolithography, mesa etching of the epitaxial layer is performed using inductively coupled plasma dry etching (ICP). The etching gas for ICP is a mixture of Cl2 and BCl3 with a gas flow ratio of Cl2:BCl3 = 100:20 (sccm). The chamber pressure is 4 mtorr, the upper and lower electrode bias voltages are 330 W / 180 W, the DC bias voltage is 180 V, and the etching rate is 35 A / s. Mesa etching can also be performed using electron cyclotron resonance plasma etching (ECR) or reactive ion etching (RIE).
[0084] S205. Prepare a sidewall passivation layer to cover the exposed substrate and the first light-emitting unit, the second light-emitting unit, the first light-emitting unit and the second light-emitting unit, and etch through holes in the sidewall passivation layer to expose the first N-type layer, the first P-type layer, the second N-type layer, the second P-type layer, the third N-type layer, the third P-type layer, the fourth N-type layer and the fourth P-type layer.
[0085] As a specific example, a 300 nm passivation layer 3 is first deposited and grown on the wafer surface using plasma-enhanced chemical deposition (PECVD). Then, windows are made on the N-type and P-type layers of the first light-emitting stack 111, the second light-emitting stack 112, the third light-emitting stack 113, and the fourth light-emitting stack 114 using standard photolithography. Finally, BOE etching is used for 50 seconds until the N-type and P-type layers at the window locations are exposed.
[0086] S206. A first P electrode, a second P electrode, a third P electrode, and a fourth P electrode are respectively fabricated on the exposed first P-type layer, second P-type layer, third P-type layer, and fourth P-type layer.
[0087] Before fabricating the P-electrode, a rapid annealing furnace (RTA) is used to anneal the P-type layer at 550°C for 10 minutes under a mixed N2 and O2 atmosphere. This process removes the passivation effect of hydrogen atoms on the magnesium (Mg) acceptor impurities in the P-type GaN, thereby releasing holes and achieving P-type conductivity. This step is performed after the P-type layer has undergone etching damage repair, thus playing a role in repairing the etching damage.
[0088] After annealing and activating p-type GaN, an indium tin oxide (ITO) thin film was magnetron sputtered onto the wafer surface using RF sputtering at a power of 60W and a chamber pressure of 1*10. -4The evaporation atmosphere was an Ar / O2 mixture. A window was then created on the surface of the P-electrode using standard photolithography. The window area was etched using ITO etching solution to fabricate the P-electrode. After the ITO thin film was prepared, it was annealed in a rapid annealing furnace at 550°C in a N2 atmosphere for 3 minutes to stabilize the molecular structure, improve conductivity, and enhance light transmittance. Defective elements in the film were removed, and the crystal lattice was rematched to eliminate film stress.
[0089] S207. A first N-electrode, a second N-electrode, a third N-electrode, and a fourth N-electrode are respectively fabricated on the exposed first N-type layer, second N-type layer, third N-type layer, and fourth N-type layer; simultaneously, a first P-electrode current extension and metal pad layer, a second P-electrode current extension and metal pad layer, a third P-electrode current extension and metal pad layer, and a fourth P-electrode current extension and metal pad layer are respectively fabricated on the first P-electrode, second P-electrode, third P-electrode, and fourth P-electrode.
[0090] To fabricate the N-type electrode, P-type electrode current spreading layer, and metal pad layer, firstly, standard photolithography is used to create electrical connection windows on the surface of the N-type layer and P-type electrode. Then, an electron beam evaporation process is used to evaporate a 1.5 μm CrPtAu metal layer on the wafer surface. Finally, the N-type electrode and P-type electrode current spreading layer and metal pad layer are fabricated using a lift-off process.
[0091] S208. Prepare a surface passivation layer and etch through holes to expose the pads of the first N electrode, the second N electrode, the third N electrode and the fourth N electrode, the first P electrode current extension and metal pad layer, the second P electrode current extension and metal pad layer, the third P electrode current extension and metal pad layer and the fourth P electrode current extension and metal pad layer to prepare a four-color adjustable LED chip.
[0092] Specifically, a 300nm passivation layer is first deposited and grown on the wafer surface using plasma-enhanced chemical deposition (PECVD). Then, windows are made on the surface of the N-electrode and P-electrode current extension and metal pads using standard photolithography. Finally, BOE etching is used for 50 seconds until the electrical connection pads at the window positions are exposed, thus completing the fabrication of a four-color adjustable same-side LED chip structure.
[0093] In summary, the multi-color tunable LED chip in the above embodiments of the present invention achieves different color temperature light outputs by constructing isolated first and second light-emitting units on the epitaxial layer and controlling the magnitude of different LED input currents with independent pads. Secondly, multiple light-emitting layers are arranged in a surrounding configuration to obtain multiple surrounding light-emitting units, thereby shortening the spatial distance between different light colors and fundamentally improving the mixing efficiency of dual-color light. Specifically, chip-level dual-color mixing is achieved by constructing cyan and orange light-emitting units on the epitaxial layer. The orange light-emitting unit is arranged around the cyan light-emitting unit, significantly shortening the spatial distance between the two light colors and fundamentally improving the mixing efficiency of cyan and orange light. By controlling the input current of the cyan and orange LEDs with independent pads, different color temperature light outputs can be achieved. This results in a monolithically integrated multi-color tunable LED chip with a simple fabrication process and uniform light mixing.
[0094] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0095] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.
Claims
1. A method for fabricating a multi-color tunable LED chip, characterized in that, include: A substrate is obtained, and a buffer layer and a plurality of light-emitting stacks are sequentially grown on the substrate. The plurality of light-emitting stacks include a first light-emitting stack and a second light-emitting stack from bottom to top. The first light-emitting stack includes a first N-type layer, a first light-emitting layer and a first P-type layer. The second light-emitting stack includes a second N-type layer, a second light-emitting layer, and a second P-type layer; The middle region of the second light-emitting stack is etched to expose the first P-type layer to obtain a window. Then, the first light-emitting stack is etched along the surrounding area until a portion of the first N-type layer is etched, and the second light-emitting stack is etched until a portion of the second N-type layer is etched to expose the first N-type layer and the second N-type layer to form an isolated first light-emitting unit and a second light-emitting unit. The first N-type layer in the etched trench region is etched until the substrate is exposed; A sidewall passivation layer is prepared to cover the exposed substrate, the first light-emitting unit, and the second light-emitting unit. Through holes are etched into the sidewall passivation layer to expose the first N-type layer, the first P-type layer, the second N-type layer, and the second P-type layer. A first P-electrode and a second P-electrode are fabricated on the exposed first P-type layer and second P-type layer, respectively; A first N-electrode and a second N-electrode are fabricated on the exposed first N-type layer and second N-type layer, respectively; and a first P-electrode current extension and metal pad layer and a second P-electrode current extension and metal pad layer are fabricated on the first P-electrode and the second P-electrode, respectively. A surface passivation layer is prepared and vias are etched to expose the first N electrode, the second N electrode, the first P electrode current extension and metal pad layer, and the pads of the second P electrode current extension and metal pad layer to prepare a multi-color tunable LED chip.
2. The method for fabricating a multi-color tunable LED chip according to claim 1, characterized in that, In the step of etching the middle region of the second light-emitting stack to expose the first P-type layer to obtain a window, the method further includes: Etching damage repair is performed on the first P-type layer in the first light-emitting stack; The repair methods include: The first P-type layer in the first light-emitting stack is etched using a low-power etching process, wherein a damage layer is generated on the surface of the first P-type layer after etching. The damaged layer was repaired by high-temperature gas annealing and removed by wet etching. Then, a P-type layer is regrown on the surface after the damaged layer is removed to replace the damaged layer and repair the original first P-type layer.
3. The method for fabricating a multi-color tunable LED chip according to claim 1, characterized in that, The steps of fabricating the first P-electrode and the second P-electrode on the exposed first P-type layer and the second P-type layer, respectively, include: The first P-type layer and the second P-type layer are activated by high-temperature annealing at 500℃-900℃ in an N2 or O2 atmosphere. The first P-electrode and the second P-electrode are simultaneously fabricated by electron beam evaporation or magnetron sputtering of the first P-type layer and the second P-type layer after activation. The first P electrode and the second P electrode are annealed in an N2 or O2 atmosphere at a temperature of 200℃-600℃. Then, windows are made on the surface of the first P electrode and the second P electrode using a standard photolithography process. The first P electrode and the second P electrode are then prepared by wet etching.
4. The method for fabricating a multi-color tunable LED chip according to claim 1, characterized in that, The steps of fabricating a first N-electrode and a second N-electrode on the exposed first N-type layer and second N-type layer, respectively; and simultaneously fabricating a first P-electrode current spread and metal pad layer and a second P-electrode current spread and metal pad layer on the first P-electrode and second P-electrode, respectively, include: The first N electrode, the second N electrode, the current extension and metal pad layer of the first P electrode, and the current extension and metal pad layer of the second P electrode are all independently controlled so that the first light-emitting unit and the second light-emitting unit can be independently controlled.
5. The method for fabricating a multi-color tunable LED chip according to claim 1, characterized in that, The steps of fabricating a first N-electrode and a second N-electrode on the exposed first N-type layer and second N-type layer, respectively; and simultaneously fabricating a first P-electrode current spread and metal pad layer and a second P-electrode current spread and metal pad layer on the first P-electrode and second P-electrode, respectively, include: The first P-electrode current extension and metal pad layer are interconnected with the second P-electrode current extension and metal pad layer to construct a common P-electrode pad. The first N electrode and the second N electrode are controlled independently so that the first light-emitting unit and the second light-emitting unit can be controlled independently. or: The first N electrode and the second N electrode are interconnected to form a common N electrode pad; The first P-electrode current extension and metal pad layer are independently controlled with the second P-electrode current extension and metal pad layer so that the first light-emitting unit and the second light-emitting unit can be independently controlled.
6. The method for fabricating a multi-color tunable LED chip according to claim 1, characterized in that, In the steps of etching the first light-emitting stack along the surrounding area until a portion of the first N-type layer is etched, and etching the second light-emitting stack until a portion of the second N-type layer is etched to expose the first N-type layer and the second N-type layer to form isolated first light-emitting units and second light-emitting units: The thickness difference between the first light-emitting layer, the first P-type layer, the second light-emitting layer, and the second P-type layer is not greater than a preset difference, so that the first N-type layer and the second N-type layer can be exposed simultaneously in one etching.
7. The method for fabricating a multi-color tunable LED chip according to claim 1, characterized in that, In the steps of etching the first light-emitting stack along the surrounding area until a portion of the first N-type layer is etched, and etching the second light-emitting stack until a portion of the second N-type layer is etched to expose the first N-type layer and the second N-type layer to form isolated first light-emitting units and second light-emitting units: When the thickness difference between the first light-emitting layer, the first P-type layer, the second light-emitting layer, and the second P-type layer is greater than a preset difference, the method includes: First, etch along the surrounding area down to the first light-emitting stack until part of the first N-type layer is etched; Then etch along the surrounding area to the second light-emitting stack until part of the second N-type layer is etched.
8. The method for fabricating a multi-color tunable LED chip according to claim 1, characterized in that, The plurality of light-emitting stacks, from bottom to top, include a first light-emitting stack, a second light-emitting stack, a third light-emitting stack, and a fourth light-emitting stack, to construct a first light-emitting unit, a second light-emitting unit, a third light-emitting unit, and a fourth light-emitting unit based on the first light-emitting stack, the second light-emitting stack, the third light-emitting stack, and the fourth light-emitting stack, wherein: The second, third, and fourth light-emitting units are arranged in sequence around the first light-emitting unit with the first light-emitting unit as the central region, and the peak wavelength gradually increases from the first light-emitting unit to the fourth light-emitting unit.
9. A multi-color adjustable LED chip, characterized in that, The multi-color tunable LED chip is prepared using the method described in any one of claims 1-8.