Via hole filling method

Abstract

A method of processing a substrate includes exposing the substrate to a boron-containing precursor to be adsorbed on the substrate, where the substrate includes a dielectric layer formed on a conductive layer, and the conductive layer is exposed at a bottom of a recess formed in the dielectric layer. The method includes: exposing the adsorbed boron-containing precursor to a plasma; and filling the recess with a conductive filler material from bottom to top by a vapor deposition process, wherein a vertical deposition rate of the conductive filler material is greater than a lateral deposition rate of the conductive filler material.

Description

[0001] Cross-reference of relevant patents and applications

[0002] This application claims priority and benefit to U.S. non-provisional patent application No. 18 / 471,823, filed on September 21, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention generally relates to methods of processing substrates, and in certain embodiments, to via filling. Background Technology

[0004] Semiconductor devices, such as integrated circuits (ICs), are typically fabricated by sequentially depositing and patterning dielectric, conductive, and semiconductor material layers on a substrate to form a network of electronic components and interconnects (e.g., transistors, resistors, capacitors, metal wires, contacts, and vias) integrated into a monolithic structure. The process flow for forming the constituent structures of semiconductor devices typically involves depositing and removing various materials while simultaneously exposing patterns of several materials on the surface of the working substrate.

[0005] The minimum size of features in patterned layers shrinks periodically to roughly double the part density at each successive technology node, thereby reducing the cost per unit function. Patterning innovations, such as immersion deep ultraviolet (i-DUV) lithography, multiple patterning, and extreme ultraviolet (EUV) optics at a wavelength of 13.5 nm, have reduced some critical dimensions to close to ten nanometers. As miniaturization continues, new problems arise with copper (Cu) wiring. Specifically, the wiring width used in devices becomes even smaller than the mean free path of electrons in Cu material, leading to increased resistance due to scattering. Therefore, at increasingly smaller scales, new wiring materials and their fabrication techniques for metal interconnects with superior material properties are likely to be desired. Summary of the Invention

[0006] A method of processing a substrate includes: exposing the substrate to a boron-containing precursor to be adsorbed onto the substrate, wherein the substrate includes a dielectric layer formed on a conductive layer, and the conductive layer is exposed at the bottom of a recess formed in the dielectric layer. The method includes: exposing the adsorbed boron-containing precursor to a plasma; and filling the recess from bottom to top with a conductive filler material using a vapor deposition process, wherein the vertical deposition rate of the conductive filler material is greater than the lateral deposition rate of the conductive filler material.

[0007] A method of processing a substrate includes: exposing the substrate to BCl3 to be adsorbed on a surface of the substrate, wherein the surface includes a dielectric layer and a conductive layer. The method further includes: exposing the adsorbed BCl3 to a plasma comprising argon and hydrogen, wherein the exposure to the plasma binds boron to the dielectric layer. The method also includes: depositing a metal on the surface, wherein the deposition rate of the metal on the conductive layer is greater than the deposition rate on the dielectric layer.

[0008] A method for forming a metal interconnect for a semiconductor device includes exposing a substrate including a via to a boron-containing precursor to be adsorbed onto the sidewalls of the via, wherein the via has a critical dimension of 20 nm or less, and a conductive material is exposed at the bottom of the via. The method includes exposing the substrate to a plasma to induce boron doping of these sidewalls; and filling the via with ruthenium (Ru) via a vapor deposition process, wherein the Ru is preferentially deposited from the bottom of the via rather than from the sidewalls. Attached Figure Description

[0009] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0010] Figures 1A to 1F Cross-sectional views of an example substrate according to various embodiments are shown at various stages during an example semiconductor manufacturing process including via filling, wherein, Figure 1A This demonstrates an incoming substrate with recesses in the dielectric layer. Figure 1B The substrate after the boron exposure step is shown. Figure 1C The substrate after the plasma exposure step is shown. Figure 1D The substrate is shown during the metal deposition step. Figure 1E The substrate after the metal deposition step is shown, and Figure 1F The substrate after etch-back and planarization is shown;

[0011] Figure 2 Cross-sectional scanning electron microscope (SEM) images of an example substrate after ruthenium (Ru) deposition in the presence of a boron exposure step are shown.

[0012] Figure 3 Cross-sectional scanning electron microscope (SEM) images of an example substrate after ruthenium (Ru) deposition without a boron exposure step are shown.

[0013] Figure 4 The image shows a cross-sectional transmission electron microscope (TEM) image of an example substrate after ruthenium (Ru) deposition in the presence of a boron exposure step;

[0014] Figures 5A to 5DAnother example substrate according to other embodiments is shown before via filling during the process flow for forming fully self-aligned vias (FSAVs). Figures 5A to 5B ) and afterwards ( Figures 5C to 5D A cross-sectional view of ), wherein, Figure 5A This shows the pre-fill cross-section perpendicular to the underlying conductive lines. Figure 5B This shows the pre-fill cross-section parallel to the underlying conductive lines. Figure 5C The filled cross-section perpendicular to the underlying conductive lines is shown, and Figure 5D The cross-section after filling is shown, parallel to the underlying conductive lines;

[0015] Figures 6A to 6D Shown in Figures 5A to 5D A cross-sectional view of the corresponding plan view of the top surface of the substrate; and

[0016] Figures 7A to 7C A process flow diagram of a via filling method according to various embodiments is shown, wherein... Figure 7A The process flow of the embodiment is shown. Figure 7B The process flow of alternative embodiments is shown, and Figure 7C Another alternative embodiment of the process flow is shown. Detailed Implementation

[0017] This application relates to methods for processing substrates, and more specifically to via filling. The techniques described herein can be applied to and are applicable to the fabrication of metal interconnects in semiconductor devices at small scales. As device feature sizes continue to shrink, minimizing resistance has become a significant challenge, especially for close metal pitches. For example, the RC delay of interconnects between conventional copper (Cu) lines and tungsten (W) contacts can limit the speed of digital circuits. New materials are being introduced at nodes of 10 nm and below to replace dense Cu lines and W contacts. Ruthenium (Ru) metal is a leading candidate to replace copper and tungsten in these and other applications. However, uniformly filling recesses with close pitch (e.g., < 20 nm) with Ru without creating voids remains a significant challenge. In most non-selective deposition methods, metal deposition on the sidewalls can be dominant. Because the sidewalls account for a large portion of the exposed surface in small vias with high aspect ratios (HAR), non-selective deposition can create voids and cause pinch-off problems. Therefore, selective bottom-up vapor deposition techniques for Ru via filling are desired.

[0018] Embodiments of this application disclose a method for via filling with a conductive material (e.g., Ru) in the presence of selective sidewall passivation. In various embodiments, the via filling method can advantageously slow down the deposition rate on the sidewalls in the recess to achieve bottom-up deposition. The inventors of this application have developed a method for selective sidewall passivation that can be applied prior to metal deposition to modify the surface of a substrate. In various embodiments, selective sidewall passivation may include a boron exposure step of adsorbing a boron-containing precursor (e.g., BCl3) and a plasma exposure step (e.g., Ar / H2 plasma) of removing boron only from the bottom surface and not from the sidewalls. The via filling method can be applied to fully self-aligned via (FSAV) formation, wherein the bottom of the via can be a conductive surface (e.g., TiN) and the sidewalls of the via can be a dielectric material (e.g., silicon oxide). During selective sidewall passivation, plasma exposure can induce boron doping of the dielectric material, which can then suppress metal deposition from the sidewalls. Therefore, various embodiments of the methods described herein enable the metal filling of vias or other recesses with close spacing dimensions (e.g., < 20 nm) without gaps or pinch-offs.

[0019] In the following text, Figures 1A to 1F The steps of a process for via filling in the presence of selective sidewall passivation, according to various embodiments, are illustrated. Figures 2 to 4 The image shows example SEM and TEM images filled with Ru. Then refer to... Figures 5A to 5D and Figures 6A to 6D Describe the application of this method in the formation of fully self-aligned vias (FSAVs). References Figures 7A to 7C This disclosure describes several embodiments of the process flow for via filling. All figures in this disclosure, including aspect ratios of features, are not drawn to scale and are for illustrative purposes only. While the various embodiments in this disclosure primarily describe the metallic filling of vias in the presence of sidewall passivation, the deposition method can be applied to filling any recessed features (e.g., lines and trenches) or any surface that may not have sidewalls, provided that a portion of the surface can be selectively passivated via the methods described herein. Any list of possible compositions, conditions, or process variations presented in this disclosure includes any reasonable combination thereof, and therefore the term "or" used in the list does not indicate any exclusive choice of a particular composition, condition, or process variation.

[0020] Figures 1A to 1F Cross-sectional views of example substrates according to various embodiments are shown at various stages during example semiconductor manufacturing processes, including via filling.

[0021] exist Figure 1AIn this process, substrate 100 may be part of or include a semiconductor device, and may undergo multiple processing steps, such as conventional processing. Therefore, substrate 100 may include semiconductor layers useful in various microelectronic devices. For example, a semiconductor structure may include substrate 100 in which various device regions are formed.

[0022] In one or more embodiments, substrate 100 may be a silicon wafer or a silicon-on-insulator (SOI) wafer. In some embodiments, substrate 100 may include a silicon-germanium wafer, a silicon carbide wafer, a gallium arsenide wafer, a gallium nitride wafer, and other compound semiconductors. In other embodiments, substrate 100 includes a heterolayer, such as silicon-germanium on silicon, gallium nitride on silicon, silicon-carbon on silicon, and a silicon-on-silicon or SOI substrate layer. In various embodiments, substrate 100 is patterned or embedded in other components of a semiconductor device.

[0023] like Figure 1A As shown, substrate 100 may further include a conductive layer (referred to as conductive layer 110) and a dielectric layer 120, wherein recess 125 may be formed in dielectric layer 120. Figure 1A As shown, the conductive layer 110 can be exposed at the bottom of the recess 125. Figure 1A Only a simplified example of substrate 100 is shown. In various embodiments, substrate 100 may include a portion of a metal interconnect (e.g., a conductive line) of a semiconductor device beneath conductive layer 110. Recess 125 may be a via, line recess, trench, or any other recess feature, and may be filled from bottom to top with a conductive filler (e.g., Ru) in the presence of sidewall passivation.

[0024] In various embodiments, the conductive layer 110 may be a barrier layer, adhesive layer, or other padding layer to improve the deposition of the conductive filler. In some embodiments, the conductive layer 110 may include titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, cobalt, or combinations thereof. In some embodiments, the thickness of the conductive layer 110 may range from 0.1 nm to 10 nm. The conductive layer 110 may be formed by, for example, ALD, CVD, or ionized physical vapor deposition (iPVD).

[0025] In another embodiment, the conductive layer 110 may be the top surface of the conductive line and comprises aluminum (Al), copper (Cu), molybdenum (Mo), ruthenium (Ru), tungsten (W), or osmium (Os). In various embodiments, the dielectric layer 120 may be an interlayer dielectric (ILD) formed for via formation and may comprise silicon oxide or a low-k dielectric, such as fluorosilicate glass (FSG) or carbon-doped silicon oxide (CDO). In various embodiments, the recess 125 may have a critical dimension (CD) of less than 50 nm and, in some embodiments, less than 20 nm. In one or more embodiments, the recess 125 may have an aspect ratio (AR) between 5:1 and 100:1.

[0026] The small CD and high aspect ratio (HAR) of the recess make it difficult to fill with metal without any voids, as metal deposition can occur on the sidewalls, which occupy most of the surface area within the recess. Therefore, preferred bottom-up deposition is often desirable to overcome the problems of pinch-offs and void formation. For this purpose, selective sidewall passivation can be performed in various embodiments as described below. Figures 1B to 1C ), so as to suppress deposition on the sidewalls during the filling process ( Figures 1D to 1E ).

[0027] Figure 1B A cross-sectional view of substrate 100 is shown after the boron exposure step.

[0028] In various embodiments, the first step of selective sidewall passivation can be a boron exposure step involving the adsorption of a boron-containing precursor. The boron exposure step may include exposing a substrate 100, wherein a boron-containing surface layer 130 may be formed. Figure 1B As shown, the boron-containing surface layer 130 can be conformally formed and cover the sidewalls within the recess 125. In some embodiments, the boron-containing surface layer 130 can be non-selectively formed and cover the surfaces of both the conductive layer 110 (i.e., the top surface and sidewalls) and the dielectric layer 120 (i.e., the bottom surface within the recess 125). While not wishing to be limited by any theory, the boron-containing surface layer 130 can be a layer of adsorbed material of a boron-containing precursor. Thus, in some embodiments, the boron-containing surface layer 130 can have a thickness of only a single layer or several atomic layers, or in one embodiment, the surface may not be completely covered by the boron-containing surface layer 130. In various embodiments, the boron-containing precursor can include boranes (B2H6), boron halides (e.g., BF3, BCl3, and BBr3), or other boron compounds. In one embodiment, the boron-containing precursor can include BCl3. In some embodiments, the boron-containing precursor can flow into the processing chamber for the process as a blend including other gases (such as rare gases or dinitrogen (N2)).

[0029] In various embodiments, the boron exposure step can be a non-plasma process performed in the absence of plasma. The absence of plasma can help ensure the isotropy of the process and the interaction between the boron-containing precursor and the sidewalls. In some embodiments, the boron exposure step can be performed at a pressure of about 0.5 Torr to about 10 Torr and a temperature of about 10°C to about 250°C. In one or more embodiments, the temperature can be between 200°C and 250°C, and in another embodiment, the temperature can be maintained below 300°C to be within the typical thermal budget for downstream processes (BEOL).

[0030] Figure 1C A cross-sectional view of the substrate is shown after the plasma exposure step.

[0031] Following the boron exposure step, a plasma exposure step can be performed to remove the boron-containing surface layer 130 only from the bottom surface, without removing it from the sidewalls. Additionally, the boron-containing surface layer 130 can be converted into a passivation layer 135 on the surface of the dielectric layer 120. Because the plasma can be oriented and anisotropic to selectively remove the boron-containing surface layer 130 only from the bottom surface (i.e., the conductive layer 110), the passivation layer 135 can exist only on the top surface and sidewalls of the dielectric layer 120, as... Figure 1C As shown.

[0032] In some embodiments, the passivation layer 135 may be formed as a boron-doped dielectric layer on the exposed portion of the dielectric layer 120. Therefore, there may not be a distinct interface between the passivation layer 135 and the underlying dielectric layer 120. In other words, this series of boron exposure steps and plasma exposure steps can be performed as a selective boron doping process to modify the surface of the dielectric layer 120 relative to the conductive layer 110.

[0033] In various embodiments, the plasma used for the plasma exposure step may include, for example, hydrogen produced from dihydrogen (H2). Further, in some embodiments, the plasma may include a rare gas, such as argon (Ar). In one embodiment, an Ar / H2 plasma with an Ar:H2 ratio of 80:20 may be used. Typically, hydrogen plasma treatment can be applied at various stages during semiconductor manufacturing, for example as a cleaning step to remove surface oxides or chlorine (Cl) contaminants from metal surfaces. In various embodiments, a plasma exposure step for selective sidewall passivation can be advantageously integrated with such a cleaning step and thus incorporated into the process flow without substantial additional process costs. In various embodiments, for plasma conditions, the source power may be between 50 W and 1000 W, and the bias power may be between 0 W and 500 W. The total gas flow rate may be between 20 sccm and 2000 sccm. The process pressure may be between 5 mTorr and 5000 mTorr. In one embodiment, the temperature may be between about 10°C and about 250°C, and in another embodiment, the temperature may be between 200°C and 250°C. In some embodiments, the plasma exposure step can be performed at zero to very low bias power, such that the effects of the plasma treatment are achieved on the sidewalls and are not substantial at the bottom surface. When the bias power is too high, the boron material can chemically interact with the surface of the conductive layer 110 at the bottom, rather than being removed from the surface.

[0034] Figure 1D A cross-sectional view of the substrate is shown during the metal deposition step.

[0035] Following selective sidewall passivation to form passivation layer 135, a metal deposition step can be performed. In various embodiments, this deposition step may not be limited to pure metal and may use any alloy or conductive material. A conductive filler (referred to herein as conductive filler 140) can be deposited using a vapor deposition process to fill recess 125. Figure 1D An intermediate stage is shown, in which only a portion of the recess 125 is filled with conductive filler 140. In various embodiments, due to the passivation layer 135, the deposition process is performed from bottom to top, wherein the vertical deposition rate of the conductive filler 140 (starting from the bottom) is greater than the lateral deposition rate of the conductive filler 140 (on the sidewalls). This bottom-up deposition can advantageously achieve void-free filling of the recess 125.

[0036] In various embodiments, the conductive filler 140 may include ruthenium (Ru). In some embodiments, chemical vapor deposition (CVD) may be used. For example, the Ru precursor ruthenium carbonyl (Ru3(CO)). 12 (Ru3(CO)) can flow into the deposition chamber containing the substrate 100, where (Ru3(CO))12 Ru can thermally decompose on the surface, and a high-purity Ru film can be formed within the recess 125. In one or more embodiments, the process conditions for Ru deposition can be as follows: the pressure in the deposition chamber is in the range of 0.1 mTorr to 1 Torr, preferably in the range of 10 mTorr to 500 mTorr, and the substrate temperature is in the range of 120°C to 300°C, preferably in the range of 130°C to 250°C.

[0037] In other embodiments, Ru deposition can be performed using Ru pentadienyl compounds, such as (cyclopentadienyl)(2,4-dimethylpentadienyl)ruthenium, bis(cyclopentadienyl)(2,4-methylpentadienyl)ruthenium, (2,4-dimethylpentadienyl)(ethylcyclopentadienyl)ruthenium, or bis(2,4-methylpentadienyl)(ethylcyclopentadienyl)ruthenium. When using these precursors, in addition to the Ru precursor, CVD can also use a reducing gas.

[0038] In alternative embodiments, the conductive filler 140 may include aluminum (Al), copper (Cu), cobalt (Co), tungsten (W), osmium (Os), or molybdenum (Mo). In one or more embodiments, more than one material may be used to fill the recess 125. For example, a seed layer suitable for metal deposition may first be selectively deposited on the substrate 100, followed by a second deposition for the main conductive filler.

[0039] Figure 1E This shows a cross-sectional view of the substrate after the metal deposition step is completed.

[0040] After the metal deposition step is completed, recess 125 ( Figures 1A to 1D It can be completely filled with conductive filler 140 without any gaps. For example... Figure 1E As shown, excess conductive filler 140 can be deposited on substrate 100, thereby covering the entire surface including the top surface of dielectric layer 120.

[0041] In some embodiments, an optional annealing process may be performed after the metal deposition step to reduce the resistance of the conductive filler 140 by increasing the grain diameter of the crystals (e.g., Ru in the conductive filler 140) and also to remove impurities such as carbon or oxygen from the conductive filler 140. The optional annealing process may be performed using a gas containing H2 gas (e.g., a forming gas (H2+Ar or H2+N2)).

[0042] Figure 1F A cross-sectional view of the substrate after etch-back and planarization is shown.

[0043] In various embodiments, excess conductive filler 140 can be removed, and the surface can be planarized, for example, by a chemical mechanical planarization (CMP) process. Therefore, as... Figure 1F As shown, the top surface of dielectric layer 120 may be without conductive filler 140.

[0044] In some embodiments, the above references may be modified. Figures 1A to 1F The described process flow aims to further improve process efficiency and sidewall passivation. In one embodiment, two plasma exposure steps may be performed for selective sidewall passivation: a first plasma exposure step (e.g., H2 / Ar plasma) prior to the boron exposure step and a second plasma exposure step (e.g., H2 / Ar plasma) following the boron exposure step. This embodiment with three steps can advantageously help to further remove impurities and surface oxides before boron treatment.

[0045] The inventors of this application demonstrated, through experimental research on the effect of boron treatment on metal deposition on different surfaces, the preferential interaction of boron with dielectric surfaces relative to conductive surfaces. To examine the selectivity suitable for forming metal interconnects in semiconductor devices, silicon oxide (SiO2) and titanium nitride (TiN) were investigated. TiN is a conductive material that can be used as a binder layer for metal deposition, such as Ru deposition. First, two surfaces (SiO2 and TiN) were treated with BCl3 and H2 / Ar plasmas, and their surface composition after each treatment was characterized using X-ray photoelectron spectroscopy (XPS). XPS analysis revealed that on SiO2, some boron material may still be present even after plasma treatment. On the other hand, on TiN, the XPS peak indicating boron assignment was significant after BCl3 exposure, but it disappeared after plasma treatment. The results indicate that plasma treatment can induce a difference in boron concentration between the two surfaces. Chlorine (Cl) material was detected from both surfaces even after plasma treatment. Next, Ru was used as an example to examine the metal deposition rate on these treated surfaces. In the presence of a certain level of Cl, BCl3 exposure followed by plasma treatment only slowed the Ru deposition rate on SiO2, while no substantial difference was found on TiN. A similar trend of reduced deposition rates after BCl3 exposure followed by plasma treatment was also confirmed for low-k dielectric surfaces. Therefore, it has been demonstrated that boron treatment followed by plasma treatment can induce preferential boron treatment (i.e., selective binding of boron on the dielectric surface), which can then lead to suppression of metal deposition on the treated dielectric surface without substantially affecting metal deposition on the conductive surface. Since sidewalls in various via-filling applications can comprise dielectric materials, suppression of metal deposition on treated dielectric surfaces can advantageously be applied to sidewall passivation and facilitate bottom-up metal deposition. This is particularly desirable at small scales with high aspect ratio (HAR) characteristics, where void formation and pinch-off within recesses (e.g., vias) with closely spaced dimensions present significant challenges. It was also found that introducing Cl into the surface also had some effect on inhibiting the deposition rate, but this effect was not significantly selective among the surfaces examined (i.e., low-k dielectrics, silicon oxide, and TiN), thus indicating the importance of boron during the pretreatment process for deposition.

[0046] Figure 2 Cross-sectional scanning electron microscope (SEM) images of an example substrate after ruthenium (Ru) deposition in the presence of a boron exposure step are shown.

[0047] Figure 3 Cross-sectional scanning electron microscope (SEM) images of an example substrate after ruthenium (Ru) deposition without a boron exposure step are shown.

[0048] Figure 4 The image shows a cross-sectional transmission electron microscope (TEM) image of an example substrate after ruthenium (Ru) deposition in the presence of a boron exposure step.

[0049] Cross-sectional SEM was used to further examine the effect of the boron exposure step on Ru deposition. Model Ru deposition experiments were performed on a substrate comprising a TiN layer and a silicon oxide layer, with a series of recesses having sidewalls of the oxide layer and a bottom surface of the TiN layer. Two pretreatment conditions were investigated: BCl3 exposure followed by Ar / H2 plasma exposure. Figure 2 ) and Ar / H2 plasma exposure only ( Figure 3 Cross-sectional SEM images were taken after Ru deposition to assess the quality of Ru filling in the recesses. On substrates with BCl3 exposure, all recesses were successfully filled with Ru without any significant voids. Figure 2 On the other hand, on substrates without BCl3 exposure (treated with Ar / H2 plasma only), Ru filling is not perfect and results in some voids, such as... Figure 3 The dashed circles in the diagram illustrate this. The results indicate that plasma processing alone may not be able to suppress sidewall deposition, and a boron exposure step is necessary to successfully passivate the surface of the dielectric layer (e.g., silicon oxide). Figure 4 As shown, transmission electron microscopy (TEM) further confirmed that there were no voids in the substrate when exposed to BCl3.

[0050] Figures 5A to 5B This illustration shows a cross-sectional view of another example substrate 200 according to other embodiments, prior to via filling during a process flow for forming self-aligned features, wherein... Figure 5A The cross-section perpendicular to the underlying conductive line 220 is shown, and Figure 5B The cross-section is shown parallel to the bottom conductive line 220.

[0051] Figures 6A to 6B Shown in Figures 5A to 5B The corresponding plan view of the top surface of substrate 200 is shown in the cross-sectional view.

[0052] The following describes, according to certain embodiments, the application of a method for via filling in fully self-aligned vias (FSAVs) in the presence of selective sidewall passivation. The details of the boron exposure and plasma exposure steps are the same as those described above and will therefore not be repeated. For brevity, the substrate structure after via and trench formation is shown.

[0053] exist Figures 5A to 5BIn this embodiment, substrate 200 may include conductive lines 220 embedded in a first dielectric layer 210, the first dielectric layer having a top dielectric surface substantially coplanar with the conductive surfaces of the conductive lines 220. The conductive lines 220 may include a metal, such as copper (Cu) or ruthenium (Ru). In some embodiments, conductive pads 302 may be formed on the conductive surfaces of the conductive lines 220. The conductive pads 320 may be used to bond a next conductive layer and prevent metal diffusion into the first dielectric layer 210, and may include, for example, titanium, titanium nitride, tantalum, tantalum nitride, or combinations thereof. The first dielectric layer 210 may include a low-k dielectric formed on substrate 200, such as fluorosilicate glass (FSG) or carbon-doped silicon oxide (CDO).

[0054] Still referencing Figures 5A to 5B A generally conformal first etch-stop layer (ESL) 312 can be formed after selective dielectric on-displacement (DoD) deposition on the second dielectric layer 310. An upper interconnect layer can be formed by forming conductive elements embedded in an interlayer dielectric (ILD) layer formed on the first ESL 312. In various embodiments, the ILD layer comprises a plurality of dielectric layers formed sequentially. A first ILD layer 510 can be formed on the first ESL 312, a second etch-stop layer (ESL) 512 can be formed on the first ILD layer 510, and a second ILD layer 514 can be formed on the second ESL 512. The first ILD layer 510 and the second ILD layer 514 may include a low-k dielectric, such as FSG or CDO. Trench formation may have been performed to form a trench 515 in the second ILD layer 514 down to the level of the second ESL 512.

[0055] Typically, the conductive lines in an interconnect layer are oriented as parallel lines perpendicular to the parallel conductive lines of vertically adjacent interconnect layers. Therefore, in Figures 6A to 6B The second ESL512 exposed at the bottom of trench 515, as shown in the plan view, is depicted as a conductive line 220 perpendicular to the lower interconnect layer; however, it should be understood that different orientations may also be used. Furthermore, because... Figure 5A The cross-section is shown parallel to and above trench 515, so the remaining portion of the second ILD layer 514 is... Figure 5A It is not visible in the middle.

[0056] Furthermore, via 523 can be formed in the ILD as follows: first, through-hole etching is performed to extend via 523 downwards to the first ESL 312; then, via-land etching is performed to further etch and remove the exposed area of ​​the first ESL 312; and via 523 is extended to expose the top conductive surface (e.g., the surface of the conductive pad 302), as shown below. Figures 5A to 5B As shown.

[0057] Figures 5C to 5D A cross-sectional view of a fully self-aligned via (FSAV) according to other embodiments is shown after the via is filled, wherein, Figure 5C The cross-section perpendicular to the underlying conductive lines is shown, and Figure 5D The cross-section is shown parallel to the underlying conductive lines.

[0058] Figures 6C to 6D Shown in Figures 5C to 5D The corresponding plan view of the top surface of the substrate shown in the cross-sectional view.

[0059] A method for via filling in the presence of selective sidewall passivation can be applied to deposit conductive filler 610 (e.g., Ru) to fill the via. Figures 5A to 5B Both vias 523 and trenches 515 are shown. The boron exposure step and subsequent plasma step advantageously passivate the sidewalls comprising the first ILD layer 510 and the second ILD layer 514, thereby enabling bottom-up deposition of the conductive filler 610. Advantageously, deposition on the sidewalls can be minimized or completely eliminated, thereby preventing void formation in the deposited conductive filler 610.

[0060] exist Figures 5C to 5D In this process, after deposition, excess conductive filler 610 can be removed, allowing conductive lines and vias of the upper interconnect layer to be embedded in the ILD layer structure. In one embodiment, a metal CMP process can be used for damascene etching and planarization. The CMP etching can be terminated at the CMP etch stop layer of the second ILD layer 514.

[0061] Figures 7A to 7C A process flow diagram of a via filling method according to various embodiments is shown. The process flow can follow the diagrams discussed above ( Figures 1B to 1E And therefore will no longer be described.

[0062] exist Figure 7A In the process flow 70, process flow 70 begins by exposing a substrate to a boron-containing precursor to be adsorbed onto the substrate, wherein the substrate includes a dielectric layer formed on a conductive layer, and wherein the conductive layer is exposed at the bottom of a recess formed in the dielectric layer (box 710). Figure 1B Subsequently, the adsorbed boron-containing precursor can be exposed to plasma (box 720, ...). Figure 1C Subsequently, the recesses were filled from bottom to top using a conductive filler material via vapor deposition, wherein the vertical deposition rate of the conductive filler material was greater than the lateral deposition rate of the conductive filler material (Box 730). Figures 1D to 1E ).

[0063] exist Figure 7BIn another process flow 72, the substrate is exposed to BCl3 on a surface to be adsorbed onto the substrate, wherein the surface includes a dielectric layer and a conductive layer (frame 712). Figure 1B Subsequently, the adsorbed BCl3 can be exposed to a plasma consisting of argon and hydrogen, where exposure to the plasma binds boron to the dielectric layer (box 722). Figure 1C Subsequently, metal is deposited on the surface, wherein the deposition rate of metal on the conductive layer is greater than the deposition rate on the dielectric layer (box 732, Figure 1D In one or more embodiments, the steps of exposure to BCl3 and exposure to plasma can be repeated prior to deposition.

[0064] exist Figure 7C In another process flow 74, the substrate, including vias, is exposed to a boron-containing precursor to be adsorbed onto the sidewalls of the vias, wherein the vias have a critical size of 20 nm or smaller, and conductive material is exposed at the bottom of the vias (box 714). Figure 1B Subsequently, the substrate can be exposed to plasma to induce boron doping of the sidewalls (box 724). Figure 1C The vias were then filled with ruthenium (Ru) via a vapor deposition process, where Ru was preferentially deposited from the bottom of the vias rather than from the sidewalls (box 734). Figures 1D to 1E ).

[0065] Example embodiments of the present invention are described below. Other embodiments can also be understood based on the entire specification and the claims set forth herein.

[0066] Example 1. A method of processing a substrate includes: exposing the substrate to a boron-containing precursor to be adsorbed onto the substrate, wherein the substrate includes a dielectric layer formed on a conductive layer, and the conductive layer is exposed at the bottom of a recess formed in the dielectric layer. The method includes: exposing the adsorbed boron-containing precursor to a plasma; and filling the recess from bottom to top with a conductive filler material by a vapor deposition process, wherein the vertical deposition rate of the conductive filler material is greater than the lateral deposition rate of the conductive filler material.

[0067] Example 2. The method as described in Example 1, wherein the boron-containing precursor comprises boron halide or borane.

[0068] Example 3. The method as described in either Example 1 or 2, wherein the boron-containing precursor comprises B2H6, BF3, BCl3, or BBr3.

[0069] Example 4. The method as described in any one of Examples 1 to 3, wherein the conductive layer comprises ruthenium (Ru), tungsten (W), or titanium (Ti).

[0070] Example 5. The method as described in any one of Examples 1 to 4, wherein the plasma comprises argon and hydrogen.

[0071] Example 6. The method as described in any one of Examples 1 to 5, wherein the dielectric layer comprises silicon oxide, and wherein exposure to the plasma induces boron doping in the silicon oxide.

[0072] Example 7. The method as described in any one of Examples 1 to 6, wherein the conductive filler material comprises ruthenium (Ru), tungsten (W), or molybdenum (Mo).

[0073] Example 8. The method as described in any one of Examples 1 to 7, wherein the exposure to the plasma removes boron from the conductive layer.

[0074] Example 9. A method of processing a substrate includes: exposing the substrate to BCl3 to be adsorbed on a surface of the substrate, wherein the surface includes a dielectric layer and a conductive layer. The method includes: exposing the adsorbed BCl3 to a plasma comprising argon and hydrogen, wherein the exposure to the plasma binds boron to the dielectric layer. The method includes: depositing a metal on the surface, wherein the deposition rate of the metal on the conductive layer is greater than the deposition rate on the dielectric layer.

[0075] Example 11. The method as described in one of Examples 9 or 10, wherein the substrate includes a recess, the conductive layer is exposed at the bottom of the recess, and the dielectric layer includes sidewalls of the recess.

[0076] Example 12. The method as described in any one of Examples 9 to 11, wherein the exposure to BCl3 is performed in the absence of plasma.

[0077] Example 13. The method as described in any one of Examples 9 to 12, wherein the metal comprises ruthenium (Ru), tungsten (W), or molybdenum (Mo).

[0078] Example 14. The method as described in any one of Examples 9 to 13, wherein the conductive layer comprises silicon oxide or silicon nitride.

[0079] Example 15. A method of forming a metal interconnect for a semiconductor device includes: exposing a substrate including a via to a boron-containing precursor to be adsorbed on the sidewalls of the via, wherein the via has a critical dimension of 20 nm or less, and a conductive material is exposed at the bottom of the via. The method includes: exposing the substrate to a plasma to induce boron doping of these sidewalls; and filling the via with ruthenium (Ru) via a vapor deposition process, wherein the Ru is preferentially deposited from the bottom of the via rather than from the sidewalls.

[0080] Example 16. The method as described in Example 15, wherein the via has an aspect ratio between 5:1 and 100:1.

[0081] Example 17. The method as described in one of Examples 15 or 16, wherein the via is filled with Ru without any voids.

[0082] Example 18. The method as described in any one of Examples 15 to 17, wherein the boron-containing precursor comprises BCl3, and wherein the plasma comprises argon and hydrogen.

[0083] Example 19. The method as described in any one of Examples 15 to 18, wherein the conductive material comprises titanium nitride.

[0084] Example 20. The method as described in any one of Examples 15 to 19, wherein the sidewalls comprise oxides.

[0085] Although the invention has been described with reference to illustrative embodiments, this specification is not intended to be limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to this specification. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A method for processing a substrate, the method comprising: The substrate is exposed to a boron-containing precursor to be adsorbed onto the substrate, the substrate including a dielectric layer formed on a conductive layer, the conductive layer being exposed at the bottom of a recess formed in the dielectric layer; The adsorbed boron-containing precursor is exposed to plasma; as well as The recess is filled from bottom to top with a conductive filler material using a vapor deposition process, wherein the vertical deposition rate of the conductive filler material is greater than the lateral deposition rate of the conductive filler material.

2. The method as described in claim 1, wherein, The boron-containing precursors include boron halides or boranes.

3. The method as described in claim 1, wherein, The boron-containing precursors include B2H6, BF3, BCl3, or BBr3.

4. The method of claim 1, wherein, The conductive layer includes ruthenium (Ru), tungsten (W), or titanium (Ti).

5. The method of claim 1, wherein, The plasma consists of argon and hydrogen.

6. The method of claim 1, wherein, The dielectric layer comprises silicon oxide, and wherein exposure to the plasma induces boron doping in the silicon oxide.

7. The method of claim 1, wherein, The conductive filler material includes ruthenium (Ru), tungsten (W), or molybdenum (Mo).

8. The method of claim 1, wherein, The exposure to the plasma removes boron from the conductive layer.

9. A method for processing a substrate, the method comprising: The substrate is exposed to BCl3 to be adsorbed onto the surface of the substrate, the surface comprising a dielectric layer and a conductive layer; The adsorbed BCl3 was exposed to a plasma consisting of argon and hydrogen, which bound boron to the dielectric layer. as well as Metal is deposited on the surface, wherein the deposition rate of the metal on the conductive layer is greater than the deposition rate on the dielectric layer.

10. The method of claim 9, further comprising, prior to the deposition, repeating the steps of exposure to BCl3 and exposure to the plasma.

11. The method of claim 9, wherein, The substrate includes a recess, the conductive layer is exposed at the bottom of the recess, and the dielectric layer includes the sidewalls of the recess.

12. The method of claim 9, wherein, The exposure to BCl3 was performed in the absence of plasma.

13. The method of claim 9, wherein, The metals include ruthenium (Ru), tungsten (W), or molybdenum (Mo).

14. The method of claim 9, wherein, The conductive layer includes titanium nitride or tantalum nitride.

15. A method of forming a metal interconnect for a semiconductor device, the method comprising: A substrate including a via is exposed to a boron-containing precursor to be adsorbed onto the sidewall of the via, the via having a critical size of 20 nm or less, and a conductive material is exposed at the bottom of the via. The substrate was exposed to plasma to induce boron doping of these sidewalls; as well as The via is filled with ruthenium (Ru) via a vapor deposition process, with Ru preferentially deposited from the bottom of the via rather than from the sidewalls.

16. The method of claim 15, wherein, The via has an aspect ratio between 5:1 and 100:

1.

17. The method of claim 15, wherein, The via is filled with Ru without any voids.

18. The method of claim 15, wherein, The boron-containing precursor includes BCl3, and the plasma includes argon and hydrogen.

19. The method of claim 15, wherein, The conductive material includes titanium nitride.

20. The method of claim 15, wherein, These sidewalls include oxides.

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