Infrared focal plane array MEMS chip and preparation method thereof

Abstract

The invention discloses an infrared focal plane array MEMS chip and a preparation method thereof. The chip comprises a readout circuit wafer, a getter module arranged on the readout circuit wafer and a suspended pixel structure located above the getter module. The preparation method comprises the following main steps: after a medium structure with a gap ring and a top micropore is formed, melting and leveling a low-melting-point material at a high temperature, depositing a getter body through the micropore, then sealing the getter body, and finally synchronously forming a suspended pixel structure and a suspended getter structure through a release process. The getter module is integrated below the pixel, the chip is sealed and protected in the whole chip manufacturing process, the low-melting-point material can be leveled, exposed and activated through heating after packaging, the packaging vacuum degree and reliability are remarkably improved, and meanwhile device miniaturization is facilitated.

Description

Technical Field

[0001] This invention belongs to the field of microelectromechanical systems (MEMS) design and manufacturing in semiconductor technology, and specifically relates to an infrared focal plane array MEMS chip and its fabrication method. Background Technology

[0002] Infrared detection technology is widely used in various fields due to its all-weather capability (day and night), good environmental adaptability, and ability to obtain richer background and target information compared to visible light. In the military field, infrared detection technology is used for remote sensing reconnaissance, missile guidance, missile defense early warning, and individual soldier night vision systems. In the industrial field, infrared detection technology is mainly used for the detection of various equipment and systems, and the detection of gas leaks such as methane, enabling faster identification of equipment malfunctions, improving production efficiency, and ensuring the safety of personnel within factories. The most common type is the uncooled infrared focal plane array detector, a core component of an infrared detection system responsible for converting infrared radiation light signals into electrical signals and outputting them. The performance of the infrared focal plane array directly affects the performance of the entire infrared detection system.

[0003] To improve detector performance, vacuum encapsulation is necessary. The third-generation detectors developed to date have clearly prioritized further reducing detector size as a key research direction. To achieve this, the most advanced and commercially viable packaging method in the field is wafer-level packaging. This method abandons traditional concepts, using MEMS fabrication methods to produce the package on a wafer basis. The infrared focal plane detector wafer is then bonded to the package wafer, completing the encapsulation of all dies on the entire wafer in a single process. This significantly improves production efficiency, and the MEMS-fabricated package offers a significant advantage in reducing package size, making this packaging method highly regarded and accepted.

[0004] Wafer-level packaging offers significant advantages in reducing the size of detector chips and packages, but it still faces many technical challenges. Maintaining the vacuum level within the package is crucial to the detector's performance. Current methods involve preparing a getter within the package and activating it during or after vacuum packaging. This allows the getter to absorb gases from within the package, thereby increasing the vacuum level.

[0005] For example, patent CN116768141A describes an infrared detector getter module and vacuum packaging structure, in which getter material is placed on a suspended support structure, arranged in parallel with functional module 8, and completely covered within a sealed microcavity. Patent CN119263192A describes an area-array pixel-packaged uncooled infrared detector and its fabrication method, in which a getter film is prepared on the structural cavity, and the getter material is deposited through release holes onto the getter region composed of second microbridges, thus fully utilizing the chip area.

[0006] As mentioned above, a good getter layout and fabrication process are crucial for reducing detector size. Despite various optimizations to getters in wafer-level packaging processes, issues remain, including small getter area, insufficient getter capacity, and incompatibility between getter manufacturing processes and MEMS processes. More importantly, to increase the specific surface area of ​​the getter, the prepared getters are generally porous. Regardless of which step in the MEMS fabrication process the getter is integrated into, it will face adverse effects from subsequent MEMS processes, leading to getter failure. For example, wet processes in MEMS fabrication can alter the surface properties of the getter material, causing gases to be adsorbed by the getter during MEMS processes, making it difficult to achieve getter performance in subsequent activation processes. Summary of the Invention

[0007] The purpose of this invention is to provide an infrared focal plane array MEMS chip and its fabrication method, which integrates the preparation of getter materials into the MEMS process. Throughout the entire process, the getter material does not come into contact with the atmosphere, nor with the wet liquids and dry gases in the MEMS process, thus effectively protecting the performance of the getter material.

[0008] To achieve the above objectives, the technical solution adopted by this invention is: a method for fabricating an infrared focal plane array MEMS chip, comprising the following steps: S1, deposit a low-melting-point material on the readout circuit wafer. The melting point of the low-melting-point material is lower than the getter activation temperature. Then, the deposited low-melting-point material is patterned to form multiple isolated first low-melting-point material layers. S2, a first polyimide layer is prepared on the first low-melting-point material layer and the exposed readout circuit wafer, and two types of PI-1 holes are etched on the first polyimide layer, namely electrical connection holes and low-melting-point material holes. The electrical connection holes penetrate to the readout circuit wafer, and the low-melting-point material holes penetrate to the first low-melting-point material layer. S3, deposit the first dielectric layer, covering the surface of the first polyimide layer and the inner walls of all PI-1 pores; S4, deposit low-melting-point material again in the low-melting-point material hole to form a second low-melting-point material layer, etch the low-melting-point material along the hole wall of the low-melting-point material hole until the circuit wafer is read out, forming a gap ring around the second low-melting-point material layer; S5, deposit a second dielectric layer on the surface of the first dielectric layer, and form micropores on the top of the second low-melting-point material layer, wherein the pore diameter of the micropores is smaller than the diameter of the second low-melting-point material after etching; S6, under process conditions where the temperature is higher than the melting point of the low-melting-point material, the first low-melting-point material layer and the second low-melting-point material layer are melted and leveled to form a low-melting-point material support, and getter material is deposited through the micropores to form a getter body; S7, forming a third medium layer covering the taker body; S8, a getter electric heating structure is formed on the third dielectric layer, and the getter electric heating structure is electrically connected to the readout circuit wafer through an electrical connection hole; S9, a second polyimide layer and a pixel structure layer containing a third polyimide layer are sequentially formed on the getter electric heating structure; S10, perform the release process to remove the first polyimide layer, the second polyimide layer and the third polyimide layer to form a suspended pixel structure, while sealing the getter body in a cavity composed of a medium layer and a low-melting-point material support.

[0009] Furthermore, in step S3, the bottom of the PI-1 hole is covered with a first dielectric layer, which is then removed by etching.

[0010] Furthermore, in step S4, when etching the low-melting-point material along the hole wall of the low-melting-point material hole, after etching the second low-melting-point material layer, the first low-melting-point material layer inside the hole is etched to the readout circuit wafer.

[0011] Furthermore, in step S6, after the getter body is formed by deposition through the micropores, its deposition range extends to the surface of the second medium layer surrounding the micropores.

[0012] Furthermore, in step S8, a fourth dielectric layer is also formed to cover the getter electric heating structure.

[0013] The present invention also proposes an infrared focal plane array MEMS chip, including a readout circuit wafer, a getter module and a suspended pixel structure. The getter module includes a low melting point material support, a gap ring, a getter body, a third dielectric layer, a getter electric heating structure and a fourth dielectric layer. The low-melting-point material support is located on the readout circuit wafer. The gap ring surrounds the low-melting-point material support and is formed by the low-melting-point material support and the first dielectric layer. The bottom of the getter body is supported by the low-melting-point material support, and its sidewalls are spaced apart from the outer wall of the gap ring. The third dielectric layer covers and seals the getter body. The getter electric heating structure is disposed on the third dielectric layer and electrically connected to the readout circuit wafer. The melting point of the low-melting-point material support is lower than the activation temperature of the getter body.

[0014] Furthermore, the material of the low-melting-point material support is a gold-indium alloy or a tin-bismuth alloy.

[0015] The beneficial effects of the present invention are: 1. The present invention integrates the preparation of getter materials into the MEMS process. During the entire process, the getter material does not come into contact with the atmosphere, nor with the wet liquid and dry gas in the MEMS process, which effectively protects the performance of the getter material.

[0016] 2. The present invention uses a low melting point material to support the getter material and the dielectric layer. During the activation process after encapsulation, the low melting point material self-levels and detaches from the first dielectric layer, exposing the getter to the same encapsulation vacuum environment as the pixel structure, which greatly improves the getter's gas absorption effect.

[0017] 3. The present invention combines the gap ring with the micropores located on top of the low melting point material to constrain the deposition and molding of the getter material, so that the getter material does not contact the gap ring or has little contact with it, thereby increasing the surface area of ​​the getter material exposed in the package and improving the getter effect.

[0018] 4. The low-melting-point material gap ring of the present invention, which is composed of low-melting-point material, first and second dielectric layers, getter, and third and fourth dielectric layers, is wrapped by two layers of PI-1 and PI-2 in the MEMS process to form a strong outer wall. It is not easy to break in subsequent processes and has high structural reliability.

[0019] 5. The present invention places the getter below the pixel, rather than on the same plane as the pixel, which significantly improves the miniaturization of the chip and detector, and is particularly suitable for wafer-level packaging and pixel-level packaging of infrared focal plane detector chips. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the fabrication of a patterned low-melting-point material layer on a readout circuit wafer in the preparation method of the present invention. Figure 2 This is a schematic diagram illustrating the fabrication of a first polyimide layer on a readout circuit wafer and the etching process to form holes in the fabrication method of the present invention. Figure 3 This is a schematic diagram showing the deposition and etching of the first dielectric layer in the preparation method of the present invention; Figure 4 This is a schematic diagram of the formation of the gap ring in the preparation method of the present invention; Figure 5 This is a schematic diagram of the deposition and etching of the second dielectric layer in the preparation method of the present invention; Figure 6 This is a schematic diagram of the low-melting-point material leveling and filling the gap ring in the preparation method of the present invention; Figure 7 This is a schematic diagram of the deposited getter material and the third dielectric layer in the preparation method of the present invention; Figure 8 This is a schematic diagram of the sequential deposition of the getter electric heating layer and the fourth dielectric layer in the preparation method of the present invention; Figure 9 This is a schematic diagram of the preparation of the second polyimide layer and the pixel structure containing the third polyimide layer in the preparation method of the present invention; Figure 10 This is a schematic diagram showing the release of the first polyimide layer, the second polyimide layer, and the third polyimide layer using a plasma release process in the preparation method of the present invention. Figure 11 This is a schematic diagram of the infrared focal plane array chip of the present invention during the activation operation after vacuum packaging; The markings in the diagram are as follows: 1. Readout circuit wafer; 2. Low-melting-point material support; 201. First low-melting-point material layer; 202. Second low-melting-point material layer; 3. First polyimide layer; 4. Low-melting-point material hole; 5. Electrical connection hole; 6. First dielectric layer; 7. Gap ring; 8. Second dielectric layer; 9. Micropore; 10. Getter body; 11. Third dielectric layer; 12. Getter electrically heated structure; 13. Fourth dielectric layer; 14. Second polyimide layer; 15. Third polyimide layer; 16. Pixel structure. Detailed Implementation

[0021] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments, but this should not be construed as limiting the invention in any way.

[0022] Example 1 A method for fabricating an infrared focal plane array MEMS chip includes the following steps: The first step is to use readout circuit wafer 1 as a substrate, clean and dry readout circuit wafer 1 to remove surface impurities and moisture, and ensure the adhesion and process stability of subsequent thin film deposition. The second step, as Figure 1As shown, a low-melting-point material is deposited on the cleaned readout circuit wafer 1. The low-melting-point material is an alloy with a melting point lower than the activation temperature of the subsequent getter, such as gold-indium alloy, tin-bismuth alloy, etc.; then, the low-melting-point material is patterned to form an isolated first low-melting-point material layer 201 located below a predetermined pixel area (e.g., Figure 2 As shown), it serves as the bottom support base for the getter module; The third step, as Figure 2 As shown, a first polyimide layer 3 (PI-1 layer) is prepared on the first low-melting-point material layer 201 and the exposed readout circuit wafer 1. Two types of PI-1 holes are formed on the first polyimide layer 3 by photolithography and etching. The first type of PI-1 hole is an electrical connection hole 5, which penetrates the first polyimide layer 3 to the readout circuit wafer 1. The second type of PI-1 hole is a low-melting-point material hole 4, which penetrates the first low-melting-point material layer 201. Step four, as Figure 3 As shown, a first dielectric layer 6 is deposited on the entire surface of the structure. The first dielectric layer 6 covers the surface of the first polyimide layer 3 and the inner walls and bottom of all PI-1 holes. Then, the first dielectric layer 6 at the bottom of the electrical connection hole 5 and the low melting point material hole 4 is removed by etching, thereby re-exposing the readout circuit wafer 1 and the first low melting point material layer 201 at the bottom of the electrical connection hole 5 and the low melting point material hole 4, respectively, while the first dielectric layer 6 is retained on the sidewalls of the electrical connection hole 5 and the low melting point material hole 4. Fifth step, as Figure 4 As shown, a low-melting-point material is deposited again in the low-melting-point material hole 4, with the deposition height not exceeding the opening of the low-melting-point material hole 4, forming a second low-melting-point material layer 202, the material of which is the same as the first low-melting-point material layer 201; the low-melting-point material deposited this time is etched along the hole wall of the low-melting-point material hole 4, and through the first low-melting-point material layer 201 deposited in the second step in the hole to the readout circuit wafer 1, forming a gap ring 7 surrounding the second low-melting-point material layer 202; Step 6, as follows Figure 5 As shown, a second dielectric layer 8 is deposited on the surface of the first dielectric layer 6, and the second dielectric layer 8 is etched at the position corresponding to the second low melting point material layer 202, thereby forming a micropore 9 on the top of the second low melting point material layer 202. The pore diameter of the micropore 9 is smaller than the diameter of the etched second low melting point material layer 202. Step 7, as Figure 6 As shown, the readout circuit wafer 1 with the above-mentioned process structure is placed in the getter material deposition equipment. The temperature of the equipment cavity is raised to a level higher than the melting point of the low melting point material. At this time, the low melting point material support part 2 (including the first low melting point material layer 201 and the second low melting point material layer 202) melts and flows to fill the bottom of the gap ring 7. Step 8, as Figure 7As shown, getter material is sputtered and deposited in the low-melting-point material hole 4 below through the micropore 9, and the getter material continues to be deposited on the second dielectric layer 8 around the hole after it extends beyond the low-melting-point material hole 4, forming getter body 10; due to the pore size limitation of the micropore 9, the sidewall of getter body 10 does not contact or only partially contacts the gap ring 7, and then a third dielectric layer 11 that can encapsulate getter body 10 is deposited on the second dielectric layer 8 around the low-melting-point material hole 4 to protect getter body 10; Step 9, as Figure 8 As shown, a getter electric heating material is deposited on the surface of the third dielectric layer 11 to form a getter electric heating structure 12. The getter electric heating structure 12 is electrically connected to the readout circuit wafer 1 through the interconnection with the electrical connection hole 5. Then, a fourth dielectric material is deposited to form a fourth dielectric layer 13 covering the getter electric heating structure 12. Thus, the getter module is formed. Step 10, as follows Figure 9 As shown, a second polyimide layer 14 (PI-2 layer) is prepared on the surface of the completed getter module structure, and a pixel structure 16 containing a third polyimide layer 15 (PI-3 layer) is prepared on it. Step 11, as follows Figure 10 As shown, a plasma release process is used in a vacuum chamber to release polyimide material to form a suspended pixel structure 16. At the same time, a sealed cavity is formed in the getter module below it, which is surrounded by a first, second, and third dielectric layer and a low-melting-point material at the bottom. The getter body 10 is surrounded in this cavity and does not come into contact with the atmosphere. Thus, the fabrication process of the infrared focal plane array MEMS chip is completed.

[0023] The aforementioned infrared focal plane array MEMS chip is encapsulated in a vacuum packaging device. The getter body 10 is activated by heating through the getter electric heating structure 12. During the initial heating process, the temperature first reaches the melting point of the low-melting-point material, causing it to melt. Since there is no PI material constraint, the low-melting-point material has a larger flow area and a lower height, detaching from the first dielectric layer 6, thus exposing the getter body 10 to the same encapsulation vacuum environment as the pixel structure 16. Figure 11 As shown; after the heating temperature reaches the activation temperature of the getter material, the getter body 10 will adsorb the excess gas in the vacuum encapsulation body, further improving the vacuum degree of the encapsulation body.

[0024] After encapsulation activation, the getter body 10 is exposed in the gap ring 7, and its direction is opposite to that of the pixel structure 16. The particles falling from the getter body 10 are confined in the cavity formed by the first dielectric layer 6 and are not easy to contact the pixel structure 16.

[0025] In this invention, all dielectric layer materials are SiO2 or SiN.

[0026] Example 2 like Figure 10 As shown, an infrared focal plane array MEMS chip, fabricated by the method described in Example 1, includes a readout circuit wafer 1, a getter module, and a suspended pixel structure 16. The getter module is disposed on the readout circuit wafer 1, and the pixel structure 16 is disposed on the getter module.

[0027] The getter module includes a low-melting-point material support 2, a gap ring 7, a getter body 10, a third dielectric layer 11, a getter electric heating structure 12, and a fourth dielectric layer 13. The low-melting-point material support 2 is located on the readout circuit wafer 1. The gap ring 7 surrounds the low-melting-point material support 2 and is formed by the low-melting-point material support 2 and the first dielectric layer 6. The bottom of the getter body 10 is supported by the low-melting-point material support 2, and its sidewalls are spaced apart from the outer wall of the gap ring 7. The third dielectric layer 11 covers and seals the getter body 10. The getter electric heating structure 12 is disposed on the third dielectric layer 11 and is electrically connected to the readout circuit wafer 1 through an electrical connection hole 5. The melting point of the low-melting-point material support 2 is lower than the activation temperature of the getter body 10.

[0028] Optionally, the top of the second medium layer 8 is provided with micropores 9, and the getter body 10 is deposited through the micropores 9. The getter body 10 continues to be deposited on the surface of the second medium layer 8 around the micropores after it extends beyond the micropores during the deposition process.

[0029] Optionally, the material of the low-melting-point material support 2 is a gold-indium alloy or a tin-bismuth alloy.

[0030] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the specific implementation of the present invention with reference to the above embodiments. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention are within the protection scope of the pending claims.

Claims

1. A method for fabricating an infrared focal plane array MEMS chip, characterized in that, Includes the following steps: S1, deposit a low-melting-point material on the readout circuit wafer. The melting point of the low-melting-point material is lower than the getter activation temperature. Then, the deposited low-melting-point material is patterned to form multiple isolated first low-melting-point material layers. S2, a first polyimide layer is prepared on the first low-melting-point material layer and the exposed readout circuit wafer, and two types of PI-1 holes are etched on the first polyimide layer, namely electrical connection holes and low-melting-point material holes. The electrical connection holes penetrate to the readout circuit wafer, and the low-melting-point material holes penetrate to the first low-melting-point material layer. S3, deposit the first dielectric layer, covering the surface of the first polyimide layer and the inner walls of all PI-1 pores; S4, deposit low-melting-point material again in the low-melting-point material hole to form a second low-melting-point material layer, etch the low-melting-point material along the hole wall of the low-melting-point material hole until the readout circuit wafer is formed to form a gap ring around the second low-melting-point material layer; S5, deposit a second dielectric layer on the surface of the first dielectric layer, and form micropores on the top of the second low-melting-point material layer, wherein the pore diameter of the micropores is smaller than the diameter of the second low-melting-point material after etching; S6, under process conditions where the temperature is higher than the melting point of the low-melting-point material, the first low-melting-point material layer and the second low-melting-point material layer are melted and leveled to form a low-melting-point material support, and getter material is deposited through the micropores to form a getter body; S7, forming a third medium layer covering the taker body; S8, a getter electric heating structure is formed on the third dielectric layer, and the getter electric heating structure is electrically connected to the readout circuit wafer through an electrical connection hole; S9, a second polyimide layer and a pixel structure layer containing a third polyimide layer are sequentially formed on the getter electric heating structure; S10, perform the release process to remove the first polyimide layer, the second polyimide layer and the third polyimide layer to form a suspended pixel structure, while sealing the getter body in a cavity composed of a medium layer and a low-melting-point material support.

2. The method for fabricating an infrared focal plane array MEMS chip according to claim 1, characterized in that, In step S3, the bottom of the PI-1 hole is covered with a first dielectric layer, which is then removed by etching.

3. The method for fabricating an infrared focal plane array MEMS chip according to claim 1, characterized in that, In step S4, when etching the low-melting-point material along the hole wall of the low-melting-point material hole, after etching the second low-melting-point material layer, the first low-melting-point material layer inside the hole is etched to the readout circuit wafer.

4. The method for fabricating an infrared focal plane array MEMS chip according to claim 1, characterized in that, In step S6, after the getter body is formed by deposition through the micropores, its deposition range extends to the surface of the second medium layer surrounding the micropores.

5. The method for fabricating an infrared focal plane array MEMS chip according to claim 1, characterized in that, In step S8, a fourth dielectric layer is also formed to cover the getter electric heating structure.

6. An infrared focal plane array MEMS chip, characterized in that, It includes a readout circuit wafer, a getter module, and a suspended pixel structure. The getter module includes a low-melting-point material support, a gap ring, a getter body, a third dielectric layer, a getter electric heating structure, and a fourth dielectric layer. The low-melting-point material support is located on the readout circuit wafer. The gap ring surrounds the low-melting-point material support and is formed by the low-melting-point material support and the first dielectric layer. The bottom of the getter body is supported by the low-melting-point material support, and its sidewalls are spaced apart from the outer wall of the gap ring. The third dielectric layer covers and seals the getter body. The getter electric heating structure is disposed on the third dielectric layer and electrically connected to the readout circuit wafer. The melting point of the low-melting-point material support is lower than the activation temperature of the getter body.

7. The infrared focal plane array MEMS chip according to claim 6, characterized in that, The material of the low-melting-point material support is a gold-indium alloy or a tin-bismuth alloy.

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