Quantum Monte Carlo simplified circuit implementation method
By simplifying the architecture of quantum Monte Carlo circuits through the collaboration of a single-layer p-bit network and a register module, the problems of high complexity and large resource consumption in traditional circuits are solved, enabling efficient hardware simulation and optimization solution generation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUAZHONG UNIV OF SCI & TECH
- Filing Date
- 2026-01-26
- Publication Date
- 2026-04-24
AI Technical Summary
In existing quantum Monte Carlo circuit hardware implementations, the high complexity, large resource consumption, high power consumption, and difficulty in guaranteeing signal integrity caused by the multi-layer replica probability bit fully connected coupling architecture make it difficult to achieve large-scale, high-efficiency hardware applications under existing integrated circuit processes.
A simplified quantum Monte Carlo circuit architecture is adopted, which works in conjunction with a single-layer p-bit network and a register module. The spatial parallel structure is replaced by time-sequential updates, and MTJ devices are used to achieve probabilistic controllability for state registration and updates, forming a closed-loop logic of "copy iteration-state inheritance".
It significantly saves chip area and wiring resources, enables efficient hardware simulation, improves the efficiency of solving combinatorial optimization problems, and reduces circuit design complexity and power consumption.
Smart Images
Figure CN121920290A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of circuit implementation technology, specifically relating to a simplified quantum Monte Carlo circuit implementation method. Background Technology
[0002] Combinatorial optimization problems are among the core challenges in computer science and operations research, widely applicable in real-world scenarios such as path planning, scheduling, communication networks, chip layout, logistics, and financial investment. Their fundamental goal is to find optimal solutions that satisfy constraints within a discrete, finite, but extremely large solution space. For example, the Traveling Salesman Problem (TSP) requires finding the shortest path between several cities; the Max-Cut Problem requires partitioning a graph into sets of vertices such that the sum of the weights of edges crossing those sets is maximized. These problems typically exhibit complex constraints and combinatorial explosion characteristics; the number of possible solutions grows exponentially with the number of variables.
[0003] To address this challenge, probabilistic computation emerged, its core idea being to utilize the randomness of p-bits as a computational resource, approximating the optimal solution to the problem through extensive random sampling. This method is particularly suitable for handling combinatorial optimization problems and can achieve efficient sampling through hardware circuits. Faced with the ever-increasing scale and complexity of computations, existing circuit structures are struggling to meet the demands in terms of resource consumption and scalability, necessitating new, efficient circuit implementation methods.
[0004] In existing technologies, P-bit networks offer a promising hardware computing architecture for solving NP-hard problems. By establishing controllable coupling between probabilistic bit units, parallelized random sampling and state evolution can be achieved, simulating the search process of heuristic algorithms at the physical level, thus solving typical combinatorial optimization tasks. However, they are inefficient when solving high-dimensional combinatorial optimization problems. The exponential consumption of computational resources does not guarantee a reliable search for the global optimum; they are prone to getting trapped in local optima, wasting a significant amount of computation exploring hopeless local regions.
[0005] In existing quantum Monte Carlo circuit networks, to simulate effects such as quantum tunneling of a single qubit, quantum Monte Carlo circuits are implemented using a multi-replica p-bit circuit network with mutual coupling. Each p-bit replica layer simulates the state of the quantum system at a specific moment, while the layers are tightly coupled to simulate quantum fluctuations. This complex replica coupling structure results in high hardware circuit design complexity, large interconnection resource overhead, large area and power consumption, and bloated circuitry that is difficult to implement. Summary of the Invention
[0006] To address the above problems, this invention proposes a simplified quantum Monte Carlo circuit implementation method.
[0007] The technical solution of this invention is: a method for implementing a simplified quantum Monte Carlo circuit includes the following steps:
[0008] S1. Generate the current replica p-bit network and calculate the total energy of the current replica p-bit network;
[0009] S2. Register the output state of the current replica p-bit network;
[0010] S3. Based on the total energy and registered items of the current replica p-bit network, sample and update the next replica p-bit network.
[0011] Furthermore, in S1, when generating the current replica p-bit network, taking the integer factorization problem as an example, the binary form of the first undetermined factor and the binary form of the second undetermined factor are mapped one-to-one with the p-bit units of the current replica p-bit network, and the total energy of the current replica p-bit network is calculated.
[0012] Furthermore, in S1, each p-bit unit corresponds to a binary bit and generates a random initial value.
[0013] Furthermore, S3 includes the following sub-steps:
[0014] S31. Sample the state value of each p-bit in the current replica p-bit network and calculate the partial derivative of the total energy corresponding to that p-bit.
[0015] S32. The partial derivative of the p-bit is scaled and adjusted by a weighting function and synthesized with the register item (i.e., the output state of the current replica p-bit network after delay) as the input voltage signal for updating the corresponding p-bit unit in the next replica p-bit network.
[0016] S33. Apply the input voltage signal to a hardware unit based on a p-bit functional device (MTJ is used as an example in this invention) and convert the input voltage value of the input voltage signal into a random output bit state.
[0017] Furthermore, in S33, the input voltage value of the input voltage signal is converted into a random output bit state by utilizing the sigmoid probability response curve characteristics of the p-bit hardware unit.
[0018] Furthermore, in S2, the output state of the current replica p-bit network is delayed and then used as a coupling term to provide input support for the sampling update of the next replica p-bit network.
[0019] Furthermore, in S2, when performing state registration, a hardware registration delay unit is used to achieve delayed transmission of state signals.
[0020] The beneficial effects of this invention are as follows: This invention proposes a single-layer physical network multiplexing technology, which replaces the spatial parallel structure with time-sequential updates to achieve equivalent simulation of multi-layer quantum Monte Carlo hardware; compared with the traditional scheme that requires the construction of a multi-layer p-bit fully connected network and the number of connections increases with the square of the scale, this invention only relies on a single-layer p-bit and register delay unit, and reproduces the evolution of multiple copies through the time-sequential control of a single-layer network on the circuit hardware, which greatly saves chip area and wiring resources. Attached Figure Description
[0021] Figure 1 A flowchart illustrating the simplified circuit implementation method for quantum Monte Carlo;
[0022] Figure 2 The graph shows the P-bit unit with MTJ as the core device and the probability controllable curve.
[0023] Figure 3 This is a detailed flowchart of the technical solution of the present invention;
[0024] Figure 4 This is a conceptual diagram of the circuit module of the technical solution of the present invention;
[0025] Figure 5 This is a diagram of a Spice lossless transmission line model.
[0026] Figure 6 This is a comparison diagram of the decomposition effects of the traditional method (left) and the integer factorization circuit of the present invention (right). Detailed Implementation
[0027] The embodiments of the present invention will be further described below with reference to the accompanying drawings.
[0028] The abbreviations and key terms are defined as follows:
[0029] p-bit (probabilistic bit): also known as probability bit, is the basic logical unit in probability calculation. It generates random binary states ("0" or "1") with adjustable probability.
[0030] Probabilistic computation: Probabilistic computation refers to a computational model that uses probability distributions or random variables as basic units, combining statistical inference and stochastic processes, for algorithm design and problem solving. This method can efficiently solve computational tasks that are difficult for deterministic algorithms to handle.
[0031] Quantum Monte Carlo (QMC) methods are a class of numerical computation techniques for quantum systems based on random sampling. They simulate the evolution and measurement of quantum states using Monte Carlo statistical principles. This method describes wave functions or spin systems in the form of probability distributions, effectively solving many-body quantum problems and achieving high-precision estimates of energy expectation, ground-state properties, and quantum correlations.
[0032] The Quantum Ising Model: The Quantum Ising Model is an important theoretical model in statistical physics and quantum mechanics used to describe the interactions and quantum state evolution of systems composed of quantum spins. It is a quantum extension of the classical Ising Model, introducing transverse fields or other quantum mechanical factors to study the role of quantum effects in spin systems.
[0033] like Figure 1 As shown, this invention provides a method for implementing a simplified quantum Monte Carlo circuit, comprising the following steps:
[0034] S1. Generate the current replica p-bit network and calculate the total energy of the current replica p-bit network;
[0035] S2. Register the output state of the current replica p-bit network;
[0036] S3. Based on the total energy and registered items of the current replica p-bit network, sample and update the next replica p-bit network.
[0037] This invention aims to address the inherent technical bottlenecks in the hardware implementation of traditional quantum Monte Carlo circuits, stemming from the use of a multi-layered, fully interconnected, probabilistic bit-coupled architecture. While this traditional architecture can effectively simulate quantum tunneling to improve the solution quality of combinatorial optimization problems, it faces significant difficulties in physical implementation: the complex inter-layer interconnect structure results in extremely high circuit design complexity and enormous wiring resource overhead, leading to a series of problems such as large chip area, high power consumption, and difficulty in guaranteeing signal integrity. This bloated implementation severely restricts its integration and application in actual chips, making it difficult to achieve large-scale, high-efficiency hardware implementation using existing integrated circuit processes. Therefore, the primary objective of this invention is to provide a novel quantum Monte Carlo circuit implementation scheme that fundamentally overcomes the aforementioned limitations in hardware resources and complexity.
[0038] In this embodiment of the invention, in S1, when generating the current replica p-bit network, taking the integer factorization problem as an example, the binary forms of the first and second undetermined factors are mapped one-to-one with the p-bit units of the current replica p-bit network, and the total energy of the current replica p-bit network is calculated. The variables to be mapped are the decision variables of the combinatorial optimization problem to be solved. Their type, quantity, and mapping method are determined according to the specific problem. This invention can be extended to all combinatorial optimization problems adapted to the quantum Monte Carlo algorithm.
[0039] In this embodiment of the invention, in S1, each p-bit unit corresponds to a binary bit and generates a random initial value.
[0040] In this embodiment of the invention, S3 includes the following sub-steps:
[0041] S31. Sample the state value of each p-bit in the current replica p-bit network and calculate the partial derivative of the total energy corresponding to that p-bit.
[0042] S32. The partial derivative of the p-bit is scaled and adjusted by a weighting function and combined with the registered item (i.e., the output state of the current replica p-bit network after the S2 register delay) to serve as the input voltage signal for updating the corresponding p-bit unit in the next replica p-bit network.
[0043] S33. Apply the input voltage signal to a hardware unit based on a p-bit functional device (MTJ is used as an example in this invention) and convert the input voltage value of the input voltage signal into a random output bit state.
[0044] In this embodiment of the invention, in S33, the input voltage value of the input voltage signal is converted into a random output bit state by utilizing the sigmoid probability response curve characteristics of the p-bit hardware unit.
[0045] In this embodiment of the invention, in S2, the output state of the current replica p-bit network is delayed and then used as a coupling term to provide input support for the sampling update of the next replica p-bit network.
[0046] In this embodiment of the invention, during state registration in S2, a hardware registration delay unit is used to achieve delayed transmission of state signals.
[0047] The core of this invention lies in proposing a simplified quantum Monte Carlo circuit architecture based on the collaborative operation of a single-layer p-bit network and a register module. The evolution of multiple replicas is reproduced through a time-series control of "current replica generation - state registration - next replica update." Specifically, by introducing a register module, the spatially parallel multi-layer replica evolution process is transformed into a time-series cyclical utilization of a single physical layer circuit. Specifically, the single-layer p-bit network first performs the generation and energy calculation of the current replica (S1), then registers and delays the output state of the current replica (S2), and finally drives the sampling update of the next replica based on the total energy and register entries of the current replica (S3), forming a closed-loop logic of "replica iteration - state inheritance."
[0048] This invention is compiled and simulated using Hspice software. The foundation is the construction of a p-bit cell with sigmoid-like activation function characteristics, preferably using a magnetic tunnel junction (MTJ) as the core device structure. This p-bit cell can utilize the current-controlled magnetic reversal characteristic of the MTJ to convert its input signal into a random output state following a sigmoid probability curve, thus achieving probabilistic controllability and providing a core source of randomness for probabilistic calculations.
[0049] like Figure 2 As shown, Figure 2 The hardware structure and probability controllable curve of the P-bit unit with MTJ as the core are shown: The P-bit unit realizes the resistance change by means of the MTJ current controllable magnetic reversal characteristic, and completes the state transition output with the corresponding external bias, input and read circuits; the corresponding probability controllable curve shows the correspondence between the input voltage and the probability of output "1". The two together provide support for the random output function of p-bit and provide feasibility guarantee for probability control.
[0050] Taking the classic combinatorial optimization problem of integer factorization as an example, we construct a circuit and a loss function E:
[0051] E=(XY-N) 2 ;
[0052] Where X and Y are undetermined factors, and N is the integer to be factored. Based on this, XY is written in binary form:
[0053] ;
[0054] Where, x p Let x1 represent the least significant bit of the undetermined factor X at the p-th bit, and y represent the least significant bit of the undetermined factor X. Q y1 represents the most significant bit of the undetermined factor Y in binary, and y2 represents the least significant bit of the undetermined factor Y in binary. qLet f(x) represent the binary value of the undetermined factor Y at the q-th bit, F represent the product of the binary multiplication of X and Y, p represent the binary bit sequence number of the undetermined factor X, and q represent the binary bit sequence number of the undetermined factor Y.
[0055] Based on the above functional form, using the single-layer p-bit network corresponding to the quantum Monte Carlo simplified circuit implementation method of this invention, the following implementation is carried out: Figure 3 The steps shown are as follows:
[0056] (1) Generate an initial p-bit network based on the quantum Ising model
[0057] The first step is to generate the current replica p-bit network, where each p-bit corresponds to a binary bit and a random initial value is generated.
[0058] The second step is to map the binary forms of X and Y to p-bits in the network one by one, and then calculate the total energy E of the system by weighting the bits by their respective bit positions.
[0059] (2) State registers
[0060] This section is the core of the invention. The key feature of the state register is the use of a lossless transmission line element from the Hspice simulation software to achieve delayed signal transmission. This transmission line, after a certain delay, takes the output state of the current replica p-bit network and, as a coupling term, enters the sampling and update module of the next replica network. This process does not require a clock control signal trigger, achieving latch-free and asynchronous flow of state information between replica layers.
[0061] like Figure 4 As shown, Figure 4The circuit module concept diagram clearly presents the core architecture of this invention: it includes three major functional modules: sampling and state update, calculation of system energy, and state register. It is equipped with a p-bit cell array based on MTJ (such as IN1, IN2, and IN3 corresponding to different p-bit inputs). The output is delayed and fed back to the sampling and update module as a coupling term through the state register module, realizing the cyclic reuse of a single-layer network. This intuitively and concretely illustrates the simplified logic of "single-layer network timing multiplexing". The innovative implementation methods of the state register module can be flexibly expanded, including but not limited to: 1) hardware register delay units (such as latch arrays), which directly realize the temporary storage and delayed transmission of state signals through hardware circuits; 2) lossless transmission line components adapted to hardware, which can complete asynchronous delay feedback of state without clock triggering; 3) passive delay register structure based on RC circuits, which realizes low-cost state delay by utilizing the charging and discharging characteristics of capacitors; 4) timing register units composed of synchronous / asynchronous flip-flops (D flip-flops, JK flip-flops, etc.), which can accurately control the state delay and transmission rhythm through clock signals; 5) multi-level delay registers implemented by shift register arrays, which support multi-level delay adjustment to adapt to different multiplexing cycle requirements; 6) cache register modules composed of static random access memory (SRAM) or dynamic random access memory (DRAM), which can realize large-capacity temporary storage of state and high-reliability multiplexing; 7) configurable register structure based on programmable logic device (FPGA) lookup table, which supports flexible adjustment of register parameters to adapt to different hardware scenarios. All of the above-mentioned register module implementation schemes can meet the core requirement of "state delay transmission-coupling feedback," and can be flexibly selected according to actual application scenarios such as chip process, delay accuracy, resource overhead, and reuse efficiency, comprehensively covering different hardware implementation scenarios and providing sufficient support for the scope of protection of the claims.
[0062] like Figure 5 As shown, Figure 5 This diagram shows a specific model of the "lossless transmission line element" scheme for the state register module built in the Hspice simulation environment, used to verify the adaptability of this register scheme to the overall architecture of this invention. The model is constructed based on Hspice simulation requirements and includes input IN, output OUT, lossless transmission line LLTR1, resistor R1, and pulse voltage source V1 (VPULSE). This model implements the signal delay function required by the state register, without clock triggering, and can asynchronously feed back the p-bit output of the current replica as the coupling term of the next replica, meeting the simplified delay design requirements of this invention. Figure 6 As shown, Figure 6This graph compares the decomposition effects of the traditional method (left) and the present invention (right) integer factorization circuit. The vertical axis represents the probability of a solution, and the horizontal axis corresponds to the solution space. The traditional multilayer circuit on the left has a dispersed probability distribution, making it difficult to focus on the optimal solution. The single-layer circuit of the present invention on the right has a more concentrated probability, intuitively demonstrating that its simplified architecture can still efficiently approach the optimal solution, confirming the balance between resource conservation and performance assurance.
[0063] (3) Sampling and State Update
[0064] First, dynamic input synthesis is performed based on register feedback and energy gradient. This stage samples the current state value of each p-bit and calculates the partial derivative (i.e., gradient) of the system energy function corresponding to that p-bit, quantifying the influence of its current state on the total system energy. Subsequently, scaling is applied using a weighting function, and the result is synthesized with inter-layer coupling values from the register module to form the input voltage signal for the next update of that p-bit unit.
[0065] Secondly, random state updates are performed using the inherent probabilistic characteristics of the p-bit unit. The synthesized input voltage is applied to the MTJ-based p-bit hardware unit. This unit utilizes its inherent sigmoid probability response curve to convert a determined input voltage value into a random output bit state. Specifically, the magnitude of the input voltage determines the probability that the unit outputs a logic 1.
[0066] Through this inherent randomness, the circuit network can perform efficient random walks in the solution space, while being guided by energy gradients and coupling terms to tend towards lower-energy optimal solutions. The entire process is carried out through time-controlled iterative loops until convergence.
[0067] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention, and should be understood that the scope of protection of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the spirit of the invention, and these modifications and combinations are still within the scope of protection of this invention.
Claims
1. A method for implementing a simplified quantum Monte Carlo circuit, characterized in that, Includes the following steps: S1. Generate the current replica p-bit network and calculate the total energy of the current replica p-bit network; S2. Register the output state of the current replica p-bit network; S3. Based on the total energy and registered items of the current replica p-bit network, sample and update the next replica p-bit network.
2. The quantum Monte Carlo simplified circuit implementation method according to claim 1, characterized in that, In step S1, when generating the current replica p-bit network, the binary forms of the first undetermined factor and the second undetermined factor are mapped one-to-one with the p-bit units of the current replica p-bit network, and the total energy of the current replica p-bit network is calculated.
3. The quantum Monte Carlo simplified circuit implementation method according to claim 2, characterized in that, In S1, each p-bit unit corresponds to a binary bit and generates a random initial value.
4. The quantum Monte Carlo simplified circuit implementation method according to claim 1, characterized in that, S3 includes the following sub-steps: S31. Sample the state value of each p-bit in the current replica p-bit network and calculate the partial derivative of the total energy corresponding to that p-bit. S32. The partial derivatives of the p-bit are scaled and adjusted by a weighting function and synthesized with the register term to serve as the input voltage signal for updating the corresponding p-bit unit in the next copy p-bit network. S33. Apply the input voltage signal to the hardware unit based on the p-bit functional device and convert the input voltage value of the input voltage signal into a random output bit state.
5. The quantum Monte Carlo simplified circuit implementation method according to claim 4, characterized in that, In step S33, the input voltage value of the input voltage signal is converted into a random output bit state by utilizing the sigmoid probability response curve characteristics of the p-bit hardware unit.
6. The method for implementing a simplified quantum Monte Carlo circuit according to claim 1, characterized in that, In step S2, the output state of the current replica p-bit network is delayed and then used as a coupling term to provide input support for the sampling update of the next replica p-bit network.
7. The quantum Monte Carlo simplified circuit implementation method according to claim 6, characterized in that, In step S2, during the registration process, a hardware registration delay unit is used to achieve delayed transmission of status signals.