Discharge protection circuit of chip and chip

Abstract

The embodiment of the invention provides a chip discharge protection circuit and a chip, the chip protection circuit comprises a plurality of input and output modules, each input and output module is provided with a ground wire network input and output port; the ground wire network is connected with the ground wire network input and output ports of the plurality of input and output modules; an isolation assembly and a resistor which are connected in parallel are arranged on a ground wire connected between two adjacent input and output modules; the isolation assembly is used for isolating ground wire network signals among the input and output modules; the resistor is used for transmitting static electricity among the input and output modules; when any input and output module generates electrostatic discharge, static electricity is discharged through the ground wire network input and output port of the input and output module, or is transmitted to the ground wire network input and output ports of other input and output modules through a resistor for discharging. Therefore, electrostatic discharge is carried out through a plurality of discharge paths, and the electrostatic discharge capability and efficiency of the chip are improved.

Description

Technical Field

[0001] This invention relates to the field of discharge protection circuit technology, and in particular to a discharge protection circuit for a chip and a chip. Background Technology

[0002] Currently, electrostatic discharge (ESD) protection of chips directly affects their reliability. In integrated circuit chip design, the design of ESD protection circuits is an indispensable part of the chip. In related technologies, static electricity in the chip's input / output modules can only be discharged through the ports in the corresponding input / output modules. This method limits the ESD discharge path to a specific area or a specific discharge path, which greatly affects the chip's ESD discharge capability and efficiency. Summary of the Invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide a discharge protection circuit for a chip and a chip that overcomes or at least partially solves the above problems.

[0004] In a first aspect, embodiments of the present invention provide a discharge protection circuit for a chip, the discharge protection circuit comprising: Multiple input / output modules, each of which is provided with a ground network input / output port; The ground network is connected to the ground network input / output ports of the plurality of input / output modules; An isolation component and a resistor connected in parallel are provided on the ground wire connecting two adjacent input / output modules; The isolation component is used to isolate the ground network signals between the various input / output modules; The resistor is used to transfer static electricity between the various input / output modules; When any of the input / output modules generates electrostatic discharge, the static electricity is discharged through the ground network input / output port of the input / output module itself, or transmitted through the resistor to the ground network input / output port of other input / output modules for discharge.

[0005] Optionally, the isolation component includes two reverse diodes connected in parallel.

[0006] Optionally, the discharge protection circuit further includes: Chip framework; The ground network input / output ports in each of the input / output modules are connected to the chip frame; When any of the input / output modules generates electrostatic discharge, the static electricity is transmitted to the chip frame through the ground network input / output port and resistor, so as to discharge the static electricity through the chip frame.

[0007] Optionally, all of the ground network input / output ports include: a first input / output port; The first input / output port is connected to the chip frame; When any of the input / output modules generates electrostatic discharge, the static electricity is transmitted to the chip frame through the first input / output port and the resistor, so as to discharge the static electricity through the chip frame.

[0008] Optionally, the discharge protection circuit further includes: The discharge pin is connected to the chip frame; When any of the input / output modules generates electrostatic discharge, the static electricity is transmitted to the chip frame through the ground network input / output port and the resistor. The chip frame then transmits the static electricity to the discharge pin to discharge the static electricity.

[0009] Optionally, the ground network input / output port in some of the input / output modules includes: a second input / output port; The second input / output port is connected to its own discharge pin; When any part of the input / output module generates electrostatic discharge, the static electricity is transmitted through the second input / output port and a resistor to its own discharge pin and the discharge pins of other input / output modules in the part of the input / output module, so as to discharge the static electricity through the discharge pins.

[0010] Optionally, some of the input / output modules are provided with a third input / output port, which is connected to the ground network input / output port in the corresponding input / output module; When electrostatic discharge occurs at the third input / output port of any part of the input / output module, the static electricity is discharged through the ground network input / output port corresponding to the third input / output port.

[0011] Optionally, the discharge protection circuit further includes: Multiple non-bleeder pins, each of the non-bleeder pins being connected to a third input / output port in a portion of the input / output module; When any of the non-discharge pins generates electrostatic discharge, the static electricity is discharged through the ground network input / output port corresponding to the third input / output port.

[0012] Optionally, the resistor is disposed in a metal layer adjacent to the isolation component.

[0013] In a second aspect, embodiments of the present invention provide a chip including the discharge protection circuit of the chip as described in the first aspect above.

[0014] The embodiments of the present invention have the following advantages: In this embodiment of the invention, the discharge protection circuit includes: multiple input / output modules, each input / output module having a ground network input / output port; a ground network connected to the ground network input / output ports of the multiple input / output modules; an isolation component and a resistor connected in parallel on the ground line connecting two adjacent input / output modules; the isolation component is used to isolate the ground network signals between the input / output modules; the resistor is used to transmit static electricity between the input / output modules; when any input / output module generates static discharge, the static electricity is discharged through the input / output module's own ground network input / output port, or transmitted through the resistor to the ground network input / output ports of other input / output modules for discharge. Therefore, when any input / output module generates static electricity, the static electricity is not only discharged through the ground network input / output circuit of the input / output module that generated the static electricity, but also through the ground network input / output ports of other input / output modules, thus achieving static electricity discharge through multiple discharge paths, improving the chip's static electricity discharge capability and efficiency. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a structural block diagram of a chip discharge protection circuit provided in an embodiment of the present invention; Figure 2 This is a structural block diagram of another chip discharge protection circuit provided in an embodiment of the present invention.

[0017] Figure label: Chip-10, Input / Output Module-01, First Input / Output Module-011, Second Input / Output Module-012, Third Input / Output Module-013, Fourth Input / Output Module-014, Ground Network Input / Output Port-0111, First Input / Output Port-01111, Second Input / Output Port-01112, Third Input / Output Port-0112, Ground Network-02, Isolation Component-03, First Isolation Component-031, Second Isolation Component-032, Third Isolation Component-033, Resistor-04, First Resistor-041, Second Resistor-042, Third Resistor-043, Chip Frame-05, Bleeding Pin-06, First Pin-061, Second Pin-062, Third Pin-063, Non-Bleeding Pin-07, Fourth Pin-071, Fifth Pin-072, Sixth Pin-073, Analog Circuit Module-08, Digital Circuit Module-09, External Ground Network-20. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] The terms "first," "second," etc., used in the specification and claims of this invention are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0020] In related technologies, static electricity in the input / output modules of a chip can only be discharged through the ports of the corresponding input / output modules. This method limits the static discharge path to a specific area or path, greatly affecting the chip's static discharge capability and efficiency. To solve the above technical problems, this invention provides a chip discharge protection circuit. The core concept of the discharge protection circuit is that it includes: multiple input / output modules, each with a ground network input / output port; a ground network connected to the ground network input / output ports of the multiple input / output modules; a parallel isolation component and a resistor on the ground line connecting two adjacent input / output modules; an isolation component for isolating ground network signals between the input / output modules; and a resistor for transmitting static electricity between the input / output modules. When any input / output module generates static discharge, the static electricity is discharged through its own ground network input / output port, or transmitted through the resistor to the ground network input / output ports of other input / output modules for discharge. Therefore, when static electricity is generated in any input / output module, it can be discharged not only through the ground network input / output circuit of the input / output module that generated the static electricity, but also through the ground network input / output ports of other input / output modules. This multiple discharge paths improve the chip's static electricity discharge capability and efficiency.

[0021] like Figure 1 The diagram shows a structural block diagram of a chip discharge protection circuit according to an embodiment of the present invention. The chip discharge protection circuit specifically includes: Multiple input / output modules 01, each of which is provided with a ground network input / output port 0111; Ground network 02 is connected to the ground network input / output port 0111 of the plurality of input / output modules 01; An isolation component 03 and a resistor 04 are connected in parallel on the ground wire connecting two adjacent input / output modules 01; The isolation component 03 is used to isolate the ground network signals between each of the input / output modules 01; The resistor 04 is used to transfer static electricity between the various input / output modules 01; When any of the input / output modules 01 generates electrostatic discharge, the static electricity is discharged through the input / output port 0111 of the ground network 02 of the input / output module 01 itself, or transmitted through the resistor 04 to the input / output port 0111 of the ground network 02 of other input / output modules 01 for discharge.

[0022] In this invention, the chip 10 may include multiple input / output modules 01, each input / output module 01 may be provided with a ground network input / output port 0111, and the ground network input / output ports 0111 of the multiple input / output modules 01 may be connected through a ground network 02. An isolation component 03 and a resistor 04 connected in parallel may be provided on the ground line between each two adjacent input / output modules 01. The isolation component 03 is used to isolate the ground network signals between each input / output module 01, so that the ground network signals in each input / output module 01 are independent of each other, and the resistor 04 is used to transmit static electricity between each input / output module 01.

[0023] In this invention, when any input / output module 01 generates electrostatic discharge, for example, when the first input / output module 01 generates electrostatic discharge, the static electricity can be discharged through the ground network input / output port 0111 in the first input / output module 011, or the static electricity can be transmitted to the ground network input / output port 0111 in other input / output modules 01 through the resistor 04, and discharged through the ground network input / output port 0111 in other input / output modules 01.

[0024] like Figure 2 The diagram shows a structural block diagram of a discharge protection circuit for another chip provided in an embodiment of the present invention.

[0025] In this embodiment of the invention, the plurality of input / output modules 01 may include a first input / output module 011, a second input / output module 012, a third input / output module 013, and a fourth input / output module 014.

[0026] In this embodiment of the invention, the isolation component 03 may include two reverse diodes connected in parallel.

[0027] In this invention, the isolation component 03 may include a first isolation component 031, a second isolation component 032, and a third isolation component 033. The first isolation component 031 may include a first diode and a second diode connected in parallel. The first diode and the second diode are reverse diodes. The anode of the first diode may be connected to the first input / output module 011, and the cathode of the first diode may be connected to the second input / output module 012. The cathode of the second diode may be connected to the first input / output module 011, and the anode of the second diode may be connected to the second input / output module 012, thereby isolating the ground network signal between the first input / output module 011 and the second input / output module 012 through the first diode and the second diode.

[0028] The second isolation component 032 may include a third diode and a fourth diode connected in parallel. The third diode and the fourth diode are reverse diodes. The anode of the third diode can be connected to the second input / output module 012, and the cathode of the third diode can be connected to the third input / output module 013. The cathode of the fourth diode can be connected to the second input / output module 012, and the anode of the fourth diode can be connected to the third input / output module 013. This isolates the ground network 02 signal between the second input / output module 012 and the third input / output module 013 through the third diode and the fourth diode.

[0029] The third isolation component 033 may include a fifth diode and a sixth diode connected in parallel. The fifth diode and the sixth diode are reverse diodes. The anode of the fifth diode can be connected to the third input / output module 013, and the cathode of the fifth diode can be connected to the fourth input / output module 014. The cathode of the sixth diode can be connected to the third input / output module 013, and the anode of the sixth diode can be connected to the fourth input / output module 014, thereby isolating the ground network signal between the third input / output module 013 and the fourth input / output module 014 through the fifth diode and the sixth diode.

[0030] In this invention, the design of the isolation component 03 with two reverse diodes connected in parallel can effectively isolate the ground network signal between two adjacent input / output modules 01, thereby making the ground network signal of each input / output module 01 independent of each other.

[0031] In this invention, the number of resistors 04 can be three, the same as the number of isolation components 03, namely a first resistor 041, a second resistor 042 and a third resistor 043. The first resistor 041 can be connected in parallel with the first isolation component 031, the second resistor 042 can be connected in parallel with the second isolation component 032, and the third resistor 043 can be connected in parallel with the third isolation component 033.

[0032] In this embodiment of the invention, resistor 04 is disposed in a metal layer adjacent to isolation component 03.

[0033] In this invention, resistor 04 is used for current limiting protection, signal integrity control, etc., and features low resistivity, small temperature coefficient, and high precision. Resistor 04 can be placed in the metal layer above the isolation component 03. The placement of resistor 04 uses the metal layer already present in chip 10, eliminating the need for adding an additional metal layer and having no impact on cost.

[0034] In this invention, resistor 04 can be a metal resistor 04. Taking UMC's 55nm process as an example, when the inner 0.2µm thick metal layer is used as a metal resistor 04, the resistance value of 04 with a width of 10µm and a length of 10µm is only 105.363mΩ. When the top 0.85µm thick metal layer is used as a metal resistor, the resistance value of 04 with a width of 10µm and a length of 10µm is only 22mΩ.

[0035] In this embodiment of the invention, the discharge protection circuit may further include: a chip frame 05; ground network input / output ports 0111 in each input / output module 01 are connected to the chip frame 05; when any input / output module 01 generates electrostatic discharge, the static electricity is transmitted to the chip frame 05 through the ground network input / output port 0111 and the resistor 04, so as to discharge the static electricity through the chip frame 05.

[0036] In this invention, the ground network input / output ports 0111 of the first input / output module 011, the second input / output module 012, the third input / output module 013, and the fourth input / output module 014 can be connected to the chip frame 05, which is located within the chip 10. When any one of the input / output modules 011, 012, or 013 generates electrostatic discharge, the static electricity can be transmitted to the chip frame 05 through the ground network input / output ports 0111 of the first input / output module 011, 012, 013, and 014, as well as the resistor 04, and then discharged through the chip frame 05. Thus, when an input / output module 01 generates electrostatic discharge, it can discharge not only through its own ground network input / output port 0111, but also through the ground network input / output ports 0111 of other input / output modules 011, increasing the capacity and efficiency of static discharge.

[0037] In this embodiment of the invention, all ground network input / output ports 0111 include: a first input / output port 01111; the first input / output port 01111 is connected to the chip frame 05; when any input / output module 01 generates electrostatic discharge, the static electricity is transmitted to the chip frame 05 through the first input / output port 01111 and the resistor 04, so as to discharge the static electricity through the chip frame 05.

[0038] In this invention, each input / output module 01's ground network input / output port 0111 can include a first input / output port 01111, which can be connected to the chip frame 05. When any one of the first input / output modules 01, second input / output module 012, or third input / output module 013 generates electrostatic discharge, the static electricity can be transmitted to the chip frame 05 through the first input / output port 01111 of the first input / output module 011, second input / output module 012, third input / output module 013, and fourth input / output module 014, as well as the resistor 04, and then discharged through the chip frame 05. Therefore, when an input / output module 01 generates electrostatic discharge, it can discharge not only through its own ground network 02 input / output port 0111, but also through the ground network 02 input / output ports 0111 of other input / output modules 01, increasing the capacity and efficiency of electrostatic discharge.

[0039] It should be noted that, in this invention, the ground wires connected to the ground network input / output ports 0111 of the multiple input / output modules 01 can be first ground network lines, and the first ground network can be VSS. The first input / output port 01111 in the first input / output module 011 can be an input / output port of the first ground network; the first input / output port 01111 in the second input / output module 012 can be an input / output port of the second ground network, and the second ground network can be VSSA. The first input / output port 01111 in the third input / output module 013 can be an input / output port of the third ground network, and the third ground network can be VSSD. The first input / output port 01111 in the fourth input / output module 014 can be an input / output port of the first ground network.

[0040] In this embodiment of the invention, the discharge protection circuit further includes: a discharge pin 06 connected to the chip frame 05; when any input / output module 01 generates electrostatic discharge, the static electricity is transmitted to the chip frame 05 through the ground network input / output port 0111 and the resistor 04, and the chip frame 05 transmits the static electricity to the discharge pin 06 to discharge the static electricity through the discharge pin 06.

[0041] In this invention, the discharge pin 06 may include a first pin 061, which can be connected to the chip frame 05. When any one of the input / output modules 01 (first, second, and third) generates electrostatic discharge, the static electricity can be transmitted to the chip frame 05 through the first input / output port 01111 of the first, second, third, and fourth input / output modules 011 and the resistor 04. The chip frame 05 then transmits the static electricity to the first pin 061 for discharge. Thus, when an input / output module 01 generates electrostatic discharge, it can discharge not only through its own ground network input / output port 0111, but also through the ground network input / output ports 0111 of other input / output modules 01 to the chip frame 05. The chip frame 05 then transmits the static electricity to the discharge pin 06 for discharge, increasing the capacity and efficiency of static discharge.

[0042] In this embodiment of the invention, the ground network input / output port 0111 in the partial input / output module 01 includes: a second input / output port 01112; the second input / output port 01112 is connected to its own discharge pin 06; when any partial input / output module 01 generates electrostatic discharge, the static electricity is transmitted through the second input / output port 01112 and the resistor 04 to its own discharge pin 06 and the discharge pin 06 of other input / output modules 01 in the partial input / output module 01, so as to discharge the static electricity through the discharge pin 06.

[0043] In this invention, some input / output modules 01 can be a first input / output module 011, a second input / output module 012, and a third input / output module 013. Each of the first input / output module 011, second input / output module 012, and third input / output module 013 can include a second input / output port 01112. The discharge pin 06 can also include a second pin 062 and a third pin 063. The second input / output port 011 of the first input / output module 011 can be connected to its own first pin 061; the second input / output port 01112 of the second input / output module 012 can be connected to its own second pin 062; and the second input / output port 01112 of the third input / output module 013 can be connected to its own third pin 063. When any one of the input / output modules 01 (first input / output module 011, second input / output module 012, and third input / output module 013) generates electrostatic discharge, the static electricity can be transmitted through the second input / output ports 01112 of the first input / output module 011, second input / output module 012, and third input / output module 013, as well as the resistor 04, to the first pin 061, second pin 062, and third pin 063 for discharge. Therefore, when an input / output module 01 generates electrostatic discharge, it can not only discharge static electricity through its own second input / output port 01112, but also transmit static electricity to the discharge pin 06 through the second input / output ports 01112 of other input / output modules 01, where the discharge pin 06 discharges the static electricity, increasing the capability and efficiency of static electricity discharge.

[0044] In this invention, the second input / output port 01112 in the first input / output module 011 can be an input / output port of a first ground network, and the second input / output port 01112 in the second input / output module 012 can be an input / output port of a second ground network, which can be a VSSA. The second input / output port 01112 in the third input / output module 013 can be an input / output port of a third ground network, which can be a VSSD.

[0045] In this embodiment of the invention, some input / output modules 01 are provided with a third input / output port 0112, which is connected to the ground network input / output port 0111 in the corresponding input / output module 01; when electrostatic discharge occurs at the third input / output port 0112 of any part of the input / output module 01, the static electricity is discharged through the ground network input / output port 0111 corresponding to the third input / output port 0112.

[0046] In this invention, some input / output modules 01 can be a first input / output module 011, a second input / output module 012, and a third input / output module 013. Each of these modules can include a third input / output port 0112. When electrostatic discharge occurs at any of the third input / output ports 0112 of the first, second, and third input / output modules 011, the static electricity can be discharged through the ground network 02 at the input / output port 0111. Therefore, when electrostatic discharge occurs at the third input / output port 0112 of the input / output module 01, the static electricity can be discharged through the ground network at the input / output port 02, increasing the capacity and efficiency of static electricity discharge.

[0047] In this embodiment of the invention, the discharge protection circuit further includes: a plurality of non-discharge pins 07, each non-discharge pin 07 being connected to a third input / output port 0112 in a partial input / output module 01; when any non-discharge pin 07 generates electrostatic discharge, the static electricity is discharged through the ground network input / output port 0111 corresponding to the third input / output port 0112.

[0048] In this invention, the discharge protection circuit may further include multiple non-discharge pins 07, which may be a fourth pin 071, a fifth pin 072, and a sixth pin 073. The fourth pin 071 may be connected to the third input / output port 0112 in the first input / output module 011, the fifth pin 072 may be connected to the third input / output port 0112 in the second input / output module 012, and the sixth pin 073 may be connected to the third input / output port 0112 in the third input / output module 013. When electrostatic discharge occurs at any of the fourth pin 071, the fifth pin 072, or the sixth pin 073, the static electricity can be discharged through the ground network input / output port 0111 corresponding to the third input / output port 0112 in each input / output module 01, thereby increasing the electrostatic discharge capability and efficiency.

[0049] To better understand the embodiments of the present invention, the following is a summary. Figure 2 In detail, the discharge protection circuit may include an analog circuit module 08, a digital circuit module 09, a first input / output module 011, a second input / output module 012, a third input / output module 013, a fourth input / output module 014, a first isolation component 031, a second isolation component 032, a third isolation component 033, a first resistor 041, a second resistor 042, a third resistor 043, a chip frame 05, a discharge pin 06, and a non-discharge pin 07.

[0050] The first input / output module 011 may include: a first input / output port 01111, a second input / output port 01112, and a third input / output port 0112, wherein the first input / output port and the second input / output port 01112 in the first input / output module 011 can be VSS ports, and the third input / output port 0112 in the first input / output module 011 can be an input / output port for digital circuit signals.

[0051] The second input / output module 012 may include: a first input / output port 01111, a second input / output port 01112, and a third input / output port 0112, wherein the first input / output port and the second input / output port 01112 in the second input / output module 012 can be VSSA ports, and the third input / output port 0112 in the second input / output module 012 can be an input / output port for analog circuit signals.

[0052] The third input / output module 013 may include: a first input / output port 01111, a second input / output port 01112, and a third input / output port 0112. The first input / output port and the second input / output port 01112 in the third input / output module 013 may be VSSD ports, and the third input / output port 0112 in the third input / output module 013 may be an input / output port for VCCD power signals.

[0053] The bleeder pin 06 may include the first pin 061, the second pin 062 and the third pin 063; the non-bleeder pin 07 may include the fourth pin 071, the fifth pin 072 and the sixth pin 073.

[0054] Analog circuit module 08 is connected to VCCA and the third input / output port 0112 of the second input / output module 012, and is also connected to the first input / output port 01111 of the second input / output module 012 via VSSA. VCCA is the power supply for analog circuit module 08, and VSSA is the ground for the analog circuit.

[0055] Digital circuit module 09 is connected to VCCD, which is also connected to the third input / output port 0112 of the third input / output module 013. Digital circuit module 09 is connected to the first input / output port 01111 of the third input / output module 013 via VSSD. VCCD is the power supply for digital circuit module 09, and VSSD is the ground for the digital circuit.

[0056] The first input / output port 01111 of the first input / output module 011 is connected to the chip frame 05 via VSS. The second input / output port 01112 of the first input / output module 011 is connected to the first pin 061 via VSS. The first pin 061 is also connected to the chip frame 05. The third input / output port 0112 of the first input / output module 011 is connected to VCC, VSS, and the fourth pin 071, respectively. VCC is the power supply for the third input / output port 0112 of the first input / output module 011, and VSS is the ground for the third input / output port 0112 of the first input / output module 011.

[0057] The first input / output port 01111 in the second input / output module 012 is connected to the chip frame 05 via VSSA, the second input / output port 01112 in the second input / output module 012 is connected to the second pin 062 via VSSA, and the third input / output port 0112 in the second input / output module 012 is connected to the fifth pin 072.

[0058] The first input / output port 01111 in the third input / output module 013 is connected to the chip frame 05 via VSSD. The second input / output port 01112 in the third input / output module 013 is connected to the third pin 063 via VSSD. The third input / output port 0112 in the third input / output module 013 is connected to the sixth pin 073 via VCCD.

[0059] The first input / output port 01111 in the fourth input / output module 014 is connected to the chip frame 05 via VSS, and the first input / output port 01111 in the third input / output module 013 is also connected to VCC.

[0060] The first isolation component 031 is connected in parallel with the first resistor 041. One end of the first isolation component 031 and the first resistor 041 are respectively connected to the second input / output port 01112 of the first input / output module 011, and the other end of the first isolation component 031 and the first resistor 041 are respectively connected to the second input / output module 012.

[0061] The second isolation component 032 is connected in parallel with the second resistor 042. One end of the second isolation component 032 and the second resistor 042 are respectively connected to the second input / output port 01112 of the second input / output module 012, and the other end of the second isolation component 032 and the second resistor 042 are respectively connected to the third input / output module 013.

[0062] The third isolation component 033 and the third resistor 043 are connected in parallel. One end of the third isolation component 033 and the third resistor 043 are respectively connected to the second input / output port 01112 of the third input / output module 013, and the other end of the third isolation component 033 and the third resistor 043 are respectively connected to the first input / output port 01111 of the fourth input / output module 014.

[0063] exist Figure 2 C1 represents the wafer body of chip 10. Only representative parts of the internal modules are shown in the simplified display. Figure 2 The C2 region in the diagram represents the specific frame and pin structure of the chip 10 wafer after packaging.

[0064] In this invention, in addition to chip 10, an external ground network 20 may also be included, which can be a board-level GND. The first pin 061 is connected to the external ground network 20 through VSS, the second pin 062 is connected to the external ground network 20 through VSSA, and the third pin 063 is connected to the external ground network 20 through VSSD.

[0065] When electrostatic discharge occurs at the fourth pin 071, the static electricity is conducted into the ground network VSS, VSSA, and VSSD. Then, it is directly discharged to the first pin 061, the second pin 062, and the third pin 063 through the second input / output ports 01112 of the first input / output module 011, the second input / output port 01112 of the second input / output module 012, and the second input / output port 01112 of the third input / output module 013. Alternatively, the static electricity is discharged to the chip frame 05 through the first input / output ports 01111 of the first input / output module 011, the first input / output port 01111 of the second input / output module 012, the first input / output port 01111 of the third input / output module 013, and the first input / output port 01111 of the fourth input / output module 014. Finally, the chip frame 05 discharges the static electricity to the first pin 061.

[0066] When electrostatic discharge occurs at the fifth pin 072, the static electricity is conducted into the ground network VSS, VSSA, and VSSD. Then, it is directly discharged to the first pin 061, the second pin 062, and the third pin 063 through the second input / output ports 01112 of the first input / output module 011, the second input / output port 01112 of the second input / output module 012, and the second input / output port 01112 of the third input / output module 013. Alternatively, the static electricity is discharged to the chip frame 05 through the first input / output ports 01111 of the first input / output module 011, the first input / output port 01111 of the second input / output module 01201, the first input / output port 01111 of the third input / output module 013, and the first input / output port 01111 of the fourth input / output module 014. Finally, the chip frame 05 discharges the static electricity to the first pin 061.

[0067] When electrostatic discharge occurs at pin 073, the static electricity is conducted into the ground network VSS, VSSA, and VSSD. Then, it is directly discharged to pins 061, 062, and 063 through the second input / output ports 01112 of the first input / output module 011, the second input / output port 01112 of the second input / output module 012, and the second input / output port 01112 of the third input / output module 013. Alternatively, the static electricity is discharged to the chip frame 05 through the first input / output ports 01111 of the first input / output module 011, the first input / output port 01111 of the second input / output module 012, the first input / output port 01111 of the third input / output module 013, and the first input / output port 01111 of the fourth input / output module 014. Finally, the chip frame 05 discharges the static electricity to pin 061.

[0068] In this invention, no matter which part generates electrostatic discharge, the electrostatic energy can be discharged to the outside through all the ground network 02, which effectively increases the electrostatic discharge discharge path and improves the protection capability of chip 10.

[0069] In this embodiment of the invention, the discharge protection circuit includes: multiple input / output modules, each input / output module having a ground network input / output port; a ground network connected to the ground network input / output ports of the multiple input / output modules; an isolation component and a resistor connected in parallel on the ground line connecting two adjacent input / output modules; the isolation component is used to isolate the ground network signals between the input / output modules; the resistor is used to transmit static electricity between the input / output modules; when any input / output module generates static discharge, the static electricity is discharged through the input / output module's own ground network input / output port, or transmitted through the resistor to the ground network input / output ports of other input / output modules for discharge. Therefore, when any input / output module generates static electricity, the static electricity is not only discharged through the ground network input / output circuit of the input / output module that generated the static electricity, but also through the ground network input / output ports of other input / output modules, thus achieving static electricity discharge through multiple discharge paths, improving the chip's static electricity discharge capability and efficiency.

[0070] This invention also provides a chip, including the discharge protection circuit of the chip as described in the above embodiments.

[0071] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0072] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0073] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0074] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0075] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0076] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0077] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0078] The discharge protection circuit and chip of the present invention have been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The above description of the embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A discharge protection circuit for a chip, characterized in that, The discharge protection circuit includes: Multiple input / output modules, each of which is provided with a ground network input / output port; The ground network is connected to the ground network input / output ports of the plurality of input / output modules; An isolation component and a resistor connected in parallel are provided on the ground wire connecting two adjacent input / output modules; The isolation component is used to isolate the ground network signals between the various input / output modules; The resistor is used to transfer static electricity between the various input / output modules; When any of the input / output modules generates electrostatic discharge, the static electricity is discharged through the ground network input / output port of the input / output module itself, or transmitted through the resistor to the ground network input / output port of other input / output modules for discharge.

2. The discharge protection circuit for the chip according to claim 1, characterized in that, The isolation component includes two reverse diodes connected in parallel.

3. The discharge protection circuit for the chip according to claim 1, characterized in that, The discharge protection circuit further includes: Chip framework; The ground network input / output ports in each of the input / output modules are connected to the chip frame; When any of the input / output modules generates electrostatic discharge, the static electricity is transmitted to the chip frame through the ground network input / output port and resistor, so as to discharge the static electricity through the chip frame.

4. The discharge protection circuit for the chip according to claim 3, characterized in that, All of the aforementioned ground network input / output ports include: a first input / output port; The first input / output port is connected to the chip frame; When any of the input / output modules generates electrostatic discharge, the static electricity is transmitted to the chip frame through the first input / output port and the resistor, so as to discharge the static electricity through the chip frame.

5. The discharge protection circuit for the chip according to claim 1, characterized in that, The discharge protection circuit further includes: The discharge pin is connected to the chip frame; When any of the input / output modules generates electrostatic discharge, the static electricity is transmitted to the chip frame through the ground network input / output port and the resistor. The chip frame then transmits the static electricity to the discharge pin to discharge the static electricity.

6. The discharge protection circuit for the chip according to claim 1, characterized in that, The ground network input / output port in part of the input / output module includes: a second input / output port; The second input / output port is connected to its own discharge pin; When any part of the input / output module generates electrostatic discharge, the static electricity is transmitted through the second input / output port and a resistor to its own discharge pin and the discharge pins of other input / output modules in the part of the input / output module, so as to discharge the static electricity through the discharge pins.

7. The discharge protection circuit for the chip according to claim 1, characterized in that, Some of the input / output modules are provided with a third input / output port, which is connected to the ground network input / output port in the corresponding input / output module; When electrostatic discharge occurs at the third input / output port of any part of the input / output module, the static electricity is discharged through the ground network input / output port corresponding to the third input / output port.

8. The discharge protection circuit for the chip according to claim 7, characterized in that, The discharge protection circuit further includes: Multiple non-bleeder pins, each of the non-bleeder pins being connected to a third input / output port in a portion of the input / output module; When any of the non-discharge pins generates electrostatic discharge, the static electricity is discharged through the ground network input / output port corresponding to the third input / output port.

9. The discharge protection circuit for the chip according to claim 1, characterized in that, The resistor is disposed in a metal layer adjacent to the isolation component.

10. A chip, characterized in that, The discharge protection circuit includes the chip as described in any one of claims 1-9 above.

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