Comparator module based on one-step two-bit architecture, calibration method, ADC and chip

Abstract

The invention relates to a comparator module based on a one-step two-bit architecture, a calibration method, an ADC (Analog to Digital Converter) and a chip in the technical field of integrated circuits. The comparator module comprises two comparator groups Group 1 and Group 2 of a one-step two-bit architecture, and the Group 1 and the Group 2 jointly form a ping-pong type structure so as to alternately perform ping-pong operation in a comparison stage and a reset stage. And the comparators in the Group 1 and the Group 2 comprise channel selection switches arranged at the input ends of the comparators. According to the invention, a one-step two-bit successive approximation analog-to-digital converter and a ping-pong successive approximation analog-to-digital converter are fused, and a new comparator calibration mechanism is introduced, so that the calibration process of the comparator can be overlapped with the analog-to-digital conversion process in time, thereby avoiding the situation that the calibration time sequence occupies extra conversion time in the process, and improving the calibration accuracy of the analog-to-digital converter. And the sampling rate of the SAR ADC and the overall conversion speed of the analog-to-digital converter are obviously improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a comparator module based on a one-step two-bit architecture ping-pong type, a comparator offset calibration method, a SAR ADC based on a one-step two-bit architecture ping-pong type, and a chip. Background Technology

[0002] With the increasing demand for high-speed, low-power data conversion, asynchronous successive approximation analog-to-digital converters (ASAR ADCs) have gradually become a research hotspot due to their advantages such as not requiring a high-frequency global clock and high energy efficiency. To further improve the conversion speed, researchers have proposed an improved scheme with a one-step two-bit (2b / cycle) successive approximation structure. For example... Figure 1 As shown, existing one-step two-bit successive approximation analog-to-digital converters (ADCs) include: a clock generation circuit, a DAC array, a SAR logic circuit, a register module, and a one-step two-bit comparator structure. However, the above structure typically contains multiple comparators to achieve parallel decision-making or alternating operation. Since comparator offset voltage is difficult to avoid due to variations in process technology, voltage, and temperature, its presence can adversely affect conversion accuracy. Therefore, in practical applications, a comparator offset calibration mechanism is usually required. In existing technologies, comparator offset calibration often relies on additional calibration cycles. This calibration process is often performed sequentially with the normal analog-to-digital conversion process, resulting in a limited sampling rate and thus occupying effective conversion time. Summary of the Invention

[0003] To address the technical problem that existing comparator calibration processes are performed sequentially with normal analog-to-digital conversion processes, resulting in limited sampling rates and thus occupying effective conversion time, this invention provides a comparator module, calibration method, ADC, and chip based on a one-step two-bit architecture.

[0004] Firstly, this invention proposes a ping-pong comparator module based on a one-step two-bit architecture, comprising two one-step two-bit comparator groups, Group1 and Group2. Group1 and Group2 together form a ping-pong structure for alternating comparison and reset operations. Each comparator in Group1 and Group2 includes a channel selection switch at its input terminal. The channel selection switch controls the differential input signal and common-mode voltage VCM to alternately enter the comparator. When the differential input signal enters the comparator, the comparator enters the comparison and reset phases. When VCM enters the comparator, the comparator enters the calibration phase.

[0005] As a preferred example, Group1 and Group2 are used to receive the same input sampling signal. φsGroup 1 and Group 2 receive clock signals of different levels, respectively. φcomp 1. φcomp 2. φcomp 1. φcomp 2 is used to control the comparator to perform comparisons or reset.

[0006] As a preferred example, the channel selection switch includes: a non-inverting input terminal Vinp with a first switch SW0; a non-inverting reference voltage terminal Vrefp with a second switch SW1; an inverting input terminal Vinn with a third switch SW2; an inverting reference voltage terminal Vrefn with a fourth switch SW3; a first common-mode voltage input terminal VCM1 connected in parallel between Vinp and Vrefp via a fifth switch SW4 and a sixth switch SW5; and a second common-mode voltage input terminal VCM2 connected in parallel between Vinn and Vrefn via a seventh switch SW6 and an eighth switch SW7.

[0007] As a preferred example, the comparator determines the value based on the received sampled signal. φs Synchronously control the actions of SW0~SW3 or synchronously control the actions of SW4~SW7. When φs When the voltage is low, SW0 to SW3 are closed, and SW4 to SW7 are open. φs When the signal is high, SW0 to SW3 are open, and SW4 to SW7 are closed.

[0008] As a preferred example, within a comparison period, when φs When it is high, the clock signal received by Group1 f comp When the clock signal changes from high to low, Group 1 will first perform calibration, then reset. Group 2 receives the clock signal. φcomp When Group 2 changes from low to high, it should first be reset and then calibrated.

[0009] when φs When it is low level, φcomp 1. The level changes from high to low and alternates. Group 1 is first compared, then reset and alternates. φcomp 2 changes from low level to high level and alternates. Group2 is first reset, then compared and alternates.

[0010] As a preferred example, the differential input signal includes: an inverting signal voltage V Sig·DAC,N In-phase signal voltage V Sig·DAC,P Inverting reference voltage V Ref·DAC,N In-phase reference voltage V Ref·DAC,P .

[0011] Secondly, this invention proposes a comparator offset calibration method for calibrating the offset of the ping-pong comparator module based on a one-step two-bit architecture as described in the first aspect. The comparator offset calibration method includes: after Group1 and Group2 enter the calibration phase, introducing an in-phase calibration voltage Vcalp and an out-of-phase calibration voltage Vcaln based on the comparison results to calibrate the comparator and eliminate the input offset voltage of the comparator.

[0012] Thirdly, this invention proposes a one-step two-bit ping-pong SAR ADC, comprising: a clock generation circuit, a DAC array, a SAR logic circuit, a register module, and the one-step two-bit ping-pong comparator module mentioned in the first aspect. The clock generation circuit is used to generate the input sampling signal. φs The DAC array is used to generate the inverted signal voltage V. Sig·DAC,N In-phase signal voltage V Sig·DAC,P Inverting reference voltage V Ref·DAC,N and in-phase reference voltage V Ref·DAC,P SAR logic circuits are used to generate clock signals. φcomp 1. φcomp 2. The comparator module is used to determine the comparator's position based on the given information. φs , φcomp 1. f comp 2. V Sig·DAC,N V Sig·DAC,P V Ref·DAC,N V Ref·DAC,P Output the comparison result. The register module is used to store the comparison result of the comparator module.

[0013] As a preferred example, the DAC array includes: at least one signal digital-to-analog converter (DAC) and at least one reference DAC. The signal DAC is used to convert the analog differential signals Vin- and Vin+ input to the ADC into corresponding V signals via a sample-and-hold circuit. Sig·DAC,N V Sig·DAC,P The reference digital-to-analog converter is used to convert the common-mode voltage VCM of the input ADC to VCM via a sample-and-hold circuit. Ref·DAC,N V Ref·DAC,P .

[0014] Fourthly, the present invention proposes a chip that is packaged from the ping-pong SAR ADC based on a one-step two-bit architecture as described in the third aspect.

[0015] The beneficial effects of this invention are as follows: This invention integrates a one-step, two-bit successive approximation analog-to-digital converter (ADC) with a ping-pong successive approximation ADC. It leverages the advantages of the one-step, two-bit architecture (reducing the number of successive approximation comparisons) and the alternating operation of the ping-pong architecture. While maintaining conversion accuracy, it effectively reduces the number of comparison operations and saves time required for comparator reset, achieving a higher sampling rate. Furthermore, this invention introduces a novel comparator calibration mechanism, allowing the comparator calibration process to overlap with the analog-to-digital conversion process in time. This avoids the calibration timing consuming additional conversion time, significantly improving the sampling rate of the SAR ADC and the overall conversion speed of the ADC. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a diagram of the traditional one-step two-bit SAR ADC architecture in existing technology; Figure 2 This is an architecture diagram of the SAR ADC based on a one-step two-bit ping-pong architecture proposed in this invention; Figure 3 This is an architecture diagram of the comparator module proposed in this invention; Figure 4 This is a comparison diagram of the timing diagrams of the present invention and the traditional SAR ADC architecture. Detailed Implementation

[0018] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0021] Please refer to Figure 2 This embodiment provides a SAR ADC based on a one-step two-bit architecture ping-pong style, comprising: a clock generation circuit, a DAC array, a SAR logic circuit, a comparator module, and a register module. Compared with existing technologies, the key innovation of this invention lies in the novel logic design of the comparator module: the comparator module includes two one-step two-bit architecture comparator groups, Group1 and Group2. Group1 and Group2 together form a ping-pong structure, alternating between comparison and reset operations to output the comparison result. Compared with the existing comparator structure where the comparison and reset processes are executed sequentially in time, the processing logic of this invention, where the comparator module alternately participates in the comparison work, is completely different. The architecture and working principle of this invention are described in detail below with reference to the SAR ADC and the comparator module: In this embodiment, the DAC array includes two signal digital-to-analog converters (DACs) and two reference DACs. The signal DACs are used to sample the input signal and achieve successive voltage approximation throughout the conversion process. The reference DACs are used to generate the reference level required for each comparison. Specifically, the two signal DACs convert the analog differential signals Vin- and Vin+ input to the SAR ADC into inverted signal voltages V through a first sample-and-hold circuit. Sig·DAC,N In-phase signal voltage V Sig·DAC,P Two reference digital-to-analog converters (DACs) convert the common-mode voltage VCM of the input ADC into an inverting reference voltage V through a second sample-and-hold circuit. Ref·DAC,N In-phase reference voltage V Ref·DAC,P .

[0022] The clock generation circuit can adopt an asynchronous timing architecture, which provides the input sampling signal for the first sample-and-hold circuit and the comparator module. φs and provides a reference sampling signal for the second sample-and-hold circuit. f R This, in turn, controls the reference digital-to-analog converter to provide a reference level (V) for the comparator module. Ref·DAC,N V Ref·DAC,P The SAR logic circuit is used to implement the SAR control logic, and it generates clock signals that are input to Group1 and Group2 respectively. φcomp 1. φcomp2. And generate a reference control signal. f REFDAC Control reference digital-to-analog converter to V Ref·DAC,N V Ref·DAC,P The scale is reduced proportionally. The register module is used to store the comparison result of the comparator module and to switch the signal digital-to-analog converter according to the comparison result via the input control signal B.

[0023] In the comparator module, the comparators in Group1 and Group2 also differ from conventional comparators, as they additionally have a channel selection switch at the comparator input. This channel selection switch is used to control the differential input signal (i.e., V). Sig·DAC,N V Sig·DAC,P V Ref·DAC,N V Ref·DAC,P The differential input signal and the common-mode voltage VCM alternately enter the comparator. When the differential input signal enters the comparator, the comparator enters the comparison and reset phases. When VCM enters the comparator, the comparator enters the calibration phase. Specifically, as... Figure 3 As shown, the channel selection switches include: a non-inverting input terminal Vinp, a non-inverting reference voltage terminal Vrefp, an inverting input terminal Vinn, an inverting reference voltage terminal Vrefn, a first common-mode voltage input terminal VCM1, and a second common-mode voltage input terminal VCM2. VCM1 and VCM2 are both used to input VCM. Vinp is equipped with a first switch SW0. Vrefp is equipped with a second switch SW1. Vinn is equipped with a third switch SW2. Vrefn is equipped with a fourth switch SW3. VCM1 is connected to Vinp via a fifth switch SW4 and to Vrefp via a sixth switch SW5. VCM2 is connected to Vinn via a seventh switch SW6 and to Vrefn via an eighth switch SW7. Please refer again... Figure 2 Since both Group1 and Group2 are one-step two-bit architectures, meaning they contain three comparators COMP0 to COMP2 internally, the clock signal CLK of COMP0 to COMP2 in Group1 is input to... φcomp 1. In Group 2, the clock signal terminals CLK of COMP0 to COMP2 are all input. φcomp 2. Enter COMP0 through COMP2 in both Group1 and Group2. φs The enable signal EN is used, and the input signals for the channel selection switches of COMP0 to COMP2 in Group1 and Group2 are also the same. Taking Group1 as an example, the Vinp input V of COMP0 is... Sig·DAC,P , Vrefp input V Ref·DAC,P Vinn input V Sig·DAC,N 、Vrefn input V Ref·DAC,N The Vinp input of COMP1 is V. Sig·DAC,P, Vrefp input V Sig·DAC,P Vinn input V Sig·DAC,N 、Vrefn input V Sig·DAC,N The Vinp input of COMP2 is V. Sig·DAC,P , Vrefp input V Ref·DAC,N Vinn input V Sig·DAC,N 、Vrefn input V Ref·DAC,P COMP0 to COMP2 correspond to the in-phase output signal OP and the inverted output signal ON, respectively. Group 1 and Group 2 use three comparators COMP0 to COMP2 to make parallel decisions on the DAC array output within a single comparison cycle, achieving 2-bit quantization and thus improving the overall conversion speed of the SARADC.

[0024] Please refer to Figure 4 In part (a), the specific working process of the comparator module is as follows: Within one comparison cycle, it first enters the sampling phase. φs When the signal is high, the first sample-and-hold circuit samples, while SW0-SW3 are open and SW4-SW7 are closed. At this time, VCM inputs Group1 and Group2, and the comparator enters the calibration phase. Meanwhile, φs When high level, Group1 receives the clock signal. φcomp When level 1 goes high, Group 1 performs calibration, updating the in-phase calibration voltage Vcalp1 and the out-of-phase calibration voltage Vcaln1 based on the comparison result. Then... φcomp When Group 1 changes from high level to low level, it changes from calibration to reset. φs When high level, Group2 receives the clock signal. φcomp When 2 goes low, Group2 is reset. After the reset is complete, φcomp When level 2 changes from low to high, Group 2 changes from reset to calibration. Then, based on the comparison result, the in-phase calibration voltage Vcalp2 and the out-of-phase calibration voltage Vcaln2 are updated. After the sampling phase ends, the comparison and reset phase begins. φs When the signal goes low, SW0-SW3 close, and SW4-SW7 open. At this time, the differential input signals are input to Group1 and Group2. First... φcomp When 1 goes high, Group 1 begins comparison, and simultaneously... φcomp When level 2 goes low, Group 2 is reset. Then, after Group 1 finishes its comparison... φcomp When the level changes from low to high, Group 2 begins comparison, and... f comp When Group 1 changes from high to low, Group 1 begins its reset. After Group 2's comparison is complete, φcomp When the level changes from low to high, Group 1 begins comparison, and Group 2 is reset. This process alternates until the end of the comparison cycle. This process repeats every comparison cycle. Figure 4 As seen in section (b), the SAD ADC with the comparator module in this embodiment saves three reset and calibration times compared to the traditional SAD ADC architecture within one comparison cycle. In summary, this invention integrates a one-step two-bit successive approximation analog-to-digital converter (ADC) with a ping-pong successive approximation ADC, leveraging the reduced successive approximation comparisons of the one-step two-bit architecture and the alternating operation of the ping-pong architecture. Compared to the traditional one-step two-bit architecture, it saves the time required for comparator reset, thereby improving the time efficiency of the analog-to-digital conversion process. Furthermore, by introducing a new comparator calibration mechanism, the comparator calibration process can overlap and run in parallel with the analog-to-digital conversion process in time, avoiding the problem of occupying effective conversion time due to setting independent calibration cycles in the prior art. This saves the time overhead of calibration and improves the overall conversion speed and sampling rate of the ADC.

[0025] In another embodiment, a comparator module based on a one-step two-bit architecture ping-pong is also proposed, which is the comparator module in the aforementioned one-step two-bit architecture ping-pong SAR ADC.

[0026] In another embodiment, a comparator offset calibration method is proposed to calibrate the offset of the ping-pong comparator module based on a one-step two-bit architecture described in the above embodiment. The comparator offset calibration method includes: when Group1 and Group2 enter the calibration phase, introducing in-phase calibration voltage Vcalp and out-of-phase calibration voltage Vcaln based on the comparison result to calibrate the comparator and eliminate the input offset voltage. Specifically, based on the comparison result of VCM entering the comparator during the calibration phase, i.e., outputting a high or low level, the polarity (direction) of the comparator offset voltage is indicated. Subsequently, the magnitude of the offset voltage is obtained through a successive approximation method: the calibration logic gradually adjusts the approximation calibration voltage and observes when the comparator output flips. For example, if the initial output is 1, the approximation calibration voltage in this direction is continuously increased until the comparator output exactly flips to 0; this critical point corresponds to the magnitude of the offset voltage. After obtaining the polarity and magnitude of the offset voltage, the offset voltage is offset by inputting corresponding and precise Vcalp and Vcaln, thereby achieving comparator offset calibration.

[0027] In another embodiment, a chip is also proposed, which is packaged from the ping-pong SAR ADC based on the one-step two-bit architecture described in the above embodiments, so that the SAR ADC provided by the present invention can be manufactured, sold and used in the form of a chip.

[0028] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0029] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A comparator module based on a one-step two-bit ping-pong architecture, characterized in that, It includes: Two comparator groups, Group1 and Group2, with a one-step, two-bit architecture; Group 1 and Group 2 together form a ping-pong structure, using ping-pong operations of alternating comparison and reset; The comparators in Group 1 and Group 2 each include a channel selection switch located at the input of the comparator. The channel selection switch is used to control the differential input signal and the common-mode voltage VCM to alternately enter the comparator. When the differential input signal enters the comparator, the comparator enters the comparison stage and the reset stage. When VCM enters the comparator, the comparator enters the calibration stage.

2. The comparator module based on a one-step two-bit ping-pong architecture according to claim 1, characterized in that, Group 1 and Group 2 are used to receive the same input sampling signal. φs ; Group 1 and Group 2 receive clock signals of different levels respectively. φcomp 1. φcomp 2; φcomp 1. φcomp 2 is used to control the comparator to perform comparisons or reset.

3. The comparator module based on a one-step two-bit ping-pong architecture according to claim 1, characterized in that, The channel selection switch includes: The first switch SW0 is equipped with a non-inverting input terminal Vinp; The non-inverting reference voltage terminal Vrefp of the second switch SW1 is provided; Vinn is provided with an inverting input terminal of the third switch SW2; The inverting reference voltage terminal Vrefn of the fourth switch SW3 is provided; The first common-mode voltage input terminal VCM1 is connected in parallel between Vinp and Vrefp via the fifth switch SW4 and the sixth switch SW5. The second common-mode voltage input terminal VCM2 is connected in parallel between Vinn and Vrefn via the seventh switch SW6 and the eighth switch SW7.

4. The comparator module based on a one-step two-bit ping-pong architecture according to claim 3, characterized in that, The comparator determines the comparator based on the received sampled signal. φs Synchronously control the actions of SW0 to SW3 or synchronously control the actions of SW4 to SW7; when φs When the voltage is low, SW0 to SW3 are closed, and SW4 to SW7 are open; when... φs When the signal is high, SW0 to SW3 are open, and SW4 to SW7 are closed.

5. The comparator module based on a one-step two-bit ping-pong architecture according to claim 4, characterized in that, Within a comparison period, when φs When it is high, the clock signal received by Group1 φcomp When the clock signal changes from high to low, Group 1 first performs calibration, then reset; Group 2 receives the clock signal. φcomp When the level changes from low to high, Group 2 should be reset first, and then calibration should be performed. when φs When it is low level, φcomp 1. The level changes from high to low and alternates. Group 1 is first compared, then reset and alternates. φcomp 2 changes from low level to high level and alternates. Group2 is first reset, then compared and alternates.

6. The comparator module based on a one-step two-bit ping-pong architecture according to claim 1, characterized in that, The differential input signal includes: an inverting signal voltage V Sig·DAC,N In-phase signal voltage V Sig·DAC,P Inverting reference voltage V Ref·DAC,N In-phase reference voltage V Ref·DAC,P .

7. A comparator offset calibration method, characterized in that, It is used to perform offset calibration on the ping-pong comparator module based on a one-step two-bit architecture as described in any one of claims 1 to 6; Comparator offset calibration methods include: Once Group1 and Group2 enter the calibration phase, the comparators are calibrated using in-phase calibration voltage Vcalp and out-of-phase calibration voltage Vcaln based on the comparison results, in order to eliminate the input offset voltage of the comparators.

8. A SAR ADC based on a one-step two-bit architecture using a ping-pong style, characterized in that, It includes: A clock generation circuit is used to generate the input sampling signal. φs ; A DAC array, used to generate an inverted signal voltage V Sig·DAC,N In-phase signal voltage V Sig·DAC,P Inverting reference voltage V Ref·DAC,N and in-phase reference voltage V Ref·DAC,P ; SAR logic circuit, used to generate clock signals φcomp 1. φcomp 2; The comparator module based on a one-step two-bit ping-pong architecture as described in any one of claims 1 to 6 is used to... φs , φcomp 1. φcomp 2. V Sig·DAC,N V Sig·DAC,P V Ref·DAC,N V Ref·DAC,P Output the comparison results; A register module is used to store the comparison results of the comparator module.

9. The SAR ADC based on a one-step two-bit architecture ping-pong ADC according to claim 8, characterized in that, The DAC array includes: At least one signal-to-analog converter is used to convert the analog differential signals Vin- and Vin+ input to the ADC into corresponding V signals via a sample-and-hold circuit. Sig·DAC,N V Sig·DAC,P ; At least one reference digital-to-analog converter is used to convert the common-mode voltage VCM of the input ADC to VCM via a sample-and-hold circuit. Ref·DAC,N V Ref·DAC,P .

10. A chip, characterized in that, It is packaged as a ping-pong SAR ADC based on a one-step two-bit architecture as described in claim 8 or 9.

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