Electric property quantitative analysis method of parallel TSV structure and parallel TSV detection structure

Abstract

The invention discloses an electrical property quantitative analysis method of a parallel TSV structure and a parallel TSV detection structure, and the electrical property quantitative analysis method is characterized in that the parallel TSV detection structure is designed and formed by at least taking parallel configuration parameters of TSV through holes as test variables. The method comprises the following steps: synchronously obtaining test results of electrical parameters or electrical related parameters of each test unit in a parallel TSV detection structure, forming a correlation model of test variables and the test results, and carrying out quantitative analysis on the relationship between the parallel configuration parameters and the electrical parameters of the parallel TSV structure based on the correlation model. Therefore, the influence of the parallel parameters on the electrical performance can be accurately evaluated. Furthermore, the association rule of different parallel configurations and electrical properties can be determined, and data support is provided for model selection of TSV parallel schemes in a three-dimensional integrated system. Meanwhile, the risks of signal distortion, poor contact and thermal failure caused by parameter mismatching and interlayer alignment offset of the parallel TSVs can be reduced, and the yield and reliability of high-power three-dimensional integrated products are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing technology, specifically to an electrical quantitative analysis method for a parallel TSV structure and a parallel TSV detection structure. Background Technology

[0002] As semiconductor devices continue to evolve towards higher density, higher performance, and smaller size, three-dimensional (3D) stacking technology has become a key path to break through the bottleneck of traditional two-dimensional planar integration and further improve chip performance and energy efficiency. In this technology system, through-silicon vias (TSVs) are the core structure for realizing vertical chip stacking and interlayer electrical interconnection. The quality of their electrical performance directly determines the signal integrity, power consumption level, and long-term reliability of the final device.

[0003] When multiple TSVs are used in parallel, inconsistencies in manufacturing processes, differences in material distribution, and parasitic effects may lead to problems such as uneven current distribution, resistance differences, and local hot spots, thereby affecting the overall circuit performance.

[0004] In practical applications, to meet the requirements of high current transmission, reduce overall on-resistance, or improve yield, multiple TSVs are often required to work together in parallel. However, in parallel applications, due to microscopic inconsistencies in the manufacturing process (such as differences in etching depth, sidewall morphology, and barrier / seed layer coverage), non-uniformity of material distribution, and unavoidable parasitic capacitance and inductance effects, the current distribution among the parallel branches becomes severely uneven, and resistance mismatch occurs, leading to excessively high local current density and hot spots. These problems not only cause additional power loss and signal distortion but also accelerate electromigration, posing a serious threat to the function, performance, and reliability of 3D stacked devices. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an electrical quantitative analysis method and a parallel TSV detection structure to quantify the influence of parallel parameters on electrical performance and improve the reliability of the parallel TSV structure.

[0006] To achieve the above and other related objectives, the present invention provides a method for electrical quantitative analysis of a parallel TSV structure, comprising:

[0007] A parallel TSV structure is provided, the parallel TSV structure including at least a first wafer, a redistribution layer is provided on the front side of the first wafer, and a first metal layer is provided on the back side of the first wafer; TSV vias are provided in the first wafer to electrically connect the redistribution layer and the first metal layer; the redistribution layer includes at least two segments, the two segments being a first segment and a last segment, and each segment is connected to the first metal layer through at least two parallel TSV vias;

[0008] At least the parallel configuration parameters of the TSV vias are used as test variables to form a parallel TSV detection structure; the parallel TSV detection structure contains variable test groups corresponding to any parallel configuration parameter, and each variable test group contains multiple test units;

[0009] The test results of electrical parameters or electrical-related parameters of each test unit in the parallel TSV detection structure are acquired synchronously to form a correlation model between test variables and test results.

[0010] The relationship between the parallel configuration parameters and electrical parameters of the parallel TSV structure is quantitatively analyzed based on the correlation model.

[0011] Optionally, the step of forming a parallel TSV detection structure, using at least the parallel configuration parameters of the TSV vias as test variables, further includes:

[0012] Using interlayer alignment offset as the test variable, a parallel TSV detection structure is formed.

[0013] Optionally, the step of forming a parallel TSV detection structure using the parallel configuration parameters of the TSV vias and the interlayer alignment offset as test variables includes:

[0014] The test group of "number-spacing-offset" variables is formed by using the number of TSV vias in parallel, the spacing between adjacent TSV vias, and the offset of TSV vias relative to the redistribution layer or the first metal layer as variables, and the TSV single via parameters as fixed quantities.

[0015] Optionally, the parallel TSV testing structure includes at least a first variable test group, a second variable test group, and a third variable test group, with each variable test group containing at least two test units; in the first variable test group, the number of TSV vias in each test unit is different; in the second variable test group, the spacing between adjacent TSV vias in each test unit is different; and in the third variable test group, the offset between the TSV vias and the redistribution layer or the first metal layer is different.

[0016] Optionally, the step of obtaining the test results of the electrical parameters and related electrical parameters of each test unit in the parallel TSV detection structure, and forming a correlation model between the test variables and the test results, includes:

[0017] The electrical parameters, thermal imaging data, and contact resistance data of each test unit in the variable test group are collected simultaneously.

[0018] Based on the collected data, a four-dimensional correlation model was established to characterize the quantitative relationship between parallel configuration parameters, interlayer alignment offset, electrical parameters and thermal stability.

[0019] Optionally, after performing a quantitative analysis of the relationship between the parallel configuration parameters and electrical parameters of the parallel TSV structure based on the correlation model, the following steps are performed:

[0020] Obtain electrical parameter data for a certain parallel TSV structure. Based on the mapping relationship between the offset data of the TSV vias relative to the redistribution layer or the first metal layer in the correlation model and the electrical parameters, determine the offset direction and offset amount of the parallel TSV structure.

[0021] Optionally, after performing a quantitative analysis of the relationship between the parallel configuration parameters and electrical parameters of the parallel TSV structure based on the correlation model, the following steps are also performed:

[0022] Based on the quantitative analysis results, a process alignment accuracy threshold for the parallel TSV structure is set.

[0023] Optionally, after performing a quantitative analysis of the relationship between the parallel configuration parameters and electrical parameters of the parallel TSV structure based on the correlation model, the following steps are also performed:

[0024] The optimal parallel configuration parameters for the parallel TSV structure are derived from the quantitative analysis results.

[0025] Optionally, the parallel TSV structure further includes: a second wafer, which is bonded to the back side of the first wafer, and a second metal layer is disposed on the surface of the second wafer bonded to the first wafer.

[0026] According to one aspect of the present invention, a parallel TSV detection structure is also provided, which is used in the above-described method for electrical quantitative analysis of the parallel TSV structure. The parallel TSV detection structure includes at least a first variable test group, a second variable test group, and a third variable test group, each variable test group containing at least two test units. In the first variable test group, the number of TSV vias in each test unit is different. In the second variable test group, the spacing between adjacent TSV vias in each test unit is different. In the third variable test group, the offset between the TSV vias and the redistribution layer or the first metal layer is different.

[0027] Each test unit includes a first wafer, a first test pad, and a second test pad. A redistribution layer is provided on the front side of the first wafer, and a first metal layer is provided on the back side of the first wafer. TSV vias are provided in the first wafer, and the TSV vias electrically connect the redistribution layer and the first metal layer. The redistribution layer includes at least two segments, namely a first segment and a last segment, and each segment is connected to the first metal layer through at least two parallel TSV vias. The first test pad is electrically connected to the first segment of the redistribution layer, and the second test pad is electrically connected to the last segment of the redistribution layer.

[0028] Compared with the prior art, the electrical quantitative analysis method and parallel TSV detection structure of the present invention have at least the following beneficial effects:

[0029] This invention designs and forms a parallel TSV detection structure by using at least the parallel configuration parameters of TSV vias as test variables. The test results of the electrical parameters or related electrical parameters of each test unit in the parallel TSV detection structure are acquired simultaneously, forming a correlation model between the test variables and the test results. Based on this correlation model, the relationship between the parallel configuration parameters and electrical parameters of the parallel TSV structure is quantitatively analyzed to achieve a precise assessment of the impact of parallel parameters on electrical performance. Furthermore, this invention can clarify the correlation between different parallel configurations (number, spacing, offset) and electrical performance, providing data support for the selection of TSV parallel schemes in 3D integrated systems. Simultaneously, it can reduce the risk of signal distortion, poor contact, and thermal failure caused by parameter mismatch and interlayer alignment offset in parallel TSVs, improving the yield and reliability of high-power 3D integrated products. Attached Figure Description

[0030] Figure 1 This is a flowchart of the electrical quantification analysis method for the parallel TSV structure in an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of the cross-sectional structure of the parallel TSV structure in an embodiment of the present invention;

[0032] Figure 3 This is a top view of the parallel TSV structure in an embodiment of the present invention;

[0033] Figure 4 This is a top view of the parallel TSV structure of the present invention, in which the number N of TSV through holes is 4 and the spacing S between adjacent TSV through holes is 1 μm.

[0034] Figure 5 This is a top view of a parallel TSV structure according to an embodiment of the present invention, where the number of TSV vias N is 4 and the spacing S between adjacent TSV vias is 0.5 μm.

[0035] Figure 6This is a schematic diagram of the structure in which the TSV via is offset relative to the first metal layer in the Y direction by a certain offset in an embodiment of the present invention;

[0036] Figure 7 This is a schematic diagram of the structure in which the TSV via is offset relative to the first metal layer in the Y direction by a certain offset in an embodiment of the present invention;

[0037] Figure 8 This is a schematic diagram of the structure in which the TSV via does not shift relative to the first metal layer and the redistribution layer in the X direction in an embodiment of the present invention;

[0038] Figure 9 This is a schematic diagram of the structure in which the TSV via is offset relative to the first metal layer and the redistribution layer in the X direction by a certain offset in an embodiment of the present invention;

[0039] Figure 10 This is a schematic diagram of the structure in which the TSV via is offset relative to the first metal layer and the redistribution layer in the X direction by a certain amount in an embodiment of the present invention.

[0040] Illustration of reference numerals in the attached diagram:

[0041] 100, First wafer; 101, Redistribution layer; 1011, First segment; 1012, Middle segment; 1013, Tail segment; 102, TSV via; 103, First metal layer; 200, Bonding layer; 300, Second wafer; 301, Second metal layer; 302, TSV via of the second wafer; 401, First test pad; 402, Second test pad. Detailed Implementation

[0042] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0043] It should be understood that the illustrations provided in the embodiments of this invention are merely schematic representations of the basic concept of the invention. Although the illustrations only show components relevant to the invention and are not drawn according to the actual number, shape, and size of components in implementation, the shape, quantity, and proportion of each component can be arbitrarily changed in actual implementation, and the component layout may also be more complex. The structures, proportions, sizes, etc., shown in the accompanying drawings are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which this application can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the invention can produce, should still fall within the scope of the technical content disclosed in this application.

[0044] Currently, there is a lack of systematic testing methods for the electrical effects of parallel TSVs, making it difficult to accurately reflect the coupling effects and overall electrical changes between parallel TSVs. Therefore, existing technologies lack a dedicated testing scheme for parallel TSV structures that can systematically reveal their complex electrical behavior and reliability issues. This results in chip designers and process engineers lacking crucial data support and model guidance during 3D integrated circuit design and process development, making it difficult to optimize parallel TSV configurations and effectively predict and mitigate potential failure risks in high-power, high-density scenarios. Specific problems are as follows:

[0045] 1) Lack of specific test schemes for TSV parallel parameters (number, spacing, offset) and electrical performance (impedance, coupling, thermal stability, signal distortion, poor contact, etc.);

[0046] 2) It is impossible to quantify the resistance matching deviation and capacitive coupling interference problems caused by the increase in the number of parallel connections;

[0047] 3) The lack of a "parallel configuration-reliability" correlation model makes it difficult to guide TSV process optimization in high-power scenarios.

[0048] To address the background technology and the aforementioned technical problems, this embodiment provides an electrical quantitative analysis method and a parallel TSV test structure. This method addresses the electrical fluctuation issues in parallel TSV scenarios by designing a dedicated test structure and quantitative analysis method to accurately assess the impact of parallel parameters on electrical performance. Furthermore, it clarifies the correlation between different parallel configurations (number, spacing, offset) and electrical performance, providing data support for selecting TSV parallel schemes in 3D integrated systems. Simultaneously, it reduces the risks of signal distortion, poor contact, and thermal failure caused by parameter mismatch and interlayer alignment offset in parallel TSVs, improving the yield and reliability of high-power 3D integrated products.

[0049] The present invention will now be described in detail with reference to specific embodiments.

[0050] Example 1

[0051] This embodiment provides an electrical quantitative analysis method for a parallel TSV structure, referring to... Figure 1 The electrical quantitative analysis method includes:

[0052] S1: A parallel TSV structure is provided, comprising at least a first wafer. A redistribution layer is disposed on the front side of the first wafer, and a first metal layer is disposed on the back side of the first wafer. TSV vias are disposed within the first wafer to electrically connect the redistribution layer to the first metal layer. The redistribution layer comprises at least two segments, namely a start segment and a finish segment, and each segment is connected to the first metal layer through at least two parallel TSV vias.

[0053] S2: At least the parallel configuration parameters of the TSV vias are used as test variables to form a parallel TSV detection structure; the parallel TSV detection structure contains variable test groups corresponding to any parallel configuration parameter, and each variable test group contains multiple test units;

[0054] S3: Synchronously acquire the test results of the electrical parameters and related electrical parameters of each test unit in the parallel TSV detection structure, and form a correlation model between test variables and test results;

[0055] S4: Quantitative analysis of the relationship between parallel configuration parameters and electrical parameters of parallel TSV structures based on correlation model.

[0056] Specifically, perform step S1, referring to... Figure 2 or Figure 3 A parallel TSV structure is provided, which includes at least a first wafer 100. A redistribution layer 101 is disposed on the front side of the first wafer 100, and a first metal layer 103 is disposed on the back side of the first wafer 100. TSV vias 102 are disposed within the first wafer 100 to electrically connect the redistribution layer 101 to the first metal layer 103. The redistribution layer 101 includes at least two segments, namely a first segment 1011 and a last segment 1013, and each segment is connected to the first metal layer 103 through at least two parallel TSV vias 102. In this embodiment, the redistribution layer 101 includes a plurality of segments spaced apart, the plurality of segments including a first segment 1011, at least one intermediate segment 1012, and a last segment 1013. The first metal layer 103 also includes multiple segments. In the top-view projection direction, the multiple segments of the first metal layer 103 are arranged one-to-one between adjacent segments of the redistribution layer 101, and each segment of the first metal layer 103 has an overlapping area with the redistribution layer 101 at both ends, and at least two parallel TSV vias 102 are arranged in the overlapping area.

[0057] In one example, refer to Figure 2 The parallel TSV structure also includes a second wafer 300, which is bonded to the back side of the first wafer 100. A second metal layer 301 is disposed on the surface of the second wafer 300 that is bonded to the first wafer 100. Optionally, the first wafer 100 and the second wafer 300 are bonded through a bonding layer 200. The bonding layer 200 has a first conductive via connected to the first metal layer 103 and a second conductive via connected to the second metal layer 301. The first and second conductive vias are correspondingly bonded to achieve interconnection between the first metal layer 103 and the second metal layer 301. Similarly, a TSV via, labeled as the TSV via 302 of the second wafer, is also disposed in the second wafer 300. For ease of testing, the parallel TSV structure of this embodiment also includes a first test pad 401 and a second test pad 402. The first test pad 401 is electrically connected to the first segment 1011 of the redistribution layer 101. The second test pad 402 is electrically connected to the tail segment 1013 of the redistribution layer 101. The first test pad 401 and the second test pad 402 serve as interfaces for test probes, ensuring stable signal transmission. Test signals are applied to the first test pad 401 and the second test pad 402 to test the parallel TSV structure, which serves as a test unit.

[0058] Step S2 is executed to form a parallel TSV detection structure, using at least the parallel configuration parameters of the TSV vias as test variables. In this embodiment, the parallel configuration parameters of the TSV vias and the interlayer alignment offset are used as test variables to form the parallel TSV detection structure. The parallel TSV detection structure includes a variable test group corresponding to any parallel configuration parameter and a variable test group for the interlayer alignment offset, with each variable test group containing multiple test units. Optionally, the parallel configuration parameters include the number of parallel TSV vias and the spacing between adjacent TSV vias in the parallel TSV structure.

[0059] Specifically, the number of parallel TSV vias, the spacing between adjacent TSV vias, and the interlayer alignment offset of the TSV vias relative to the redistribution layer 101 or the first metal layer 103 are used as variables, while the TSV single-via parameter is used as a fixed quantity, forming a variable test group of "number-spacing-offset". Therefore, the parallel TSV detection structure in this embodiment includes a first variable test group, a second variable test group, and a third variable test group, each containing at least two test units. In the first variable test group, the number of TSV vias in each test unit is different. In the second variable test group, the spacing between adjacent TSV vias in each test unit is different. In the third variable test group, the offset of the TSV vias relative to the redistribution layer or the first metal layer is different.

[0060] Optionally, each variable test group includes a benchmark test unit and at least one variable test unit, wherein the benchmark test unit is used to form a control with the variable test units. The TSV via parameters of each test unit are uniform, for example, the diameter of the TSV via is 2μm and the aspect ratio is 10:1.

[0061] The parallel TSV detection structure includes a first variable test group, where the variable refers to the number of parallel TSV vias. (Refer to...) Figure 4 The number of parallel TSV vias 102 in the variable test unit is N = 4, 6, or 8, where... Figure 4 Taking N=4 as an example, the spacing S=1μm between adjacent TSV vias 102 in the parallel TSV structure. The center of the TSV via 102 is perfectly aligned with the center of the first metal layer 103 and the center of the redistribution layer 101 (X / Y axis offset=0). The impedance reduction is recorded as the number of parallel connections increases; for example, how much the impedance decreases when N=8 compared to N=2, the capacitance increment (parallel capacitance superposition effect), and the change in transmission efficiency are recorded. The impact of the "number of parallel connections" on basic electrical parameters is quantified, providing a basis for selecting the number of TSVs in high-current transmission scenarios. In this embodiment, refer to... Figure 3 The number of parallel TSV vias 102 in the benchmark unit is N=2, and the spacing between adjacent TSV vias 102 in the parallel TSV structure is S=1μm. The center of the TSV via 102 is perfectly aligned with the center of the first metal layer 103 and the center of the redistribution layer 101 (X / Y axis offset = 0). The reference impedance R0, capacitance C0, and transmission efficiency η0 are collected as the comparison baseline for subsequent offset scenarios. OVL shift interference is eliminated to ensure that the differences in subsequent tests are only caused by "parallel configuration parameters + offset".

[0062] The parallel TSV testing structure includes a second variable test group, where the variable refers to the spacing between adjacent TSV vias in the parallel TSV structure. (Refer to...) Figure 5 With the number of parallel connections fixed at N=4, the spacing S between adjacent TSV through-holes 102 is adjusted to (0.5μm, 1.5μm, 2μm). Figure 5 The diagram uses S=0.5 μm. The center of the TSV via 102 is perfectly aligned with the center of the first metal layer 103 and the center of the redistribution layer 101 (X / Y axis offset = 0). Coupling capacitance (smaller S indicates stronger coupling), heat accumulation (smaller S indicates poorer heat dissipation), and impedance fluctuation are measured at different spacings. The optimal spacing is determined by balancing integration density and electrical reliability, taking into account both area and performance. In this embodiment, reference is made to... Figure 4The number of parallel TSV vias 102 in the benchmark unit is N=4, and the spacing between adjacent TSV vias 102 in the parallel TSV structure is S=1μm. The center of the TSV via 102 is perfectly aligned with the center of the first metal layer 103 and the center of the redistribution layer 101 (X / Y axis offset=0).

[0063] The parallel TSV testing structure includes a third variable test group, where the variable refers to the offset of the TSV relative to the redistribution layer and the first metal layer. (See reference...) Figure 6 or Figure 7 With a fixed parallel quantity N=2 and a spacing S=1μm, offsets in the X / Y axes are introduced through process control. This offset range can cover common offset intervals in actual mass production. For example, regarding the offset of TSV via 102 relative to the first metal layer 103: the center of TSV via 102 deviates from the wiring center of the first metal layer 103, such as an offset of 0.5D / D / 2D in the negative Y-axis direction, where D is the diameter of TSV via 102. Figure 6 As shown, in the positive Y-axis direction, the edge of the TSV via 102 falls exactly within the first metal layer 103 relative to the first metal layer 103. Figure 7 As shown, the TSV via 102 falls exactly outside the edge of the first metal layer 103, and the edge is in contact with the first metal layer 103. Similarly, the offset of the TSV via 102 relative to the redistribution layer 101 is similar to the offset of the TSV via 102 relative to the first metal layer 103 described above. Figure 8 As shown, the center of the TSV via 102 is perfectly aligned with the center of the first metal layer 103 and the center of the redistribution layer 101 (X / Y axis offset = 0), so that... Figure 8 Used as a benchmark for comparison. In one example, such as Figure 9 As shown, the edge of the TSV via 102 falls exactly within the first metal layer 103 and the redistribution layers (1011, 1012, 1013). Figure 10 As shown, the outer edge of the TSV via 102 is just connected to the first metal layer 103 and the redistribution layers (1011, 1012, 1013). Record the change in interconnect resistance as the offset increases, for example, whether the resistance increases by more than 50% when the offset is 0.5D compared to when there is no offset. Detect the impact of "partial contact defects" caused by the offset, such as the TSV only being connected to the first metal layer 103 at its edge, on transmission efficiency. Observe whether the offset causes additional coupling interference, such as misalignment causing a shortened distance between the TSV and the adjacent redistribution layer 101. In this embodiment, refer to... Figure 3 and Figure 8The number of parallel TSV vias 102 in the benchmark unit is N=2, and the spacing between adjacent TSV vias 102 in the parallel TSV structure is S=1μm. The center of the TSV via 102 is perfectly aligned with the center of the first metal layer 103 and the center of the redistribution layer 101 (X / Y axis offset=0).

[0064] Step S3 involves simultaneously acquiring the test results of the electrical parameters and related electrical parameters of each test unit in the parallel TSV detection structure, forming a correlation model between the test variables and the test results. Specifically, the electrical parameters, thermal imaging data, and contact resistance data of each test unit in the variable test group are collected simultaneously. Based on the collected data, a four-dimensional correlation model is established to characterize the quantitative relationship between parallel configuration parameters, interlayer alignment offset, electrical parameters, and thermal stability. Optionally, the electrical parameters are high-frequency electrical parameters, including at least one of impedance, capacitance, and transmission efficiency.

[0065] Step S4 involves a quantitative analysis of the relationship between the parallel configuration parameters and electrical parameters of the parallel TSV structure based on the correlation model. In the example above, this quantitative analysis may include: recording the impedance reduction as the number of parallel connections increases, for example, how much the impedance decreases when N=8 compared to N=2, the capacitance increment (parallel capacitance superposition effect), and the change in transmission efficiency. Quantifying the impact of the "number of parallel connections" on the basic electrical parameters provides a basis for selecting the number of TSVs for high-current transmission scenarios. Measuring the coupling capacitance (the smaller S is, the stronger the coupling), heat accumulation degree (the smaller S is, the worse the heat dissipation), and impedance fluctuations at different spacings. Balancing "integration density" and "electrical reliability" to determine the optimal spacing that balances area and performance. Recording the change in interconnect resistance as the offset increases, for example, whether the resistance increases by more than 50% when the offset is 0.5D compared to when there is no offset. Detecting the impact of "partial contact defects" caused by offset, such as the effect on transmission efficiency when only the edge of the TSV is connected to the first metal layer 103. Observing whether the offset causes additional coupling interference, such as misalignment causing a shortened distance between the TSV and the adjacent rewiring layer 101.

[0066] In this embodiment, after quantitative analysis, the relationship between parallel configuration parameters and electrical parameters, and the relationship between interlayer alignment offset and electrical parameters in the correlation model are obtained. Based on the above relationships or correlation rules, at least one of the following operations is performed:

[0067] Based on the quantitative analysis results, the optimal parallel configuration parameters of the parallel TSV structure are derived, achieving ±0.05μm level spacing optimization.

[0068] The electrical parameter data of a certain parallel TSV structure is obtained. Based on the mapping relationship between the offset data of the TSV via 102 relative to the redistribution layer 101 or the first metal layer 103 in the correlation model and the electrical parameters, the offset direction and offset amount of the parallel TSV structure are determined, providing a direct basis for adjusting the alignment parameters of the bonding device.

[0069] Based on the quantitative analysis results, the process alignment accuracy threshold of the parallel TSV structure is set to achieve the definition of the ±0.1μm level offset tolerance threshold.

[0070] Optionally, the thermomechanical life or potential failure risk of a parallel TSV structure can be predicted by using an association model based on the real-time or initial electrical parameters of the structure, so as to evaluate the reliability of the parallel TSV structure.

[0071] Example 2

[0072] This embodiment provides a parallel TSV detection structure, which is used in the electrical quantification analysis method of the parallel TSV structure in Embodiment 1. (Refer to...) Figure 2 The parallel TSV testing structure includes at least a first variable test group, a second variable test group, and a third variable test group, with each variable test group containing at least two test units. Within the first variable test group, the number of TSV vias 102 within each test unit is different. Within the second variable test group, the spacing between adjacent TSV vias 102 within each test unit is different. Within the third variable test group, the offset of the TSV vias 102 from the redistribution layer 101 or the first metal layer 103 is different.

[0073] Each test unit includes a first wafer 100, a first test pad 401, and a second test pad 402. A redistribution layer 101 is disposed on the front side of the first wafer 100, and a first metal layer 103 is disposed on the back side of the first wafer 100. A TSV via 102 is disposed within the first wafer 100, which electrically connects the redistribution layer 101 to the first metal layer 103. The redistribution layer 101 includes at least two segments, namely a first segment 1011 and a last segment 1013. Each segment is connected to the first metal layer 103 through at least two parallel TSV vias 102. The first test pad 401 is electrically connected to the first segment 1011 of the redistribution layer 101, and the second test pad 402 is electrically connected to the last segment 1013 of the redistribution layer 101.

[0074] In this embodiment, refer to Figure 2The redistribution layer 101 includes multiple segments spaced apart, each segment including a first segment 1011, at least one intermediate segment 1012, and a last segment 1013. The first metal layer 103 also includes multiple segments. In a top-view projection direction, the multiple segments of the first metal layer 103 are arranged one-to-one between adjacent segments of the redistribution layer 101, and each segment of the first metal layer 103 has overlapping areas with the redistribution layer 101 at both ends, with at least two parallel TSV vias 102 disposed in the overlapping areas.

[0075] In one example, refer to Figure 2 The parallel TSV structure also includes a second wafer 300, which is bonded to the back side of the first wafer 100. A second metal layer 301 is disposed on the surface of the second wafer 300 that is bonded to the first wafer 100. Optionally, the first wafer 100 and the second wafer 300 are bonded together through a bonding layer 200. The bonding layer 200 has a first conductive via connected to the first metal layer 103 and a second conductive via connected to the second metal layer 301. The first and second conductive vias are correspondingly bonded to achieve interconnection between the first metal layer 103 and the second metal layer 301.

[0076] Optionally, each variable test group includes a benchmark test unit and at least one variable test unit, wherein the benchmark test unit is used to form a control with the variable test units. The TSV via 102 parameters of each test unit are uniform, for example, the diameter of the TSV via 102 is 2μm and the aspect ratio is 10:1.

[0077] The parallel TSV detection structure includes a first variable test group, where the variable refers to the number of parallel TSV vias. (Refer to...) Figure 4 The number of parallel TSV vias 102 in the variable test unit is N = 4, 6, or 8, where... Figure 4 Taking N=4 as an example, the spacing S=1μm between adjacent TSV vias 102 in the parallel TSV structure. The center of the TSV via 102 is perfectly aligned with the center of the first metal layer 103 and the center of the redistribution layer 101 (X / Y axis offset = 0). In this embodiment, refer to... Figure 3 The number of parallel TSV vias 102 in the benchmark unit is N=2, and the spacing between adjacent TSV vias 102 in the parallel TSV structure is S=1μm. The center of the TSV via 102 is perfectly aligned with the center of the first metal layer 103 and the center of the redistribution layer 101 (X / Y axis offset=0).

[0078] The parallel TSV testing structure includes a second variable test group, where the variable refers to the spacing between adjacent TSV vias in the parallel TSV structure. (Refer to...) Figure 5With the number of parallel connections fixed at N=4, the spacing S between adjacent TSV through-holes 102 is adjusted to (0.5μm, 1.5μm, 2μm). Figure 5 The diagram uses S=0.5 μm for illustration. The center of the TSV via 102 is perfectly aligned with the center of the first metal layer 103 and the center of the redistribution layer 101 (X / Y axis offset = 0). In this embodiment, refer to... Figure 4 The number of parallel TSV vias 102 in the benchmark unit is N=4, and the spacing between adjacent TSV vias 102 in the parallel TSV structure is S=1μm. The center of the TSV via 102 is perfectly aligned with the center of the first metal layer 103 and the center of the redistribution layer 101 (X / Y axis offset=0).

[0079] The parallel TSV testing structure includes a third variable test group, where the variable refers to the offset of the TSV relative to the redistribution layer and the first metal layer. (See reference...) Figure 6 or Figure 7 With a fixed parallel quantity N=2 and a spacing S=1μm, offsets in the X / Y axes are introduced through process control. This offset range can cover common offset intervals in actual mass production. For example, regarding the offset of TSV via 102 relative to the first metal layer 103: the center of TSV via 102 deviates from the wiring center of the first metal layer 103, such as an offset of 0.5D / D / 2D in the negative Y-axis direction, where D is the diameter of TSV via 102. Figure 6 As shown, in the positive Y-axis direction, the edge of the TSV via 102 falls exactly within the first metal layer 103 relative to the first metal layer 103. Figure 7 As shown, the TSV via 102 falls exactly outside the edge of the first metal layer 103, and the edge is in contact with the first metal layer 103. Similarly, the offset of the TSV via 102 relative to the redistribution layer 101 is similar to the offset of the TSV via 102 relative to the first metal layer 103, as described above. Figure 8 As shown, the center of the TSV via 102 is perfectly aligned with the center of the first metal layer 103 and the center of the redistribution layer 101 (X / Y axis offset = 0). Figure 9 As shown, the edge of the TSV via 102 falls exactly within the first metal layer 103 and the redistribution layers (1011, 1012, 1013). Figure 10 As shown, the outer edge of the TSV via 102 is exactly connected to the first metal layer 103 and the redistribution layers (1011, 1012, 1013). In this embodiment, the number of parallel TSV vias 102 in the benchmark unit is N=2, and the spacing between adjacent TSV vias 102 in the parallel TSV structure is S=1μm. The center of the TSV via 102 is perfectly aligned with the center of the first metal layer 103 and the center of the redistribution layer 101 (X / Y axis offset = 0).

[0080] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for electrical quantitative analysis of a parallel TSV structure, characterized in that, include: A parallel TSV structure is provided, the parallel TSV structure including at least a first wafer, a redistribution layer disposed on the front side of the first wafer, and a first metal layer disposed on the back side of the first wafer; TSV vias are disposed in the first wafer to electrically connect the redistribution layer to the first metal layer; the redistribution layer includes at least two segments, the two segments being a first segment and a last segment, and each segment is connected to the first metal layer through at least two parallel TSV vias; A parallel TSV detection structure is formed by using at least the parallel configuration parameters of the TSV vias as test variables; the parallel TSV detection structure includes variable test groups corresponding to any parallel configuration parameter, and each variable test group includes multiple test units; The test results of the electrical parameters or electrical-related parameters of each test unit in the parallel TSV detection structure are acquired synchronously to form a correlation model between test variables and test results; The relationship between the parallel configuration parameters and electrical parameters of the parallel TSV structure is quantitatively analyzed based on the aforementioned correlation model.

2. The electrical quantitative analysis method according to claim 1, characterized in that, The step of forming a parallel TSV detection structure, using at least the parallel configuration parameters of the TSV vias as test variables, further includes: Using interlayer alignment offset as the test variable, a parallel TSV detection structure is formed.

3. The electrical quantitative analysis method according to claim 2, characterized in that, The step of forming a parallel TSV detection structure using the parallel configuration parameters of the TSV vias and the interlayer alignment offset as test variables includes: Using the number of TSV vias in parallel, the spacing between adjacent TSV vias, and the offset of the TSV vias relative to the redistribution layer or the first metal layer as variables, and the TSV single-via parameter as a fixed quantity, a variable test group of "number-spacing-offset" is formed.

4. The electrical quantitative analysis method according to claim 2, characterized in that, The parallel TSV detection structure includes at least a first variable test group, a second variable test group, and a third variable test group, each variable test group containing at least two test units; in the first variable test group, the number of TSV vias in each test unit is different; in the second variable test group, the spacing between adjacent TSV vias in each test unit is different; in the third variable test group, the offset of the TSV vias from the redistribution layer or the first metal layer is different.

5. The electrical quantitative analysis method according to claim 3 or 4, characterized in that, The step of obtaining the test results of the electrical parameters and related electrical parameters of each test unit in the parallel TSV detection structure, and forming a correlation model between test variables and test results, includes: The electrical parameters, thermal imaging data, and contact resistance data of each test unit in the variable test group are collected simultaneously. Based on the collected data, a four-dimensional correlation model was established to characterize the quantitative relationship between parallel configuration parameters, interlayer alignment offset, electrical parameters and thermal stability.

6. The electrical quantitative analysis method according to claim 2, characterized in that, After performing a quantitative analysis of the relationship between the parallel configuration parameters and electrical parameters of the parallel TSV structure based on the aforementioned correlation model, the following steps are executed: Obtain electrical parameter data of a certain parallel TSV structure, and determine the offset direction and offset amount of the parallel TSV structure based on the mapping relationship between the offset data of the TSV vias relative to the redistribution layer or the first metal layer and the electrical parameters in the correlation model.

7. The electrical quantitative analysis method according to claim 2, characterized in that, After performing a quantitative analysis of the relationship between the parallel configuration parameters and electrical parameters of the parallel TSV structure based on the aforementioned correlation model, the following steps are also performed: Based on the quantitative analysis results, a process alignment accuracy threshold is set for the parallel TSV structure.

8. The electrical quantitative analysis method according to claim 1, characterized in that, After performing a quantitative analysis of the relationship between the parallel configuration parameters and electrical parameters of the parallel TSV structure based on the aforementioned correlation model, the following steps are also performed: The optimal parallel configuration parameters for the parallel TSV structure are derived from the quantitative analysis results.

9. The electrical quantitative analysis method according to claim 1, characterized in that, The parallel TSV structure further includes: a second wafer, which is bonded to the back side of the first wafer, and a second metal layer is disposed on the surface of the second wafer that is bonded to the first wafer.

10. A parallel TSV detection structure, characterized in that, The parallel TSV detection structure is used in the electrical quantitative analysis method of the parallel TSV structure according to any one of claims 1 to 7; the parallel TSV detection structure includes at least a first variable test group, a second variable test group, and a third variable test group, each variable test group containing at least two test units; in the first variable test group, the number of TSV vias in each test unit is different; in the second variable test group, the spacing between adjacent TSV vias in each test unit is different; in the third variable test group, the offset of the TSV vias from the redistribution layer or the first metal layer is different; Each test unit includes a first wafer, a first test pad, and a second test pad. A redistribution layer is disposed on the front side of the first wafer, and a first metal layer is disposed on the back side of the first wafer. A TSV via is disposed in the first wafer, and the TSV via electrically connects the redistribution layer to the first metal layer. The redistribution layer includes at least two segments, namely a first segment and a last segment, and each segment is connected to the first metal layer through at least two parallel TSV vias. The first test pad is electrically connected to the first segment of the redistribution layer, and the second test pad is electrically connected to the last segment of the redistribution layer.

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