EMMC power supply circuit and system

Abstract

The invention provides an eMMC power supply circuit and system, and relates to the technical field of embedded memorizers, the circuit comprises a voltage detection module, a power supply gating module, a filtering module, a first step-down modulation module, a digital kernel module, a second step-down modulation module, a third step-down modulation module and an NAND module, the voltage detection module is connected with the power supply gating module, and the power supply gating module is connected with the filtering module. The voltage detection module is used for detecting communication interface voltage and dividing a fluctuation range corresponding to the communication interface voltage into a first voltage gear and a second voltage gear; the power supply gating module is respectively connected with the filtering module and the first step-down modulation module, and the power supply gating module is used for transmitting the communication interface voltage at a first voltage gear to the digital kernel module from the filtering module and transmitting the communication interface voltage at a second voltage gear to the digital kernel module from the first step-down modulation module; the second step-down modulation module is connected with the NAND module; and the third step-down modulation module is connected with the NAND module. According to the invention, the utilization efficiency of the eMMC power supply circuit can be improved.

Description

Technical Field

[0001] This invention relates to the field of embedded memory technology, and more particularly to an eMMC power supply circuit and system. Background Technology

[0002] Embedded multimedia cards (eMMC), as an embedded storage solution integrating NAND Flash memory and a controller, are widely used in smartphones, tablets, IoT devices, industrial control, automotive electronics, and other fields due to their compact structure and simplified interface design. Their technical specifications are defined and standardized by JEDEC (Journal of Solid State Technology), such as the eMMC 5.0 and eMMC 5.1 standards.

[0003] Chinese Patent CN107886997B discloses an eMMC testing device and method. The device includes a host, an eMMC voltage controller, an eMMC chip, and an eMMC controller. The host sends voltage range control commands to the eMMC voltage controller. The eMMC voltage controller outputs a target test voltage to the eMMC chip's power supply according to the voltage range control commands sent by the host. The eMMC chip receives the test commands sent by the eMMC controller and feeds back the test results to the eMMC controller. The eMMC controller receives the test commands sent by the host and sends the test results fed back by the eMMC chip to the host, allowing the host to determine whether the powered eMMC chip is operating normally based on the test results. However, the above solution only tests the eMMC chip under different voltage ranges using an external host and eMMC voltage controller, failing to achieve automatic detection of voltage levels and adaptive switching of power paths, resulting in insufficient utilization efficiency of the testing device. Therefore, it is necessary to provide an eMMC power supply circuit and system to improve the utilization efficiency of the eMMC power supply circuit. Summary of the Invention

[0004] In view of this, the present invention proposes an eMMC power supply circuit and system.

[0005] This invention provides an eMMC power supply circuit, including a voltage detection module, a power gating module, a filtering module, a first buck modulation module, a digital core module, a second buck modulation module, a third buck modulation module, and a NAND module, wherein... The voltage detection module is connected to the power selection module. The voltage detection module is used to detect the externally input communication interface voltage and divide the fluctuation range of the communication interface voltage into a first voltage level and a second voltage level. The power selection module is connected to the filtering module and the first buck modulation module respectively. The power selection module is used to transfer the communication interface voltage at the first voltage level from the filtering module to the digital kernel module, and to transfer the communication interface voltage at the second voltage level from the first buck modulation module to the digital kernel module. The second buck modulation module is connected to the NAND module, and the second buck modulation module is used to convert the externally input storage access voltage into the power supply voltage for the NAND module; The third buck modulation module is connected to the NAND module, and the third buck modulation module is used to convert the externally input storage access voltage into the interface voltage supplied to the NAND module.

[0006] Based on the above technical solutions, preferably, the voltage detection module includes a PMOS transistor Q1, an NMOS transistor Q2, a PMOS transistor Q3, and an NMOS transistor Q4. The drain of the PMOS transistor Q1 and the source of the NMOS transistor Q2 are both connected to the communication interface voltage input terminal. The source of the PMOS transistor Q1 and the drain of the NMOS transistor Q2 are both connected to the filter module. The gate of the PMOS transistor Q1 and the gate of the NMOS transistor Q2 are connected through the power selection module. The drain of the PMOS transistor Q3 and the source of the NMOS transistor Q4 are both connected to the communication interface voltage input terminal. The source of the PMOS transistor Q3 and the drain of the NMOS transistor Q4 are both connected to the first buck modulation module. The gate of the PMOS transistor Q3 and the gate of the NMOS transistor Q4 are connected through the power selection module.

[0007] Based on the above technical solutions, preferably, the power selection module includes a comparator and multiple selection logic circuits. The non-inverting input terminal of the comparator is connected to the multiple selection logic circuits respectively, the inverting input terminal of the comparator is connected to the reference voltage input terminal, and the output terminal of the comparator is connected to the gate of the PMOS transistor Q1 or the gate of the PMOS transistor Q4.

[0008] More preferably, the selection logic circuit includes a first MOSFET, a second MOSFET, an inverter, a logic gate, a first resistor, and a second resistor. The first common terminal of the first MOSFET and the second MOSFET is connected to the non-inverting input terminal of the comparator and the remaining selection logic circuit, respectively. The second common terminal of the first MOSFET and the second MOSFET is connected to the common terminal of the first resistor and the second resistor. The gate of the first MOSFET is connected to the input terminal of the inverter and the output terminal of the logic gate, respectively. The gate of the second MOSFET is connected to the output terminal of the inverter. The input terminal of the logic gate is connected to multiple selection signal input terminals. The other end of the first resistor is connected to the communication interface voltage input terminal and the positive power supply terminal of the comparator, respectively. The other end of the second resistor is connected to the remaining selection logic circuit.

[0009] More preferably, the filtering module includes a resistor R1 and a capacitor C1. One end of the resistor R1 is connected to the voltage detection module, and the other end of the resistor R1 is connected to one end of the capacitor C1 and the digital kernel module, respectively. The other end of the capacitor C1 is grounded.

[0010] More preferably, the first buck modulation module includes a PMOS transistor Q5, resistors R2 and R3, capacitor C2, buffer BUF1, and error amplifier EA1. The source of the PMOS transistor Q5 is connected to the positive power supply terminal of the error amplifier EA1 and the voltage detection module. The drain of the PMOS transistor Q5 is connected to one end of resistor R2, one end of capacitor C2, and the digital core module. The gate of the PMOS transistor Q5 is connected to the other end of capacitor C2 and the output terminal of the error amplifier EA1 through the buffer BUF1. The non-inverting input terminal of the error amplifier EA1 is connected to the reference voltage input terminal. The inverting input terminal of the error amplifier EA1 is connected to the common terminal of resistors R2 and R3. The inverting power supply terminal of the error amplifier EA1 and the other end of resistor R3 are grounded together.

[0011] More preferably, the second buck modulation module includes a PMOS transistor Q6, resistors R4 and R5, capacitor C3, buffer BUF2, and error amplifier EA2. The source of the PMOS transistor Q6 is connected to the positive power supply terminal and the storage access voltage input terminal of the error amplifier EA2, respectively. The drain of the PMOS transistor Q6 is connected to one end of resistor R4, one end of capacitor C3, and the NAND module, respectively. The gate of the PMOS transistor Q6 is connected to the other end of capacitor C3 and the output terminal of error amplifier EA2 through buffer BUF2, respectively. The non-inverting input terminal of error amplifier EA2 is connected to the reference voltage input terminal. The inverting input terminal of error amplifier EA2 is connected to the common terminal of resistors R4 and R5. The inverting power supply terminal of error amplifier EA2 and the other end of resistor R5 are grounded together.

[0012] More preferably, the third buck modulation module includes a PMOS transistor Q7, resistors R6 and R7, capacitor C4, buffer BUF3, and error amplifier EA3. The source of the PMOS transistor Q7 is connected to the positive power supply terminal and the storage access voltage input terminal of the error amplifier EA3, respectively. The drain of the PMOS transistor Q7 is connected to one end of resistor R6, one end of capacitor C4, and the NAND module, respectively. The gate of the PMOS transistor Q7 is connected to the other end of capacitor C4 and the output terminal of the error amplifier EA3 through the buffer BUF3, respectively. The non-inverting input terminal of the error amplifier EA3 is connected to the reference voltage input terminal. The inverting input terminal of the error amplifier EA3 is connected to the common terminal of resistors R6 and R7. The inverting power supply terminal of the error amplifier EA3 and the other end of resistor R7 are grounded together.

[0013] More preferably, the first MOS transistor is a PMOS transistor and the second MOS transistor is an NMOS transistor.

[0014] A second aspect of this application provides an eMMC power system, the eMMC power system including the eMMC power circuit.

[0015] The eMMC power supply circuit and system provided by this invention have the following advantages over the prior art: (1) The voltage of the external communication interface is divided into the first voltage level and the second voltage level by the voltage detection module, and the power supply path is automatically selected by the power selection module. This realizes automatic identification and adaptive power supply for different external interface voltages. When the external communication interface voltage is in the appropriate first voltage level, the filtering and direct power supply method is adopted instead of going through the step-down modulation stage, which reduces the loss in the voltage conversion process. The first step-down modulation module is only activated when the voltage is in the second level, avoiding unnecessary conversion. By selecting different power supply paths according to the voltage level, the overall utilization efficiency of the eMMC power circuit is improved, and the internal power consumption and temperature rise of the chip are reduced. At the same time, for the second voltage level that exceeds the safe working range of the digital core, the power supply is converted by the first step-down modulation module before power supply, which can effectively prevent high voltage from being directly applied to the digital core and avoid damage to the core due to overvoltage.

[0016] (2) By driving and controlling the gates of both pairs of MOS transistors through the power selection module, the paths corresponding to different voltage levels can be quickly and clearly distinguished and switched, ensuring that the voltage detection results can be accurately mapped to different power paths. The complementary PMOS and NMOS structures reduce the on-resistance and improve the power switching quality. Furthermore, Q1 and Q2, Q3 and Q4 respectively form similar complementary transmission gate structures. When the corresponding level is selected, PMOS and NMOS are turned on together, significantly reducing the path resistance and reducing the voltage drop and power consumption when the communication interface voltage is sent to the filter module or the first buck modulation module. This is beneficial to ensure that the subsequent digital core module obtains a more stable voltage that is closer to the target value. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of the eMMC power supply circuit provided by the present invention; Figure 2 A circuit diagram of the voltage detection module, the filtering module, and the first buck modulation module provided by the present invention; Figure 3 A circuit diagram of the power selection module provided by the present invention; Figure 4 The circuit diagrams of the second and third buck modulation modules provided by the present invention are shown.

[0019] Explanation of reference numerals in the attached diagram: 1. Voltage detection module; 2. Power selection module; 3. Filtering module; 4. First buck modulation module; 5. Digital core module; 6. Second buck modulation module; 7. Third buck modulation module; 8. NAND module. Detailed Implementation

[0020] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0021] This invention discloses an eMMC power supply circuit, with reference to... Figure 1 and Figure 2 The aforementioned eMMC power supply circuit includes a voltage detection module 1, a power gating module 2, a filtering module 3, a first buck modulation module 4, a digital core module 5, a second buck modulation module 6, a third buck modulation module 7, and a NAND module 8. The voltage detection module 1 is connected to the power selection module 2. The voltage detection module 1 is used to detect the externally input communication interface voltage and divide the fluctuation range of the communication interface voltage into a first voltage level and a second voltage level.

[0022] In this embodiment, the voltage detection module 1 includes a PMOS transistor Q1, an NMOS transistor Q2, a PMOS transistor Q3, and an NMOS transistor Q4. The drain of PMOS transistor Q1 and the source of NMOS transistor Q2 are both connected to the communication interface voltage input terminal. The source of PMOS transistor Q1 and the drain of NMOS transistor Q2 are both connected to the filter module 3. The gate of PMOS transistor Q1 and the gate of NMOS transistor Q2 are connected through the power selection module 2. The drain of PMOS transistor Q3 and the source of NMOS transistor Q4 are both connected to the communication interface voltage input terminal. The source of PMOS transistor Q3 and the drain of NMOS transistor Q4 are both connected to the first buck modulation module 4. The gate of PMOS transistor Q3 and the gate of NMOS transistor Q4 are connected through the power selection module 2.

[0023] The communication interface voltage VCCQ is first input to the voltage detection module 1. The voltage detection module 1 determines the magnitude of the communication interface voltage VCCQ. If it is between 1.70-1.95V or 2.7-3.6V, the power selection module 2 connects the communication interface voltage VCCQ to the first buck modulation module 4. The first buck modulation module 4 converts the communication interface voltage VCCQ into a power supply suitable for the digital core (approximately 1.0~1.2V). If the voltage detection module 1 detects that the communication interface voltage VCCQ is between 1.1-1.3V, the power selection module 2 connects the communication interface voltage VCCQ to the filtering module 3. After filtering, the communication interface voltage VCCQ is supplied to the digital core. The other storage access voltage VCC of the eMMC power circuit is supplied to the second buck modulation module 6 and the third buck modulation module 7. The second buck modulation module 6 and the third buck modulation module 7 generate the interface voltage and power supply voltage required by the NAND module 8 in the eMMC.

[0024] It is understood that the voltage detection module 1 consists of a voltage divider resistor string, a multiplexing logic circuit, a comparator, and other components. First, the input communication interface voltage VCCQ is divided into multiple voltage values ​​by the voltage divider resistor string. Then, the multiplexing logic circuit selects an appropriate distributed voltage value and inputs it to one input terminal of the comparator. The other terminal of the comparator is connected to an internal reference voltage. The comparator outputs a voltage detection signal by comparing the voltage values ​​at the two input terminals. This voltage detection output signal generally has two cases: high voltage and low voltage. In this embodiment, high voltage is defined as the voltage detection signal input to the power selection module 2. In other embodiments, low voltage can also be defined as the voltage detection signal input to the power selection module 2.

[0025] The voltage detection module 1 consists of two sets of PMOS / NMOS transistors. The common terminal of PMOS transistor Q1 and NMOS transistor Q2 is connected to the filter module 3 to form a direct power supply path for the communication interface voltage. The common terminal of PMOS transistor Q3 and NMOS transistor Q4 is connected to the first buck modulation module 4 to form a path where the communication interface voltage is stepped down before being supplied to the power supply. The gates of PMOS transistors Q1 and Q2, and the gates of PMOS transistors Q3 and Q4, are connected to each other through the power selection module 2. When the control level output by the power selection module 2 is in one state, PMOS transistors Q1 and Q2 are turned on while PMOS transistors Q3 and Q4 are turned off, and the communication interface voltage is directly sent to the digital core module 5 after being processed by the filter module 3. When the control level is in another state, PMOS transistors Q3 and Q4 are turned on while PMOS transistors Q1 and Q2 are turned off, and the communication interface voltage is sent to the first buck modulation module 4, where it is stepped down and regulated before being supplied to the digital core module 5.

[0026] In this embodiment, the gates of both pairs of MOSFETs are driven and controlled by the power selection module 2, enabling rapid and clear differentiation and switching of paths corresponding to different voltage levels, ensuring that the voltage detection results can be accurately mapped to different power paths. The complementary PMOS and NMOS structures reduce on-resistance and improve power switching quality. Furthermore, Q1 and Q2, and Q3 and Q4 respectively constitute similar complementary transmission gate structures. When the corresponding level is selected, both the PMOS and NMOS are turned on, significantly reducing path resistance and lowering the voltage drop and power consumption when the communication interface voltage is sent to the filter module 3 or the first buck modulation module 4. This helps ensure that the subsequent digital core module 5 obtains a more stable voltage closer to the target value. When one path is turned off, the PMOS and NMOS are simultaneously cut off, effectively blocking that path and reducing the impact of the turn-off path on the other path. The physical branching of different voltage levels by the two pairs of MOSFETs achieves electrical isolation of different voltage paths, reducing the risk of mutual interference, crosstalk, and false triggering, thereby improving the reliability of system power supply and detection.

[0027] Meanwhile, by setting two pairs of MOSFETs in the voltage detection module 1, which are respectively connected to the filter module 3 and the first buck modulation module 4, and cooperating with the power selection module 2 to selectively drive the corresponding gates according to the detection results, the communication interface voltage in different level ranges can be segmented. This avoids the problem of false turn-on or simultaneous conduction of two paths when the voltage is close to the threshold value of the segment, thus improving the stability and accuracy of voltage segment judgment and switching. By directly using the Q1 to Q4 MOSFET structure inside the chip to realize the switching and selection of the voltage path, there is no need to add discrete components such as relays and analog switch chips. This is beneficial to improve the integration of the power management circuit, reduce the number of peripheral components and board space, and, since standard CMOS devices are used, the device matching and process consistency are good, resulting in higher overall reliability.

[0028] The power selection module 2 is connected to the filter module 3 and the first buck modulation module 4 respectively. The power selection module 2 is used to transfer the communication interface voltage at the first voltage level from the filter module 3 to the digital kernel module 5, and to transfer the communication interface voltage at the second voltage level from the first buck modulation module 4 to the digital kernel module 5.

[0029] In this embodiment, the power selection module 2 includes a comparator and multiple selection logic circuits. The non-inverting input of the comparator is connected to the multiple selection logic circuits, the inverting input of the comparator is connected to the reference voltage input, and the output of the comparator is connected to the gate of PMOS transistor Q1 or the gate of PMOS transistor Q4.

[0030] The selection logic circuit includes a first MOSFET, a second MOSFET, an inverter, a logic gate, a first resistor, and a second resistor. The first common terminal of the first MOSFET and the second MOSFET is connected to the non-inverting input of the comparator and the remaining selection logic circuit, respectively. The second common terminal of the first MOSFET and the second MOSFET is connected to the common terminal of the first resistor and the second resistor, respectively. The gate of the first MOSFET is connected to the input of the inverter and the output of the logic gate, respectively. The gate of the second MOSFET is connected to the output of the inverter. The input of the logic gate is connected to multiple selection signal input terminals. The other end of the first resistor is connected to the communication interface voltage input terminal and the positive power supply terminal of the comparator, respectively. The other end of the second resistor is connected to the remaining selection logic circuit. The first MOSFET is a PMOS transistor, and the second MOSFET is an NMOS transistor.

[0031] Understandably, each selection logic circuit includes a first MOSFET, a second MOSFET, an inverter, a logic gate, and two resistors. The logic gate receives a multiplexing signal and outputs a control signal based on the selected operating mode. The control signal, after passing through the inverter, drives the gates of the first and second MOSFETs respectively, thereby controlling the conduction state of the two transistors. The common terminal of the first and second MOSFETs is connected to a set of resistors, generating different voltage distributions or current magnitudes under the drive of the communication interface voltage. The outputs of multiple selection logic circuits converge at the non-inverting input of the comparator, which is equivalent to selecting one range from a set of selectable resistors, making the non-inverting input of the comparator form a reference voltage Vref corresponding to a certain voltage range. By changing the selection signal of the selection logic circuit, the communication interface voltage range to be detected by the circuit can be flexibly set, such as a low voltage range (1.1V~1.3V) or a high voltage range (1.7V~1.95V, 2.7V~3.6V, etc.).

[0032] In this embodiment, through the cooperation of the first MOSFET, the second MOSFET, logic gates, and inverters, the non-inverting input of the comparator can be connected to other selection logic circuits, and also connected to the communication interface voltage and reference potential through a resistor network. The logic gate input receives multiple selection signals, allowing for flexible selection of the comparator input path based on different operating modes, interface configurations, or status signals. This enables configurability of the voltage detection / range judgment strategy, improving the circuit's adaptability and scalability. The gate of the first MOSFET is connected to both the inverter input and the logic gate output, while the gate of the second MOSFET is connected to the inverter output, forming a complementary conduction relationship: when the logic gate output is in a defined state, the inverter controls the first and second MOSFETs to be either on and off, or in a complementary state. This avoids competition and shoot-through current caused by simultaneous conduction of two paths, ensuring that the comparator's non-inverting input is connected to only one valid circuit path at any given time, improving the reliability and power consumption performance of the selection logic.

[0033] The comparator's inverting input is connected to the reference voltage input, while its non-inverting input receives voltage signals generated by the selection logic circuits. When the externally input communication interface voltage changes, the corresponding resistor network output voltage also changes. The comparator compares the voltage at its non-inverting input with the reference voltage in real time. When it detects that the communication interface voltage crosses a preset threshold, the comparator output level flips, forming a voltage detection signal.

[0034] The voltage detection signal is transmitted to the gates of Q1 to Q4 through the power selection module 2, enabling the circuit to automatically switch between the direct power supply path and the step-down path: when the communication interface voltage is in the first voltage range (such as the low voltage range), the comparator drives Q1 and Q2 to conduct and Q3 and Q4 to turn off, and VCCQ is directly powered by the filter module 3; when the communication interface voltage is in the second voltage range (such as the high voltage range), the comparator drives Q3 and Q4 to conduct and Q1 and Q2 to turn off, and VCCQ is sent to the first step-down modulation module 4, and is powered after step-down regulation.

[0035] Furthermore, such as Figure 3 As shown, the first selection logic circuit includes a PMOS transistor Q8, an NMOS transistor Q9, an inverter N1, a logic gate A1, resistors R8 and R9. The source of PMOS transistor Q8 and the drain of NMOS transistor Q9 are connected to the non-inverting input of comparator COMP and the common terminal of the PMOS and NMOS transistors of the remaining selection logic circuits, respectively. The drain of PMOS transistor Q8 and the source of NMOS transistor Q9 are connected to the common terminal of resistors R8 and R9. The gate of PMOS transistor Q8 is connected to the common terminal of inverter N1 and logic gate A1. The gate of NMOS transistor Q9 is connected to the output terminal of inverter N1. The input terminal of logic gate A1 is connected to multiple selection signal input terminals. The other end of resistor R8 is connected to the communication interface voltage input terminal and the positive power supply terminal of comparator COMP, respectively. The other end of resistor R9 is connected to one end of resistor R10 and the common terminal of the source of PMOS transistor Q10 and NMOS transistor Q11, respectively.

[0036] The second selection logic circuit includes a PMOS transistor Q10, an NMOS transistor Q11, an inverter N2, a logic gate A2, resistors R9 and R10. The source of PMOS transistor Q10 and the drain of NMOS transistor Q11 are connected to the non-inverting input of comparator COMP and the common terminal of the PMOS and NMOS transistors of the remaining selection logic circuits, respectively. The drain of PMOS transistor Q10 and the source of NMOS transistor Q11 are connected to the common terminal of resistors R9 and R10. The gate of PMOS transistor Q10 is connected to the common terminal of inverter N2 and logic gate A2. The gate of NMOS transistor Q11 is connected to the output terminal of inverter N2. The input terminal of logic gate A2 is connected to multiple selection signal input terminals. The other end of resistor R10 is connected to the third selection logic circuit.

[0037] The nth selection logic circuit includes a PMOS transistor Qn-1, an NMOS transistor Qn, an inverter Nn, a logic gate An, a resistor Rn-1, and a resistor Rn. The source of PMOS transistor Qn-1 and the drain of NMOS transistor Qn are connected to the non-inverting input of comparator COMP and the common terminal of the PMOS and NMOS transistors of the remaining selection logic circuits, respectively. The drain of PMOS transistor Qn-1 and the source of NMOS transistor Qn are connected to the common terminal of resistor Rn-1 and resistor Rn. The gate of PMOS transistor Qn-1 is connected to the common terminal of inverter Nn and logic gate An. The gate of NMOS transistor Qn is connected to the output terminal of inverter Nn. The input terminal of logic gate An is connected to multiple selection signal input terminals. The other end of resistor Rn-1 is connected to the communication interface voltage input terminal and the positive power supply terminal of comparator COMP, respectively. The other end of resistor Rn and the inverting input terminal of comparator COMP are grounded together.

[0038] In this embodiment, the digital kernel module 5 is used to perform protocol control and logic processing on the data read and write process of the eMMC, and obtains the preset kernel operating voltage through the filtering module 3 or the first buck modulation module 4 to ensure that it can work stably under different communication interface voltage conditions.

[0039] The filter module 3 includes a resistor R1 and a capacitor C1. One end of the resistor R1 is connected to the voltage detection module 1, and the other end of the resistor R1 is connected to one end of the capacitor C1 and the digital core module 5. The other end of the capacitor C1 is grounded. The filter module 3 forms an RC filter network consisting of the series resistor R1 and the capacitor C1 to ground. When the communication interface voltage is at the first voltage level and is introduced through the Q1 and Q2 paths, VCCQ is first reduced by R1 before being sent to the digital core module 5. At the same time, C1 forms a bypass path to ground to filter out power supply ripple and high-frequency noise, thereby improving power supply stability.

[0040] The first buck modulation module 4 includes a PMOS transistor Q5, resistors R2 and R3, capacitor C2, buffer BUF1, and error amplifier EA1. The source of PMOS transistor Q5 is connected to the positive power supply terminal of error amplifier EA1 and voltage detection module 1, respectively. The drain of PMOS transistor Q5 is connected to one end of resistor R2, one end of capacitor C2, and digital core module 5, respectively. The gate of PMOS transistor Q5 is connected to the other end of capacitor C2 and the output terminal of error amplifier EA1 through buffer BUF1, respectively. The non-inverting input terminal of error amplifier EA1 is connected to the reference voltage input terminal. The inverting input terminal of error amplifier EA1 is connected to the common terminal of resistors R2 and R3. The inverting power supply terminal of error amplifier EA1 and the other end of resistor R3 are grounded together.

[0041] In this embodiment, the first buck modulation module 4 is essentially an LDO buck regulator circuit, consisting of a PMOS transistor Q5, voltage divider resistors R2 and R3, capacitor C2, buffer BUF1, and error amplifier EA1. Q5 acts as a series regulator, with its source connected to the communication interface voltage input and its drain outputting the bucked voltage. The output terminal forms a feedback voltage divider through R2 and R3, and the feedback voltage is fed into the inverting input of EA1. The non-inverting input of EA1 is connected to the reference voltage input. EA1 compares the feedback voltage with the reference voltage and adjusts the output according to the deviation. This adjustment drives the gate of Q5 through buffer BUF1, changing the on-resistance of Q5 and thus stabilizing the output voltage. C2 is connected in parallel with the output terminal to achieve frequency compensation and output filtering, improving voltage regulation accuracy and transient response characteristics. Through this structure, the first buck modulation module 4 converts the higher communication interface voltage into a suitable operating voltage for the digital core module 5, achieving compatibility with different interface voltage standards.

[0042] Since an external power supply also provides the storage access voltage VCC to this power circuit to power the internal circuitry of the NAND memory module, this embodiment uses a second buck modulation module 6 and a third buck modulation module 7 to perform two independent buck regulation operations on this voltage, respectively supplying power to the core power supply and interface power supply of the NAND module 8.

[0043] The second buck modulation module 6 is connected to the NAND module 8. The second buck modulation module 6 is used to convert the externally input storage access voltage into the power supply voltage for the NAND module 8.

[0044] In this embodiment, please refer to Figure 4 The second buck modulation module 6 includes a PMOS transistor Q6, resistors R4 and R5, capacitor C3, buffer BUF2, and error amplifier EA2. The source of PMOS transistor Q6 is connected to the positive power supply terminal and the storage access voltage input terminal of error amplifier EA2, respectively. The drain of PMOS transistor Q6 is connected to one end of resistor R4, one end of capacitor C3, and NAND module 8, respectively. The gate of PMOS transistor Q6 is connected to the other end of capacitor C3 and the output terminal of error amplifier EA2 through buffer BUF2. The non-inverting input terminal of error amplifier EA2 is connected to the reference voltage input terminal. The inverting input terminal of error amplifier EA2 is connected to the common terminal of resistors R4 and R5. The inverting power supply terminal of error amplifier EA2 and the other end of resistor R5 are grounded together.

[0045] The second buck modulation module 6 has a similar structure to the first buck modulation module 4, consisting of a PMOS transistor Q6, voltage divider resistors R4 and R5, capacitor C3, buffer BUF2, and error amplifier EA2. The source of Q6 is connected to the storage access voltage input terminal; the drain of Q6 is output to the NAND module 8 via R4 and C3, corresponding to one working voltage of the NAND internal logic OR array; R4 and R5 divide the output voltage and feed it back to EA2; after comparing it with the reference voltage, EA2 controls the gate of Q6 through BUF2 to achieve voltage regulation of this output voltage.

[0046] The third buck modulation module 7 is connected to the NAND module 8. The third buck modulation module 7 is used to convert the externally input storage access voltage into the interface voltage supplied to the NAND module 8.

[0047] In this embodiment, please continue to refer to Figure 4 The third buck modulation module 7 includes a PMOS transistor Q7, resistors R6 and R7, capacitor C4, buffer BUF3, and error amplifier EA3. The source of PMOS transistor Q7 is connected to the positive power supply terminal and the storage access voltage input terminal of error amplifier EA3, respectively. The drain of PMOS transistor Q7 is connected to one end of resistor R6, one end of capacitor C4, and NAND module 8, respectively. The gate of PMOS transistor Q7 is connected to the other end of capacitor C4 and the output terminal of error amplifier EA3 through buffer BUF3, respectively. The non-inverting input terminal of error amplifier EA3 is connected to the reference voltage input terminal. The inverting input terminal of error amplifier EA3 is connected to the common terminal of resistors R6 and R7. The inverting power supply terminal of error amplifier EA3 and the other end of resistor R7 are grounded together.

[0048] The third buck modulation module 7 is also an LDO structure, consisting of PMOS transistor Q7, resistors R6 and R7, capacitor C4, buffer BUF3, and error amplifier EA3. Its operation is the same as the second buck modulation module 6, except that its output voltage setting is different. It provides another interface voltage for the NAND module 8, such as an I / O interface or a specific word line drive voltage. By independently bucking the same memory access voltage in two separate paths, this embodiment can meet the voltage level and stability requirements of different sub-circuits within the NAND module 8, improving the reliability of the eMMC device in various operating modes such as programming, erasing, and reading.

[0049] In this embodiment, the NAND module 8 is used to perform non-volatile storage of user data and management data in units of pages, and completes data programming, erasing and reading operations under the control of the digital kernel module 5; the NAND module 8 is provided with core power supply voltage and interface voltage by the second buck modulation module 6 and the third buck modulation module 7 respectively, so as to meet the voltage level and stability requirements of its internal sub-circuits.

[0050] Implementation Principle: By performing graded detection and multi-channel voltage regulation on the external communication interface voltage VCCQ and the storage access voltage VCC, an adaptive and stable operating power supply is provided to the digital core and NAND storage modules. Specifically, the voltage detection module 1, in conjunction with the power selection module 2, compares and classifies the input communication interface voltage into a first voltage level and a second voltage level: When VCCQ is in the low voltage level, the power selection module 2 controls the switching transistor to directly supply the communication interface voltage to the digital core via the filter module 3; when VCCQ is in the high voltage level, the communication interface voltage is sent to the first buck modulation module 4, where it is stepped down and regulated by an LDO before being output to the digital core, thus achieving automatic compatibility with different interface standards. Simultaneously, the storage access voltage VCC is converted into the core power supply voltage and interface voltage required by the NAND module 8 through the second buck modulation module 6 and the third buck modulation module 7, respectively, achieving graded voltage regulation for different sub-circuits within the NAND. Through this structure, this power supply circuit adapts to multiple input voltage levels while ensuring the stability of the power supply to each functional module.

[0051] In this embodiment, the voltage detection module 1 divides the external communication interface voltage into a first voltage level and a second voltage level, and works in conjunction with the power selection module 2 to automatically select the power supply path. This achieves automatic identification and adaptive power supply for different external interface voltages. When the external communication interface voltage is at the appropriate first voltage level, a filtering and direct power supply method is used, without additional step-down modulation, reducing losses in the voltage conversion process. The first step-down modulation module 4 is only activated when the voltage is at the second level, avoiding unnecessary conversion. This method of selecting different power supply paths according to voltage level improves the overall utilization efficiency of the eMMC power circuit, reduces internal chip power consumption and temperature rise, and ensures that for the second voltage level, which exceeds the safe operating range of the digital core, power is supplied after conversion by the first step-down modulation module 4, effectively preventing high voltage from being directly applied to the digital core and avoiding overvoltage damage. The hierarchical design of voltage detection, gating, and step-down allows this power circuit to adapt to a wider range of external input interface voltages, enhancing the product's adaptability and reliability to different main controllers and different standard interfaces. The first module provides independent and stable core and interface voltages for NAND module 8, improving storage performance and compatibility. The second buck modulation module 6 converts the external storage access voltage into the power supply voltage for the internal operation of NAND module 8, ensuring that the storage cells and control circuits operate under stable and safe voltage. The third buck modulation module 7 converts the same external storage access voltage into the interface voltage required by the NAND interface, allowing the NAND I / O level to match different controllers or different standards. The communication interface voltage path and NAND power / interface voltage are all detected, selected, and stepped down within this eMMC power circuit, eliminating the need to add multiple LDOs or DC-DC modules at the board level.

[0052] By integrating multiple voltage conversion and management functions into a single circuit, the number of external components is reduced, lowering BOM costs and PCB area, while also reducing the complexity of power supply routing and potential sources of interference.

[0053] This application also provides an eMMC power system applied to an eMMC chip integrating a digital core module 5 and a NAND module 8, for providing multiple stable power supplies to the digital core module 5 and the NAND module 8. This eMMC power system includes the eMMC power circuit of any of the above embodiments.

[0054] In this embodiment, the eMMC power system is equipped with a communication interface voltage input terminal and a storage access voltage input terminal. The communication interface voltage input terminal receives the communication interface voltage VCCQ from the host side, and the storage access voltage input terminal receives the storage access voltage VCC from the host side. The communication interface voltage VCCQ is detected and path-selected by the voltage detection module 1 and the power selection module 2: when VCCQ is in the preset first voltage level, the power selection module 2 controls the communication interface voltage to be directly supplied to the digital kernel module 5 after being processed by the filtering module 3; when VCCQ is in the preset second voltage level, the power selection module 2 controls the communication interface voltage to be sent to the first buck modulation module 4, and after being buck-regulated, it is supplied to the digital kernel module 5. Thus, the eMMC power system automatically adapts to different communication interface voltage standards.

[0055] Simultaneously, the memory access voltage VCC is input to both the second buck modulation module 6 and the third buck modulation module 7. The second buck modulation module 6 converts VCC into a first output voltage, which serves as the core power supply voltage for the NAND module 8; the third buck modulation module 7 converts VCC into a second output voltage, which serves as the interface voltage for the NAND module 8. By performing dual-path independent buck regulation on the same memory access voltage, the eMMC power system can meet the voltage level and stability requirements of different sub-circuits within the NAND module 8.

[0056] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An eMMC power supply circuit, characterized in that, It includes a voltage detection module (1), a power selection module (2), a filtering module (3), a first buck modulation module (4), a digital core module (5), a second buck modulation module (6), a third buck modulation module (7), and a NAND module (8), wherein, The voltage detection module (1) is connected to the power selection module (2). The voltage detection module (1) is used to detect the externally input communication interface voltage and divide the fluctuation range corresponding to the communication interface voltage into a first voltage level and a second voltage level. The power selection module (2) is connected to the filter module (3) and the first buck modulation module (4) respectively. The power selection module (2) is used to transfer the communication interface voltage at the first voltage level from the filter module (3) to the digital kernel module (5), and to transfer the communication interface voltage at the second voltage level from the first buck modulation module (4) to the digital kernel module (5). The second buck modulation module (6) is connected to the NAND module (8), and the second buck modulation module (6) is used to convert the externally input storage access voltage into the power supply voltage supplied to the NAND module (8); The third buck modulation module (7) is connected to the NAND module (8), and the third buck modulation module (7) is used to convert the externally input storage access voltage into the interface voltage supplied to the NAND module (8).

2. The eMMC power supply circuit as described in claim 1, characterized in that, The voltage detection module (1) includes a PMOS transistor Q1, an NMOS transistor Q2, a PMOS transistor Q3, and an NMOS transistor Q4. The drain of the PMOS transistor Q1 and the source of the NMOS transistor Q2 are both connected to the voltage input terminal of the communication interface. The source of the PMOS transistor Q1 and the drain of the NMOS transistor Q2 are both connected to the filter module (3). The gate of the PMOS transistor Q1 and the gate of the NMOS transistor Q2 are connected through the power selection module (2). The drain of the PMOS transistor Q3 and the source of the NMOS transistor Q4 are both connected to the voltage input terminal of the communication interface. The source of the PMOS transistor Q3 and the drain of the NMOS transistor Q4 are both connected to the first buck modulation module (4). The gate of the PMOS transistor Q3 and the gate of the NMOS transistor Q4 are connected through the power selection module (2).

3. The eMMC power supply circuit as described in claim 2, characterized in that, The power selection module (2) includes a comparator and multiple selection logic circuits. The non-inverting input of the comparator is connected to the multiple selection logic circuits respectively. The inverting input of the comparator is connected to the reference voltage input. The output of the comparator is connected to the gate of the PMOS transistor Q1 or the gate of the PMOS transistor Q4.

4. The eMMC power supply circuit as described in claim 3, characterized in that, The selection logic circuit includes a first MOSFET, a second MOSFET, an inverter, a logic gate, a first resistor, and a second resistor. The first common terminal of the first MOSFET and the second MOSFET is connected to the non-inverting input terminal of the comparator and the remaining selection logic circuit, respectively. The second common terminal of the first MOSFET and the second MOSFET is connected to the common terminal of the first resistor and the second resistor, respectively. The gate of the first MOSFET is connected to the input terminal of the inverter and the output terminal of the logic gate, respectively. The gate of the second MOSFET is connected to the output terminal of the inverter, respectively. The input terminal of the logic gate is connected to multiple selection signal input terminals, respectively. The other end of the first resistor is connected to the communication interface voltage input terminal and the positive power supply terminal of the comparator, respectively. The other end of the second resistor is connected to the remaining selection logic circuit.

5. The eMMC power supply circuit as described in claim 1, characterized in that, The filtering module (3) includes a resistor R1 and a capacitor C1. One end of the resistor R1 is connected to the voltage detection module (1), and the other end of the resistor R1 is connected to one end of the capacitor C1 and the digital kernel module (5). The other end of the capacitor C1 is grounded.

6. The eMMC power supply circuit as described in claim 1, characterized in that, The first buck modulation module (4) includes a PMOS transistor Q5, resistors R2 and R3, capacitor C2, buffer BUF1, and error amplifier EA1. The source of the PMOS transistor Q5 is connected to the positive power supply terminal of the error amplifier EA1 and the voltage detection module (1). The drain of the PMOS transistor Q5 is connected to one end of the resistor R2, one end of the capacitor C2, and the digital core module (5). The gate of the PMOS transistor Q5 is connected to the other end of the capacitor C2 and the output terminal of the error amplifier EA1 through the buffer BUF1. The non-inverting input terminal of the error amplifier EA1 is connected to the reference voltage input terminal. The inverting input terminal of the error amplifier EA1 is connected to the common terminal of the resistors R2 and R3. The inverting power supply terminal of the error amplifier EA1 and the other end of the resistor R3 are grounded together.

7. The eMMC power supply circuit as described in claim 1, characterized in that, The second buck modulation module (6) includes a PMOS transistor Q6, resistors R4 and R5, capacitor C3, buffer BUF2, and error amplifier EA2. The source of the PMOS transistor Q6 is connected to the positive power supply terminal and the storage access voltage input terminal of the error amplifier EA2, respectively. The drain of the PMOS transistor Q6 is connected to one end of the resistor R4, one end of the capacitor C3, and the NAND module (8), respectively. The gate of the PMOS transistor Q6 is connected to the other end of the capacitor C3 and the output terminal of the error amplifier EA2 through the buffer BUF2, respectively. The non-inverting input terminal of the error amplifier EA2 is connected to the reference voltage input terminal. The inverting input terminal of the error amplifier EA2 is connected to the common terminal of the resistors R4 and R5. The inverting power supply terminal of the error amplifier EA2 and the other end of the resistor R5 are grounded together.

8. The eMMC power supply circuit as described in claim 7, characterized in that, The third buck modulation module (7) includes a PMOS transistor Q7, resistors R6 and R7, capacitor C4, buffer BUF3, and error amplifier EA3. The source of the PMOS transistor Q7 is connected to the positive power supply terminal and the storage access voltage input terminal of the error amplifier EA3, respectively. The drain of the PMOS transistor Q7 is connected to one end of resistor R6, one end of capacitor C4, and the NAND module (8), respectively. The gate of the PMOS transistor Q7 is connected to the other end of capacitor C4 and the output terminal of error amplifier EA3 through buffer BUF3, respectively. The non-inverting input terminal of error amplifier EA3 is connected to the reference voltage input terminal. The inverting input terminal of error amplifier EA3 is connected to the common terminal of resistors R6 and R7. The inverting power supply terminal of error amplifier EA3 and the other end of resistor R7 are grounded together.

9. The eMMC power supply circuit as described in claim 4, characterized in that, The first MOS transistor is a PMOS transistor, and the second MOS transistor is an NMOS transistor.

10. An eMMC power supply system, characterized in that, The eMMC power system includes the eMMC power circuit as described in any one of claims 1 to 9.

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