Control circuit and method for time sequence of depletion type solid state power controller
By designing a timing control circuit for a depletion-type solid-state power controller and combining timing control of capacitors and resistors, the problem of brief power loss during power-on and power-off processes of depletion-type intelligent power distribution safety switches is solved, realizing continuous conduction and restart functions, which are suitable for the lightweight and high reliability requirements of aerospace equipment.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIAN MICROELECTRONICS TECH INST
- Filing Date
- 2026-01-08
- Publication Date
- 2026-04-28
AI Technical Summary
In existing technologies, depletion-type intelligent power distribution safety switches have a problem of brief power loss during the bias power-on and power-off process, which cannot meet the requirements of initial power-on and load connection. Moreover, the timing management requirements of line design are much higher than those of traditional intelligent power distribution safety switches.
A timing control circuit for a depletion-mode solid-state power controller was designed. By combining a first circuit structure, a second circuit structure, a first comparator N1, a third circuit structure, a second comparator N2, and a depletion-mode VDMOS transistor M1, along with the design of capacitor C1 and resistors, precise timing control is achieved, ensuring that the depletion-mode VDMOS transistor M1 remains on during power-on and power-off processes. Furthermore, miniaturization and high reliability are achieved through a hybrid integrated circuit structure using thick-film technology.
It realizes the continuous conduction function of intelligent power distribution safety switch during power-on and power-off processes, replacing the function of traditional fuses, and has a restart function. It is suitable for the lightweight, miniaturized and high reliability requirements of aerospace equipment and is applicable to pyrotechnic modules in aerospace scenarios such as satellites and space stations.
Smart Images
Figure CN121939964A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor hybrid integrated circuit design technology, specifically to a timing control circuit and method for a depletion-type solid-state power controller. Background Technology
[0002] With the continuous development of the aerospace industry, the carrying capacity of new-generation space launch vehicles has been greatly improved, and the scale of models has been continuously expanded, resulting in a significant increase in the number of supporting electronic equipment. This change has made the power demand of equipment increasingly complex, placing higher demands on the performance of power supply and distribution systems, and driving the power supply and distribution systems to gradually evolve from traditional to intelligent, integrated, miniaturized, and lightweight.
[0003] However, traditional relay-based power supply and distribution systems can no longer meet the demands of current intelligent power supply and distribution systems in terms of intelligence and reliability. Against this backdrop, solid-state power distribution technology has become the mainstream trend in the industry. This technology was first widely used in the US aerospace field, and with its increasing maturity, its research and application in my country's spacecraft power supply and distribution systems are gradually unfolding.
[0004] Solid-state power controllers (SSPCs) are the core components of solid-state power distribution systems. They integrate the switching function of relays and the protection function of circuit breakers, playing a crucial role in controlling the on / off state of loads. With the increasing demands for power distribution system control, SSPCs also need to possess the characteristics of fuses, ensuring that the load is connected when the bus is initially energized.
[0005] In existing technologies, conventional intelligent power distribution safety switches mostly use enhancement-mode VDMOS transistors, which require front-end control to achieve bus conduction, and cannot directly meet the initial power-on load connection requirements. To solve this problem, the industry has begun to explore the design of depletion-mode intelligent power distribution safety switches using N-channel depletion-mode VDMOS transistors. This type of switch can achieve initial default conduction when not powered on, and its function is more in line with the usage habits of traditional fuses and circuit breakers. Moreover, after fault troubleshooting, it can resume operation through reset and control turn-on commands.
[0006] However, most of the related drive components in the industry are based on the enhancement VDMOS transistor design. If it is adapted to the depletion-type smart power distribution safety switch, the timing management requirements of its circuit design are much higher than those of the traditional smart power distribution safety switch. This problem has become the core bottleneck in the development of depletion-type solid-state power controllers. Summary of the Invention
[0007] In order to overcome the defects of the prior art, the purpose of this invention is to provide a control circuit and method for the timing of a depletion-type solid-state power controller, so as to solve the problem of brief power loss during the biasing and power-off process of the depletion-type intelligent power distribution safety switch in the prior art.
[0008] This invention is achieved through the following technical solution: In a first aspect, the present invention provides a control circuit for the timing of a depletion-type solid-state power controller, comprising a first circuit structure, a second circuit structure, a first comparator N1, a third circuit structure, a second comparator N2, and a depletion-type VDMOS transistor M1. One end of the first circuit structure is connected to the power supply terminal VDD, and the other end is connected to the power supply VEE. The first circuit structure forms a first path with the power supply terminal VDD and the power supply terminal VEE. One end of the second circuit structure is connected to the power supply terminal VDD, and the other end is connected to the GND terminal of the pre-amplifier chip. The second circuit structure forms a second path with the power supply terminal VDD and the GND terminal of the pre-amplifier chip. The non-inverting input of the first comparator N1 is connected to the first path structure, and the inverting input is connected to the second path. One end of the third circuit structure is connected to the power supply terminal VDD, and the other end is connected to the power supply terminal VEE. The third circuit structure, the power supply terminal VDD, and the power supply terminal VEE form a third path. The inverting input of the second comparator N2 is connected to the output of the first comparator N1 via a third path, and the non-inverting input is connected to the output MOS_OUT of the preceding driver chip. The output of the second comparator N2 is connected to the gate of the depletion-type VDMOS transistor M1.
[0009] Preferably, the first circuit structure includes a first resistor R1 and a second resistor R2 connected in series; The power supply terminal VDD, the first resistor R1, the second resistor R2, and the power supply terminal VEE form a first path; The non-inverting input of the first-stage comparator N1 is connected between the first resistor R1 and the second resistor R2.
[0010] Preferably, the second circuit structure includes a third resistor R3 and a Zener diode DZ1 connected in series; The power supply terminal VDD, the third resistor R3, and the GND terminal of the pre-amplifier driver chip DZ1 form a second path. The inverting input of the first-stage comparator N1 is connected between the third resistor R3 and the Zener diode DZ1.
[0011] Preferably, the third circuit structure includes a fourth resistor R4 and a fifth resistor R5 connected in series; The power supply terminal VDD, the fourth resistor R4, the fifth resistor R5, and the power supply terminal VEE form a third path; The output of the first-stage comparator N1 is connected to the inverting terminal of the second comparator N2 via the fourth resistor R4 and the fifth resistor R5.
[0012] Furthermore, the third circuit structure also includes a capacitor C1, which is connected in parallel with the fifth resistor R5 to slow down the rate of voltage change at the inverting input of the second comparator N2.
[0013] Preferably, it also includes a sixth resistor R6 and a seventh resistor R7; One end of the sixth resistor R6 is connected to the power supply terminal VDD, and the other end is connected to the seventh resistor R7. The output terminal of the second comparator N2 is connected to the common point of the sixth resistor R6 and the seventh resistor R7, and then connected to the gate of the depletion-type VDMOS transistor M1 through the seventh resistor R7. The sixth resistor R6 is a pull-up resistor used to stabilize the output signal of the second comparator N2; the seventh resistor R7 is used to provide current limiting protection for the gate of the depletion-type VDMOS transistor M1.
[0014] Secondly, the present invention also provides a timing control method for a depletion-type solid-state power controller, based on the aforementioned timing control circuit for a depletion-type solid-state power controller, including a bias power supply power-on process and a bias power supply power-off process, as detailed below: The bias power supply power-on process includes: the bias power supply is powered on, simultaneously supplying power to the front-end driver chip, power supply terminal VDD, and power supply terminal VEE; the voltage at the non-inverting input of the second comparator N2 rises rapidly, and the output voltage of the first comparator N1 drops rapidly to the power supply terminal VEE; the inverting input of the second comparator N2 first receives the power supply terminal VEE voltage, and then rises slowly through capacitor C1 to the voltage divider reference of the fourth resistor R4 and the fifth resistor R5; the voltage at the non-inverting input of the second comparator N2 is always greater than the voltage at the inverting input, so that the gate of the depletion-type VDMOS transistor M1 receives 0V or a positive voltage, keeping the VDMOS transistor M1 on; The bias power supply de-energization process includes: the bias power supply is de-energized, the voltage at the inverting input of the first comparator N1 remains unchanged initially, and the voltage at the non-inverting input drops rapidly, causing the output of the first comparator N1 to drop rapidly to the power supply terminal VEE, and then rise slowly to 0V through capacitor C1 and be transmitted to the inverting input of the second comparator N2; the voltage at the non-inverting input of the second comparator N2 drops rapidly to 0V; the voltage at the non-inverting input of the second comparator N2 is always greater than the voltage at the inverting input, so that the gate of the depletion-type VDMOS transistor M1 receives 0V or a positive voltage, keeping the depletion-type VDMOS transistor M1 on.
[0015] Furthermore, the power supply terminal VDD is a +10V power supply, and the power supply terminal VEE is a -10V power supply. The power supply terminals VDD and VEE are obtained by conversion from the bias power supply 5V.
[0016] Furthermore, the non-inverting input of the first comparator N1 is connected to the voltage divided by the first resistor R1 and the second resistor R2, and the inverting input of the first comparator N1 is connected to the voltage regulated by the third resistor R3 and the Zener diode DZ1.
[0017] Furthermore, the inverting input of the second comparator N2 simultaneously receives the output signal of the first comparator N1 and the voltage divider signal from the fourth resistor R4 and the fifth resistor R5.
[0018] Compared with the prior art, the present invention has the following beneficial technical effects: This invention provides a timing control circuit for a depletion-type solid-state power controller. Through the coordinated structure of a first circuit, a second circuit, and a first comparator N1, combined with the capacitor and resistor design in the third circuit to delay the voltage change at the inverting terminal of the second comparator N2, a precise timing control structure is formed. This synergistic cooperation at the structural level enables the intelligent power distribution safety switch to remain continuously conducting during power-on and power-off processes. Furthermore, relying on the connections of the resistors and comparators in the circuit, operation can be restored after fault clearing via reset and control on-state commands. Thus, at the structural level, it supports the functional replacement of traditional fuses and the realization of restart functions. Simultaneously, this control circuit adopts a hybrid integrated circuit structure based on thick-film technology. This structure inherently possesses miniaturization characteristics, effectively reducing the overall weight and volume of the circuit. The thick-film technology design further enhances the circuit's reliability, meeting the requirements of lightweight, miniaturized, and highly reliable power distribution components in aerospace equipment. Therefore, it possesses broad application prospects and market potential.
[0019] This invention also provides a timing control method for a depletion-type solid-state power controller. By designing a step of simultaneously supplying power to the front-end driver chip and the power supply terminals VDD and VEE when the bias power supply is powered on, and combining this with the timing logic of the rapid rise of the voltage at the non-inverting input of the second comparator N2 and the delay of the voltage rise at the inverting input via capacitor C1, combined with the rapid change of the output voltage of the first comparator N1, it can be ensured that the voltage at the non-inverting input of the second comparator N2 is always greater than the voltage at the inverting input, thereby stably achieving a 0V or positive voltage at the gate of the depletion-type VDMOS transistor M1 to remain on. During the de-energization process, relying on the early-stage stability characteristics of the voltage at the inverting input of the first comparator N1, the rapid decrease in the voltage at the non-inverting input, and the delaying effect of capacitor C1 on the voltage change at the inverting input of the second comparator N2, the voltage difference between the non-inverting and inverting inputs of the second comparator N2 is maintained, further ensuring the continuous on-state of the depletion-type VDMOS transistor M1. Meanwhile, the design of connecting the non-inverting and inverting inputs of the first comparator N1 to the corresponding resistor voltage divider and Zener diode voltage respectively, along with the logic of the inverting input of the second comparator N2 simultaneously receiving the output signal of the first comparator N1 and the resistor voltage divider signal, improves the reliability of timing judgment. This timing control logic at this method level not only realizes the function of the intelligent power distribution safety switch being initially turned on when not powered on, replacing the traditional fuse and providing a stable circuit state basis for restarting after a fault, but its precise timing coordination also meets the stringent requirements of aerospace equipment for power supply stability. Combined with the circuit's radiation resistance and other characteristics, it can be stably applied in pyrotechnic modules in aerospace scenarios such as satellites and space stations, and has broad application value. Attached Figure Description
[0020] Figure 1 This is a control circuit structure diagram of the timing of the depletion-type solid-state power controller in an embodiment of the present invention; Figure 2 This is a diagram illustrating the process of establishing the non-inverting and inverting inputs of comparator N2 when the bias power supply of 5V is powered on in an embodiment of the present invention. Figure 3 This is a diagram illustrating the process of establishing the non-inverting and inverting inputs of comparator N2 when the 5V bias power supply is de-energized in this embodiment of the invention. In the diagram: R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; C1, capacitor; DZ1, Zener diode; N1, first comparator; N2, second comparator; M1, depletion-mode VDMOS transistor. Detailed Implementation
[0021] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0022] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0023] The purpose of this invention is to provide a control circuit and method for timing of a depletion-type solid-state power controller, so as to solve the problem of brief power loss during the biasing and power-off process of a depletion-type intelligent power distribution safety switch in the prior art.
[0024] The present invention will now be described in further detail with reference to the accompanying drawings: Example 1 See Figure 1In one embodiment of the present invention, a control circuit for the timing of a depletion-type solid-state power controller is provided, including a first circuit structure, a second circuit structure, a first comparator N1, a third circuit structure, a second comparator N2, and a depletion-type VDMOS transistor M1; one end of the first circuit structure is connected to the power supply terminal VDD, and the other end is connected to the power supply terminal VEE, and the first circuit structure forms a first path with the power supply terminal VDD and the power supply terminal VEE; one end of the second circuit structure is connected to the power supply terminal VDD, and the other end is connected to the GND terminal of the front-end driver chip, and the second circuit structure forms a first path with the power supply terminal VDD. The first comparator N1 forms a second path with the GND terminal of the pre-stage driver chip; the non-inverting terminal of the first comparator N1 is connected to the first path structure, and the inverting terminal is connected to the second path; one end of the third circuit structure is connected to the power supply terminal VDD, and the other end is connected to the power supply terminal VEE, and the third circuit structure forms a third path with the power supply terminal VDD and the power supply terminal VEE; the inverting terminal of the second comparator N2 is connected to the output terminal of the first comparator N1 through the third path, and the non-inverting terminal is connected to the output MOS_OUT terminal of the pre-stage driver chip; the output terminal of the second comparator N2 is connected to the gate of the depletion-type VDMOS transistor M1.
[0025] Specifically, the first circuit structure includes a first resistor R1 and a second resistor R2 connected in series; the power supply terminal VDD, the first resistor R1, the second resistor R2 and the power supply terminal VEE form a first path; the non-inverting input of the first stage comparator N1 is connected between the first resistor R1 and the second resistor R2.
[0026] In this embodiment, the first resistor R1 and the second resistor R2 are connected in series and then connected between the power supply terminals VDD and VEE to form a voltage divider path; the non-inverting input of the first comparator N1 is connected to the connection node of R1 and R2, and can obtain the voltage obtained by the voltage divider of R1 and R2.
[0027] Specifically, the second circuit structure includes a third resistor R3 and a Zener diode DZ1 connected in series; the power supply terminal VDD, the third resistor R3, and the GND terminal of the pre-stage driver chip of the Zener diode DZ1 form a second path; the inverting terminal of the first stage comparator N1 is connected between the third resistor R3 and the Zener diode DZ1, serving as the reference for the first comparator N1.
[0028] In this embodiment, the third resistor R3 is connected in series with the Zener diode DZ1 and then connected between the power supply terminal VDD and the GND terminal of the front-end driver chip. The Zener diode DZ1 can stabilize the voltage across its two ends. The inverting input of the first comparator N1 is connected to the connection node of R3 and DZ1, and can obtain the stable voltage after being regulated by DZ1. This voltage will be used as the inverting input reference of the first comparator N1 and compared with the input voltage of the non-inverting input.
[0029] Specifically, the third circuit structure includes a fourth resistor R4 and a fifth resistor R5 connected in series; the power supply terminal VDD, the fourth resistor R4, the fifth resistor R5 and the power supply terminal VEE form a third path; the output terminal of the first stage comparator N1 is connected to the inverting terminal of the second comparator N2 through the fourth resistor R4 and the fifth resistor R5.
[0030] In this embodiment, the fourth resistor R4 and the fifth resistor R5 are connected in series between the power supply terminals VDD and VEE to form a voltage divider path to provide a reference voltage. At the same time, the output terminal of the first comparator N1 is connected to the connection node of R4 and R5, and then transmitted to the inverting terminal of the second comparator N2. This allows the inverting terminal of the second comparator N2 to simultaneously receive the output signal of the first comparator N1 and the voltage divider signal of R4 and R5, providing a composite input signal for the voltage comparison logic of the second comparator N2.
[0031] The third circuit structure also includes a capacitor C1, which is connected in parallel with the fifth resistor R5 to slow down the rate of voltage change at the inverting terminal of the second comparator N2.
[0032] In this embodiment, capacitor C1 is connected in parallel across the fifth resistor R5. Utilizing the charging and discharging characteristics of the capacitor, when the node voltage corresponding to the inverting input of the second comparator N2 changes, C1 will slow down the voltage change rate of that node through the charging and discharging process, thereby delaying the voltage change rate of the inverting input of the second comparator N2. This adjusts the timing of the voltage change at the inverting input of the second comparator N2 to meet the timing control requirements of the matching circuit.
[0033] In this embodiment, a sixth resistor R6 and a seventh resistor R7 are also included. One end of the sixth resistor R6 is connected to the power supply terminal VDD, and the other end is connected to the seventh resistor R7. The output terminal of the second comparator N2 is connected to the common point of the sixth resistor R6 and the seventh resistor R7, and then connected to the gate of the depletion-type VDMOS transistor M1 through the seventh resistor R7. The sixth resistor R6 is a pull-up resistor used to stabilize the output signal of the second comparator N2. The seventh resistor R7 is used to provide current limiting protection for the gate of the depletion-type VDMOS transistor M1.
[0034] In this embodiment, the sixth resistor R6 serves as a pull-up resistor, with one end connected to the power supply terminal VDD and the other end connected to the seventh resistor R7. When the output of the second comparator N2 is in a high-impedance state, R6 can pull the output level to the voltage corresponding to the power supply terminal VDD, thereby stabilizing the output signal of the second comparator N2. The seventh resistor R7 is connected in series between the output terminal of the second comparator N2 and the gate of the depletion-type VDMOS transistor M1, which can limit the current flowing into the gate of the depletion-type VDMOS transistor M1, avoid excessive current damage to the gate of M1, and achieve gate current limiting protection for the VDMOS transistor M1.
[0035] Example 2 This embodiment also provides a timing control method for a depletion-mode solid-state power controller. Based on the aforementioned timing control circuit for a depletion-mode solid-state power controller, it includes a 5V bias power-on process and a 5V bias power-off process, as detailed below: according to Figure 2 As shown, the 5V bias power supply power-on process includes: the bias power supply is powered on, simultaneously supplying power to the front-end driver chip, power supply terminal VDD, and power supply terminal VEE; the voltage at the non-inverting input of the second comparator N2 quickly rises from 0V to 10V, and the output voltage of the first comparator N1 quickly drops to the power supply terminal VEE; the inverting input of the second comparator N2 first receives the power supply terminal VEE voltage, and then rises slowly through capacitor C1 to the voltage divider reference of the fourth resistor R4 and the fifth resistor R5; the voltage at the non-inverting input of the second comparator N2 is always greater than the voltage at the inverting input, so that the gate of the depletion-type VDMOS transistor M1 receives 0V or a positive voltage, keeping the VDMOS transistor M1 on; according to Figure 3 As shown, the 5V bias power supply de-energization process includes: the bias power supply is de-energized, the voltage at the inverting input of the first comparator N1 remains unchanged initially, and the voltage at the non-inverting input drops rapidly, causing the output of the first comparator N1 to drop rapidly to the power supply terminal VEE, and then rise slowly to 0V through capacitor C1 and be transmitted to the inverting input of the second comparator N2; the voltage at the non-inverting input of the second comparator N2 drops rapidly from 10V to 0V; the voltage at the non-inverting input of the second comparator N2 is always greater than the voltage at the inverting input, so that the gate of the depletion-type VDMOS transistor M1 receives 0V or a positive voltage, keeping the depletion-type VDMOS transistor M1 on.
[0036] Specifically, the power supply VDD is a +10V power supply, and the power supply VEE is a -10V power supply. Both the power supply VDD and the power supply VEE are obtained by conversion from the bias power supply 5V.
[0037] Specifically, the non-inverting input of the first comparator N1 is connected to the voltage divided by the first resistor R1 and the second resistor R2, and the inverting input of the first comparator N1 is connected to the voltage regulated by the third resistor R3 and the Zener diode DZ1.
[0038] Specifically, the inverting input of the second comparator N2 simultaneously receives the output signal of the first comparator N1 and the voltage divider signal from the fourth resistor R4 and the fifth resistor R5.
[0039] In this embodiment, the depletion-mode solid-state power controller can guarantee default conduction upon initial power-on and has I 2 With T-protection / short-circuit protection functions and trip status feedback function, it meets the characteristics of high reliability, long life and miniaturization, and can replace traditional relays, fuses and circuit breakers. It is widely used in various aerospace systems and other high-reliability application fields.
[0040] The circuit uses a depletion-mode power transistor, which is initially powered on by default. This is different from a solid-state power controller that controls the output of an enhancement-mode power transistor through a bias power supply. Therefore, in the circuit design, in addition to ensuring the reliability of steady-state operation, the influence of the bias power supply power-on and power-off process on the power output switching transistor should also be considered. Incorrect timing will cause abnormal power output.
[0041] During the bias power supply power-on process, it is necessary to ensure that the drive output is always greater than the self-set reference, and the drive output power-on speed is faster than the self-set reference power-on speed. During the bias power supply power-off process, it is also necessary to ensure that the drive output is always greater than the self-set reference, but at this time, it is required that the drive output power-down speed is slower than the self-set reference power-up speed. This invention uses a hardware design approach, through the combination design of comparators, resistors, and capacitors, to control the timing of circuit switching, thereby solving the problem of brief power-down during the bias power-on and power-off processes of the depletion-type intelligent power distribution safety switch.
[0042] In summary, this invention, through timing design, enables the intelligent power distribution safety switch to remain continuously conductive during power-on and power-off processes, functionally replacing traditional fuses and providing a restart function. Combined with the miniaturization technology of hybrid integrated circuits using thick-film technology, the overall circuit offers significant advantages in terms of weight, size, and reliability. By selecting components that meet radiation resistance requirements, this technology can be widely applied to pyrotechnic modules in satellites, space stations, and spacecraft, demonstrating a very broad application prospect and market potential.
[0043] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A control circuit for the timing of a depletion-type solid-state power controller, characterized in that, It includes a first circuit structure, a second circuit structure, a first comparator N1, a third circuit structure, a second comparator N2, and a depletion-type VDMOS transistor M1; One end of the first circuit structure is connected to the power supply terminal VDD, and the other end is connected to the power supply VEE. The first circuit structure forms a first path with the power supply terminal VDD and the power supply terminal VEE. One end of the second circuit structure is connected to the power supply terminal VDD, and the other end is connected to the GND terminal of the pre-amplifier chip. The second circuit structure forms a second path with the power supply terminal VDD and the GND terminal of the pre-amplifier chip. The non-inverting input of the first comparator N1 is connected to the first path structure, and the inverting input is connected to the second path. One end of the third circuit structure is connected to the power supply terminal VDD, and the other end is connected to the power supply terminal VEE. The third circuit structure, the power supply terminal VDD, and the power supply terminal VEE form a third path. The inverting input of the second comparator N2 is connected to the output of the first comparator N1 via a third path, and the non-inverting input is connected to the output MOS_OUT of the preceding driver chip. The output of the second comparator N2 is connected to the gate of the depletion-type VDMOS transistor M1.
2. The control circuit for the timing of a depletion-type solid-state power controller according to claim 1, characterized in that, The first circuit structure includes a first resistor R1 and a second resistor R2 connected in series; The power supply terminal VDD, the first resistor R1, the second resistor R2, and the power supply terminal VEE form a first path; The non-inverting input of the first-stage comparator N1 is connected between the first resistor R1 and the second resistor R2.
3. The control circuit for the timing of a depletion-type solid-state power controller according to claim 1, characterized in that, The second circuit structure includes a third resistor R3 and a Zener diode DZ1 connected in series; The power supply terminal VDD, the third resistor R3, and the GND terminal of the pre-amplifier driver chip DZ1 form a second path. The inverting input of the first-stage comparator N1 is connected between the third resistor R3 and the Zener diode DZ1.
4. The control circuit for the timing of a depletion-type solid-state power controller according to claim 1, characterized in that, The third circuit structure includes a fourth resistor R4 and a fifth resistor R5 connected in series; The power supply terminal VDD, the fourth resistor R4, the fifth resistor R5, and the power supply terminal VEE form a third path; The output of the first-stage comparator N1 is connected to the inverting terminal of the second comparator N2 via the fourth resistor R4 and the fifth resistor R5.
5. The control circuit for the timing of a depletion-type solid-state power controller according to claim 4, characterized in that, The third circuit structure also includes a capacitor C1, which is connected in parallel with the fifth resistor R5 to slow down the rate of voltage change at the inverting input of the second comparator N2.
6. The control circuit for the timing of a depletion-type solid-state power controller according to claim 1, characterized in that, It also includes the sixth resistor R6 and the seventh resistor R7; One end of the sixth resistor R6 is connected to the power supply terminal VDD, and the other end is connected to the seventh resistor R7. The output terminal of the second comparator N2 is connected to the common point of the sixth resistor R6 and the seventh resistor R7, and then connected to the gate of the depletion-type VDMOS transistor M1 through the seventh resistor R7. The sixth resistor R6 is a pull-up resistor used to stabilize the output signal of the second comparator N2; the seventh resistor R7 is used to provide current limiting protection for the gate of the depletion-type VDMOS transistor M1.
7. A timing control method for a depletion-type solid-state power controller, characterized in that, The control circuit based on the timing of the depletion-type solid-state power controller according to any one of claims 1-6 includes a bias power supply power-on process and a bias power supply power-off process, as detailed below: The bias power supply power-on process includes: the bias power supply is powered on, simultaneously supplying power to the front-end driver chip, power supply terminal VDD, and power supply terminal VEE; the voltage at the non-inverting input of the second comparator N2 rises rapidly, and the output voltage of the first comparator N1 drops rapidly to the power supply terminal VEE; the inverting input of the second comparator N2 first receives the power supply terminal VEE voltage, and then rises slowly through capacitor C1 to the voltage divider reference of the fourth resistor R4 and the fifth resistor R5; the voltage at the non-inverting input of the second comparator N2 is always greater than the voltage at the inverting input, so that the gate of the depletion-type VDMOS transistor M1 receives 0V or a positive voltage, keeping the VDMOS transistor M1 on; The bias power supply de-energization process includes: the bias power supply is de-energized, the voltage at the inverting input of the first comparator N1 remains unchanged initially, and the voltage at the non-inverting input drops rapidly, causing the output of the first comparator N1 to drop rapidly to the power supply terminal VEE, and then rise slowly to 0V through capacitor C1 and be transmitted to the inverting input of the second comparator N2; the voltage at the non-inverting input of the second comparator N2 drops rapidly to 0V; the voltage at the non-inverting input of the second comparator N2 is always greater than the voltage at the inverting input, so that the gate of the depletion-type VDMOS transistor M1 receives 0V or a positive voltage, keeping the depletion-type VDMOS transistor M1 on.
8. A timing control method for a depletion-type solid-state power controller according to claim 7, characterized in that, The power supply terminal VDD is a +10V power supply, and the power supply terminal VEE is a -10V power supply. The power supply terminals VDD and VEE are obtained by conversion from the bias power supply 5V.
9. The timing control method for a depletion-type solid-state power controller according to claim 7, characterized in that, The non-inverting input of the first comparator N1 is connected to the voltage divided by the first resistor R1 and the second resistor R2, and the inverting input of the first comparator N1 is connected to the voltage regulated by the third resistor R3 and the Zener diode DZ1.
10. The timing control method for a depletion-type solid-state power controller according to claim 7, characterized in that, The inverting input of the second comparator N2 simultaneously receives the output signal of the first comparator N1 and the voltage divider signal of the fourth resistor R4 and the fifth resistor R5.