Test method based on test machine power board card

Abstract

The invention relates to the technical field of semiconductor testing, and particularly discloses a testing method based on a testing machine power board card, which comprises the following steps: S1, initializing hardware of the power board card, and collaboratively completing basic preparation by each module; s2, flexible configuration and configuration validity verification of a power supply channel are realized through Hash value verification of three terminals; s3, in a normal test stage, completing power supply, real-time parameter acquisition, operation state monitoring and protection, test data record analysis and report generation of the DUT; s4, the PCIe link state is monitored in real time in the testing process, if it is detected that the link is abnormal, a self-recovery type safety isolation mechanism is started, and automatic isolation, abnormal alarm and link self-recovery are completed; and S5, according to a firmware upgrading requirement, executing a remote online upgrading process of the FPGA firmware, and realizing remote downloading and online configuration of the main firmware. According to the invention, the power board card channel expansion flexibility is improved, the development and maintenance cost is greatly reduced, and the test efficiency and accuracy are improved.

Description

A testing method based on the power supply board of a test machine Technical Field

[0001] This invention relates to the field of semiconductor testing technology, and more specifically to a testing method based on a test machine power supply board. Background Technology

[0002] In a test system, the power supply board is the key interface connecting the test system and the device under test (DUT). It is responsible for providing the DUT with a programmable, stable and high-precision power supply, and at the same time undertakes the measurement of key parameters such as voltage, current and power consumption. Its performance directly determines the accuracy and repeatability of the test results.

[0003] The power supply boards in existing test systems generally adopt a two-level control architecture of PC+FPGA. This architecture has many technical defects: First, the PC is only responsible for issuing fixed-format binary control instructions, while the FPGA undertakes a large number of core functions such as instruction parsing, channel management, and power output control. When the complexity of the DUT function and the scale of parallel testing increase, and the number of power channels needs to be adjusted, the instruction format on the PC side needs to be redefined, and a large amount of logic on the FPGA side also needs to be modified and verified, resulting in high development costs, poor code reusability, and limited system scalability. Second, the FPGA performs firmware boot configuration through onboard EEPROM. Firmware upgrades cannot be performed remotely, and upgrade failures can easily lead to system unrecoverability, resulting in low equipment maintainability and reliability. Third, if the communication link between the FPGA and the host computer is abnormal, it will lead to failure in issuing control instructions, interruption of measurement data feedback, and even loss of control of channel output, causing electrical shock to the DUT and poor system fault tolerance. Summary of the Invention

[0004] The purpose of this invention is to provide a testing method based on the power supply board of a test machine, so as to solve the problems of poor scalability, easy damage to the DUT due to link abnormalities, and low firmware upgrade efficiency of the traditional two-level control architecture, and improve the stability, scalability and maintainability of the test system.

[0005] The objective of this invention can be achieved through the following technical solution: a testing method based on a power supply board of a test machine, implemented using a power supply board based on a hierarchical control architecture of PC, TCPU, and FPGA. The power supply board includes a DC-DC power conversion module, a clock module, a control module, a device power supply module, a relay module, a multiplexer module, an analog-to-digital converter module, and a calibration module. The control module consists of a TCPU and an FPGA, communicating via a PCIe channel. The TCPU communicates with the PC via Gigabit Ethernet. The testing method includes the following steps: S1, power supply board hardware initialization, where each module collaboratively completes basic preparations such as power supply, clock provision, and device configuration. The DC-DC power conversion module converts 48V high voltage into multiple sets of low-voltage power supplies within the board. The clock module consists of an FPGA, a TCPU, and an analog-to-digital converter module. The digital-to-digital converter provides a stable clock source, and the calibration module completes linear calibration for each current range; S2, executes the channel-level configuration consistency verification process, and realizes flexible configuration and configuration validity verification of the power channel through hash value verification of the PC, TCPU and FPGA terminals. After successful verification, it enters the normal testing phase; otherwise, it is reconfigured; S3, in the normal testing phase, it completes the power supply of DUT, real-time parameter acquisition, operation status monitoring and protection, test data recording and analysis and report generation; S4, during the test, it monitors the PCIe link status in real time. If a link abnormality is detected, it starts a self-recovering security isolation mechanism to complete automatic isolation, abnormal alarm and link self-recovery; S5, according to the firmware upgrade requirements, it executes the remote online upgrade process of FPGA firmware to realize remote download and online configuration of the main firmware.

[0006] As a further aspect of the present invention: In step S2, the channel-level configuration consistency verification process specifically includes: S21, the PC reads the DUT information, the number of power supply domains and the parallel testing requirements, calculates the power channel resources, generates a channel configuration instruction, and simultaneously uses the SHA-256 hash algorithm to generate a hash value P based on the key information of the configuration instruction, and sends the configuration instruction to the TCPU via Gigabit Ethernet; S22, after receiving the configuration instruction, the TCPU generates a hash value T, updates the internal channel resource mapping table, completes channel allocation and release, and writes the allocation result into the FPGA's parameter register; S23, the FPGA generates a hash value F based on the content of the parameter register, dynamically reconstructs the power channel resources, performs internal self-test and basic calibration, and uploads the hash value F and the self-test result to the TCPU via the PCIe bus; S24, the TCPU uploads the hash values ​​T and F to the PC, and the PC compares the hash values ​​of P, T, and F. If all three are consistent, the configuration is valid, and the process proceeds to step S3; if any hash value is inconsistent, the process returns to step S21 to re-initiate the configuration.

[0007] As a further aspect of the present invention: the normal testing phase described in step S3 specifically includes: S31, the PC starts the test task according to the test plan, and the control module sends a configuration command to the device power supply module to configure the range, output mode and protection threshold of the DPS; S32, the power board continuously collects the voltage and current parameters of each channel, and the analog quantity output by the DPS is selected by the multiplexer and converted into a digital quantity by the analog-to-digital converter module, and transmitted back to the TCPU through the PCIe channel to achieve real-time monitoring; S33, the system continuously judges the operating status of the DUT and the power board. If output exceeding the limit, current transient impact exceeding the standard, channel abnormality, board temperature and pressure abnormality, etc. are detected, the system automatically executes protection strategies such as alarm, limiting, and shutdown; S34, various parameters during the test process are recorded in real time to the database or log file and displayed visually on the host computer interface; S35, after the test is completed, the system performs data filtering and noise reduction, power consumption characteristic analysis, DUT stability and degradation evaluation, and automatically generates test conclusions and test reports.

[0008] As a further aspect of the present invention: the self-recovering security isolation mechanism described in step S4 specifically includes: S41, during the system startup phase, the TCPU sets an initial timeout for the FPGA's internal timer, activates the link watchdog function, and the TCPU sends heartbeat packets to the FPGA at fixed intervals and triggers the FPGA's internal link register; S42, the FPGA continuously checks whether the link register is set. If it is set, the PCIe link is determined to be normal, the timer is reset, and the channel output remains normal; if it is not set and the timer reaches the timeout threshold, the PCIe link is determined to be abnormal, the hardware isolation logic is immediately activated, the output and measurement path of the corresponding power channel are shut down, and the link watchdog abnormal event is triggered; S43, the FPGA outputs a reset signal to the TCPU reset terminal. After the TCPU restarts, it reinitializes the PCIe channel, rebuilds the link communication with the FPGA, and restores heartbeat detection and link monitoring. The entire process requires no manual intervention.

[0009] As a further aspect of the present invention: the initial timeout is set to 10s, and the fixed period for the TCPU to send heartbeat packets is 1s.

[0010] As a further aspect of the present invention: the remote online upgrade process of the FPGA firmware in step S5 specifically includes: S51, the FPGA firmware is split into a fixed startup firmware Bin1 and an updatable main firmware Bin2. Bin1 is pre-fixed in EEPROM for secure startup of the FPGA; S52, Bin2 is remotely downloaded to the memory of the TCPU via Gigabit Ethernet; S53, the TCPU sends a startup signal to FPGA1 via the PCIe protocol. After FPGA1 receives the initialization completion flag returned by FPGA2, the TCPU writes Bin2 into the FIFO of FPGA1 as 32-bit data; S54, FPGA1 splits the 32-bit data into an 8-bit data stream and sends it to FPGA2 to complete the transmission of Bin2; S55, after the transmission is completed, FPGA2 sends a configuration completion signal back to the end register of FPGA1. The TCPU reads the register to confirm successful configuration, FPGA2 enters the working state, and the TCPU accesses the register of FPGA2 via the PCIe protocol to start the device communication interface logic.

[0011] As a further aspect of the present invention: the power supply module of the device consists of multiple DPS, each DPS channel can independently output programmable voltage and current, and can also provide a larger current through parallel connection mode. The DPS supports the working modes of voltage-current measurement (FVMI) and current-voltage measurement (FIMV).

[0012] As a further aspect of the present invention: the relay module includes a DPS channel switch relay and a calibration path relay, which respectively realize the functions of channel on / off isolation and calibration circuit switching; the calibration module supports current ranges including 5uA, 25uA, 250uA, 2.5mA, 25mA, 500mA, and 1.2A.

[0013] As a further aspect of the present invention: the TCPU and the PC send and receive data packets via the TCP / IP protocol, and the FPGA's main firmware upgrade supports parallel upgrades of multiple boards.

[0014] The beneficial effects of this invention are as follows: It adopts a hierarchical control architecture of PC, TCPU, and FPGA, migrating the high-level logic originally concentrated in the FPGA to the TCPU. The FPGA retains only the low-level register group and device communication timing interface, ensuring its logic structure remains stable and unmodified by changes in the number of channels or strategies. This improves code reusability and architectural scalability, and reduces development costs. The proposed channel-level configuration consistency verification protocol achieves dynamic and flexible channel configuration through hash value verification at the PC, TCPU, and FPGA ends, ensuring strong configuration consistency and effectively avoiding DUT damage, abnormal power outages, or distorted test results caused by channel configuration errors. The designed self-recovering security isolation mechanism can quickly achieve hardware isolation and link self-recovery in the event of PCIe link anomalies without manual intervention, ensuring the electrical safety of the DUT and boards and significantly improving system stability and fault tolerance. The implemented FPGA firmware remote online upgrade function breaks the limitations of traditional on-site programming, supports parallel upgrades of multiple boards, improves firmware maintenance and product iteration efficiency, and ensures safe FPGA startup through the separation design of startup firmware and main firmware, avoiding system failures caused by firmware upgrade failures. Attached Figure Description

[0015] The invention will now be further described with reference to the accompanying drawings.

[0016] Figure 1 is a schematic diagram of the overall structure of the power supply board of the present invention; Figure 2 is a schematic diagram of the process of channel expansion and channel configuration consistency verification of the present invention; Figure 3 is a schematic diagram of the process of the self-recovery security isolation mechanism of the present invention; Figure 4 is a schematic diagram of the process of remote online upgrade of the present invention; Figure 5 is a schematic diagram of the process of online configuration of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] In a test system, the power supply board is responsible for providing a programmable, stable, and high-precision power supply to the Device Under Test (DUT), serving as one of the most critical interfaces between the test system and the DUT. Through precise setting and monitoring of voltage and current, the power supply board not only ensures that the DUT operates under the conditions specified in the datasheet but also undertakes the measurement of key parameters such as voltage, current, and power consumption, directly determining the accuracy and repeatability of the test results.

[0019] In existing test equipment systems, power supply boards typically employ a two-tier control architecture consisting of a host computer (PC) and a programmable logic array (FPGA). The PC is only responsible for generating and issuing binary control instructions in a fixed format, while the FPGA handles a large number of core functions such as instruction parsing, channel management, power output control, range switching, and calibration. With the rapid increase in the complexity of DUT functions and the scale of concurrent testing, the demand for independently controllable power domains on power supply boards has significantly increased. In the traditional two-tier architecture, if the number of channels changes, the instruction format on the PC side must be redefined, and a large amount of logic on the FPGA side also needs to be modified and re-verified, resulting in high development costs, poor code reusability, and limited system scalability. Simultaneously, the FPGA requires firmware boot configuration via an onboard electrically erasable programmable read-only memory (EEPROM), making remote firmware upgrades impossible. A failed upgrade could lead to system unrecoverability, severely impacting the maintainability and reliability of the equipment.

[0020] To address the aforementioned limitations, this invention proposes a hierarchical control architecture comprising a PC, a TCPU, and an FPGA. In this architecture, a Transfer Central Processing Unit (TCPU) is added to the power supply board, and high-level logic such as process control, channel resource management, and policy scheduling, originally concentrated on the FPGA, is migrated to the TCPU for execution. The FPGA retains only the underlying register set and timing interfaces related to device communication, thus ensuring the long-term stability of the FPGA's logic structure, which remains unchanged regardless of channel quantity or policy variations, significantly improving code reusability and architectural scalability. Simultaneously, the TCPU communicates with the PC via Gigabit Ethernet, and the TCPU interacts with the FPGA at high speed through on-board PCIe channels, achieving higher interface bandwidth, better signal integrity, and more controllable electromagnetic compatibility performance.

[0021] Based on this layered architecture, the present invention further achieves the following three key innovations: First, it supports flexible expansion of the number of power channels and proposes a channel-level configuration consistency verification protocol.

[0022] The PC (PC) doesn't need to concern itself with the physical channel layout and FPGA internal resource allocation; it only needs to provide an abstract channel configuration description and generate a hash value P for the channel configuration. The TCPU (Tunneling CPU) parses the configuration instructions from the PC and maps resources, generating a corresponding hash value T. The FPGA performs a self-test based on its register contents, generates a hash value F, and sends it back to the TCPU. The TCPU sends the locally generated hash value T and the hash value F generated by the FPGA back to the PC. Only when the hash values ​​of the PC, TCPU, and FPGA are consistent—that is, the channel-level configuration is consistent—is the normal testing process allowed. If inconsistency is detected, a reconfiguration process is automatically triggered to avoid DUT (Device Under Test) damage, abnormal power outages, or distorted test results caused by incorrect channel configuration. This protocol enables dynamic expansion of the number of channels and ensures strong consistency and high reliability in each channel reconfiguration process.

[0023] Second, a self-recovery isolation mechanism (SRI) is introduced to ensure system security and recovery capabilities in the event of PCIe link anomalies.

[0024] In a PC, TCPU, and FPGA architecture, the TCPU and FPGA communicate at high speed via a PCIe channel. A PCIe link disconnection directly results in the inability to issue control commands, transmit measurement data, or even cause uncontrolled channel output, untimely power shutdown, or electrical shock to the DUT. To address this, this invention incorporates a link watchdog and safety isolation mechanism between the TCPU and FPGA. Upon detecting an anomaly, the TCPU immediately shuts down the corresponding channel's output and measurement paths via hardware isolation logic, ensuring the DUT and board are not affected by uncontrolled power. Then, the link watchdog is triggered, and the TCPU automatically performs PCIe link reset, FPGA-side endpoint reinitialization, and register resynchronization to restore normal communication capabilities. Through the SRI mechanism, even if the PCIe channel is unexpectedly disconnected, system safety isolation is guaranteed, preventing DUT damage and allowing recovery without manual intervention, significantly improving the stability and fault tolerance of the test system.

[0025] Third, it enables true remote online upgrades and remote maintenance capabilities.

[0026] This invention splits the FPGA firmware into a fixed boot firmware (Bin1) and an updatable main firmware (Bin2). Bin1 is embedded in EEPROM to ensure secure boot; Bin2 is stored in TCPU and can be remotely downloaded via Gigabit Ethernet and sent to the FPGA via PCIe for online reconfiguration. This structure eliminates the need for on-site operation using JTAG cables; it supports parallel upgrades of multiple boards and enables remote maintenance, greatly improving project management efficiency.

[0027] The overall structure of the power supply board is shown in Figure 1. It consists of a DC power conversion module, a clock module, a control module, a device power supply module, a relay module, a multiplexer module, an analog-to-digital converter module, and a calibration module. These modules work together to provide precise power and measurement for the DUT.

[0028] DC-DC power conversion module: Power supply is like the "blood" of the system, providing the energy foundation for all circuits on the board. Incorrect voltage or excessive ripple can cause device malfunctions, so high-quality power conversion is crucial. This module is responsible for converting the 48V high voltage input from the power cabinet into multiple sets of low-voltage power supplies required by the board, such as 12V, 8V, 5V, 3.3V, 1.8V, 1.2V, and 1.0V, providing a stable and reliable power supply for all functional modules.

[0029] Clock Module: The clock is like the "heart" of the system, determining the timing of logic flips and data sampling. If the clock malfunctions, the entire system will crash, resulting in timing violations and functional errors. The clock module's responsibility is to provide an accurate and stable clock source for critical components such as the FPGA, TCPU, and analog-to-digital converter, ensuring the normal operation of the global logic.

[0030] Control Module: The control module is the "nervous system" of the power supply board, consisting of a process control unit (TCPU) and a device communication interface unit. The two communicate at high speed via the Peripheral Component Interconnect Express (PCIe) bus. The TCPU is responsible for parsing control commands from the PC and generating control flows for power channels, relays, calibration, and measurement paths. The FPGA receives commands from the process control module through the PCIe interface and further distributes them to various devices on the board, implementing functions such as relay on / off control, multiplexer switching, calibration path selection, and parallel control of multiple DPS channels.

[0031] Device Power Supply Module: This module consists of multiple DPS (Digital Power Supply System) channels, each capable of independently outputting programmable voltage and current, or providing larger currents through parallel connection. The process control module pre-configures the DPS's range, output mode, and protection thresholds according to the DUT (Device Under Test) requirements. Furthermore, the DPS supports multiple operating modes, such as applied voltage-current measurement (FVMI) and applied current-voltage measurement (FIMV). Measurement results are output in analog form, converted by a multiplexer and analog-to-digital converter, and then fed back to the device communication interface module.

[0032] Relay Modules: Relay modules are divided into two categories. One category is the DPS channel switch relay, which is used to realize functions such as channel power-on, power-off, and isolation. The other category is the calibration path relay, which is used to switch different calibration circuits to realize the calibration and verification of each current range.

[0033] Multiplexer module: This module is used to select measurement signals from different DPS channels or analog quantities from different voltage / current nodes, and send the selected signals to the analog-to-digital converter to realize multiplexing measurement of multiple analog quantities.

[0034] Analog-to-digital converter module: The analog-to-digital converter module converts the analog voltage or current signal from the multiplexer into a digital quantity and uploads it to the device communication interface module, and then transmits it back to the process control module via the PCIe channel to realize real-time monitoring of power output.

[0035] Calibration Module: Since the DPS has multiple current ranges (5uA, 25uA, 250uA, 2.5mA, 25mA, 500mA, 1.2A), each range requires independent calibration to ensure accuracy. The calibration module provides a standard reference path and calibration load, enabling the system to perform linear calibration on each range, ensuring consistency and high accuracy in power output and measurement.

[0036] The hierarchical control architecture of PC, TCPU and FPGA in this invention specifically includes a channel-level configuration consistency verification protocol, a self-recovering security isolation mechanism and remote online upgrade: (I) Channel-level configuration consistency verification protocol: As shown in Figure 2, the overall system process can be divided into the channel configuration stage (stage A) and the normal test stage (stage B).

[0037] Phase A: Channel Configuration Phase: Step 1: PC-side Channel Planning and Hash Value Generation P: The PC first reads the DUT information, the number of power domains, and the parallel testing (concurrent testing) requirements, and calculates the required power channel resources. Then, it generates channel configuration instructions. Simultaneously, based on the key information in the channel configuration instructions, the PC uses the SHA-256 hash algorithm to generate the corresponding hash value P for subsequent consistency verification. Finally, the channel configuration instructions are sent to the TCPU via Gigabit Ethernet.

[0038] Step Two: TCPU-side Channel Management and Hash Value Generation T: After receiving the channel configuration command, the TCPU calculates the hash value T on its side according to the configuration command. Then, it updates the internal channel resource mapping table to complete the allocation and release of channels. Finally, the allocation results (including channel number, range, initial voltage / current values, etc.) are written to the FPGA's parameter register to achieve fine-grained configuration of devices on the board.

[0039] Step 3: FPGA-side channel reconstruction and hash value generation F: The FPGA calculates the hash value F on the FPGA side based on the parameter register content written by the TCPU. Then, the power channel resources are dynamically reconstructed, including power path configuration and range switching. After channel initialization is completed, the FPGA performs internal self-test and basic calibration, and uploads the hash value F and the self-test result to the TCPU via the PCIe bus.

[0040] Step 4: PC performs channel-level configuration consistency verification: After receiving hash values ​​T and F, these two hash values ​​are compared with the local hash value P. Only when all three hash values ​​are consistent is the configuration considered valid and the system enters phase B. If any hash value is inconsistent, the system returns to step 1 to re-initiate the configuration process to prevent incorrect configuration from damaging the DUT.

[0041] Phase B: Normal Testing Phase: Step 1: Start the testing process: The PC client starts the corresponding test tasks according to the test plan.

[0042] Step 2: Real-time Data Acquisition: The power supply board continuously acquires key parameters such as voltage and current for each channel. The analog signals at the DPS output are converted into digital signals by a multiplexer and analog-to-digital converter, and then returned to the process control module via PCIe for real-time monitoring.

[0043] Step 3: Health status judgment and fault alarm: The system continuously judges the operating status of the DUT and power board, including: (1) whether the output exceeds the limit; (2) whether the current transient impact exceeds the standard; (3) whether the channel is abnormally disconnected or disconnected; (4) whether the board temperature and voltage are within the safe range.

[0044] Once an anomaly is detected, the system will automatically implement protection strategies such as alarms, limiting, and shutdown to ensure the safety of the DUT and the test platform.

[0045] Step 4: Data Recording and Visualization: Various parameters during the test are recorded in real time to the database or log file and presented in the form of curves, numerical panels or statistical tables on the host computer interface, enabling intuitive monitoring and backtracking.

[0046] Step 5: Data Analysis and Report Generation: After the test is completed, the system will automatically perform: (1) data filtering and noise reduction; (2) power consumption characteristic analysis; (3) DUT stability and degradation assessment; (4) test conclusion generation.

[0047] Ultimately, test reports and data analysis documents are automatically generated, providing a basis for subsequent R&D verification or mass production testing.

[0048] By modularizing the testing process of the power board in two phases, A and B, the system can flexibly adjust the number of channels, thereby significantly improving code reusability and enhancing the scalability of the overall architecture.

[0049] (II) Self-Recovery Isolation (SRI): In the PC, TCPU, and FPGA architecture of this invention, the TCPU and FPGA communicate at high speed through the PCIe channel. This channel carries channel configuration commands, power control parameters, and real-time measurement data, and is a critical link to ensure stable system operation. Once the PCIe channel experiences jitter, abnormal disconnection, deadlock, or data blockage, control commands cannot be issued, measurement results cannot be transmitted, and it may even cause uncontrolled channel output and failure to shut down the power supply as expected, thereby posing a serious threat to the electrical safety of the DUT.

[0050] To address this, the present invention introduces a self-recovery security isolation mechanism (SRI) as shown in Figure 3 between the TCPU and the FPGA. Its core is the collaborative operation of a link watchdog and hardware isolation logic to achieve automatic detection, proactive isolation, and rapid self-recovery of PCIe anomalies. The workflow is as follows: Step 1: First, during system startup, the TCPU sets an initial timeout for the timer inside the FPGA (10s in this embodiment) and activates the link watchdog function. Subsequently, the TCPU sends heartbeat packets to the FPGA at fixed intervals (1s in this embodiment) and triggers a link register within the FPGA.

[0051] Step 2: Then, during operation, the FPGA continuously monitors whether the link register is set: 1) If the link register is set, the FPGA can receive the heartbeat packet from the TCPU normally, which is considered that the PCIe link is normal. At this time, the FPGA resets the timer to the initial value and continues to maintain normal channel output; 2) If the link register is not set, the FPGA will continue to monitor whether the timer reaches the timeout threshold; when the timeout occurs, the FPGA determines that the PCIe channel is abnormal and immediately starts the hardware isolation logic: shuts down the output path and measurement path of the corresponding power channel to ensure that the DUT will not be damaged due to power failure, and simultaneously triggers the link watchdog abnormal event.

[0052] Step 3: Finally, after the abnormal event is triggered, the FPGA outputs a reset signal to the TCPU's reset pin, forcing the TCPU to automatically restart. After restarting, the TCPU reinitializes the PCIe channel and re-establishes communication with the FPGA, restoring normal heartbeat detection and link monitoring processes. The entire self-recovery process requires no manual intervention and can continuously and cyclically monitor and repair the PCIe link status, thereby significantly improving the reliability and fault tolerance of the power supply board in actual test environment.

[0053] (III) Remote Online Upgrade: As products are upgraded, firmware programs also need to be updated and iterated. Traditionally, the Bin program is burned onto each board individually on-site via JTAG. This not only requires engineers to be physically present at the machine, but also, in the case of multiple boards and a large number of products, the upgrade process is cumbersome and extremely inefficient, severely hindering product iteration. Furthermore, traditional power supply boards rely on Electrically Erasable Programmable Read-Only Memory (EEPROM) to directly configure the FPGA. If the written firmware has problems, it may cause the system to fail to boot properly, or even pose a potential risk of damage to FPGA-controlled devices, affecting both system maintainability and stability.

[0054] Based on this, as shown in Figure 4, we introduced a layered architecture of PC, TCPU, and FPGA, enabling the system to support remote online upgrades and simultaneously perform batch upgrades on multiple boards, significantly improving product maintenance and iteration efficiency. As shown in Figure 4, the power board only has a stable bootloader Bin1 embedded in its EEPROM at the factory, used for power-on configuration of FPGA1. This bootloader firmware remains unchanged throughout the product lifecycle, therefore it does not need to be rewritten with product upgrades. The actual FPGA2 program Bin2, which requires iteration, is stored in the TCPU's memory (downloaded to the TCPU via gigabit network from an external workbench). After system startup, the TCPU transfers the Bin2 file to FPGA1 via the PCIe protocol, and FPGA1 performs online configuration of FPGA2 through the Xilinx Slave SelectMap mode.

[0055] The specific process is shown in Figure 5: First, the TCPU sends a "start signal" to FPGA2 by controlling the start register in FPGA1. Upon receiving this signal, FPGA2 returns an "initialization complete" flag. Then, the TCPU writes Bin2 as 32-bit data into the First In First Out (FIFO) buffer inside FPGA1. FPGA1 then automatically splits this into an 8-bit data stream and continuously sends it to FPGA2. After all firmware transmission is complete, FPGA2 sends a "configuration complete" signal to the end register of FPGA1. The TCPU reads this register to confirm successful configuration. Once configured, FPGA2 immediately enters the working state. The TCPU can then access the parameter registers and control registers in FPGA2 via the PCIe protocol, start the device communication interface logic, and interact with peripheral devices such as analog-to-digital converters, relays, multiplexers, and DPS.

[0056] Because the TCPU is connected to the external workbench via Gigabit Ethernet, the Bin2 firmware can be remotely downloaded to the power supply board, enabling true online upgrades. Simultaneously, this mechanism supports parallel updates for multiple boards, significantly reducing manual operations, improving system maintenance efficiency, and avoiding the firmware corruption risk associated with traditional EEPROM direct-fit methods. This, in turn, significantly enhances the reliability and scalability of the entire power supply board system.

[0057] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the present invention should still fall within the scope of the present invention.

Claims

1. A testing method based on a test machine power supply board, characterized in that, A power supply board based on a hierarchical control architecture of PC, TCPU, and FPGA is implemented. The power supply board includes a DC-DC power conversion module, a clock module, a control module, a device power supply module, a relay module, a multiplexer module, an analog-to-digital converter module, and a calibration module. The control module consists of a TCPU and an FPGA that communicate via a PCIe channel. The TCPU communicates with the PC via Gigabit Ethernet. The testing method includes the following steps: S1, power supply board hardware initialization. Each module collaboratively completes the basic preparations for power supply, clock provision, and device configuration. The DC-DC power conversion module converts 48V high voltage into multiple sets of low-voltage power supplies within the board. The clock module provides a stable clock source for the FPGA, TCPU, and analog-to-digital converter. The calibration module completes... S2. Perform linear calibration of each current range; S3. Execute the channel-level configuration consistency verification process, and realize the flexible configuration and configuration validity verification of the power channel through hash value verification of PC, TCPU and FPGA. After the verification is successful, it enters the normal test phase. If it fails, it is reconfigured; S4. In the normal test phase, complete the power supply of DUT, real-time parameter acquisition, operation status monitoring and protection, test data recording and analysis and report generation; S5. Monitor the PCIe link status in real time during the test. If the link abnormality is detected, start the self-recovery security isolation mechanism to complete automatic isolation, abnormal alarm and link self-recovery; S6. According to the firmware upgrade requirements, execute the remote online upgrade process of FPGA firmware to realize the remote download and online configuration of the main firmware.

2. The testing method based on the power supply board of a testing machine according to claim 1, characterized in that, In step S2, the channel-level configuration consistency verification process specifically includes: S21, the PC reads the DUT information, the number of power supply domains and the parallel test requirements, calculates the power channel resources, generates a channel configuration command, and simultaneously uses the SHA-256 hash algorithm to generate a hash value P based on the key information of the configuration command, and sends the configuration command to the TCPU via Gigabit Ethernet; S22, after receiving the configuration command, the TCPU generates a hash value T, updates the internal channel resource mapping table, completes channel allocation and release, and writes the allocation result into the FPGA's parameter register; S23, the FPGA generates a hash value F based on the content of the parameter register, dynamically reconstructs the power channel resources, performs internal self-test and basic calibration, and uploads the hash value F and the self-test result to the TCPU via the PCIe bus; S24, the TCPU uploads the hash values ​​T and F to the PC, and the PC compares the hash values ​​of P, T, and F. If all three are consistent, the configuration is valid, and the process proceeds to step S3; if any hash value is inconsistent, the process returns to step S21 to re-initiate the configuration.

3. The testing method based on the power supply board of a testing machine according to claim 1, characterized in that, The normal testing phase described in step S3 specifically includes: S31, the PC starts the test task according to the test plan, and the control module sends configuration instructions to the device power supply module to configure the range, output mode and protection threshold of the DPS; S32, the power board continuously collects the voltage and current parameters of each channel, and the analog quantity output by the DPS is selected by the multiplexer and converted into a digital quantity by the analog-to-digital converter module, and transmitted back to the TCPU through the PCIe channel to achieve real-time monitoring; S33, the system continuously judges the operating status of the DUT and the power board. If output exceeding the limit, current transient surge exceeding the standard, channel abnormality, or board temperature and pressure abnormality is detected, the system automatically executes the protection strategy of alarm, limit, and shutdown; S34, various parameters during the test process are recorded in real time to the database or log file and displayed visually on the host computer interface; S35, after the test is completed, the system performs data filtering and noise reduction, power consumption characteristic analysis, DUT stability and degradation evaluation, and automatically generates test conclusions and test reports.

4. The testing method based on the power supply board of a testing machine according to claim 1, characterized in that, The self-recovering security isolation mechanism described in step S4 specifically includes: S41, during the system startup phase, the TCPU sets an initial timeout for the FPGA's internal timer, activates the link watchdog function, and sends heartbeat packets to the FPGA at fixed intervals, triggering the FPGA's internal link register; S42, the FPGA continuously checks whether the link register is set. If it is set, the PCIe link is determined to be normal, the timer is reset, and the channel output remains normal; if it is not set and the timer reaches the timeout threshold, the PCIe link is determined to be abnormal, the hardware isolation logic is immediately activated, the output and measurement path of the corresponding power channel are shut down, and the link watchdog abnormal event is triggered; S43, the FPGA outputs a reset signal to the TCPU reset terminal. After the TCPU restarts, it reinitializes the PCIe channel, rebuilds the link communication with the FPGA, and restores heartbeat detection and link monitoring. The entire process requires no manual intervention.

5. The testing method based on the power supply board of a testing machine according to claim 4, characterized in that, The initial timeout is set to 10 seconds, and the fixed period for the TCPU to send heartbeat packets is 1 second.

6. The testing method based on the power supply board of a testing machine according to claim 1, characterized in that, The remote online upgrade process of the FPGA firmware described in step S5 specifically includes: S51, the FPGA firmware is split into a fixed startup firmware Bin1 and an updatable main firmware Bin2. Bin1 is pre-fixed in EEPROM for secure FPGA startup; S52, Bin2 is remotely downloaded to the TCPU's memory via Gigabit Ethernet; S53, the TCPU sends a startup signal to FPGA1 via PCIe protocol. After FPGA1 receives the initialization completion flag returned by FPGA2, the TCPU writes Bin2 into FPGA1's FIFO as 32-bit data; S54, FPGA1 splits the 32-bit data into an 8-bit data stream and sends it to FPGA2, completing the transmission of Bin2; S55, after FPGA2 completes the transmission, it sends a configuration completion signal to FPGA1's end register. The TCPU reads the register to confirm successful configuration, FPGA2 enters the working state, and the TCPU accesses FPGA2's registers via PCIe protocol to start the device communication interface logic.

7. The testing method based on the power supply board of a testing machine according to claim 1, characterized in that, The power supply module of the device consists of multiple DPSs. Each DPS channel can independently output programmable voltage and current, and can also provide a larger current through parallel connection. The DPS supports the working modes of voltage-current measurement (FVMI) and current-voltage measurement (FIMV).

8. The testing method based on the power supply board of a testing machine according to claim 1, characterized in that, The relay module includes a DPS channel switch relay and a calibration path relay, which respectively realize the functions of channel on / off isolation and calibration circuit switching; the calibration module supports current ranges including 5uA, 25uA, 250uA, 2.5mA, 25mA, 500mA, and 1.2A.

9. The testing method based on the power supply board of a testing machine according to claim 1, characterized in that, The TCPU and PC communicate via TCP / IP protocol to send and receive data packets, and the FPGA's main firmware upgrade supports parallel upgrades of multiple boards.

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