Programmable periodic pulse signal generation method based on FPGA (Field Programmable Gate Array) and application thereof

Abstract

The invention provides an FPGA-based programmable periodic pulse signal generation method and application thereof, and belongs to the technical field of electronic measurement. In order to solve the problems that the large dynamic range and the high resolution are difficult to consider at the same time and hardware resources are consumed synchronously by multiple channels in the prior art, according to the method, coarse delay is achieved through FPGA system clock counting, and next pulse parameters are calculated through accumulation of remaining decimal parts; picosecond-level fine delay is realized by constructing a three-level cascade architecture consisting of a lookup table, a coarse carry chain and a fine carry chain; and XOR synthesis waveforms after rising edges and falling edges are independently generated respectively. In addition, the inter-channel transmission delay difference is compensated by correcting the initial calculation parameters. According to the multi-channel pulse signal generation circuit, high-precision, low-jitter and strictly-aligned-phase multi-channel pulse signals can be generated only by utilizing pure logic resources of the FPGA.

Description

Technical Field

[0001] This invention belongs to the field of electronic measuring instruments and digital logic circuit technology, specifically relating to a programmable periodic pulse signal generation method based on FPGA and its application, which is particularly suitable for test systems or control systems that require multi-channel strict synchronization and picosecond-level resolution. Background Technology

[0002] Periodic pulse signals are the "heartbeat" commands in fields such as digital integrated circuits, high-speed communication, radar testing, and power electronics. Their frequency stability, duty cycle accuracy, and phase synchronization between multiple channels directly determine the system's performance.

[0003] The existing technical solutions for generating periodic pulse signals mainly include the following:

[0004] 1. Application-Specific Integrated Circuit (ASIC) or Dedicated Clock Chip Solution: Although it has high accuracy and stability, its functions are fixed and cannot be changed once it is fabricated. It also cannot flexibly adapt to non-standard timing requirements, has a long development cycle, high cost, and lacks versatility.

[0005] 2. GPIO toggle solution based on CPU / MCU: Due to the limitations of operating system scheduling and instruction execution pipeline, its timing control accuracy is usually only at the microsecond level, and there is huge time jitter, which cannot meet the requirements of high-performance testing.

[0006] 3. FPGA-based hard-core PLL / MMCM solution: This solution utilizes the integrated phase-locked loop resources within the FPGA. While offering good stability, the limited number of PLLs makes it difficult to support high-density, multi-channel applications. Furthermore, the PLL's dynamic reconfiguration speed is slow, and the phase adjustment granularity is limited by the VCO frequency, making it difficult to achieve arbitrary picosecond-level fine-tuning.

[0007] 4. Existing Solutions Based on FPGA Delay Lines: While some existing technologies (such as the prior art CN109656123A) propose a "coarse counting + fine delay" approach, they typically use a single IDELAY / ODELAY primitive or a simple carry chain. The limitations of existing technologies are: a single delay device cannot simultaneously achieve both "large dynamic range" and "high resolution." For example, while using a carry chain alone provides high accuracy, the delay range is short and cannot cover the entire clock cycle; while using logic delays alone results in excessively large steps and insufficient accuracy. Furthermore, in multi-channel synchronous applications, existing technologies usually require adding an extra hardware delay line to each channel to compensate for phase deviations (skew) caused by PCB traces, resulting in a significant waste of valuable FPGA logic resources.

[0008] Therefore, there is an urgent need for a programmable periodic pulse signal generation method based on FPGA and its application to solve the problems existing in the current technology. Summary of the Invention

[0009] This application provides a method for generating programmable periodic pulse signals based on FPGA and its application. It addresses the problems of current technology, such as the difficulty in achieving a balance between large dynamic range (covering the entire clock cycle) and picosecond-level high resolution without relying on scarce hard core resources (such as PLLs), and the need to consume additional hardware resources for phase compensation when synchronizing multiple channels.

[0010] The core technology of this invention lies in the adoption of a three-level cascaded architecture of "LUT coarse delay + coarse CARRY8 medium delay + fine CARRY8 fine delay" to achieve full-cycle coverage with picosecond precision, and the use of the initial phase parameter (M1 / S1) pre-bias algorithm to achieve strict phase alignment of multiple channels with zero hardware overhead.

[0011] In a first aspect, this application provides a method for generating a programmable periodic pulse signal based on an FPGA, the method comprising the following steps: Parameter configuration steps: Obtain the period parameter and duty cycle parameter of the periodic pulse signal to be generated; Period generation steps: Counting is performed under the drive of the FPGA system clock, and the number of system clock cycles required for the next pulse trigger is calculated in real time as well as the fractional part of the period that is less than one system clock cycle. Among them, the remaining fractional part of the current pulse that is not divisible by the system clock is accumulated into the calculation of the next pulse to maintain the continuity of the phase. Edge generation steps: When the count reaches an integer multiple of the system operating clock cycles, a trigger signal is generated, and rising edge generation and falling edge generation are performed based on the trigger signal respectively; The rising edge generation process includes: using the logic delay resources inside the FPGA to delay the first level signal by the time length corresponding to the fractional period and then flipping it; The falling edge generation process includes: independently calculating the falling edge delay time based on the period parameter, duty cycle parameter, and remaining fractional part, and using the logic delay resources inside the FPGA to flip the second level signal after delaying the falling edge delay time; Waveform integration steps: Perform a logical XOR operation on the first and second level signals after inversion to synthesize the final periodic pulse signal.

[0012] Furthermore, the use of the logic delay resources inside the FPGA is specifically implemented using a multi-level cascaded delay chain architecture, which includes a first-level delay unit, a second-level delay unit, and a third-level delay unit connected in series. The first-level delay unit is constructed using the lookup table resources inside the FPGA to achieve coarse delays with nanosecond-level steps; the second-level delay unit is constructed using the carry chain resources inside the FPGA to achieve medium delays with hundreds of picosecond-level steps; and the third-level delay unit is constructed using the carry chain resources inside the FPGA to achieve fine delays with tens of picosecond-level steps.

[0013] Furthermore, the delay step of the first-level delay unit is greater than the delay step of the second-level delay unit, and the delay step of the second-level delay unit is greater than the delay step of the third-level delay unit; Programmable periodic pulse signal generation methods also include: The fractional period portion is quantized and mapped to a first control word, a second control word, and a third control word, which are used to control the lookup table level accessed by the first-level delay unit, the carry chain tap position selected by the second-level delay unit, and the carry logic path of the third-level delay unit, respectively.

[0014] Furthermore, in the period generation step, the specific logic for calculating the integer multiple of the system operating clock cycles M2 and the fractional period part S2 required for the next pulse signal is as follows: Add the remaining fractional part S1 generated by this pulse to the period parameter Tx, and divide by the FPGA system operating clock period Ts; The integer part of the quotient is M2, and the remainder is S2.

[0015] Furthermore, in the falling edge generation process, the specific logic for independently calculating the falling edge delay time T2 is as follows: Calculate according to the formula T2=D0×Tx+S1; Where D0 is the duty cycle parameter, Tx is the period parameter, and S1 is the remaining fractional part generated by this pulse; The calculated T2 is decomposed into an integer part M3 that can be divided by the FPGA system's operating clock cycle and a minor delay part S3 that cannot be divided. The minor delay part S3 is used to control the logic delay resources in the falling edge generation process.

[0016] Furthermore, the method for generating programmable periodic pulse signals, applied to pulse generation systems containing multiple channels, also includes a multi-channel phase calibration step: Determine the inherent hardware transmission path delay difference of each channel relative to the reference channel; When each channel generates the first pulse signal, the initial integer multiple of the system operating clock cycles and the initial fractional period of each channel in the cycle generation step are corrected according to the inherent hardware transmission path delay difference. By adjusting the initial calculation parameters for the first pulse generated by each channel, the inherent hardware transmission path delay difference is compensated, thus achieving phase alignment of multi-channel pulse signals.

[0017] Furthermore, the correction of the initial integer multiple of the system operating clock cycles and the initial fractional period specifically includes: If a channel has a lag delay difference relative to the reference channel, then subtract the lag delay difference from the initial fractional period of that channel; When the result of the subtraction operation is negative, borrow from the initial integer multiple of the system clock cycle number, convert the time difference into the system clock cycle number for subtraction, and use the remainder after conversion as the corrected initial fractional period part.

[0018] Furthermore, the waveform integration step also includes boundary protection processing: Real-time monitoring of duty cycle parameters; When the duty cycle parameter is 0%, a low-level signal is forced to be output, and the logical XOR operation is not performed. When the duty cycle parameter is 100%, a high-level signal is forced to be output, and the logical XOR operation is not performed; The logical XOR operation is performed only when the duty cycle parameter is in the open range of 0% to 100%.

[0019] Secondly, this application provides a programmable periodic pulse signal generation device based on FPGA, comprising: The parameter control module is used to receive and store the period parameters and duty cycle parameters of the periodic pulse signal; The period generation module is used to count based on the FPGA system's operating clock, calculate the next pulse trigger time by accumulating the remainder, generate a trigger enable signal, and output the currently accumulated fractional period. The dual-edge generation module includes a rising edge generation unit and a falling edge generation unit that operate in parallel. Each unit contains a multi-level variable delay chain composed of lookup table resources and carry chain resources, which is used to generate delayed rising edges and falling edges according to the trigger enable signal and the fractional period part, respectively. The waveform integration module is used to perform an XOR logic operation on the outputs of the rising edge generation unit and the falling edge generation unit to output the target pulse signal.

[0020] Thirdly, this application provides a readable storage medium storing a computer program, the computer program including program code for controlling a process to execute the process, the process including the programmable periodic pulse signal generation method described above.

[0021] The main contributions and innovations of this invention are as follows: 1. Achieving a perfect balance between "high resolution" and "large dynamic range": By constructing a three-level delay chain architecture of "lookup table (LUT, ~1.25ns step)" + "coarse carry chain (CARRY8, ~350ps step)" + "fine carry chain (CARRY8, ~50ps step)", this invention successfully achieves ultra-high adjustment accuracy at the 50ps level while covering system clock cycles of more than 5ns. It solves the technical challenge that a single delay device cannot cross the clock cycle dead zone.

[0022] 2. Achieved multi-channel phase calibration with zero hardware overhead: Unlike existing technologies that require stacking additional hardware delay lines to align channel phases, this invention creatively modifies the initial parameters (M1 and S1) at the algorithm level to perform "parameter pre-biasing" at the source of pulse generation. This method does not consume any additional FPGA logic resources or routing resources to compensate for phase skew caused by differences in PCB traces or I / O transmissions, greatly reducing system complexity.

[0023] 3. High scalability and flexibility: Since this invention is completely independent of the scarce hard core resources (PLL / MMCM) inside the FPGA and only uses the most basic logic units (LUT and CARRY), it can be easily replicated and expanded to dozens or even hundreds of channels in a single FPGA, and the frequency, duty cycle and phase of each channel can be configured independently and dynamically.

[0024] 4. Extremely low jitter characteristics: Implemented through all-digital logic, it avoids the power supply noise coupling problem in analog PLL circuits. Combined with fine edge control logic, it controls the jitter of pulse signals to an extremely low level, making it suitable for high-precision test and measurement fields.

[0025] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent. Attached Figure Description

[0026] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a structural diagram of an FPGA-based programmable periodic pulse signal generation system (device) according to an embodiment of this application; Figure 2 This is a flowchart of a programmable periodic pulse signal generation method based on FPGA according to an embodiment of this application; Figure 3 This is a waveform diagram according to an embodiment of this application. Detailed Implementation

[0027] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with one or more embodiments of this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of one or more embodiments of this specification as detailed in the appended claims.

[0028] It should be noted that the steps of the corresponding methods are not necessarily performed in the order shown and described in this specification in other embodiments. In some other embodiments, the methods may include more or fewer steps than described in this specification. Furthermore, a single step described in this specification may be broken down into multiple steps in other embodiments; and multiple steps described in this specification may be combined into a single step in other embodiments.

[0029] Example 1: Single-channel high-precision pulse signal generation system (device) like Figure 1 As shown, this embodiment provides a programmable periodic pulse signal generation system (device) based on FPGA. This device is implemented entirely using the pure logic resources within the FPGA and does not rely on the hard-core phase-locked loop (PLL) within the FPGA. The system mainly consists of a parameter control module, a period generation module, two dual edge generation modules (including edge generation module 1 and edge generation module 2), and a waveform integration module. The specific method for generating the programmable periodic pulse signal is as follows: Figure 2 As shown, the specific steps are as follows: 1. Parameter control module and quantization logic The parameter control module communicates with the host computer via a UART or PCIe interface to receive user-defined pulse period (Tx) and duty cycle (D0) parameters. To adapt to the discrete-time system of the FPGA, this module needs to convert the physical time parameters into a count value based on the FPGA system operating clock (Ts) and a control word (a string of binary code) based on the minimum delay step.

[0030] In this embodiment, the FPGA system operating clock frequency is set to 200MHz, i.e., the period Ts = 5ns.

[0031] The minimum delay resolution of the system is determined by the fine delay unit, denoted as . .

[0032] The parameter control module quantizes the received floating-point periodic parameters into: .

[0033] For example, the minimum resolution of the period is set to 5 / 2. 28 When the pulse period needs to be set to 21ns and the duty cycle to 25%, the set period value parameter is 21 / (5 / 2). 28 =1127428915, the set duty cycle parameter is 21×0.25 / (5 / 2) 28 =281857228. For ease of description, in the following embodiments, the FPGA's system operating clock period, minimum period resolution, pulse period, and duty cycle all use the above values.

[0034] 2. Period generation module and phase accumulation mechanism The cycle generation module is the timing core of the system, operating in the FPGA system clock domain. Internally, this module maintains a cycle counter and a remaining fraction register.

[0035] Its core logic lies in resolving the accumulated error of non-integer multiples of clock cycles. The specific working steps are as follows: (1) Initialization: When the first pulse is generated, set the initial integer multiple of the cycle number M1=1 and the initial fractional part S1=0.

[0036] (2) Counting trigger: The counter starts counting from 1. When the count value reaches the currently set integer multiple of the number of cycles M (M1 for the first pulse), an enable pulse of one system clock cycle is output.

[0037] (3) Next Parameter Calculation: While outputting the enable pulse, the module calculates the parameters required for the next pulse trigger in parallel. The calculation formula is as follows:

[0038]

[0039] in, This represents the currently accumulated decimal part that is not divisible. This represents the decimal part for the next iteration.

[0040] Technical effect: By The accumulation is carried over to the next calculation, which actually realizes a phase accumulation function similar to direct digital frequency synthesis (DDS), ensuring that the average frequency of the pulse sequence is strictly equal to the set value during long-term operation, and that the phase is continuous without drift.

[0041] 3. Dual-edge generation module and three-level delay architecture (core hardware implementation) This embodiment employs a strategy of "independently generating two-sided edges".

[0042] Edge generation module 1: Used to generate rising edges (generate the rising edge transition of a pulse signal). After receiving an enable pulse, it is delayed for a certain period of time. Then, the output level is toggled.

[0043] Edge generation module 2: Used to generate falling edges (generating the falling edge transition of a pulse signal). Its delay time... It needs to be calculated independently based on the duty cycle; the formula is: .

[0044] Calculated It is also broken down into an integer clock cycle part (for coarse counting waits) and a fractional part (for fine delays).

[0045] In order to achieve a resolution of 50ps while covering a dynamic range of 5ns (one system clock cycle), the above edge generation modules all adopt a "three-level cascaded delay chain architecture".

[0046] This delay chain consists of a first-stage delay unit, a second-stage delay unit, and a third-stage delay unit connected in series: Level 1 (Coarse Delay): Lookup Table (LUT) Delay Chain A LUT cell (such as the LUT6 in the Xilinx Ultrascale series) in the FPGA is used as a logic buffer. The number of LUT stages in the input signal path is controlled by a multiplexer. In this embodiment, the physical delay of a single LUT stage is approximately 1.25ns. This stage is responsible for handling coarse adjustments in the range of 1.25ns to 5ns.

[0047] Level 2 (Medium Delay): Coarse Carry Chain (Coarse Carry 8) The CARRY8 carry chain primitive in the FPGA is utilized. CARRY8 consists of 8 carry multiplexers (MUXCY) and 8 XOR gates. Signals are input to the carry input of CARRY8, and different delay lengths are achieved by selecting different CO (CarryOut) output ports. In this embodiment, CARRY8 is configured such that the delay step of each tap is approximately 350ps. This stage is responsible for filling the gaps between LUT steps, with a dynamic range covering approximately 1400ps.

[0048] Level 3 (Fine Delay): Fine Carry Chain (Fine CARRY8) While also utilizing CARRY8 resources, this embodiment achieves an ultra-fine delay step of approximately 50 ps and a dynamic range of approximately 350 ps by controlling the combined logic path of the S-port (selection port) and DI-port (data port) within the carry chain, or by leveraging specific wiring delay differences during CARRY8 cascading.

[0049] Example of the work process: Assume the fractional part of the current delay is S = 3.95 ns.

[0050] The control logic decomposes it into: .

[0051] The logic circuit controls the serial input path of the three LUT units. The coarse CARRY8 selects the 0th tap, and the fine CARRY8 selects the 4th level delay path, thereby synthesizing the target delay.

[0052] 4. Waveform Integration Module This module receives the rising edge signal (denoted as Sig_A) output by edge generation module 1 and the falling edge signal (denoted as Sig_B) output by edge generation module 2.

[0053] The module internally contains an XOR gate. Output signal. .

[0054] Special boundary protection: The module also includes duty cycle monitoring logic. When the duty cycle is set to 0%, it forces the output logic 0; when the duty cycle is 100%, it forces the output logic 1, bypassing the XOR logic to prevent glitches caused by extremely narrow pulses.

[0055] Example 2: Multi-channel phase calibration method like Figure 2 As shown in Example 1, this example further describes how to eliminate the hardware transmission delay difference (T) between channels in a multi-channel application scenario. skew The method.

[0056] In actual hardware circuits, the PCB trace lengths from the FPGA pins to the output connectors of different channels (Channel A, Channel B, etc.) are often different, or the I / O delays of different banks within the FPGA are different, which results in a phase difference in the physical output even if they are logically triggered synchronously.

[0057] This embodiment employs parameter pre-biasing technology, eliminating the need for additional hardware delay line resources. The specific steps are as follows: 1. Measurement Deviation: After the system is powered on, the inherent delay difference T between the measurement channel X and the reference channel (such as channel 0) is measured, using the rising edge as the reference. skew Assume that the time lag between channel 1 and channel 0 is measured to be 1.5 ns.

[0058] 2. Parameter Correction: During the initialization phase of the periodic generation module in Channel 1, instead of using the default M1=1 and S1=0, these two parameters are manually adjusted to "advance" the logic generation time of Channel 1 by 1.5ns, thereby offsetting the lag in the physical path. The correction formula is:

[0059] If the calculation result Then borrow from the integer part:

[0060]

[0061] Application example: Suppose Ts = 5ns, and channel 1 lags by 1.5ns. Initial parameters: M1 = 1, S1 = 0.

[0062] Calculation correction:

[0063] Since the value is less than 0, a borrow is required:

[0064] (Note: If the actual counter does not support 0, more cycles can be borrowed forward or combined with global trigger delay processing. This is only an algorithm illustration. In engineering, the default M1 is usually made large enough, for example, M1=10.)

[0065] Therefore, the initial state of channel 1 is configured as M1=0 (i.e., immediate trigger), and the initial fractional delay is set to 3.5ns. Compared to the original state, the logic output of channel 1 is brought forward by 1.5ns, which exactly cancels out the physical lag and achieves strict alignment with the physical edge of channel 0.

[0066] Example 3 To more intuitively illustrate the phase accumulation mechanism of the period generation module and the cooperative relationship of the edge generation module in this invention, Figure 3 A specific example of waveform generation timing is shown.

[0067] In this example, the system parameters are set as follows: The FPGA system's clock cycle (Ts) is 5 ns. To facilitate digital logic calculations, the system internally uses fixed-point time representation, with a minimum cycle resolution of 5 / 2. 28 ns. Therefore, in the normalized numerical representation, Ts=2 28 (i.e., 268435456).

[0068] The period (Tx) of the pulse signal to be generated is 21 ns in physical time. Since 21 ns is not an integer multiple of 5 ns (21 / 5 = 4.2), there is a fractional margin of 0.2 clock cycles. Its normalized value is Tx = 21 / (5 / 2) 28 =1127428915.

[0069] Duty cycle to be generated (D0): 25%. The corresponding normalized baseline value for the falling edge delay is 281857228.

[0070] like Figure 3 As shown, the generation process and parameter calculation of the first three consecutive pulses are as follows: 1. First pulse (initial state): Status: The system has just started up and there is no historical phase accumulation.

[0071] Periodic parameters: Initial integer count target M1=1, initial fractional part S1=0.

[0072] Rising edge: The edge generation module 1 flips after a delay of S1=0.

[0073] Falling edge: Calculate the delay T2 = D0 × Tx + S1 = 281857228. Decompose it into integer clock cycles M3 = 1(281857228 / 2) 28 The integer part of the time and the fractional delay S3 = 13421772. After counting one clock cycle, the edge generation module 2 flips after a fine delay of S3 (approximately 0.25ns).

[0074] Pre-calculation for the next iteration: Calculate the integer span of the next pulse: M2=(S1+Tx) / Ts=4 (i.e. 4 system clock cycles).

[0075] Calculate the remainder passed to the next pulse: S2=(S1+Tx)%Ts=53687091 (corresponding to approximately 1 ns of physical time, or 0.2 clock cycles).

[0076] 2. Second pulse (phase compensation): Status: Inherited the remainder S1 = 53687091 from the previous calculation. This means the ideal pulse start point lags behind the current clock edge by 1 ns. At this time, M1 = 4.

[0077] Rising edge: Edge generation module 1 uses a three-stage delay chain to precisely delay the output signal by S1 (approximately 1ns) before flipping it.

[0078] Falling edge: Since the starting point is delayed, the falling edge must also be delayed accordingly. Calculate T2 = 281857228 + 53687091 = 335544319. Decompose to obtain M3 = 1, S3 = 67108863.

[0079] Pre-calculation for the next iteration: M2=(53687091+1127428915) / 2 28 =4.

[0080] S2=(53687091+1127428915)%2 28 =107374182 (corresponding to approximately 2 ns of physical time, or 0.4 clock cycles).

[0081] 3. The third pulse (cumulative duration): State: Inherited remainder S1 = 107374182. Phase lag accumulates further. At this point, M1 = 4.

[0082] Rising edge: Edge generation module 1 delay S1 (approximately 2ns).

[0083] Falling edge: T2 = 281857228 + 107374182 = 389231410. Decomposition yields M3 = 1, S3 = 120795954.

[0084] Pre-calculation for the next iteration: The calculated remainder S2 will continue to increase (161,061,273, approximately 3 ns). Technical effect explanation: As can be seen from the above process, with the generation of the pulse sequence, the fractional part S (i.e., S1, S2, ...) continuously changes (0→0.2Ts→0.4Ts→0.6Ts...). When the fractional part accumulates for more than one system clock cycle (Ts), the integer part M2 in the calculation formula will automatically increase by 1 (from 4 to 5), while the fractional part S automatically wraps around. This mechanism ensures that during long-cycle operation, the generated pulse frequency is strictly locked at 21 ns, preventing "frequency drift" due to the FPGA clock being 5 ns. Furthermore, the rising and falling edges of each pulse are precisely aligned to the theoretical time using a fine delay unit (LUT+CARRY8), minimizing jitter caused by quantization errors.

[0085] Example 4 This embodiment also provides a readable storage medium storing a computer program, the computer program including program code for controlling a process to execute the process, the process including the FPGA-based programmable periodic pulse signal generation method according to Embodiment 1.

[0086] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementations, and will not be repeated here.

[0087] Generally, various embodiments can be implemented in hardware or dedicated circuitry, software, logic, or any combination thereof. Some aspects of the invention can be implemented in hardware, while others can be implemented by firmware or software executed by a controller, microprocessor, or other computing device, but the invention is not limited thereto. Although various aspects of the invention may be shown and described as block diagrams, flowcharts, or using some other graphical representation, it should be understood that, by way of non-limiting example, these blocks, apparatuses, systems, techniques, or methods described herein can be implemented in hardware, software, firmware, dedicated circuitry or logic, general-purpose hardware or controllers or other computing devices, or some combination thereof.

[0088] Embodiments of the present invention can be implemented by computer software, which may be executable by a data processor of a mobile device, such as a processor entity, or by hardware, or by a combination of software and hardware. Computer software or programs (also referred to as program products) including software routines, applets, and / or macros can be stored in any device-readable data storage medium, and they include program instructions for performing specific tasks. The computer program product may include one or more computer-executable components configured to perform the embodiments when the program is run. The one or more computer-executable components may be at least one piece of software code or a portion thereof. Additionally, it should be noted in this respect that, as Figure 2 Any box in the logical flow can represent a program step, or interconnected logic circuits, boxes and functions, or a combination of program steps and logic circuits, boxes and functions. Software can be stored on physical media such as memory chips or blocks of storage implemented within a processor, magnetic media such as hard disks or floppy disks, and optical media such as DVDs and their data variants, CDs, etc. The physical medium is a non-transient medium.

[0089] Those skilled in the art should understand that the technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments have been described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for generating programmable periodic pulse signals based on FPGA, characterized in that, Includes the following steps: Parameter configuration steps: Obtain the period parameter and duty cycle parameter of the periodic pulse signal to be generated; Period generation steps: Counting is performed under the drive of the FPGA system clock, and the number of system clock cycles required for the next pulse trigger and the fractional period portion that is less than one system clock cycle are calculated in real time; wherein, the calculation adds the remaining fractional part of the current pulse that is not divisible by the system clock to the calculation of the next pulse to maintain the continuity of the phase; Edge generation step: When the count reaches an integer multiple of the system operating clock cycles, a trigger signal is generated, and rising edge generation processing and falling edge generation processing are performed based on the trigger signal respectively; The rising edge generation process includes: using the logic delay resources inside the FPGA to delay the first level signal by the time length corresponding to the fractional period before flipping it; The falling edge generation process includes: independently calculating the falling edge delay time based on the period parameter, duty cycle parameter, and the remaining fractional part, and using the logic delay resources inside the FPGA to toggle the second level signal after delaying the falling edge delay time; Waveform integration step: Perform a logical XOR operation on the first level signal and the second level signal after inversion to synthesize the final periodic pulse signal.

2. The programmable periodic pulse signal generation method as described in claim 1, characterized in that, The use of the internal logic delay resources of the FPGA is specifically implemented by adopting a multi-level cascaded delay chain architecture, which includes a first-level delay unit, a second-level delay unit, and a third-level delay unit connected in series. The first-level delay unit is constructed using the lookup table resources inside the FPGA to achieve coarse delays with nanosecond-level steps; the second-level delay unit is constructed using the carry chain resources inside the FPGA to achieve medium delays with hundreds of picosecond-level steps; and the third-level delay unit is constructed using the carry chain resources inside the FPGA to achieve fine delays with tens of picosecond-level steps.

3. The programmable periodic pulse signal generation method as described in claim 2, characterized in that, The delay step of the first-level delay unit is greater than the delay step of the second-level delay unit, and the delay step of the second-level delay unit is greater than the delay step of the third-level delay unit; The programmable periodic pulse signal generation method further includes: The fractional period portion is quantized and mapped into a first control word, a second control word, and a third control word, which are used to control the lookup table level accessed by the first-level delay unit, the carry chain tap position selected by the second-level delay unit, and the carry logic path of the third-level delay unit, respectively.

4. The programmable periodic pulse signal generation method as described in claim 1, characterized in that, In the period generation step, the specific logic for calculating the integer multiple of the system operating clock cycles M2 and the fractional period part S2 required for the next pulse signal is as follows: Add the remaining fractional part S1 generated by this pulse to the period parameter Tx, and divide by the FPGA system operating clock period Ts; The integer part of the quotient is M2, and the remainder is S2.

5. The programmable periodic pulse signal generation method as described in claim 1, characterized in that, In the falling edge generation process, the specific logic for independently calculating the falling edge delay time T2 is as follows: Calculate according to the formula T2=D0×Tx+S1; Where D0 is the duty cycle parameter, Tx is the period parameter, and S1 is the remaining fractional part generated by this pulse; The calculated T2 is decomposed into an integer part M3 that can be divided by the FPGA system's operating clock cycle and a minor delay part S3 that cannot be divided. The minor delay part S3 is used to control the logic delay resources in the falling edge generation process.

6. The programmable periodic pulse signal generation method as described in claim 1, characterized in that, The method is applied to a pulse generation system containing multiple channels, and the programmable periodic pulse signal generation method further includes a multi-channel phase calibration step: Determine the inherent hardware transmission path delay difference of each channel relative to the reference channel; When each channel generates the first pulse signal, the initial integer multiple of the system operating clock cycles and the initial fractional period portion of each channel in the cycle generation step are corrected according to the inherent hardware transmission path delay difference. By adjusting the initial calculation parameters for generating the first pulse in each channel, the inherent hardware transmission path delay difference is compensated, thereby achieving phase alignment of multi-channel pulse signals.

7. The programmable periodic pulse signal generation method as described in claim 6, characterized in that, The correction of the initial integer multiple of the system operating clock cycles and the initial fractional period specifically includes: If a channel has a lag delay difference relative to the reference channel, then the lag delay difference is subtracted from the initial fractional period of the channel; When the result of the subtraction operation is negative, borrow from the initial integer multiple of the system clock cycle number, convert the time difference into the system clock cycle number for subtraction, and use the remainder after conversion as the corrected initial fractional period part.

8. The programmable periodic pulse signal generation method as described in claim 1, characterized in that, The waveform integration process also includes boundary protection: Real-time monitoring of the duty cycle parameter; When the duty cycle parameter is 0%, a low-level signal is forced to be output, and the logical XOR operation is not performed; When the duty cycle parameter is 100%, a high-level signal is forced out, and the logical XOR operation is not performed; The logical XOR operation is performed only when the duty cycle parameter is in the open range of 0% to 100%.

9. A programmable periodic pulse signal generation device based on FPGA, characterized in that, include: The parameter control module is used to receive and store the period parameters and duty cycle parameters of the periodic pulse signal; The period generation module is used to count based on the FPGA system's operating clock, calculate the next pulse trigger time by accumulating the remainder, generate a trigger enable signal, and output the currently accumulated fractional period. The dual-edge generation module includes a rising edge generation unit and a falling edge generation unit that operate in parallel. Each unit contains a multi-level variable delay chain composed of lookup table resources and carry chain resources, which are used to generate delayed rising edges and falling edges according to the trigger enable signal and the fractional period portion, respectively. The waveform integration module is used to perform an XOR logic operation on the outputs of the rising edge generation unit and the falling edge generation unit to output the target pulse signal.

10. A readable storage medium, characterized in that, The readable storage medium stores a computer program, the computer program including program code for controlling a process to execute the process, the process including the programmable periodic pulse signal generation method according to any one of claims 1 to 8.

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