Core particle interconnection physical layer interface circuit integrated with self-test function and chip test method
By integrating a self-test function into the chip interconnect physical layer interface circuit, the test steps are automatically executed by the MCU, solving the problems of cumbersome operation and high cost in traditional testing, and realizing efficient and reliable chip interconnect testing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING XINLI TECH INNOVATION CENT CO LTD
- Filing Date
- 2026-02-04
- Publication Date
- 2026-05-01
AI Technical Summary
In traditional chip interconnect testing environments, the test instrument and HiPi Phy interact frequently, which is cumbersome to operate. This results in complex sequencing programs on the host computer software, high testing costs, a high probability of testing errors, difficulty in locating faults, and excessively long testing times.
The integrated self-test function of the chip interconnect physical layer interface circuit includes physical layer circuit, test control circuit and storage circuit. It automatically executes predefined test steps through microcontroller unit (MCU), reduces the interaction between the test machine and HiPi phy, and forms a closed loop system.
It simplifies testing operations, reduces testing costs, improves testing accuracy and reliability, shortens testing time, reduces the probability of errors, and saves testing costs.
Smart Images
Figure CN121960358A_ABST
Abstract
Description
Chip-to-interconnect physical layer interface circuit with integrated self-test function and chip testing method Technical Field
[0001] This invention belongs to the field of chip testing technology, and particularly relates to a chip interconnect physical layer interface circuit with integrated self-test function and a chip testing method. Background Technology
[0002] Traditional chip interconnect testing environments present technical challenges: frequent interaction between the test instrument and HiPi Phy leads to cumbersome operation, resulting in complex sequencing programs on the host computer software, high testing costs, a high probability of errors during testing, difficulty in locating whether the fault lies with the test instrument or HiPi Phy, and excessively long testing times. Summary of the Invention
[0003] The purpose of this invention is to solve the problems in the prior art, such as the increased complexity of the host computer software sequencing program due to cumbersome operation, the greatly increased testing cost due to the need for customized test cards and test programs, the increased probability of test errors, and the difficulty in locating whether the fault is in the test machine or HiPi Phy.
[0004] To this end, the present invention provides a chip interconnect physical layer interface circuit with integrated self-test function, comprising: a physical layer circuit for realizing data transmission and reception between chips; a test control circuit connected to the physical layer circuit; and a storage circuit for storing test programs and configuration parameters; wherein the test control circuit is configured to: automatically execute the test program stored in the storage circuit in response to a single test start command initiated by an external test device, control the physical layer circuit to complete a series of predefined test steps, collect test status, and output the summarized test result status to the external test device.
[0005] Furthermore, preferably, in the chip interconnect physical layer interface circuit with integrated self-test function of the present invention, the test control circuit is a microcontroller unit and the storage circuit is a read-only memory.
[0006] Furthermore, preferably, in the chip interconnect physical layer interface circuit with integrated self-test function of the present invention, the predefined test steps include at least two of the following: power-on detection, phase-locked loop configuration and locking, link training, and loopback testing.
[0007] Furthermore, preferably, in the chip interconnect physical layer interface circuit with integrated self-test function of the present invention, if the training fails during the execution of the link training step, the test control circuit is configured to automatically call up the spare training parameter set from the storage circuit to retrain without the intervention of external test equipment.
[0008] Furthermore, preferably, in the chip interconnect physical layer interface circuit with integrated self-test function of the present invention, when performing the loopback test step, the test control circuit is configured to automatically control the physical layer circuit to switch its operating rate and perform tests at multiple predefined rate points to determine the optimal operating rate.
[0009] Furthermore, preferably, in the chip interconnect physical layer interface circuit with integrated self-test function of the present invention, the operating rate is switched by configuring the division ratio of the phase-locked loop.
[0010] Furthermore, preferably, in the chip interconnect physical layer interface circuit with integrated self-test function of the present invention, the physical layer circuit includes multiple input / output units; each input / output unit integrates a built-in self-test stimulus generator and a data comparator; in loopback test mode, the stimulus generator generates test data, which is sent to the receiving path via the sending path and the internal loopback path, and the data comparator compares the received data with the sent data to determine the functional status of the input / output unit.
[0011] Furthermore, preferably, in the chip interconnect physical layer interface circuit with integrated self-test function of the present invention, the built-in self-test stimulus generator supports multiple test stimulus modes, including at least three of the following: pseudo-random sequence, fixed mode, checkerboard mode, row stripe mode, column stripe mode, and one-hot code mode.
[0012] Furthermore, preferably, in the chip interconnect physical layer interface circuit with integrated self-test function of the present invention, the test control circuit is also configured to summarize the test status of each input / output unit and generate statistical status information representing the overall test results.
[0013] Furthermore, preferably, the present invention also provides a chip testing method applied to any of the above-mentioned chip interconnect physical layer interface circuits with integrated self-test functions. The method includes: an external testing device sending a test start command to the test control circuit; the test control circuit responding to the command automatically executing a test program stored in the storage circuit, sequentially controlling the physical layer circuit to complete power-on detection, clock locking, link training, and loopback testing; the test control circuit collecting and summarizing the status of each test step; and the external testing device reading the final test result status from the test control circuit.
[0014] Using this invention, an MCU can be embedded in the HIPI PHY. In test mode, the MCU executes the test tasks and test data of the test machine, forming a closed-loop system that is not affected by external devices. This results in more accurate testing, more convenient, faster, and more reliable operation, and saves testing costs. Attached Figure Description
[0015] Figure 1 is a schematic diagram showing a core D2D HIPI PHY structure according to a preferred embodiment of the present invention.
[0016] Figure 2 is a schematic diagram illustrating the working interaction between the chip D2D HIPI PHY and the testing machine according to a preferred embodiment of the present invention.
[0017] Figure 3 is a schematic diagram illustrating the internal architecture of a core D2D HIPI PHY according to a preferred embodiment of the present invention.
[0018] Figure 4 is a schematic diagram illustrating the interaction process between the chip D2D HIPI PHY and the testing machine according to a preferred embodiment of the present invention.
[0019] Figure 5 is a schematic diagram illustrating a loopback test for each HIPI IO according to a preferred embodiment of the present invention.
[0020] Figure 6 is a schematic diagram illustrating the loopback test procedure for each HIPI PHY IO according to a preferred embodiment of the present invention. Detailed Implementation
[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Other embodiments or modifications obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.
[0022] According to a preferred embodiment of the present invention, the structure of the chip D2D HIPI PHY is shown in Figure 1, and the whole consists of two parts: a wafer tester and the D2D HIPI PHY to be tested; the tester provides test programs and probe cards.
[0023] The D2D HIPI PHY mainly consists of two parts: HIPI PHY Test and PHY Layer. HIPI PHY Test is mainly the interface circuit that interfaces with the test machine during PHY testing, supporting the JTAG protocol; the PHY mainly consists of PLL, HIPI Logic PHY, and HIPI Analog PHY.
[0024] In this scenario where the wafer-to-die (D2D) HIPI PHY interacts with the testing machine, the testing machine is a wafer testing machine equipped with a host computer control circuit and a probe card. The host computer control circuit mainly provides the test control program, issues test commands, collects test information, and makes judgments. The probe card provides the wafer die's JTAG signal and the DIE's power supply voltage, enabling the wafer die to function normally and interact with the testing machine to complete the testing work. The specific process is shown in Figure 2 and explained below.
[0025] (1) The test machine initiates a test start command. The HIPI PHY detects the start command and starts powering on immediately. It operates at a very low frequency, less than 100MHz. Data is initiated by TX and received by RX. If the sent and received data are consistent, it indicates that the power-on is on and the initiation status is normal. After the test machine receives the status information, it starts the next step.
[0026] (2) Start configuring the PLL to operate in a normal high-speed state. If the maximum transmission rate of HIPI is 32Gbps, then the output frequency of the PLL should be configured to be 16GHz. After the PLL configuration is completed, enter the locked state and initiate the PLL locking state. After the test machine receives the status information, it will start the next step.
[0027] (3) The test machine sends initialization information to initialize the PHY. After the initialization is completed, the initiation status is normal. After the test machine receives the status information, it starts the next step.
[0028] (4) The test machine issues a PHY training command to start configuring the first set of training parameters for the PHY. If the training fails, the initiation status fails. After receiving the status information, the test machine initiates the second set of training parameters. If the training is successful, the initiation status is normal. After receiving the status information, the test machine starts the next step.
[0029] (5) If the previous training step fails, continue to issue the next set of training parameters until the training is successful. If the previous training step is successful, start the loopback test mode.
[0030] (6) The PHY enters loopback mode. The PHY TX initiates test data, and the PHY RX receives and compares the data. If they are inconsistent, the initiation status fails. After receiving the status information, the test machine starts the next step. If the data received by RX and TX are consistent, the initiation status is successful. After receiving the status information, the test machine continues to the next test step.
[0031] (7) If the test in step (6) fails, the link speed can be reduced so that the PLL operates at the second lowest frequency (e.g., 8GHz), returning to step 2 and repeating the work of steps (2~6). If the test in step (6) is successful, select the test stimulus and use different test stimuli to detect the fault of the PHY link.
[0032] (8) After the test is completed, collect the test data.
[0033] The above testing process reveals the following technical challenges: 1) Frequent interaction between the tester and HiPi Phys. The Tester can only proceed to the next step after receiving a response from HiPi Phys. This operation is cumbersome and frequent operations increase the complexity of the sequencing program on the host computer software. In addition, customized test cards and test programs are required, which greatly increases the testing cost.
[0034] 2) The test machine needs to provide test programs. Due to the complexity of the test programs, they require a long time to verify. The test machine interacts frequently with HiPiPhy, and there are too many uncontrollable factors, which increases the probability of errors during the test and makes it difficult to locate whether the fault is in the test machine or HiPiPhy.
[0035] 3) The host computer test program of the test machine needs to be customized according to the requirements of HIPI PHY. It takes a long time to communicate to complete the code writing and debugging of the test program, which will delay the test and increase the test cost and workload.
[0036] 4) The frequent interaction between the test machine and HiPi Phy via JTAG results in a long test time, which greatly increases the test cost.
[0037] This invention solves the problem of D2D HIPI PHY testing for core particles and has the following prominent advantages: 1. It reduces the frequent interaction between the tester and the HiPi PHY, reduces the workload of the tester, lowers the complexity of the tester, and reduces the testing cost.
[0038] 2. The interaction between the test machine and HiPi phy is greatly reduced. It is all done by the PHY's own system, which is not affected by the test environment. This can improve test quality and make it easier to locate the problem.
[0039] 3. No need to customize host computer test programs for the test machine, saving test costs.
[0040] 4. Because the testing operation is simple and can be completed in a short time, it can save a lot of testing time and reduce a lot of testing costs.
[0041] According to a preferred embodiment of the present invention, the internal architecture of the chip-based D2D HIPI PHY is described below. As shown in Figure 3, the internal architecture system of the chip-based D2D HIPI PHY mainly consists of four parts: HIPI PHYTest, MCU, ROM, PLL, and HIPI PHY. HIPI PHY Test is an interconnect module with the test machine, capable of receiving test commands issued by the test machine. Simultaneously, the test machine can read the test status information of the HIPI PHY. The ROM stores the test program and the parameters for training the HIPI PHY during testing. The MCU can receive test commands issued by the test machine, and in test mode, read the test program in the ROM, start the test, and collect the test status of the PLL and HIPI PHY. In test mode, the PLL and HIPI PHY report their working status to the MCU, which then summarizes and reports the information to the test machine.
[0042] Because the test program running on the MCU has undergone extensive verification before the DIE is fabricated, its stability is ensured, which brings more convenience to the testing work.
[0043] According to a preferred embodiment of the present invention, the interaction method between the chip D2D HIPI PHY and the Teset is described as follows. As shown in Figure 4, the test machine initiates a test start command, the HIPI PHY automatically completes the test, generates the test status of each IO, and the test machine reads the status information. As shown in Figure 4, during the test, the MCU and HIPI PHY operate in a closed loop. The MCU initiates the test start and test task, the HIPI PHY receives the test command, performs the test, and reports the test status.
[0044] According to a preferred embodiment of the present invention, the test loopback mode is described as follows. Figure 5 shows a loopback test diagram of an IO. In the 2.5D advanced package, a single Macro TX / RX has a total of 33 data IOs: 32 data IOs and 1 repair IO. The 33 data IOs correspond to 33 modules shown in Figure 5, where a single IO is as follows: 1) Set the lp_bypass bit of the Test control register to 1 through the APB interface, indicating that the loopback test mode is now supported; otherwise, it is normal mode. Set bit[0] of the Test control register to 1 through the APB interface, indicating that the loopback test mode is now started. The BIST stimulus corresponding to test_mode[2:0] generates the test stimulus. 2) Within the TX logic PHY, a single IO corresponds to one BIST Unit data generator, which sends 16-bit pseudo-random data to the TX analog for parallel-to-serial forwarding to the TXIO PAD. The validity is controlled by lp_bypass. The TX data bypasses to the RX, where the RX Analog PHY receives the data and sends it to the RX Logic PHY for data comparison through serial-to-parallel conversion. If the data matches, it indicates success; otherwise, it indicates failure. io0_status[1:0] = 2`b01 indicates failure; = 2`b10 indicates success.
[0045] 3) For the entire 33 IOs, the status information lk_status[3:0]=0x9 indicates that all are correct; =0xA indicates that all are incorrect; =0xB indicates that there is at least one incorrect IO.
[0046] According to a preferred embodiment of the present invention, the testing process is as follows.
[0047] As shown in Figure 6, the test machine initiates the test command, and the MCU starts the test after receiving the test command. The process is as follows: power on -> PLL lock -> link training -> loopback mode -> test stimulus mode 0 -> test stimulus mode 1 -> test stimulus mode 2 -> test stimulus mode 3 -> test stimulus mode 4 -> test stimulus mode 5 -> collect test status -> output the test status of PHY IO. When PHY link training fails during testing, the PLL output can be adjusted to lower the PHY's operating rate. This is generally done at several frequency points: PLL_DIV[2:0] = 0x0, PLL outputs a 0.5GHz clock, corresponding to power-on startup and a 0.5GHz rate; PLL_DIV[2:0] = 0x1, PLL outputs a 2GHz clock, corresponding to an IO rate of 4Gbps; PLL_DIV[2:0] = 0x2, PLL outputs a 4GHz clock, corresponding to an IO rate of 8Gbps; PLL_DIV[2:0] = 0x3, PLL outputs an 8GHz clock, corresponding to an IO rate of 16Gbps; PLL_DIV[2:0] = 0x4, PLL outputs a 9GHz clock, corresponding to an IO rate of 18Gbps; PLL_DIV[2:0] = 0x5, The PLL outputs a 12GHz clock, corresponding to an IO rate of 24Gbps; PLL_DIV[2:0]= 0x6, the PLL outputs a 16GHz clock, corresponding to an IO rate of 32Gbps.
[0048] During testing, if an error occurs at the IO rate of 32Gbps, the PLL output frequency will be adjusted, starting from 12GHz and iterating through the frequency points to find the optimal frequency, which will then be recorded and reported.
[0049] The test stimuli correspond to the following: BIST stimulus generation test stimuli: 3`b000: PRBS stimulus, for random fault detection; 3`b001: Fixed stimulus, mainly used to detect fixed faults; 3`b010: Chessboard stimulus, mainly used to detect bridging faults between interconnected signals; 3`b011: Row stripe stimulus, mainly used to detect inter-row bridging faults; 3`b100: Column stripe stimulus, mainly used to detect inter-column bridging faults; 3`b101: One-hot stimulus, mainly used to detect crosstalk between interconnected signals.
[0050] According to a preferred embodiment of the present invention, the following beneficial effects are achieved.
[0051] Because MCUs are lightweight, their area is less than 0.015 mm² under SMIC's 12nm process; compared to the area of HIPI PHY, it is negligible.
[0052] As a lightweight MCU, it can operate at frequencies below 100MHz, and its power consumption is negligible compared to the HIPI PHY. The MCU only works during testing; under normal circumstances, it is not working and is in a powered-off state.
[0053] Since the area and power consumption of the MCU are negligible, and its impact on the HIPI PHY is even more negligible, the MCU can be embedded in the HIPI PHY. In test mode, the MCU executes the test tasks and test data of the test machine, forming a closed-loop system that is not affected by external devices, resulting in more accurate testing and more convenient operation.
[0054] As a closed-loop testing system, only the HIPI PHY and MCU interact, enabling rapid testing with shorter testing time, higher reliability, and reduced testing costs.
[0055] There is no need to interact with the test machine for more information. The test machine does not need to develop test programs and test stimuli, which reduces the workload of the test machine and saves testing workload and testing costs.
[0056] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0057] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.
[0058] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
[0059] The above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively describe all possible implementations here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.
Claims
1. A chip interconnect physical layer interface circuit with integrated self-test function, characterized in that, include: Physical layer circuitry is used to enable data transmission and reception between chips; test control circuitry is connected to the physical layer circuitry. A storage circuit is used to store test programs and configuration parameters; wherein, the test control circuit is configured to: in response to a single test start command initiated by an external test device, automatically execute the test program stored in the storage circuit, control the physical layer circuit to complete a series of predefined test steps, collect test status, and output the summarized test result status to the external test device.
2. The chip interconnect physical layer interface circuit with integrated self-test function according to claim 1, characterized in that, The test control circuit is a microcontroller unit, and the storage circuit is a read-only memory.
3. The chip interconnect physical layer interface circuit with integrated self-test function according to claim 1, characterized in that, The predefined test steps include at least two of the following: power-on detection, phase-locked loop configuration and locking, link training, and loopback testing.
4. The chip interconnect physical layer interface circuit with integrated self-test function according to claim 3, characterized in that, If training fails during the link training step, the test control circuit is configured to automatically retrieve a spare set of training parameters from the storage circuit for retraining without the need for external test equipment intervention.
5. The chip interconnect physical layer interface circuit with integrated self-test function according to claim 3, characterized in that, During the loopback test, the test control circuit is configured to automatically control the physical layer circuit to switch its operating rate and perform tests at multiple predefined rate points to determine the optimal operating rate.
6. The chip interconnect physical layer interface circuit with integrated self-test function according to claim 5, characterized in that, The operating rate is switched by configuring the division ratio of the phase-locked loop.
7. The chip interconnect physical layer interface circuit with integrated self-test function according to claim 1, characterized in that, The physical layer circuit includes multiple input / output units; each input / output unit integrates a built-in self-test stimulus generator and a data comparator; in loopback test mode, the stimulus generator generates test data, which is sent to the receiving path via the sending path and the internal loopback path, and the data comparator compares the received data with the sent data to determine the functional status of the input / output unit.
8. The chip interconnect physical layer interface circuit with integrated self-test function according to claim 7, characterized in that, The built-in self-test stimulus generator supports multiple test stimulus modes, including at least three of the following: pseudo-random sequence, fixed mode, checkerboard mode, row stripe mode, column stripe mode, and one-hot code mode.
9. The chip interconnect physical layer interface circuit with integrated self-test function according to claim 7, characterized in that, The test control circuit is also configured to summarize the test status of each input / output unit and generate statistical status information representing the overall test results.
10. A chip testing method, applied to a chip interconnect physical layer interface circuit with integrated self-test function as described in any one of claims 1 to 9, characterized in that, The method includes: an external test device sending a test start command to the test control circuit; the test control circuit responding to the command automatically executing the test program stored in the storage circuit, and sequentially controlling the physical layer circuit to complete power-on detection, clock locking, link training, and loopback testing; the test control circuit collecting and summarizing the status of each test step; and the external test device reading the final test result status from the test control circuit.