Pixel circuit, chip, display device and display system

Abstract

The invention discloses a pixel circuit, a chip, a display device and a display system, and belongs to the technical field of display circuits, the pixel circuit comprises pixel points and a driving circuit, and the pixel points comprise a red LED, a green LED and a blue LED; a clock terminal, a data terminal, a power supply terminal and a grounding terminal; the clock end is connected with a carrier voltage so as to supply power to the red LED; the data end accesses a data signal; the power supply end is connected with an input voltage so as to supply power to the driving circuit, the green LED and the blue LED; the grounding end is connected with the power ground; the driving circuit decodes the data signal based on the carrier voltage so as to output a first driving current to the red LED, output a second driving current to the green LED and output a third driving current to the blue LED; therefore, the number of the pins is reduced, the distance between the pins is increased, the interference between signals is reduced, the PCB yield is improved, and the application scene of the chip is expanded.

Description

Pixel circuits, chips, display devices and display systems Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a pixel circuit, chip, display device and display system. Background Technology

[0002] In the context of rapid growth in the ultra-high-definition display market, Active Matrix ICs (AMICs) are rapidly becoming a hot research and development direction in the industry due to their ability to integrate with micro light-emitting diode (Micro LED) chips in the same package (such as pixel circuits) to achieve "lamp-driver integration." However, due to the small product spacing in AMIC application scenarios, higher requirements are placed on chip packaging. When packaging AMICs, interference between signals is generally reduced by decreasing the number of pins and increasing the pin spacing, thereby improving the printed circuit board (PCB) yield and expanding the chip's application scenarios. For related AMICs, since the driving voltage of red LEDs is lower than that of blue and green LEDs, separate power supplies are needed for red and blue / green LEDs to reduce overall chip power consumption. This necessitates separate packaging of pins for the red LED power supply and the blue / green LED driver power supply, resulting in an increased number of pins and a reduced pin spacing, which in turn leads to a lower PCB yield. Therefore, related pixel circuits result in a larger number of chip package pins, smaller pin spacing, and lower PCB yield. Summary of the Invention

[0003] The purpose of this application is to provide a pixel circuit, chip, display device and display system, which aims to solve the problems of large number of chip package pins, small pin spacing and low PCB yield caused by the related pixel circuit.

[0004] This application provides a pixel circuit including pixels, which include a red LED, a green LED, and a blue LED. The pixel circuit has: a clock terminal for receiving a carrier voltage to power the red LED; a data terminal for receiving a data signal; a power supply terminal for receiving an input voltage to power a driving circuit, the green LED, and the blue LED; and a ground terminal connected to the power ground. The pixel circuit further includes: a driving circuit connected to the clock terminal, the data terminal, the power supply terminal, the ground terminal, the red LED, the green LED, and the blue LED, for decoding the data signal based on the carrier voltage to output a first driving current to the red LED, a second driving current to the green LED, and a third driving current to the blue LED.

[0005] In one embodiment, the pixel circuit includes: a level resolution circuit connected to the clock terminal, used to perform level shifting on the carrier voltage to output a clock signal; a protocol resolution circuit connected to the data terminal and the level resolution circuit, used to perform protocol resolution on the data signal based on the clock signal to obtain a grayscale signal; a PWM circuit connected to the protocol resolution circuit, used to output a first PWM signal, a second PWM signal, and a third PWM signal based on the grayscale signal; and an output circuit connected to the PWM circuit, used to output a first driving current based on the first PWM signal, output a second driving current based on the second PWM signal, and output a third driving current based on the third PWM signal.

[0006] In one embodiment, the protocol parsing circuit is specifically used to perform protocol parsing on the data signal based on the clock signal to obtain a grayscale signal and a peak current signal; the output circuit is also connected to the protocol parsing circuit and is specifically used to output the first driving current based on the peak current signal and the first PWM signal, output the second driving current based on the peak current signal and the second PWM signal, and output the third driving current based on the peak current signal and the third PWM signal.

[0007] In one embodiment, the level resolution circuit includes: a voltage divider circuit connected to the clock terminal for dividing the carrier voltage to output a divided voltage signal; a first comparator circuit connected to the voltage divider circuit for comparing the divided voltage signal with a first reference voltage to output a first comparator signal; a second comparator circuit connected to the voltage divider circuit for comparing the divided voltage signal with a second reference voltage to output a second comparator signal; and a logic circuit connected to the first comparator circuit and the second comparator circuit for performing logic processing on the first comparator signal and the second comparator signal to output the clock signal.

[0008] This invention also provides a chip, characterized in that the chip includes the pixel circuit described above.

[0009] The present invention also provides a pixel circuit, characterized in that the pixel circuit includes a red LED, a green LED, a blue LED, and the pixel circuit described above.

[0010] This invention also provides a display device, characterized in that it includes a control circuit and m*n pixel circuits as described above; the control circuit is connected to the m*n pixel circuits, and is used to receive display data and output m carrier voltages and n data signals based on the display data; the m carrier voltages are connected one-to-one to the m rows of pixel circuits, and the n data signals are connected one-to-one to the n columns of pixel circuits; or the m carrier voltages are connected one-to-one to the m columns of pixel circuits, and the n data signals are connected one-to-one to the n rows of pixel circuits; wherein m and n are both positive integers.

[0011] In one embodiment, when m carrier voltages are connected to m rows of pixel circuits in a one-to-one correspondence, and n data signals are connected to n columns of pixel circuits in a one-to-one correspondence: the control circuit is specifically used to access the display data, and output m carrier voltages sequentially based on the display data, and during the output of the i-th carrier voltage, output each data signal corresponding to each pixel circuit in the i-th row in a sequential manner; where i is a positive integer less than or equal to m.

[0012] In one embodiment, when m carrier voltages are connected to m columns of pixel circuits in a one-to-one correspondence, and n data signals are connected to n rows of pixel circuits in a one-to-one correspondence: the control circuit is specifically used to access the display data, and output m carrier voltages sequentially based on the display data, and during the output of the j-th carrier voltage, output each data signal corresponding to each pixel circuit in the j-th column in a sequential manner; where j is a positive integer less than or equal to m.

[0013] This invention also provides a display system, characterized in that it includes L cascaded display devices as described above.

[0014] In one embodiment, the control circuit in the kth display device is further configured to forward the display data to the control circuit in the (k+1)th display device; where k is a positive integer less than or equal to L-1.

[0015] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: Since the input voltage powers the pixel circuit, green LED and blue LED, and the carrier voltage powers the red LED, and the pixel circuit decodes the data signal based on the carrier voltage to output each driving current to each color LED, by using the carrier voltage as both the clock reference of the pixel circuit and the power supply voltage of the red LED, the number of pins can be reduced and the pin spacing can be increased when the driving circuit and the Micro LED chip are integrated in the same package (such as the pixel circuit), thereby reducing interference between signals, improving PCB yield, and expanding the application scenarios of the chip. Attached Figure Description

[0016] To more clearly illustrate the technical inventions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 is a schematic diagram of a pixel circuit according to an embodiment of this application; Figure 2 is a schematic diagram of a driving circuit according to an embodiment of this application; Figure 3 is a schematic diagram of another driving circuit according to an embodiment of this application; Figure 4 is a schematic diagram of a level resolution circuit according to an embodiment of this application; Figure 5 is a partial example circuit structure diagram of a level resolution circuit according to an embodiment of this application; Figure 6 is a schematic diagram of the pixel circuit package according to an embodiment of this application; Figure 7 is a schematic diagram of another pixel circuit according to an embodiment of this application; Figure 8 is a schematic diagram of a display device according to an embodiment of this application; Figure 9 is a schematic diagram of another display device according to an embodiment of this application; Figure 10 is a schematic diagram of a display system according to an embodiment of this application. Detailed Implementation

[0018] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0019] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0020] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0022] Figure 1 shows a schematic diagram of the pixel circuit provided in a preferred embodiment of this application. For ease of explanation, only the parts related to this embodiment are shown, and the details are as follows: The pixel circuit includes pixels, and the pixels include red LEDs, green LEDs and blue LEDs; the pixel circuit has a clock terminal DCLK, a data terminal DIN, a power supply terminal VCC and a ground terminal GND.

[0023] The clock terminal DCLK is used to connect the carrier voltage VCLK to power the red LED; the data terminal DIN is used to connect the data signal SDA; the power supply terminal VCC is used to connect the input voltage VGB to power the driver circuit, green LED, and blue LED; the ground terminal GND is connected to the power ground; the driver circuit is connected to the clock terminal DCLK, the data terminal DIN, the power supply terminal VCC, the ground terminal GND, the red LED, the green LED, and the blue LED, and is used to decode the data signal SDA based on the carrier voltage VCLK to output a first drive current to the red LED, a second drive current to the green LED, and a third drive current to the blue LED.

[0024] It is understandable that the carrier voltage VCLK has a first level and a second level, wherein the voltage of the first level is greater than the power supply voltage of the red LED, and the voltage of the second level is greater than the voltage of the first level; in specific implementation, the voltage of the second level can be 3.8V, and the voltage of the first level can be 2.8V.

[0025] With the above scheme, the carrier voltage VCLK serves as both the clock reference for the pixel circuit and the power supply voltage for the red LED. Therefore, when the driving circuit and the Micro LED chip are integrated into the same package (such as the pixel circuit), the number of pins can be reduced and the pin spacing can be increased, thereby reducing interference between signals, improving PCB yield, and expanding the application scenarios of the chip.

[0026] As shown in Figure 2, the driving circuit includes a level parsing circuit 10, a protocol parsing circuit 20, a PWM circuit 30, and an output circuit 40.

[0027] The level parsing circuit 10, connected to the clock terminal DCLK, is used to level-shift the carrier voltage VCLK to output a clock signal; the protocol parsing circuit 20, connected to the data terminal DIN and the level parsing circuit 10, is used to perform protocol parsing on the data signal SDA based on the clock signal to obtain a grayscale signal; the PWM circuit 30, connected to the protocol parsing circuit 20, is used to output a first PWM signal, a second PWM signal, and a third PWM signal based on the grayscale signal; the output circuit 40, connected to the PWM circuit 30, is used to output a first drive current based on the first PWM signal, a second drive current based on the second PWM signal, and a third drive current based on the third PWM signal.

[0028] It is understandable that the level resolution circuit 10 can be implemented in the following ways: 1) by using at least one diode, where at least one diode performs level shifting on the carrier voltage VCLK to output a clock signal; 2) by using a comparator.

[0029] It should be noted that the PWM circuit 30 is specifically used to obtain the first duty cycle to the third duty cycle based on the grayscale signal, and output a first PWM signal with the first duty cycle, a second PWM signal with the second duty cycle, and a third PWM signal with the third duty cycle.

[0030] As an example and not a limitation, the output circuit 40 is specifically configured to output a first drive current based on a preset current and a first PWM signal, output a second drive current based on a preset current and a second PWM signal, and output a third drive current based on a preset current and a third PWM signal. It is understood that the maximum current from the first drive current to the third drive current is the preset current; the duty cycle of the first drive current is related to the duty cycle of the first PWM signal; the duty cycle of the second drive current is related to the duty cycle of the second PWM signal; and the duty cycle of the third drive current is related to the duty cycle of the third PWM signal.

[0031] The above technical solution enables the decoding of the data signal SDA based on the carrier voltage VCLK to drive the red, green, and blue LEDs. The circuit is simple and reliable by using PWM signals to generate the drive current.

[0032] As shown in Figure 3, the protocol parsing circuit 20 is specifically used to perform protocol parsing on the data signal SDA based on the clock signal to obtain the grayscale signal and the peak current signal; the output circuit 40 is also connected to the protocol parsing circuit 20, and is specifically used to output the first drive current based on the peak current signal and the first PWM signal, output the second drive current based on the peak current signal and the second PWM signal, and output the third drive current based on the peak current signal and the third PWM signal.

[0033] Understandably, the peak current signal carries peak current information, thereby enabling the preset current to be adjustable, which in turn enables the brightness of the pixel to be adjustable, thus improving the flexibility of the pixel circuit.

[0034] As shown in Figure 4, the level resolution circuit 10 includes a voltage divider circuit 11, a first comparator circuit 12, a second comparator circuit 13, and a logic circuit 14.

[0035] Voltage divider circuit 11, connected to the clock terminal DCLK, is used to divide the carrier voltage VCLK to output a divided voltage signal; first comparator circuit 12, connected to voltage divider circuit 11, is used to compare the divided voltage signal with a first reference voltage Vref1 to output a first comparator signal; second comparator circuit 13, connected to voltage divider circuit, is used to compare the divided voltage signal with a second reference voltage Vref2 to output a second comparator signal; logic circuit 14, connected to first comparator circuit 12 and second comparator circuit 13, is used to perform logic processing on the first comparator signal and the second comparator signal to output a clock signal.

[0036] Figure 5 shows a partial example circuit structure of the level resolution circuit provided in an embodiment of the present invention. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below: The voltage divider circuit 11 includes a first resistor R1 and a second resistor R2; the first end of the first resistor R1 constitutes the input terminal of the voltage divider circuit 11 and is connected to the clock terminal DCLK to receive the carrier voltage VCLK; the second end of the first resistor R1 and the first end of the second resistor R2 are connected to form the output terminal of the voltage divider circuit 11 and are connected to the first comparator circuit 12 and the second comparator circuit 13 to receive the voltage divider signal; the second end of the second resistor R2 is connected to the power supply ground.

[0037] It includes a first comparator U1; the non-inverting input terminal of the first comparator U1 forms the first input terminal of the first comparator circuit 12 and is connected to the voltage divider circuit 11 to receive the voltage divider signal; the inverting input terminal of the first comparator U1 forms the second input terminal of the first comparator circuit 12 to receive the first reference voltage Vref1; the output terminal of the first comparator U1 forms the output terminal of the first comparator circuit 12 and is connected to the logic circuit 14 to output the first comparison signal.

[0038] The second comparator circuit 13 includes a second comparator U2; the non-inverting input terminal of the second comparator U2 constitutes the first input terminal of the second comparator circuit 13 and is connected to the voltage divider circuit 11 to receive the voltage divider signal; the inverting input terminal of the second comparator U2 constitutes the second input terminal of the second comparator circuit 13 to receive the second reference voltage Vref2; the output terminal of the second comparator U2 constitutes the output terminal of the second comparator circuit 13 and is connected to the logic circuit 14 to output the second comparison signal.

[0039] It is understood that the specific circuit structure of the voltage divider circuit 11, the first comparator circuit 12 and the second comparator circuit 13 described above is only one embodiment, and can be implemented in other ways.

[0040] The logic circuit 14 includes a first NOR gate U3, a second NOR gate U4, and a first NOT gate U5. The first input terminal of the first NOR gate U3 constitutes the first input terminal of the logic circuit 14 and is connected to the first comparator circuit 12 to receive a first comparison signal. The input terminal of the first NOT gate U5 constitutes the second input terminal of the logic circuit 14 and is connected to the second comparator circuit 13 to receive a second comparison signal. The output terminal of the first NOT gate U5 is connected to the second input terminal of the second NOR gate U4. The output terminal of the first NOR gate U3 is connected to the first input terminal of the second NOR gate U4. The second input terminal of the first NOR gate U3 and the output terminal of the second NOR gate U4 are connected and together constitute the output terminal of the logic circuit 14, which is connected to the protocol parsing circuit 20 to output a clock signal.

[0041] Understandably, when the first reference voltage is greater than the second reference voltage, and the carrier voltage VCLK is greater than the first threshold, the voltage divider signal is greater than the first reference voltage Vref1 and the second reference voltage Vref2. Both the first comparison signal and the second comparison signal are at high levels, therefore the clock signal is at a high level. When the carrier voltage VCLK is less than the second threshold, the voltage divider signal is less than the first reference voltage Vref1 and the second reference voltage Vref2. Both the first comparison signal and the second comparison signal are at low levels, therefore the clock signal is at a low level. When the carrier voltage VCLK is greater than the second threshold and less than the first threshold, the voltage divider signal is less than the first reference voltage Vref1 and greater than the second reference voltage Vref2. The first comparison signal is at a low level, and both the second comparison signals are at high levels, therefore the clock signal maintains its original level polarity.

[0042] The above technical solution was used to analyze the carrier voltage VCLK, thereby obtaining the clock signal.

[0043] This application also provides a chip, which includes the pixel circuit described above.

[0044] Figure 6 shows a schematic diagram of the pixel circuit package provided in a preferred embodiment of this application. As can be seen from Figure 4, the packaged pixel circuit has only 4 pins, which reduces the number of pins for powering the red LED compared to related pixel circuits. Figure 7 shows a schematic diagram of the pixel circuit structure provided in a preferred embodiment of this application.

[0045] The above technical solution encapsulates the driving circuit, red LED, green LED, and blue LED in a single module (it is worth noting that this pixel circuit can be a display chip), thereby reducing the size and making it possible to increase pixel density. At the same time, it can improve the PCB yield.

[0046] Figure 8 shows a schematic diagram of a display device provided in a preferred embodiment of this application, and Figure 9 shows another schematic diagram of a display device provided in a preferred embodiment of this application. For ease of explanation, only the parts related to this embodiment are shown, and the details are as follows: The above-mentioned display device includes a control circuit 80 and m*n pixel circuits as described above; the control circuit 80 is connected to the m*n pixel circuits and is used to access display data and output m carrier voltages VCLK and n data signals SDA based on the display data; where m and n are both positive integers.

[0047] As shown in Figure 8, m carrier voltages VCLK are connected to the m-row pixel circuits one-to-one, and n data signals SDA are connected to the n-column pixel circuits one-to-one; or as shown in Figure 9, m carrier voltages VCLK are connected to the m-column pixel circuits one-to-one, and n data signals SDA are connected to the n-row pixel circuits one-to-one.

[0048] Each chip (such as AMIC) independently controls one pixel. The data terminals DIN of each row or column of AMIC are connected in parallel, and the clock terminals DCLK of each column or row of AMIC are connected in parallel, forming a crisscrossing connection network. The resulting display module array has m carrier voltages VCLK and n data signals SDA, all controlled by a control circuit 80.

[0049] Understandably, after receiving a frame of display data, the display device will first send AMIC data of clock group 1 (corresponding to the first carrier voltage VCLK), then send AMIC data of clock group 2 (corresponding to the first carrier voltage VCLK), and so on, sending display data of M AMICs in sequence, thereby realizing the control of the entire display device.

[0050] The above technical solution realizes a display device with m*n pixels, and the pixels are integrated with the Micro LED chip. The number of pins and the pin spacing are increased, thereby reducing interference between signals, improving PCB yield, and increasing the pixel density of the display device.

[0051] As an example and not a limitation, m carrier voltages VCLK are connected to m rows of pixel circuits one by one, and n data signals SDA are connected to n columns of pixel circuits one by one; the control circuit 80 is specifically used to receive display data and output m carrier voltages VCLK sequentially based on the display data, and during the output of the i-th carrier voltage VCLK, it sequentially outputs each data signal SDA corresponding to each pixel circuit in the i-th row; where i is a positive integer less than or equal to m.

[0052] With the above technical solution, the data terminal DIN of each AMIC in each row only needs to be connected to the data terminal DIN of one control circuit 80. By using time-division multiplexing, the data terminal DIN of the control circuit 80 can control each AMIC in that row, which simplifies the circuit design and saves the port resources of the control circuit 80.

[0053] As an example and not a limitation, m carrier voltages VCLK are connected to m column pixel circuits one by one, and n data signals SDA are connected to n row pixel circuits one by one; the control circuit 80 is specifically used to receive display data, and output m carrier voltages VCLK sequentially based on the display data, and during the output of the j-th carrier voltage VCLK, output each data signal SDA corresponding to each pixel circuit in the j-th column sequentially; where j is a positive integer less than or equal to m.

[0054] With the above technical solution, the data terminal DIN of each AMIC in each column only needs to be connected to the data terminal DIN of one control circuit 80. By using time-division multiplexing, the data terminal DIN of the control circuit 80 can control each AMIC in that column, which simplifies the circuit design and saves the port resources of the control circuit 80.

[0055] Figure 10 shows a schematic diagram of a display system provided in a preferred embodiment of this application. For ease of explanation, only the parts related to this embodiment are shown, and the details are as follows: The display system is characterized in that it includes L cascaded display devices as described above.

[0056] It is understandable that display devices can receive display data and support cascading forwarding, thereby enabling the cascading expansion of display arrays.

[0057] In one embodiment, the control circuit in the kth display device is further configured to forward display data to the control circuit in the (k+1)th display device; where k is a positive integer less than or equal to L-1.

[0058] As an example and not a limitation, the control circuit in the kth display device can directly forward the display data to the control circuit in the (k+1)th display device. The control circuit in each display device extracts the display data in the data frame corresponding to its own identifier, and outputs m carrier voltages in sequence according to the display data in the data frame corresponding to its own identifier. During the output of the i-th carrier voltage, it outputs the data signals corresponding to each pixel circuit in the i-th row in sequence.

[0059] As an example and not a limitation, the control circuit in the kth display device may intercept display data from the previous preset number of data frames and forward the intercepted display data to the control circuit in the (k+1)th display device.

[0060] The above technical solution enables cascading forwarding of display data, thereby achieving cascading expansion of the display array. It should be understood that the sequence numbers of the steps in the above embodiments do not imply the order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0061] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A pixel circuit, characterized in that, The system includes pixels, which include red LEDs, green LEDs, and blue LEDs; the pixel circuit has a clock terminal for receiving a carrier voltage to power the red LEDs. The data terminal is used to receive data signals; The power supply terminal is used to connect the input voltage to power the driving circuit, the green LED, and the blue LED; The grounding terminal is connected to the power supply ground. The pixel circuit further includes: the driving circuit, which is connected to the clock terminal, the data terminal, the power supply terminal, the ground terminal, the red LED, the green LED, and the blue LED, for decoding the data signal based on the carrier voltage, so as to output a first driving current to the red LED, output a second driving current to the green LED, and output a third driving current to the blue LED.

2. The pixel circuit as described in claim 1, characterized in that, The driving circuit includes: a level resolution circuit connected to the clock terminal, used to perform level shifting on the carrier voltage to output a clock signal; a protocol resolution circuit connected to the data terminal and the level resolution circuit, used to perform protocol resolution on the data signal based on the clock signal to obtain a grayscale signal; a PWM circuit connected to the protocol resolution circuit, used to output a first PWM signal, a second PWM signal, and a third PWM signal based on the grayscale signal; and an output circuit connected to the PWM circuit, used to output a first driving current based on the first PWM signal, output a second driving current based on the second PWM signal, and output a third driving current based on the third PWM signal.

3. The pixel circuit as described in claim 2, characterized in that, The protocol parsing circuit is specifically used to perform protocol parsing on the data signal based on the clock signal to obtain a grayscale signal and a peak current signal; the output circuit is also connected to the protocol parsing circuit and is specifically used to output the first driving current based on the peak current signal and the first PWM signal, output the second driving current based on the peak current signal and the second PWM signal, and output the third driving current based on the peak current signal and the third PWM signal.

4. The pixel circuit as described in claim 2, characterized in that, The level resolution circuit includes: a voltage divider circuit connected to the clock terminal for dividing the carrier voltage to output a divided voltage signal; a first comparator circuit connected to the voltage divider circuit for comparing the divided voltage signal with a first reference voltage to output a first comparator signal; a second comparator circuit connected to the voltage divider circuit for comparing the divided voltage signal with a second reference voltage to output a second comparator signal; and a logic circuit connected to the first comparator circuit and the second comparator circuit for performing logic processing on the first comparator signal and the second comparator signal to output the clock signal.

5. A chip, characterized in that, The chip includes the pixel circuitry as described in any one of claims 1 to 4.

6. A display device, characterized in that, It includes a control circuit and m*n pixel circuits as described in any one of claims 1 to 4; the control circuit is connected to the m*n pixel circuits, and is used to access display data and output m carrier voltages and n data signals based on the display data; the m carrier voltages are connected to the m rows of pixel circuits one by one, and the n data signals are connected to the n columns of pixel circuits one by one. Alternatively, m carrier voltages can be connected one-to-one to m columns of pixel circuits, and n data signals can be connected one-to-one to n rows of pixel circuits; where m and n are both positive integers.

7. The display device as claimed in claim 6, characterized in that, When m carrier voltages are connected to the pixel circuits in m rows in a one-to-one correspondence, and n data signals are connected to the pixel circuits in n columns in a one-to-one correspondence: the control circuit is specifically used to access the display data, and output m carrier voltages sequentially based on the display data, and during the output of the i-th carrier voltage, output each data signal corresponding to each pixel circuit in the i-th row in a sequential manner; where i is a positive integer less than or equal to m.

8. The display device as claimed in claim 6, characterized in that, When m carrier voltages are connected to m columns of pixel circuits in a one-to-one correspondence, and n data signals are connected to n rows of pixel circuits in a one-to-one correspondence: the control circuit is specifically used to access the display data, and output m carrier voltages sequentially based on the display data, and during the output of the j-th carrier voltage, output each data signal corresponding to each pixel circuit in the j-th column in a sequential manner; where j is a positive integer less than or equal to m.

9. A display system, characterized in that, Includes L cascaded display devices as described in any one of claims 6 to 8.

10. The display system as claimed in claim 9, characterized in that, The control circuit in the kth display device is further configured to forward the display data to the control circuit in the (k+1)th display device; where k is a positive integer less than or equal to L-1.

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