Voltage control circuit

Abstract

The invention discloses a voltage control circuit, relates to the field of SRAM (Static Random Access Memory) chip design, and aims to solve the problem of poor calculation accuracy of an SRAM storage unit in the prior art. The circuit comprises a current source circuit, an operational amplifier and a transmission gate, the current source circuit is connected with an operational amplifier, the operational amplifier is connected with a transmission gate, and the transmission gate is connected with a right word line of the SRAM storage unit; a current source circuit is used for providing zero-temperature-coefficient current, and when the voltage between a grid electrode and a source electrode of a target transistor is larger than threshold voltage, the target transistor is made to be in a saturation region; an operational amplifier connected into a voltage follower circuit structure is used as a negative feedback circuit in the voltage control circuit; the transmission gate is used for transmitting and isolating a control signal in the voltage control circuit; therefore, the current of the transmission tube in the SRAM memory cell in the calculation mode fluctuates in a small range, so that the calculation accuracy of the SRAM memory cell is improved.

Description

Technical Field

[0001] This invention relates to the field of SRAM chip design, and in particular to a voltage control circuit. Background Technology

[0002] Static Random Access Memory (SRAM) is a type of random access memory that retains data without requiring refresh. Its "static" characteristic stems from the use of bistable flip-flops in the memory cells, directly storing binary data (0 / 1) through the stable state of the circuit. A more advanced SRAM memory exists in the prior art; please refer to [link to relevant documentation]. Figure 1 , Figure 1 This is a schematic diagram of the computing circuit structure of SRAM memory in the prior art; Figure 1 The storage and computing structure shown can input signals via word lines, and then multiply the input signals with the stored values. In this SRAM storage and computing structure, the current in the SRAM's transfer transistor changes with temperature, leading to inaccurate calculation results. For MOSFETs in traditional process nodes, as the temperature increases, the computing current in the transfer transistor decreases, and the output voltage representing the multiplication result also decreases. If the temperature change is too large, the calculation result will be incorrect. The situation is reversed for MOSFETs in advanced process nodes, resulting in similarly incorrect calculation results. This deteriorates the computing function of the SRAM computing circuit, leading to low calculation accuracy.

[0003] Therefore, there is an urgent need to design a more advanced control circuit to solve the problem of poor calculation accuracy of SRAM memory cells in the existing technology. Summary of the Invention

[0004] The purpose of this invention is to provide a voltage control circuit for controlling the word line voltage of the current-mode SRAM memory for in-memory calculation. This circuit can prevent temperature from adversely affecting the calculation function of the current-mode in-memory calculation circuit, and ensure that the current of the transmission transistor in the SRAM memory cell in calculation mode fluctuates within a small range, so that temperature does not cause significant interference to the calculation. This solves the problem of poor calculation accuracy of SRAM memory cells in the prior art.

[0005] To achieve the above objectives, the present invention provides the following technical solution: This invention provides a voltage control circuit, which may include: Current source circuits, operational amplifiers, and transmission gates; The current source circuit is connected to the operational amplifier, the operational amplifier is connected to the transmission gate, and the transmission gate is connected to the right word line of the SRAM memory cell. The current source circuit is used to provide a current with zero temperature coefficient, so that the target transistor is in the saturation region when the voltage between the gate and source of the target transistor is greater than a threshold voltage; the target transistor refers to the transistor connected to the operational amplifier in the current source circuit. The operational amplifier is connected as a voltage follower circuit structure for use in the negative feedback circuit of the voltage control circuit. The transmission gate is used to transmit and isolate control signals in the voltage control circuit.

[0006] Preferably, the current source circuit may include an ideal current source, a fifth NMOS transistor, and a sixth NMOS transistor; One end of the ideal current source is connected to the power supply terminal, and the other end is connected to the drain of the fifth NMOS transistor; the drain of the fifth NMOS transistor is connected to the non-inverting input terminal of the operational amplifier, the gate is connected to the drain of the fifth NMOS transistor, and the source is connected to the drain of the sixth NMOS transistor; the gate of the sixth NMOS transistor is connected to the power supply terminal, and the source is grounded.

[0007] Preferably, the inverting input terminal of the operational amplifier is connected to the output terminal of the operational amplifier, and the output terminal is connected to the transmission gate.

[0008] Preferably, the transmission gate may include a third PMOS transistor, a fourth PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; The drain of the third PMOS transistor is connected to the right word line of the SRAM memory cell, the gate is connected to the enable terminal, and the source is grounded; the source of the eighth NMOS transistor is connected to the drain of the third PMOS transistor, the gate is connected to the reverse enable terminal, and the drain is grounded. The drain of the fourth PMOS transistor is connected to the right word line of the SRAM memory cell, the gate is connected to the reverse enable terminal, and the source is connected to the output terminal of the operational amplifier circuit; the source of the seventh NMOS transistor is connected to the drain of the fourth PMOS transistor, the gate is connected to the enable terminal, and the drain is connected to the output terminal of the operational amplifier circuit.

[0009] Preferably, when the input of the SRAM memory cell is high, the enable terminal is input with a high level, the inverting enable terminal is input with a low level, the seventh NMOS transistor and the fourth PMOS transistor are turned on, and the eighth NMOS transistor and the third PMOS transistor are turned off; the voltage control circuit inputs a high level to the right word line of the SRAM memory cell.

[0010] Preferably, when the input of the SRAM memory cell is low, the enable terminal is input with a low level, the reverse enable terminal is input with a high level, the seventh NMOS transistor and the fourth PMOS transistor are turned off, and the eighth NMOS transistor and the third PMOS transistor are turned on; the voltage control circuit inputs a low level to the right word line of the SRAM memory cell.

[0011] Preferably, when the voltage control circuit and SRAM memory cell use conventional process node transistors and the temperature rises, the carrier mobility of the fifth NMOS transistor and the sixth NMOS transistor decreases and the current tends to decrease. Then, the constant current provided by the ideal current source is used to increase the gate voltage of the fifth NMOS transistor and the voltage of the non-inverting input terminal of the operational amplifier, so as to increase the voltage of the right word line input to the SRAM memory cell, thereby suppressing the decrease in the current of the third NMOS transistor.

[0012] Preferably, when the voltage control circuit and SRAM memory cell use conventional process node transistors and the temperature decreases, the carrier mobility of the fifth NMOS transistor and the sixth NMOS transistor increases, and the current tends to increase. Then, the constant current provided by the ideal current source is used to reduce the gate voltage of the fifth NMOS transistor and the voltage of the non-inverting input terminal of the operational amplifier, so as to reduce the voltage of the right word line input to the SRAM memory cell and suppress the increase of the current of the third NMOS transistor.

[0013] Preferably, when the voltage control circuit and SRAM memory cell use advanced process node transistors and the temperature decreases, the threshold voltages of the fifth NMOS transistor and the sixth NMOS transistor rise, and the current tends to decrease. Then, the constant current provided by the ideal current source increases the gate voltage of the fifth NMOS transistor and the voltage at the non-inverting input of the operational amplifier, thereby increasing the voltage input to the right word line of the SRAM memory cell to suppress the decrease in the current of the third NMOS transistor.

[0014] Preferably, when the voltage control circuit and SRAM memory cell use advanced process node transistors and the temperature rises, the threshold voltages of the fifth NMOS transistor and the sixth NMOS transistor decrease and the current tends to increase. Then, the constant current provided by the ideal current source is used to reduce the gate voltage of the fifth NMOS transistor and the voltage at the non-inverting input of the operational amplifier, so that the voltage input to the right word line of the SRAM memory cell is reduced, thereby suppressing the increase of the current of the third NMOS transistor.

[0015] Compared with existing technologies, the voltage control circuit provided by this invention, through the arrangement of a current source circuit, an operational amplifier, and a transmission gate; connecting the current source circuit to the operational amplifier, the operational amplifier to the transmission gate, and the transmission gate to the right word line of the SRAM memory cell; utilizing the current source circuit to provide a zero-temperature coefficient current, causing the target transistor to be in the saturation region when the voltage between the gate and source of the target transistor is greater than the threshold voltage; further utilizing the operational amplifier connected as a voltage follower circuit structure as a negative feedback circuit in the voltage control circuit; and utilizing the transmission gate to transmit and isolate the control signal in the voltage control circuit; thereby generating a word line control voltage according to the input value of the voltage control circuit, and controlling the change of the word line voltage when the chip temperature changes, so that the transmission transistor current in the SRAM memory cell in computing mode fluctuates within a small range, preventing temperature from causing significant interference to the calculation; improving the calculation accuracy of the SRAM memory cell, and solving the problem of poor calculation accuracy of SRAM memory cells in existing technologies. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of the computing circuit structure of SRAM memory in the prior art; Figure 2 A schematic diagram of the circuit structure of the voltage control circuit provided by the present invention; Figure 3 A schematic diagram illustrating the working principle of the voltage control circuit provided by this invention when cooling down traditional process nodes or heating up advanced process nodes; Figure 4 A schematic diagram illustrating the working principle of the voltage control circuit provided by this invention when heating up traditional process nodes or cooling down advanced process nodes; Figure 5 A schematic diagram illustrating the control effect of the MOS transistor of the voltage control circuit provided by the present invention on the SRAM memory cell at the 28nm process node.

[0017] Figure reference numerals: 10-current source circuit, 20-operational amplifier, 30-transmission gate, 40-SRAM memory cell. Detailed Implementation

[0018] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" are not necessarily different.

[0019] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0020] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding related objects have an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0021] In such Figure 1 In the SRAM-based memory computing structure shown, if the SRAM input is 1 (WLR=1), the word line is on, the stored value Q is 1, QB is 0, and current flows through the SRAM transfer transistor near QB. If the input is 1 (WLR=1), the word line is on, the stored value is 0, QB is 1, and no current flows through the SRAM transfer transistor near QB. If the input is 0 (WLR=0), the transfer transistor is off, and regardless of whether the stored value is 0 or 1, no current flows through the transfer transistor near the SRAM. Furthermore, the magnitude of the discharge current of the SRAM cells on the BLB can be statistically analyzed using multiplication and accumulation. For example... Figure 1As shown on the left, M1, M2, M3, and M4 together constitute the CCM (Cascade Current Mirror) circuit; M2 and M4 form a voltage clamp; M1 and M3 mirror the current from VDD to M2 to M4 to the load capacitor C. Capacitor C collects the mirrored current and converts it into an output voltage (Vout). Due to the clamping effect of M2 and M4, the voltage of BL changes only slightly during discharge. Its working principle is as follows: During the pre-charge process, BL charges to approximately VDD / 2, Vout is grounded, and VCM / VG is connected to VDD; then CCM enters the pre-read phase, VG is connected to BL, and to ensure that M1, M2, M3, and M4 operate in the saturation region, the bias voltage of VCM is set to approximately VDD / 2. CCM requires a very short pre-read time to keep the voltage of BL stable before the WLR pulse arrives. Finally, multi-line reading begins, the multi-line word line is activated, and M1 and M3 mirror the total current IBL on the bit lines during multi-line reading. The mirrored current is collected through capacitor C to form the output voltage Vout, representing the calculation result. Since the voltage clamp clamps the BL voltage at approximately 70% of VDD, the BL voltage changes only slightly during multi-line reading.

[0022] Therefore, when the temperature changes, Figure 1 The current in the SRAM transfer transistor of a circuit can change, leading to inaccurate calculation results. As described in the background section, when the temperature increases from low to high, the calculation current in the transfer transistor at traditional process nodes decreases, resulting in a decrease in the output voltage representing the multiplication result. If the temperature change is too large, the calculation result will be incorrect. Conversely, when the temperature increases from low to high, the calculation current in the transfer transistor at advanced process nodes increases, resulting in an increase in the output voltage representing the multiplication result, which will also lead to calculation errors.

[0023] In view of this, the present invention provides a voltage control circuit for controlling the word line voltage of the current-mode SRAM memory for in-memory calculation. This circuit can prevent temperature from adversely affecting the calculation function of the current-mode in-memory calculation circuit, and ensure that the current of the transmission transistor in the SRAM memory cell in calculation mode fluctuates within a small range, so that temperature does not cause significant interference to the calculation. This improves the calculation accuracy of the SRAM memory cell and solves the problem of poor calculation accuracy of SRAM memory cells in the prior art.

[0024] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings: Please see Figure 2 , Figure 2This is a schematic diagram of the voltage control circuit provided by the present invention. It should be noted that the voltage control circuit provided by the present invention is applied to the current-mode in-memory calculation circuit of the SRAM memory cell to prevent temperature from adversely affecting the calculation function of the current-mode in-memory calculation circuit. This ensures that the current of the transmission transistor in the SRAM memory cell in calculation mode fluctuates within a small range, preventing temperature from significantly interfering with the calculation.

[0025] exist Figure 2 In this circuit, the voltage control circuit may include: a current source circuit 10, an operational amplifier 20, and a transmission gate 30; wherein, the operational amplifier 20 is connected as a voltage follower circuit structure.

[0026] Specifically, the current source circuit 10 can be connected to the operational amplifier 20, the operational amplifier 20 can be connected to the transmission gate 30, and the transmission gate 30 can be connected to the right word line of the SRAM memory cell 40. This allows the current source circuit 10 to provide a zero-temperature coefficient current, causing the target transistor to be in the saturation region when the voltage between the gate and source of the target transistor exceeds the threshold voltage. The target transistor refers to the transistor connected to the operational amplifier in the current source circuit. The operational amplifier is then used as the negative feedback circuit in the voltage control circuit. The transmission gate is then used to transmit and isolate the control signal in the voltage control circuit. The voltage control circuit and... Figure 2 The right word line of the leftmost SRAM memory cell is connected, thereby using a voltage control circuit to control the word line voltage.

[0027] It should be noted that transistors exhibit different performance characteristics under different temperature conditions. The current of a MOSFET is closely related to temperature.

[0028] The formula can be used: (1); Determine the current of the MOSFET in the saturation region; where, Indicates the current of the MOSFET in the saturation region. Indicates carrier mobility, Indicates the capacitance per unit area of ​​the oxide layer. Indicates the width-to-length ratio of the channel, Indicates gate-source voltage, Indicates threshold voltage, Indicates channel modulation correction term, Indicates drain-source voltage, This represents the channel length modulation coefficient.

[0029] Specifically, temperature primarily affects carrier mobility. and threshold voltage This affects the current. Carrier mobility has a negative temperature coefficient. As temperature increases, the thermal vibration of the semiconductor lattice intensifies, enhancing the scattering of carriers (electrons or holes) and leading to a decrease in their mobility. This reduces the channel conductivity, causing the current to tend to decrease. Threshold voltage also has a negative temperature coefficient. Increased temperature increases the intrinsic carrier concentration in the semiconductor material, leading to a decrease in the gate voltage (threshold voltage) required to form a conductive channel. GS This means that the effective overdrive voltage increases, and the current tends to increase. At traditional process nodes, the supply voltage is higher, resulting in a larger Vgs - Vth value. The effect of decreased carrier mobility is far stronger than the effect of decreased threshold voltage. Therefore, the overall performance is that the MOSFET saturation current decreases with increasing temperature. However, at advanced process nodes (65nm and below), to reduce power consumption, the supply voltage is significantly reduced, causing the Vgs - Vth value to become very small. This leads to a temperature reversal effect. At this point, even a small change in the threshold voltage Vth has a significant impact on the drive current. As temperature increases, the current-enhancing effect of the decrease in Vth begins to outweigh the weakening effect of the decrease in mobility, ultimately resulting in the MOSFET current increasing with increasing temperature.

[0030] To prevent temperature from adversely affecting the computational function of the current-mode in-memory computing circuit, the voltage control circuit provided by this invention can generate word line control voltage based on the input value of the SRAM memory cell, and control the change of word line voltage when the chip temperature changes. This ensures that the current of the transmission transistor in the SRAM memory cell in computing mode fluctuates within a small range, preventing temperature from causing significant interference to the computation. This improves the computational accuracy of the SRAM memory cell and solves the problem of poor computational accuracy of SRAM memory cells in the prior art.

[0031] As an alternative embodiment, please continue reading Figure 2 ,exist Figure 2 In the SRAM memory cell 40, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor may be included.

[0032] Specifically, the source of the first PMOS transistor can be connected to the power supply terminal, its gate can be connected to the gate of the first NMOS transistor and the drain of the second NMOS transistor, and its drain can be connected to the signal terminal Q; the drain of the second PMOS transistor can be connected to the signal terminal Q, and its source can be grounded; further, the source of the second PMOS transistor can be connected to the power supply terminal, its gate can be connected to the gate of the second NMOS transistor and the drain of the first NMOS transistor, and its drain can be connected to the inverted signal terminal QB; the drain of the second PMOS transistor can be connected to the inverted signal terminal QB, and its source can be grounded; the gate of the fourth MOS transistor can be connected to the left word line of the SRAM memory cell, and its drain can be connected to the signal terminal Q; the gate of the third MOS transistor can be connected to the right word line of the SRAM memory cell, and its drain can be connected to the inverted signal terminal QB; thus, the SRAM memory cell of the present invention is constituted.

[0033] Furthermore, the current source circuit 10 may include an ideal current source, a fifth NMOS transistor, and a sixth NMOS transistor. Among them, the fifth NMOS transistor is the target transistor.

[0034] Specifically, one end of the ideal current source can be connected to the power supply terminal, and the other end can be connected to the drain of the fifth NMOS transistor; the drain of the fifth NMOS transistor can be connected to the non-inverting input terminal of the operational amplifier, the gate can be connected to the drain of the fifth NMOS transistor, and the source can be connected to the drain of the sixth NMOS transistor; the gate of the sixth NMOS transistor can be connected to the power supply terminal, and the source can be grounded. This yields the current source circuit provided by this invention, which provides a zero-temperature coefficient current, causing the target transistor to be in the saturation region when the voltage between the gate and source of the target transistor is greater than the threshold voltage.

[0035] exist Figure 2 In the current source circuit, an ideal current source can provide a current with zero temperature coefficient, which is input to transistors MN5 and MN6. The gate of transistor MN6 is connected to the power supply voltage, and the gate and drain of transistor MN5 are connected together. As long as the voltage between the gate and the source is greater than the threshold voltage, transistor MN5 will be in the saturation region.

[0036] Furthermore, the inverting input terminal of operational amplifier 20 can be connected to the output terminal of operational amplifier, and the output terminal can be connected to the transmission gate, so that the voltage changes of the non-inverting input terminal and the inverting input terminal of operational amplifier are the same; thus, the operational amplifier is configured as a voltage follower structure, which serves as a negative feedback structure; that is, the closed-loop gain of the circuit is 1, and the voltage at the non-inverting input terminal changes accordingly.

[0037] Furthermore, the transmission gate 30 may include a third PMOS transistor, a fourth PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor.

[0038] Specifically, the drain of the third PMOS transistor can be connected to the right word line of the SRAM memory cell, the gate to the enable terminal, and the source to ground; the source of the eighth NMOS transistor can be connected to the drain of the third PMOS transistor, the gate to the reverse enable terminal, and the drain to ground; the drain of the fourth PMOS transistor can be connected to the right word line of the SRAM memory cell, the gate to the reverse enable terminal, and the source to the output terminal of the operational amplifier circuit; the source of the seventh NMOS transistor can be connected to the drain of the fourth PMOS transistor, the gate to the enable terminal, and the drain to the output terminal of the operational amplifier circuit; thus forming two sub-transmission gates, which can respectively deliver control voltages of different voltage levels to the SRAM memory cell.

[0039] Based on this, the voltage control circuit provided by this invention is constructed. The working principle of the voltage control circuit is as follows: When the input of the SRAM memory cell is high, the enable terminal is input with a high level, the inverting enable terminal is input with a low level, the seventh NMOS transistor and the fourth PMOS transistor are turned on, and the eighth NMOS transistor and the third PMOS transistor are turned off; the voltage control circuit inputs a high level to the right word line of the SRAM memory cell. When the input of the SRAM memory cell is low, the enable terminal is input with a low level, the inverting enable terminal is input with a high level, the seventh NMOS transistor and the fourth PMOS transistor are turned off, and the eighth NMOS transistor and the third PMOS transistor are turned on; the voltage control circuit inputs a low level to the right word line of the SRAM memory cell.

[0040] Specifically, in Figure 2 In the process, when the input of the SRAM memory cell is high, en=1, enb=0, at which time MN7 and MP4 are turned on, MN8 and MP3 are turned off, and the high level is input to WLR; when the input is low, en=0, enb=1, at which time MN7 and MP4 are turned off, MN8 and MP3 are turned on, and the low level is input to WLR; thus, the current of the third NMOS transistor can be controlled through WLR.

[0041] Furthermore, since the change in MOSFET current with temperature depends on the trade-off between "threshold voltage change" and "mobility change," which is also related to the process node, the change in current with temperature when using the voltage control circuit provided by this invention to control the word lines of the SRAM memory cell will result in two scenarios. The first scenario is that both the voltage control circuit and the SRAM memory cell are composed of transistors from conventional process nodes, i.e., the MOSFET process node is 65nm or higher.

[0042] As the temperature rises, the carrier mobility of the fifth and sixth NMOS transistors decreases, meaning that the decrease in carrier mobility of the fifth and sixth NMOS transistors dominates this path; the current tends to decrease, so the constant current provided by the ideal current source is used to increase the gate voltage of the fifth NMOS transistor and the voltage at the non-inverting input of the operational amplifier, thereby increasing the voltage of the right word line input to the SRAM memory cell to suppress the decrease in the current of the third NMOS transistor.

[0043] As the temperature decreases, the carrier mobility of the fifth and sixth NMOS transistors increases, meaning that the increased carrier mobility of the fifth and sixth NMOS transistors dominates this path. The current tends to increase, so the constant current provided by the ideal current source is used to reduce the gate voltage of the fifth NMOS transistor and the voltage at the non-inverting input of the operational amplifier, thereby reducing the voltage on the right word line input to the SRAM memory cell and suppressing the increase in current of the third NMOS transistor.

[0044] The second scenario involves voltage control circuits and SRAM memory cells constructed using advanced process node transistors, specifically MOS transistors with a process node below 65nm.

[0045] When the temperature decreases, the threshold voltages of the fifth and sixth NMOS transistors rise, meaning that the increase in the threshold voltages of the fifth and sixth NMOS transistors dominates the path. The current tends to decrease, so the constant current provided by the ideal current source increases the gate voltage of the fifth NMOS transistor and the voltage at the non-inverting input of the operational amplifier, thereby increasing the voltage on the right word line of the SRAM memory cell to suppress the decrease in the current of the third NMOS transistor.

[0046] As the temperature rises, the threshold voltages of the fifth and sixth NMOS transistors decrease, meaning that the decrease in the threshold voltages of the fifth and sixth NMOS transistors dominates the path. The current tends to increase, so the constant current provided by the ideal current source is used to reduce the gate voltage of the fifth NMOS transistor and the voltage at the non-inverting input of the operational amplifier, thereby reducing the voltage on the right word line input to the SRAM memory cell to suppress the increase in current of the third NMOS transistor.

[0047] For details, please refer to Figures 3 to 4 , Figure 3 A schematic diagram illustrating the working principle of the voltage control circuit provided by this invention when cooling down traditional process nodes or heating up advanced process nodes; Figure 4 A schematic diagram illustrating the working principle of the voltage control circuit provided by this invention when heating up traditional process nodes or cooling down advanced process nodes.

[0048] exist Figure 3In a circuit where all transistors are MOSFETs from traditional process nodes, as temperature rises, the current supplied by the current source remains constant, but the carrier mobility of transistors MN5 and MN6 decreases, leading to a dominant decrease in current. To maintain a constant current, Vgs needs to increase, and the gate voltage VG of MN5 needs to rise to accommodate the decreased carrier mobility. The increase in the MN5 gate voltage VG leads to an increase in the voltage at the non-inverting input of the operational amplifier, and the output voltage VH of the operational amplifier follows suit. This increases the gate voltage of the transfer transistor in the SRAM cell, resulting in a decrease in the current change of MN3. Conversely, if all transistors in the circuit are MOSFETs from advanced process nodes, as temperature decreases, the current supplied by the current source remains constant, but the threshold voltage of transistors MN5 and MN6 rises, leading to a dominant decrease in current. To maintain a constant current, Vgs needs to increase, and the gate voltage VG of MN5 needs to rise to accommodate the increased threshold voltage. This increase in the MN5 gate voltage VG leads to an increase in the voltage at the non-inverting input of the operational amplifier, and the output voltage VH of the operational amplifier follows suit. This increases the gate voltage of the transfer transistor in the SRAM cell, resulting in a decrease in the current change of MN3. Figure 4 In this circuit, if all transistors are MOSFETs from a traditional process node, the current supplied by the current source remains constant as the temperature decreases. However, the carrier mobility of transistors MN5 and MN6 increases, leading to a dominant increase in current. To maintain a constant current, Vgs needs to decrease, and the gate voltage VG of MN5 needs to decrease to accommodate the increased carrier mobility. The decrease in the gate voltage VG of MN5 causes a decrease in the voltage at the non-inverting input of the operational amplifier, which in turn causes a decrease in the output voltage VH of the operational amplifier. This decrease in the gate voltage of the transfer transistor in the SRAM cell reduces the change in current of MN3.

[0049] If the transistors in the circuit are all MOSFETs from advanced process nodes, when the temperature rises, the current supplied by the current source remains constant. The threshold voltages of transistors MN5 and MN6 decrease, dominating the trend, and the current tends to increase. To maintain a constant current, Vgs needs to decrease, and the gate voltage VG of MN5 decreases to accommodate the threshold voltage drop. The decrease in the gate voltage VG of MN5 leads to a decrease in the voltage at the non-inverting input of the operational amplifier, causing the output voltage VH of the operational amplifier to decrease accordingly. This, in turn, lowers the gate voltage of the transfer transistor in the SRAM cell, resulting in a smaller change in the current of MN3.

[0050] It should be noted that when the input signal of an SRAM memory cell is multiplied by the stored value, current flows through the SRAM transfer transistor near QB only when WLR=1, the stored value Q is 1, and QB is 0. In other cases, no calculation current is generated. To avoid calculation errors caused by temperature, we need to focus on word line voltage control in this situation. In the voltage control circuit provided by this invention, MN2 and MN6 are in the same state, with their gates connected to a high level and their sources grounded. Because the operational amplifier is configured as a voltage follower, the voltage changes at the non-inverting and inverting inputs are the same, so the gate voltage changes of MN3 and MN5 are also the same. At this time, the structures of MN2 and MN3 are symmetrical with those of MN5 and MN6, and the currents of MN5 and MN6 remain unchanged. Therefore, the transfer transistor current in the SRAM memory cell in calculation mode is almost constant. When WLR=0, MN3 is turned off, and no calculation current is generated in the transfer transistor. When WLR=1, the stored value Q is 0, and QB is 1, there is no potential difference, and no calculation current is generated in MN3.

[0051] Based on this, the present invention provides a voltage control circuit that can prevent temperature from adversely affecting the calculation function of the current-mode in-memory calculation circuit, so that the current of the transmission tube in the SRAM memory cell in calculation mode fluctuates within a small range, and the temperature will not cause significant interference to the calculation circuit, thereby improving the calculation accuracy of the SRAM memory cell and solving the problem of poor calculation accuracy of SRAM memory cells in the prior art.

[0052] Furthermore, to more fully illustrate the beneficial effects of the present invention, examples of these effects are provided below. Please refer to [link / reference needed]. Figure 5 , Figure 5 This diagram illustrates the control effect of the MOS transistor in the voltage control circuit provided by this invention on the SRAM memory cell at the 28nm process node. It should be noted that... Figure 5 The diagram shows the changes in current and voltage curves as the temperature rises under advanced process nodes, corresponding to the increase in MOSFET current.

[0053] exist Figure 5In the diagram, the curve corresponding to current 2 represents the change in MOSFET output current with temperature when the transistor gate voltage remains constant without voltage control circuit control. From the current 2 curve, it is clear that as the temperature changes from -45℃ to 125℃, the current changes from 0.49uA at -45℃ to 2.53uA at 125℃. The curve corresponding to the input voltage represents the change in voltage at the non-inverting input terminal of the op-amp with temperature, the curve corresponding to the output voltage represents the change in voltage at the output terminal of the op-amp with temperature, and the curve corresponding to current 1 represents the change in MOSFET current with temperature when the voltage control circuit provided in this invention is used for word line voltage control. The operation of the word line control circuit is consistent with the analysis described above. In other words, as the temperature rises, the voltage at the non-inverting input of the op-amp decreases, which in turn lowers the voltages at the inverting input and output. The op-amp output is connected to the gate of transistor MN3 through a transmission gate. As the gate voltage of MN3 decreases, the current increase in MN3 slows down. The curve corresponding to current 1 shows a very small change in current as the temperature changes from -45℃ to 125℃, with the current changing from 0.95uA at -45℃ to 1.07uA at 125℃. The simulation results demonstrate that the word line voltage control circuit is significantly effective in controlling the MOSFET's resistance to temperature fluctuations, making the impact of temperature on the current-based memory calculation results smaller and improving the circuit's ability to withstand temperature fluctuations.

[0054] Based on this, the voltage control circuit provided by the present invention can generate word line control voltage according to the input value of the memory, and adjust the word line voltage change through negative feedback when the chip temperature changes, so that the current of the transmission tube in the SRAM memory cell in the computing mode remains basically unchanged, suppressing the interference of temperature change on the calculation; improving the calculation accuracy of the SRAM memory cell and solving the problem of poor calculation accuracy of the SRAM memory cell in the prior art.

[0055] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0056] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A voltage control circuit, characterized in that, include: Current source circuits, operational amplifiers, and transmission gates; The current source circuit is connected to the operational amplifier, the operational amplifier is connected to the transmission gate, and the transmission gate is connected to the right word line of the SRAM memory cell. The current source circuit is used to provide a zero-temperature coefficient current, so that the target transistor is in the saturation region when the voltage between the gate and source of the target transistor is greater than the threshold voltage. The target transistor refers to the transistor connected to the operational amplifier in the current source circuit; The operational amplifier is connected as a voltage follower circuit structure for use in the negative feedback circuit of the voltage control circuit. The transmission gate is used to transmit and isolate control signals in the voltage control circuit.

2. The voltage control circuit as described in claim 1, characterized in that, The current source circuit includes an ideal current source, a fifth NMOS transistor, and a sixth NMOS transistor; One end of the ideal current source is connected to the power supply terminal, and the other end is connected to the drain of the fifth NMOS transistor; the drain of the fifth NMOS transistor is connected to the non-inverting input terminal of the operational amplifier, the gate is connected to the drain of the fifth NMOS transistor, and the source is connected to the drain of the sixth NMOS transistor; the gate of the sixth NMOS transistor is connected to the power supply terminal, and the source is grounded.

3. The voltage control circuit as described in claim 2, characterized in that, The inverting input terminal of the operational amplifier is connected to the output terminal of the operational amplifier, and the output terminal is connected to the transmission gate.

4. The voltage control circuit as described in claim 3, characterized in that, The transmission gate includes a third PMOS transistor, a fourth PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; The drain of the third PMOS transistor is connected to the right word line of the SRAM memory cell, the gate is connected to the enable terminal, and the source is grounded; the source of the eighth NMOS transistor is connected to the drain of the third PMOS transistor, the gate is connected to the reverse enable terminal, and the drain is grounded. The drain of the fourth PMOS transistor is connected to the right word line of the SRAM memory cell, the gate is connected to the reverse enable terminal, and the source is connected to the output terminal of the operational amplifier circuit; the source of the seventh NMOS transistor is connected to the drain of the fourth PMOS transistor, the gate is connected to the enable terminal, and the drain is connected to the output terminal of the operational amplifier circuit.

5. The voltage control circuit as described in claim 4, characterized in that, When the input of the SRAM memory cell is high, the enable terminal inputs a high level, the inverting enable terminal inputs a low level, the seventh NMOS transistor and the fourth PMOS transistor are turned on, and the eighth NMOS transistor and the third PMOS transistor are turned off; the voltage control circuit inputs a high level to the right word line of the SRAM memory cell.

6. The voltage control circuit as described in claim 4, characterized in that, When the input of the SRAM memory cell is low, the enable terminal inputs a low level, the inverting enable terminal inputs a high level, the seventh NMOS transistor and the fourth PMOS transistor are turned off, and the eighth NMOS transistor and the third PMOS transistor are turned on; the voltage control circuit inputs a low level to the right word line of the SRAM memory cell.

7. The voltage control circuit as described in claim 4, characterized in that, When the voltage control circuit and SRAM memory cell use conventional process node transistors and the temperature rises, the carrier mobility of the fifth NMOS transistor and the sixth NMOS transistor decreases, and the current tends to decrease. Therefore, the gate voltage of the fifth NMOS transistor and the voltage of the non-inverting input terminal of the operational amplifier are increased by using a constant current provided by an ideal current source, so as to increase the voltage of the right word line input to the SRAM memory cell and suppress the decrease of the current of the third NMOS transistor.

8. The voltage control circuit as described in claim 4, characterized in that, When the voltage control circuit and SRAM memory cell use conventional process node transistors and the temperature decreases, the carrier mobility of the fifth NMOS transistor and the sixth NMOS transistor increases, and the current tends to increase. Then, the constant current provided by the ideal current source is used to reduce the gate voltage of the fifth NMOS transistor and the voltage of the non-inverting input terminal of the operational amplifier, so as to reduce the voltage of the right word line input to the SRAM memory cell and suppress the increase of the current of the third NMOS transistor.

9. The voltage control circuit as described in claim 4, characterized in that, When the voltage control circuit and SRAM memory cell use advanced process node transistors and the temperature decreases, the threshold voltages of the fifth NMOS transistor and the sixth NMOS transistor rise, and the current tends to decrease. Then, the gate voltage of the fifth NMOS transistor and the voltage of the non-inverting input terminal of the operational amplifier are increased by using a constant current provided by an ideal current source, so as to increase the voltage of the right word line input to the SRAM memory cell and suppress the decrease of the current of the third NMOS transistor.

10. The voltage control circuit as described in claim 4, characterized in that, When the voltage control circuit and SRAM memory cell use advanced process node transistors and the temperature rises, the threshold voltages of the fifth NMOS transistor and the sixth NMOS transistor decrease, and the current tends to increase. Then, the constant current provided by the ideal current source is used to reduce the gate voltage of the fifth NMOS transistor and the voltage at the non-inverting input of the operational amplifier, so as to reduce the voltage of the right word line input to the SRAM memory cell and suppress the increase of the current of the third NMOS transistor.

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