Inverter parallel networking method and device, computer equipment and storage medium

Abstract

The invention discloses a parallel networking method and device for an inverter, computer equipment and a storage medium, and the method comprises the steps: triggering a parallel matching process when a parallel number setting instruction issued by external equipment is received, or the access of a new inverter and the conflict of parallel numbers are detected; the inverter broadcasts a matching message including a parallel operation number, a random judgment value, a parallel operation number setting flag bit and an updating state flag bit on the bus; when the number conflict occurs, determining a way-giving inverter based on the random judgment value and the flag bit; and the way-giving inverter generates a candidate parallel operation number according to a candidate number selection rule, performs occupation detection through bus interaction, and completes parallel operation number updating and broadcasting after confirming that the candidate parallel operation number is not occupied until the conflict is eliminated. Therefore, automatic distribution and unique convergence of parallel operation numbers are realized, manual configuration and shutdown debugging are reduced, online equipment increase and decrease and smooth reconstruction are supported, and networking reliability and maintainability are improved.

Description

Inverter parallel grid connection methods, devices, computer equipment and storage media Technical Field

[0001] This invention relates to the fields of power electronics and communication technology, and in particular to a method, apparatus, computer equipment, and storage medium for parallel networking of inverters. Background Technology

[0002] In existing inverter parallel systems, to achieve parallel operation and centralized management of multiple inverters, it is typically necessary to distinguish each inverter node on the bus network and complete command routing and parameter synchronization based on node identifiers. A more common engineering practice is to pre-set a fixed parallel operation number (or slave address) for each inverter during the factory or field installation and commissioning phase, through methods such as DIP switches, programming, or host computer configuration. The master node then sends control commands to the target node on the bus based on this number. When unified settings are required for multiple inverters, synchronization commands can be broadcast, and each slave node responds accordingly.

[0003] This method of fixed numbering and manual configuration is simple to implement, easy for engineers to understand, and easy to implement quickly within existing communication protocol frameworks, thus it is widely used in most parallel application scenarios. However, this method is highly dependent on manual configuration, resulting in high system deployment and maintenance costs; when adding or replacing equipment, or when on-site misconfiguration leads to duplicate parallel numbers, it is prone to addressing confusion, response conflicts, or network instability and convergence problems, making it difficult to support online hot-swapping and smooth expansion.

[0004] Therefore, how to achieve automatic networking of inverter nodes in a parallel system, so that the parallel numbering can be dynamically allocated and conflicts can be effectively avoided, has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] Based on this, it is necessary to provide a method, apparatus, computer equipment, and storage medium for parallel networking of inverters to address the above-mentioned technical problems. This method has the advantages of enabling automatic networking of inverter nodes in a parallel system, dynamically allocating parallel numbers, and effectively avoiding conflicts.

[0006] A method for parallel networking of inverters is disclosed, the method being applied to a parallel system comprising inverters, including a master node inverter and at least one slave node inverter, the master node inverter and the slave node inverter being connected via a bus communication connection. The method includes: triggering a parallel matching process upon receiving a parallel number setting command from an external device or detecting a new inverter access event or a parallel number conflict event; in the parallel matching process, the inverters broadcast a matching message on the bus, the matching message containing a parallel number, a random decision value, and a status flag, the status flag including a parallel number setting flag and an update flag. Status flag bit; when the parallel operation numbers of the first inverter and the second inverter conflict, based on the random decision value, the parallel operation number setting flag bit, and the update status flag bit, the yielding inverter is determined between the first inverter and the second inverter; the yielding inverter generates a candidate parallel operation number according to a preset candidate number selection rule, and performs occupancy detection through bus interaction to determine that the candidate parallel operation number is not occupied by other inverters; when it is determined that it is not occupied by other inverters, the candidate parallel operation number is set as the parallel operation number of the yielding inverter and the update information is broadcast until there is no parallel operation number conflict, the parallel matching process is completed, and the parallel system after networking is obtained.

[0007] Optionally, after completing the parallel matching process and obtaining the networked parallel system, the method further includes: each inverter performing validity verification on its stored parallel operation parameters to obtain verification results; determining candidate synchronization source nodes with synchronization qualifications based on the verification results; determining a synchronization source node based on the parallel number among the candidate synchronization source nodes; broadcasting the parallel operation parameters on the bus by the synchronization source node; and receiving the parallel operation parameters and updating the parallel operation parameters stored locally by other inverter nodes besides the synchronization source node, so as to achieve consistency of parallel operation parameters in the networked parallel system.

[0008] Optionally, after completing the parallel matching process and obtaining the networked parallel system, the method further includes: the master node inverter receiving a control command sent by an external device, the control command carrying a target address, the control command being a read command or a write command; when the target address is a first preset address, the master node inverter executing the control command and returning a response to the external device; when the target address is not the first preset address, the master node inverter determining the target parallel number based on the target address, encapsulating the control command into a bus message and sending it on the bus; the slave node inverter corresponding to the target parallel number receiving the bus message and generating a response message, and sending the response message to the master node inverter via the bus; the master node inverter converting the response message into a response recognizable by the external device and returning it.

[0009] Optionally, the step of encapsulating the control command into a bus message and sending it on the bus includes: determining the frame type, data source, sender parallel number, and target parallel number based on the control command, wherein the frame type is used to distinguish between a sending message and a response message; generating an initial bus message, and writing the frame type, the data source, the sender parallel number, and the target parallel number into the extended identifier of the initial bus message to form the bus message and send it to the bus.

[0010] Optionally, the master node inverter determines the target parallel inverter number based on the target address, encapsulates the control command into a bus message, and sends it on the bus, including: when the control command is the write command, the master node inverter determines whether the write command is synchronous or asynchronous based on the register address corresponding to the write command; if the write command is asynchronous, the slave node inverter corresponding to the target parallel inverter number is a single one; if the write command is synchronous, the target parallel inverter number is a broadcast value, and the corresponding slave node inverters are all the slave node inverters; when the write command is asynchronous, the bus message corresponding to the write command is sent to the single slave node inverter corresponding to the target parallel inverter number; when the write command is synchronous, the bus message corresponding to the write command is sent to all the slave node inverters.

[0011] Optionally, when the control instruction is the write instruction and the write instruction is of the synchronous type, sending the response message to the master node inverter via the bus includes: determining a delay transmission duration for each slave node inverter based on the parallel number of the slave node inverter; and sending the response message to the master node inverter via the bus after the delay transmission duration is reached.

[0012] Optionally, determining the yielding inverter among the first inverter and the second inverter based on the random decision value, the parallel number setting flag, and the update status flag includes: determining the first inverter as the yielding inverter when the parallel number setting flag of the second inverter is a first preset value and the parallel number setting flag of the first inverter is not a first preset value; and determining the second inverter as the yielding inverter when the parallel number setting flag of the first inverter is a first preset value and the parallel number setting flag of the second inverter is not a first preset value. The inverter with the parallel number setting flag is the same for the first inverter and the second inverter, and the update status flag of the first inverter is different from the update status flag of the second inverter. The inverter with the update status flag of the second inverter is determined to be the yielding inverter. When the parallel number setting flag is the same for the first inverter and the second inverter, and the update status flag of the first inverter is the same as the update status flag of the second inverter, the yielding inverter is determined based on the random decision value of the first inverter and the second inverter.

[0013] A parallel networking device for inverters is provided, the device being applied to a parallel system, the parallel system including inverters, each inverter including a master node inverter and at least one slave node inverter, the master node inverter and the slave node inverter being connected via a bus for communication. The device includes: a trigger module, used to trigger a parallel matching process upon receiving a parallel number setting command from an external device or detecting a new inverter access event or a parallel number conflict event; and a broadcast module, used to broadcast a matching message on the bus by the inverter during the parallel matching process, the matching message including a parallel number, a random decision value, and a status flag, the status flag including a parallel number setting flag and an update status flag. The system comprises: a decision module, used to determine the yielding inverter from the first inverter and the second inverter when the parallel operation numbers of the first inverter and the second inverter conflict, based on the random decision value, the parallel operation number setting flag bit, and the update status flag bit; a generation module, used for the yielding inverter to generate a candidate parallel operation number according to a preset candidate number selection rule, and to perform occupancy detection through bus interaction to determine that the candidate parallel operation number is not occupied by other inverters; and a setting module, used to set the candidate parallel operation number as the parallel operation number of the yielding inverter and broadcast update information when it is determined that it is not occupied by other inverters, until there is no parallel operation number conflict, thus completing the parallel matching process and obtaining the parallel system after networking.

[0014] A computer device includes a memory, a processor, and computer-readable instructions stored in the memory and executable on the processor, wherein the processor, when executing the computer-readable instructions, implements the above-described method for parallel networking of an inverter.

[0015] A readable storage medium storing computer-readable instructions, which, when executed by a processor, implement the above-described method for parallel networking of inverters.

[0016] The aforementioned inverter parallel networking method, apparatus, computer equipment, and storage medium trigger a parallel matching process upon receiving a parallel number setting command from an external device or detecting a new inverter access event or a parallel number conflict event. In this parallel matching process, the inverter broadcasts a matching message on the bus. The matching message includes a parallel number, a random decision value, and a status flag, including a parallel number setting flag and an update status flag. When the parallel numbers of the first inverter and the second inverter conflict, the random decision value is used to determine the parallel matching process. The decision value, the parallel number setting flag, and the update status flag are used to determine the yielding inverter among the first and second inverters. The yielding inverter generates a candidate parallel number according to a preset candidate number selection rule and performs occupancy detection through bus interaction to determine if the candidate parallel number is occupied by other inverters. When it is determined that it is not occupied by other inverters, the candidate parallel number is set as the parallel number of the yielding inverter and the update information is broadcast until there is no parallel number conflict, thus completing the parallel matching process and obtaining the networked parallel system. By triggering the matching process when a new node access or parallel number conflict is detected, the yielding inverter is determined using a matching message containing a random decision value and a setting / update flag. Combined with candidate number generation and occupancy detection, conflict-free number allocation is completed, enabling the parallel system to automatically converge to a network state with unique numbers. This reduces manual configuration and downtime debugging costs, supports online addition and removal of equipment and smooth reconfiguration, and improves the reliability and maintainability of the parallel network. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 is a flowchart illustrating a parallel networking method for inverters according to an embodiment of the present invention; Figure 2 is a structural diagram illustrating a parallel system according to an embodiment of the present invention; Figure 3 is a flowchart illustrating a master node routing method according to an embodiment of the present invention; Figure 4 is a flowchart illustrating a response data processing method according to an embodiment of the present invention; Figure 5 is a flowchart illustrating a frame transmission processing method according to an embodiment of the present invention; Figure 6 is a structural diagram illustrating a parallel networking device for inverters according to an embodiment of the present invention; Figure 7 is a schematic diagram illustrating a computer device according to an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] In one embodiment, as shown in FIG1, a method for parallel networking of inverters is provided. The method is applied to a parallel system, the parallel system including inverters, the inverters including a master node inverter and at least one slave node inverter, the master node inverter and the slave node inverter are connected by bus communication, including the following steps: 101. When receiving a parallel number setting instruction issued by an external device or detecting a new inverter access event or a parallel number conflict event, a parallel matching process is triggered.

[0021] In this embodiment of the invention, the above-mentioned parallel system can be further illustrated by a structural diagram of the parallel system shown in Figure 2. In Figure 2, the leftmost box represents the host computer (i.e., the external device). The host computer plays the role of monitoring and control entry point, issuing control commands or data reading commands to the outside. The messages are organized in Modbus format and include information such as the target parallel number, function code, register address, and read / write data. The host computer also receives response messages from the field, which are used to display the status, record data, or continue to issue subsequent commands.

[0022] The box on the right of the host computer represents master node inverter 1. Master node inverter 1 maintains Modbus communication with the host computer on one end, and connects to the bus on the other end to interconnect with other parallel inverters via the bus, acting as a gateway and forwarding node. After receiving a request from the host computer, master node inverter 1 can first read the target parallel inverter number carried in the request and perform routing judgment: if the target parallel inverter number points to itself, or the target address is a broadcast address, master node inverter 1 completes the corresponding register read / write or parameter update on itself and directly returns the result to the host computer; if the target parallel inverter number points to another inverter, master node inverter 1 converts the host computer request into a message that can be transmitted on the bus side and broadcasts it on the bus, while entering a waiting state to receive data returned by the target inverter, and then organizes the returned result into a response message that can be recognized by the host computer and sends it back.

[0023] The two horizontal lines running through the entire diagram to the right of master node inverter 1 correspond to the physical bus links. In the diagram, the two differential lines (i.e., the bus) are identified by H and L, with H corresponding to the high line and L to the low line. Multiple inverters are connected in parallel on the same pair of differential lines to form a multi-point communication channel. The arrow pointing from master node inverter 1 to the bus on the right indicates that master node inverter 1 is sending a broadcast message to the bus; the arrow returning from the right to master node inverter 1 indicates that a parallel inverter is sending its processing result back to the bus, which is then received by master node inverter 1.

[0024] Parallel inverters 2, 3, 4, and 5 on the right represent slave node inverters connected to the same bus. Each slave node inverter has its own local parallel number and message parsing capability, continuously listening to bus messages. Whenever a slave node inverter receives a matching message, it first checks whether the target parallel number or broadcast address carried in the message meets the reception conditions: if the target parallel number is equal to the local parallel number, it enters the processing flow; if the target address is a broadcast address, it also enters the processing flow; if the target parallel number is inconsistent with the local number and is not a broadcast address, it remains silent to reduce bus load. After entering the processing flow, the slave node inverter completes register read / write, parameter setting, or status reporting according to the message content, and sends the execution result back through the bus. The lines and arrows in the diagram from each parallel inverter to the bus and back to master node inverter 1 are used to express the sending path of the return message.

[0025] The text surrounding the master node inverter 1 and each parallel inverter in the diagram corresponds to two key actions: the master node inverter 1 is responsible for "responding locally or broadcasting and forwarding after determining the target address and waiting for a reply", and the slave node inverter is responsible for "determining the target parallel number or broadcast address and deciding whether to receive or ignore it". These two actions work together so that the host computer only needs to send a Modbus request to the master node inverter 1 to indirectly access any parallel inverter on the bus, and in the broadcast setting scenario, multiple parallel inverters can receive the same instruction together.

[0026] Specifically, the purpose of triggering the parallel matching process is to limit the reallocation of parallel connection numbers to necessary moments, ensuring that the parallel network maintains low interference and low load during stable operation, only entering a short-cycle convergence process when the topology or numbering changes. Triggering sources include parallel connection number setting commands issued by external devices, as well as new inverter access events and parallel connection number conflict events generated on the field side. External devices provide a centralized management entry point, facilitating manual planning or correction of parallel connection numbers during maintenance; field-side events cover unattended scenarios such as hot-swapping, power-on restarts, and line restoration, ensuring the parallel network has self-healing capabilities.

[0027] Parallel number setting instructions are used to express the intention to set or modify the parallel number of a specific inverter. These instructions can be forwarded from the master node inverter to the bus side and executed by the target inverter. The instructions typically include the target parallel number, the write register address, and the write value. The write value represents the new parallel number or related configuration parameters. For example, when an external device needs to adjust the parallel number of a slave node inverter to a preset value, it can send a write instruction. The master node inverter resolves and routes the instruction, forwards it to the bus, and the target inverter completes the write and returns the execution result. Alternatively, during the commissioning phase, when it is necessary to limit the range of automatically assigned parallel numbers, parameters such as the allowed range, reserved numbers, or automatic allocation switches can be written to the configuration area of ​​each inverter, ensuring that subsequent number allocation only occurs within the allowed range.

[0028] The "New Inverter Joining Event" describes the occurrence of a new node in a parallel network. This event can be triggered actively by the newly joined inverter or passively identified by existing inverters while listening to bus messages. Common identification criteria include changes in bus message behavior, such as the appearance of a previously unseen matching message source on the bus, or the emergence of a new node declaration message cycle; changes in link activity status can also be included, such as the bus transitioning from prolonged idle to continuous activity. For example, after a newly joined inverter powers on, it begins broadcasting a matching message with an initial parallel number and a random decision value. Any existing inverter receiving this message can determine that a new node has joined, thus entering the matching phase to jointly complete the numbering convergence. Another scenario is when an inverter experiences a power outage and then power-on, re-participating in the matching message broadcast; this is also considered a joining event and triggers the convergence process.

[0029] Parallel number conflict events describe situations where duplicate parallel numbers exist within a parallel network. Conflicts can be directly detected during matching message exchanges or indirectly inferred through service messages during stable operation. Direct detection involves comparing the sender's parallel number carried in the matching message with the local parallel number; a match indicates a conflict. Indirect inference involves observing abnormal service interactions, such as multiple responses to a request corresponding to the same target parallel number, or the master node inverter receiving return messages from different sources but identified as having the same parallel number. For example, if two inverters have the same default parallel number and are simultaneously connected to the bus, they can detect the duplicate number and trigger a conflict upon receiving each other's matching messages. Another example is if an external device writes an already occupied value as the parallel number for one inverter, causing the target inverter to communicate with external devices using the new number. Other inverters, upon resolving the duplicate number, will trigger a conflict and enter a repair phase.

[0030] The parallel matching process is used to drive the entire network into the numbering convergence mode after the triggering conditions are met. Typical actions include matching message broadcasting, conflict detection, yielding node determination, candidate number generation and occupancy detection, number update and update information broadcasting, until no duplicate parallel numbers appear in the parallel network.

[0031] 102. In the parallel matching process, the inverter broadcasts a matching message on the bus.

[0032] In this embodiment of the invention, the matching message is used to publish local parallel access number occupancy information and decision information within the parallel network, leveraging the broadcast characteristics of the bus to achieve mutual discovery and status alignment between nodes. After the matching phase begins, the inverter (which can be either a master node inverter or a slave node inverter) sends the matching message to the bus. The message is received and parsed by other inverters connected to the same bus, thereby forming a shared understanding of the parallel access number occupancy status and providing a basis for subsequent conflict detection and yield node determination. The matching message can be a 32-bit random number matching instruction, containing the parallel access number, a random decision value, and a status flag. The status flag consists of a parallel access number setting flag and an update status flag.

[0033] The random decision value is used to break symmetry when both conflicting parties lack external authority and update their states consistently, preventing oscillations caused by simultaneous number updates from both sides. The random decision value can be generated using a pre-defined bit-width unsigned number, such as a 32-bit unsigned random number. This value is generated by the inverter control unit upon entering the matching phase using a hardware random source or pseudo-random algorithm and remains unchanged within a matching cycle until matching ends or a new matching cycle is triggered, at which point a new random decision value is generated. The source of the random decision value can include timer counts, analog-to-digital conversion noise samples, power-on jitter, register readings, etc., as seeds to improve the difference in generated values ​​between different inverters. For example, after detecting an access event, the inverter enters the matching phase, immediately reads the current count of the microcontroller's timer, and superimposes a sample result from the analog-to-digital conversion of an unconnected channel as a random seed. A 32-bit random decision value is obtained through a linear congruential or shift register algorithm, and then written into the matching message and broadcast.

[0034] The parallel operation number setting flag indicates that the parallel operation number originates from an externally configured attribute, thus reflecting the authority of external management during conflict resolution. The parallel operation number setting flag can be implemented using one or more bits. A valid state indicates that the current parallel operation number was obtained by an external device through configuration writing or command setting, while an invalid state indicates that the current parallel operation number was generated by an automatic allocation process or is in a default initial state. The timing of setting the parallel operation number setting flag can be linked to the external device's action of writing the parallel operation number. For example, after the inverter receives a parallel operation number setting command and completes the writing, it sets the parallel operation number setting flag to a valid state and carries this flag in subsequent matching messages. The timing of clearing the parallel operation number setting flag can be associated with factory reset, automatic reallocation, or maintenance commands to reflect that the parallel operation number no longer has an externally configured attribute. For instance, if maintenance personnel change the parallel operation number of an inverter to a specified value through an external device, and the inverter successfully writes the value, it sets the parallel operation number setting flag to valid. In the event of a conflict, this flag will be kept unchanged, prompting other nodes to give way.

[0035] The update status flag indicates whether the inverter is currently in the parallel number update process. This ensures that only one inverter in the parallel network is allowed to perform the update action when a conflict occurs, reducing repeated conflicts caused by simultaneous updates from both sides. The update status flag can be implemented using a single bit. A valid status indicates that the inverter has entered the candidate number search, occupancy detection, or number switching process, while an invalid status indicates that the inverter is in stable occupancy or has not yet started updating. The update status flag can be set to be set when it is determined that the inverter needs to yield and is preparing to start candidate number generation. The flag can be cleared after candidate number occupancy detection is completed, the switch is successful, and the update information has been broadcast. For example, after an inverter detects a parallel number conflict and is determined to be the yielding node, it immediately sets the update status flag to valid and starts incrementing the candidate parallel number generation. At the same time, it carries the valid update status flag with each broadcast matching message, allowing other inverters to recognize that the current node is updating, thereby avoiding repeated adjudication and repeated updates for the same conflict.

[0036] 103. When the parallel operation numbers of the first inverter and the second inverter conflict, the give-way inverter is determined between the first inverter and the second inverter based on the random decision value, the parallel operation number setting flag bit and the update status flag bit.

[0037] In this embodiment of the invention, when a parallel inverter number conflict occurs, one inverter needs to be designated as the yielding inverter to perform subsequent parallel inverter number adjustment and re-occupancy detection. The other inverter retains its current parallel inverter number to ensure that the parallel network can gradually converge in a deterministic manner and avoid repeated oscillations. The determination of the yielding inverter is based on the random decision value carried in the matching message, the parallel inverter number setting flag, and the update status flag. These three pieces of information are used to reflect the authority of the external setting, to reflect whether the current state constraint is in the number update process, and to provide a symmetry-breaking decision basis when there is a lack of state differences.

[0038] The parallel connection number setting flag reflects whether the parallel connection number originates from an external device's explicit setting. When one of the conflicting parties has an externally set number, the adjudication result tends to keep the externally set parallel connection number unchanged, thereby reducing the probability of the operation and maintenance configuration being overridden by the automatic allocation mechanism and improving the consistency of network management. The update status flag reflects whether one of the conflicting parties has entered the number update process. When one party has entered the update process, the adjudication result allows that party to continue completing the number update and prompts the other party to wait, to avoid repeated conflicts caused by both parties entering the update process simultaneously. The random adjudication value provides a basis for breaking the asymmetry when the conflicting parties lack external setting differences and their update statuses are consistent, making the adjudication result a unique choice between the conflicting parties and promoting the smooth progress of the parallel connection number adjustment to the next stage.

[0039] Through the above methods, conflict resolution can maintain a consistent convergence direction under different conflict causes: external setting priority ensures configuration stability, update state constraints ensure process stability, and random resolution ensures unique results, thus providing a clear execution entity for subsequent candidate parallel machine number generation and occupancy detection.

[0040] 104. The give-way inverter generates candidate parallel operation numbers according to the preset candidate number selection rules, and performs occupancy detection through bus interaction to determine whether the candidate parallel operation number is occupied by other inverters.

[0041] In this embodiment of the invention, after the give-off inverter is determined, the parallel operation number reselection stage begins. Candidate parallel operation numbers are generated using candidate number selection rules, and occupancy detection is completed via bus interaction until an unoccupied candidate parallel operation number is found. The candidate number selection rules limit the search space and search method for candidate parallel operation numbers, avoiding disordered attempts over an excessively large range that would cause excessively long matching times, while ensuring rapid convergence in scenarios where the scale of the parallel network is known or controlled. The candidate number selection rules can pre-configure a fixed number range, which can be a continuous integer interval. For example, the allowed parallel operation numbers can be limited to between a first preset value and a sixth preset value. The upper limit of the range can be determined by the planned number of parallel operation units, product specifications, or parameters issued by external devices.

[0042] Candidate parallel inverter numbers can be generated using a cyclic increment method. Starting from the current parallel inverter number, the number increments by a step size to obtain the next candidate parallel inverter number. When the increment exceeds the upper limit of the fixed number range, it loops back to the lower limit of the fixed number range and continues incrementing until one or more cycles are completed. To avoid duplicate conflicts caused by multiple yielding inverters attempting to pass in the same sequence at the same time, the starting point of the cyclic increment can be chosen to be the current parallel inverter number plus one, or the starting point can be offset by combining a random decision value, so that the attempt sequences of different yielding inverters are different. For example, if the fixed number range is one to six, and the current parallel inverter number is two, the candidate parallel inverter numbers can be tried in the order of three, four, five, six, one, two; if the current parallel inverter number is six, the candidate parallel inverter numbers can be tried in the order of one, two, three, four, five, six.

[0043] Occupancy detection is used to determine whether a candidate parallel connection number is already in use by another inverter in the parallel network. Occupancy detection is implemented based on a bus broadcast mechanism. The yielding inverter broadcasts a matching message carrying the candidate parallel connection number on the bus for each candidate parallel connection number and listens for matching messages or conflict warnings returned by the bus within a preset detection window. The preset detection window can be a fixed duration to cover bus arbitration delays, message propagation, and processing time by other inverters. If a matching message carrying the same parallel connection number is received from another inverter within the preset detection window, it is determined that the candidate parallel connection number is already in use. The candidate parallel connection number generation process continues to generate the next candidate parallel connection number and initiates occupancy detection again. If no matching message carrying the same parallel connection number is received within the preset detection window, it is determined that the candidate parallel connection number is not in use and is identified as an allocatable parallel connection number. To improve the reliability of occupancy detection, occupancy detection can adopt repeated broadcasting and multiple listening methods. For example, multiple matching messages can be broadcast continuously for the same candidate parallel number. As long as the same parallel number message is detected in any listening window, it is determined to be occupied. Only when the same parallel number message is not detected in all listening windows is it determined to be idle.

[0044] By generating candidate parallel operation numbers in a cyclic increment and combining them with bus broadcast to complete real-time occupancy detection, the power inverter can quickly locate unoccupied parallel operation numbers within a fixed number range. This avoids the deployment complexity and maintenance costs caused by manual dialing or pre-programming of fixed numbers, while providing a definite number update result for the stable convergence of the subsequent parallel operation network.

[0045] 105. When it is determined that the candidate paralleling number is not occupied by other inverters, the paralleling number of the candidate inverter is set to the paralleling number of the yielding inverter and the update information is broadcast until there is no paralleling number conflict, the paralleling matching process is completed and the paralleling system after networking is obtained.

[0046] In this embodiment of the invention, after the occupancy detection confirms that the candidate parallel operation number is not occupied by other inverters, the yielding inverter writes the candidate parallel operation number into its own parallel operation number parameter, thus switching the parallel operation number declared externally by the inverter from the original conflict number to the new number. The writing of the parallel operation number can be synchronously updated to the volatile memory area for use during operation, or it can be further written to the non-volatile memory area to maintain a consistent numbering configuration after a power outage and restart. After the writing is completed, the parallel operation number carried in subsequent matching messages reflects the new number.

[0047] After the parallel inverter number is switched, the update information is broadcast via the bus to inform other inverters in the parallel network that their local numbers have changed, ensuring that each node's understanding of the parallel inverter number occupancy and the parallel topology is synchronized in a timely manner. The update information can be implemented using the same carrier as the matching message; that is, the yielding inverter rebroadcasts the matching message with the new parallel inverter number and indicates in the status flag that the update process is complete or the update status has been released, facilitating other inverters to update their locally maintained number tables or neighbor tables. Alternatively, the update information can be implemented using a separate topology update message, carrying the correspondence between the old and new parallel inverter numbers, or carrying node characteristics along with the new parallel inverter number, to reduce ambiguity when other inverters update their local records. For example, after the yielding inverter switches from parallel inverter number two to parallel inverter number four, it immediately broadcasts a matching message carrying parallel inverter number four. Upon receiving this message, other inverters mark parallel inverter number four as occupied and, if necessary, delete the occupancy association with parallel inverter number two, thus completing the topology update.

[0048] The parallel matching process ends when no more parallel number conflicts occur. If the parallel network does not detect duplicate parallel numbers within a preset time period, or if no number conflicts are found in several consecutive matching message exchanges between inverters, the matching process terminates and enters the stable operation phase. If a new inverter is detected joining or a conflict is caused by external device modification during the stable operation phase, the matching process can be triggered again and the above number switching and update broadcast process can be repeated until the parallel network converges again to a network state with unique parallel numbers. This allows for the addition, removal, and numbering of parallel nodes without downtime, ensuring that the parallel operation after networking maintains unique identification and manageability.

[0049] In this embodiment of the invention, upon receiving a parallel operation number setting command from an external device or detecting a new inverter access event or a parallel operation number conflict event, a parallel operation matching process is triggered. During this process, the inverter broadcasts a matching message on the bus. The matching message includes a parallel operation number, a random decision value, and a status flag, including a parallel operation number setting flag and an update status flag. When the parallel operation numbers of the first inverter and the second inverter conflict, based on the random decision value, the parallel operation number setting flag, and the update status flag, a yielding inverter is determined between the first and second inverters. The yielding inverter generates a candidate parallel operation number according to a preset candidate number selection rule and performs occupancy detection through bus interaction to determine if the candidate parallel operation number is not occupied by other inverters. When it is determined that it is not occupied by other inverters, the candidate parallel operation number is set as the parallel operation number of the yielding inverter, and update information is broadcast. This process continues until there are no more parallel operation number conflicts, completing the parallel operation matching process and obtaining the networked parallel operation system. By triggering a matching process when a new node is detected or a parallel number conflict is detected, the matching message containing a random decision value and a set / update flag is used to determine the give-way inverter. Combined with candidate number generation and occupancy detection, a conflict-free number allocation is completed, enabling the parallel system to automatically converge to a network state with unique numbers. This reduces manual configuration and downtime debugging costs, supports online addition and removal of equipment and smooth reconfiguration, and improves the reliability and maintainability of the parallel network.

[0050] Optionally, after completing the parallel matching process and obtaining the parallel system after networking, each inverter can perform validity verification on its own stored parallel operation parameters to obtain the verification result; based on the verification result, candidate synchronization source nodes with synchronization qualifications are determined; among the candidate synchronization source nodes, the synchronization source node is determined based on the parallel number; the synchronization source node broadcasts the parallel operation parameters on the bus; other inverter nodes besides the synchronization source node receive the parallel operation parameters and update the parallel operation parameters stored locally to achieve consistency of parallel operation parameters in the parallel system after networking.

[0051] In this embodiment of the invention, after the parallel matching process is completed and the network is established, the parallel operation enters an available state. However, the parallel operation parameters may still differ between the inverters. For example, one inverter may have been individually adjusted, another may have been restored to its old configuration after a power outage, or a different default value may have been written to one inverter during factory or maintenance. To avoid control deviations during parallel operation caused by parameter inconsistencies, a parallel operation parameter synchronization phase can be further triggered after the network is established, ensuring that the key parameters within the parallel network remain consistent across the inverters.

[0052] The parameter synchronization phase begins with each inverter performing a validity check on its locally stored parallel operation parameters. The parameters are typically stored in non-volatile memory, such as flash memory or erasable programmable read-only memory, and the check method can be cyclic redundancy check (CRC). A successful check indicates the availability of the locally stored parameters, while a failure indicates the parameters may have been accidentally corrupted, are incomplete, or have not been initialized. The check results are used to generate synchronization eligibility identifiers. Only inverters that pass the check are included in the candidate synchronization source node set, thus preventing erroneous parameters from spreading throughout the network. For example, one inverter might write a new set of parallel operation parameters during maintenance and complete a CRC write-back. After restarting, the check passes, and the inverter becomes eligible for synchronization. Another inverter, however, experiences a power outage during a write operation, resulting in incomplete data. After restarting, the CRC fails, and the inverter does not enter the candidate synchronization source node set.

[0053] After the candidate synchronization source nodes are determined, a unique synchronization source node needs to be selected from the candidate set to assume the broadcasting responsibility, in order to avoid parameter conflicts caused by simultaneous broadcasts from multiple sources. The determination of the synchronization source node can be based on the parallel unit number, using an election rule that prioritizes the node with the smallest parallel unit number. This ensures the election process is deterministic and repeatable, and allows each node to independently obtain a consistent result without relying on central coordination. The candidate node with the smallest parallel unit number becomes the synchronization source node, and the remaining candidate nodes abandon broadcasting and switch to receiving updates. For example, if the candidate synchronization source nodes include two inverters with parallel unit number one and parallel unit number three, the inverter corresponding to parallel unit number one becomes the synchronization source node; if the node corresponding to parallel unit number one fails the verification and is not eligible for synchronization, then the node corresponding to parallel unit number three becomes the synchronization source node.

[0054] Once the synchronization source node is determined, it broadcasts the parallel operation parameters on the bus. The broadcast message can contain parameter data and version information, or parameter data and cyclic redundancy check (CRC) values, facilitating consistency checks by the receiving end before writing. Other inverter nodes, besides the synchronization source node, listen to the bus and receive the broadcast parallel operation parameters. They write the received parameters to their local storage area and update the parameter cache used during operation. If necessary, they recalculate the CRC after writing and write it back to ensure validity checks are passed upon subsequent restarts. By receiving updates from other nodes through synchronization source broadcasts, the networked parallel system can quickly establish a unified baseline of operating parameters, providing a foundation for consistent voltage and current control, protection thresholds, and parallel scheduling during parallel operation.

[0055] Optionally, after completing the parallel matching process and obtaining the parallel system after networking, the master node inverter can also receive control commands sent by external devices. The control commands carry the target address and can be read or write commands. When the target address is a first preset address, the master node inverter executes the control command and returns a response to the external device. When the target address is not the first preset address, the master node inverter determines the target parallel number based on the target address, encapsulates the control command into a bus message, and sends it on the bus. The slave node inverter corresponding to the target parallel number receives the bus message, generates a response message, and sends the response message to the master node inverter via the bus. The master node inverter converts the response message into a response that can be recognized by the external device and returns it.

[0056] In this embodiment of the invention, the master node inverter assumes the responsibility of command entry and forwarding between external devices and the parallel network on the bus side. This allows external devices to access any inverter within the parallel network using the Modbus interaction method, without needing to be aware of the dynamic networking details on the bus side. External devices send control commands via Modbus. These commands carry the target address and distinguish between read and write commands. Read commands can read from registers with function codes 0x03 or 0x04, while write commands can write to registers with function codes 0x06 or 0x10. After receiving the control commands, the master node inverter first parses the target address and performs routing decisions to achieve two addressing modes: direct address access and parallel number mapping access.

[0057] When the target address is the first preset address, the control command points to the inverter currently directly connected to the external device. The master node inverter completes register read or write operations locally and encapsulates the execution result into a response that can be recognized by the external device. The first preset address can be set to address one to form a fixed direct address entry, so that the external device can reliably access the directly connected device through this address regardless of how the parallel number of the master node inverter changes. This supports plug-and-play replacement of the master node inverter and reduces the complexity of on-site commissioning.

[0058] When the target address is not the first preset address, the master node inverter determines the target parallel unit number based on the target address and encapsulates the control command into a bus message, sending it to the bus side so that the slave node inverter corresponding to the target parallel unit number can receive and execute it. An offset mapping relationship can be used between the target address and the target parallel unit number. This mapping relationship can be set so that the target address equals the target parallel unit number plus one, making address two correspond to parallel unit number one, and address three correspond to parallel unit number two, thus associating the Modbus address space of the external device with the parallel unit number space within the parallel network. Through offset mapping, external devices only need to address within a unified Modbus address space when initiating commands. Dynamic network topology changes in the underlying parallel network do not require external device configuration; the master node inverter can complete the addressing conversion and forwarding.

[0059] Specifically, the relationship between the target address and the target parallel unit number can be further illustrated by a MODBUS address and inverter ID mapping table as shown in Table 1 below: Table 1

[0060] In Table 1, the MODBUS address is the target address, and the inverter parallel ID is the target parallel number. A fixed mapping is established between the Modbus address space on the external device side and the parallel number space within the parallel network, enabling external devices to access different inverter nodes without being aware of dynamic changes in the parallel network. In Table 1, each Modbus address corresponds to a master node inverter. The master node inverter serves as the direct connection entry point for external devices, ensuring that external devices always access the currently directly connected inverter through the same address, without needing to worry about changes in the master node inverter's parallel number within the parallel network. The design of a non-fixed master node inverter parallel number supports plug-and-play replacement of the master node role. Even if the inverter directly connected to the external device is replaced in the field, as long as the external device still accesses it through address one, the access target will still stably point to the directly connected device, thereby reducing the workload of reconfiguring addresses and debugging.

[0061] In Table 1, Modbus addresses, starting from number two, are sequentially mapped to the parallel node number space within the parallel network, forming a fixed offset relationship with an offset of one. The correspondence rule is that the Modbus address equals the parallel node number plus one, or the parallel node number equals the Modbus address minus one. Based on this mapping, an external device uses Modbus address two to access the inverter of the parallel node with parallel node number one, uses Modbus address three to access the inverter of the parallel node with parallel node number two, and so on. Through this fixed offset mapping, external devices maintain a consistent addressing convention, while the master node inverter is responsible for converting the Modbus address to the target parallel node number after receiving the command and forwarding it to the bus side, thus achieving addressing decoupling.

[0062] This mapping relationship applies to both read and write command scenarios. In the read scenario, the external device initiates a register read request with the target address. The master node inverter calculates the target parallel node number based on Table 1 and forwards the request. The request is executed by the slave node inverter corresponding to the target parallel node number and returns data, which is then converted into a Modbus acknowledgment and sent back by the master node inverter. In the write scenario, the external device initiates a register write request with the target address. The master node inverter similarly calculates the target parallel node number based on Table 1 and forwards the request. The slave node inverter corresponding to the target parallel node number completes the write and returns a write confirmation, which is then sent back to the external device by the master node inverter. Through the fixed mapping relationship in Table 1, the external device only needs to remember address 1 for accessing directly connected devices, and addresses 2 and above for accessing slave nodes in parallel node number order, thus achieving centralized management and control of the parallel network.

[0063] After the master node inverter determines the target parallel device number, it converts the control commands from the external device into bus messages that can be transmitted on the bus side. These bus messages are sent on the bus and listened to by each slave node inverter. When the receiving conditions are met, the slave node inverter corresponding to the target parallel device number parses the bus message and performs register read or write operations, generating an acknowledgment message which is then returned to the master node inverter via the bus. Upon receiving the acknowledgment message, the master node inverter converts the acknowledgment content into a Modbus acknowledgment that the external device can recognize and sends it back, thus completing end-to-end transparent access.

[0064] To adapt to routing and acknowledgment on the bus side, message encapsulation can use an extended identifier field to carry routing information. This extended identifier field can include frame type, data source, sender parallel node number, and target parallel node number. The frame type distinguishes between sending and acknowledgment, and the target parallel node number indicates whether it's a unicast or broadcast target. Through this encapsulation method, the master node inverter performs protocol conversion and data forwarding, while the slave node inverter executes commands and sends back results. This allows external devices to access inverter nodes with different parallel node numbers within the parallel network without changing their communication habits.

[0065] Optionally, in the step of encapsulating control commands into bus messages and sending them on the bus, the frame type, data source, sender parallel number, and target parallel number can be determined based on the control commands. The frame type is used to distinguish between the sent message and the response message. An initial bus message is generated, and the frame type, data source, sender parallel number, and target parallel number are written into the extended identifier of the initial bus message to form a bus message and send it to the bus.

[0066] In this embodiment of the invention, when the master node inverter forwards control commands from external devices to the bus side, it can use an extended identifier to carry routing and source information, so that the bus-side nodes can complete message identification, target filtering, and response feedback without relying on additional handshakes. To this end, the control commands are first parsed during the encapsulation stage to obtain four types of fields: frame type, data source, sender parallel device number, and target parallel device number. These four types of fields are written into the extended identifier of the bus message, forming a self-describing bus message before it is sent to the bus.

[0067] The extended identifier uses a 32-bit field divided into bytes, including frame type, data source, sender parallel unit number, and target parallel unit number, with each field occupying eight bits. The frame type distinguishes between downlink transmission messages and uplink acknowledgment messages. Downlink transmission messages can be set to a first preset value, such as hexadecimal 1A (0x1A), to represent a request sent from the master node inverter to the bus side; uplink acknowledgment messages can be set to a second preset value, such as hexadecimal 1B (0x1B), to represent an acknowledgment returned from the slave node inverter to the master node inverter. The data source identifies the origin of the control command. The data source can be set to a first source value indicating a host computer source, such as hexadecimal 01 (0x01), or a second source value indicating a platform source, such as hexadecimal 02 (0x02). Other values ​​are reserved for future expansion. The sender parallel unit number identifies the sending node of the bus message. In downlink transmission messages, the sender parallel unit number corresponds to the parallel unit number of the master node inverter, while in uplink acknowledgment messages, the sender parallel unit number corresponds to the parallel unit number of the slave node inverter that generated the acknowledgment. The target parallel unit number indicates whether the message is a unicast or broadcast target. In unicast scenarios, the target parallel unit number is entered as the target inverter parallel unit number. In broadcast scenarios, the target parallel unit number can be set to a preset broadcast value, such as zero (i.e., 0x00), to indicate scenarios requiring multiple nodes to receive the message, such as synchronization settings.

[0068] Bus message generation can begin with an initial bus message, which includes an extended identifier field and a data field. The extended identifier field carries the four types of byte fields mentioned above, while the data field carries the service content of the control command. After determining the four types of fields, the master node inverter sequentially writes the frame type, data source, sender parallel number, and target parallel number into the corresponding byte positions of the extended identifier, completing the extended identifier construction. Then, it writes the function code, register address, and data payload carried by the control command into the data field, forming a complete bus message and sending it to the bus. Upon receiving the message, each inverter on the bus side first parses the extended identifier and determines whether to accept or process it based on the target parallel number. Then, it determines whether the current message is a request or an acknowledgment based on the frame type. Finally, it performs register read / write operations based on the data field and generates an acknowledgment message to send back. By carrying frame type, source, and routing information through the extended identifier, bus-side communication in a multi-node concurrent environment more easily achieves deterministic message filtering and reliable return, and provides a foundation for subsequent broadcast settings and acknowledgment scheduling strategies.

[0069] Optionally, in the step where the master node inverter determines the target parallel inverter number based on the target address, encapsulates the control command into a bus message, and sends it on the bus, if the control command is a write command, the master node inverter can further determine whether the write command is synchronous or asynchronous based on the register address corresponding to the write command; if the write command is asynchronous, the slave node inverter corresponding to the target parallel inverter number is a single one; if the write command is synchronous, the target parallel inverter number is a broadcast value, and the corresponding slave node inverters are all slave node inverters; when the write command is asynchronous, the bus message corresponding to the write command is sent to the single slave node inverter corresponding to the target parallel inverter number; when the write command is synchronous, the bus message corresponding to the write command is sent to all slave node inverters.

[0070] In this embodiment of the invention, after a write control command arrives at the master node inverter, the master node inverter not only calculates the target parallel unit number based on the target address, but also determines whether the write command is synchronous or asynchronous based on the register address corresponding to the write command. This allows for automatic switching between single-node writes and network-wide synchronous writes. The write command may include a single-register write command with function code 0x06 and a multi-register write command with function code 0x10. The register address indicates the parameter being written. Different parameter items can be pre-classified into synchronous parameter registers and asynchronous parameter registers according to their purpose. Synchronous parameters are used for critical configurations affecting the consistency of parallel operation, while asynchronous parameters are used for configurations independent of a single unit or configurations related to an individual node.

[0071] When the register address points to the asynchronous parameter register, the write instruction is determined to be asynchronous. The slave inverter corresponding to the target parallel number is a single node. The master inverter generates a bus message according to the target parallel number mapped from the target address and sends it to the bus. The target field in the extended identifier is filled with the target parallel number, making the bus message exhibit unicast semantics. After receiving the message, the slave inverter corresponding to the target parallel number executes the write and generates an acknowledgment message to return to the master inverter. The master inverter converts the acknowledgment into an acknowledgment that can be recognized by the external device and returns it, forming a single-node closed-loop write. This process corresponds to an asynchronous write path, where the target node directly acknowledges, and the master inverter completes the forwarding and return.

[0072] When the register address points to the synchronization parameter register, the write instruction is determined to be of the synchronization type. In this case, the write intent is directed to all slave inverters in the parallel network. The master inverter sets the target parallel number to a broadcast value and generates a bus message. The target field in the extended identifier is filled with the broadcast value to express broadcast semantics. The broadcast value can be 0x00 for the target field, indicating a synchronization setting scenario. After the bus message is sent on the bus, all slave inverters, upon detecting that the target field is a broadcast value, enter the receiving process and execute the write, thus achieving consistent writing of the same parameter across multiple nodes. After the synchronization type write is completed, each slave inverter can generate an acknowledgment message and return it to the master inverter. The master inverter then aggregates the multiple acknowledgment results to form a unified response to external devices. This process corresponds to the synchronization write path, where the master inverter broadcasts the write and organizes the write results across the entire network before replying to external devices.

[0073] The above-mentioned method for determining synchronous and asynchronous types eliminates the need for external devices to explicitly specify the forwarding mode when sending write commands. The master node inverter can automatically select the mode based solely on the register address: the asynchronous type uses a unicast method with the target parallel number and is directly responded to by a single target node, while the synchronous type uses a broadcast method with the target parallel number 0x00 and is effective to all slave node inverters.

[0074] Optionally, when the control command is a write command and the write command is of the synchronous type, in the step of sending the response message to the master node inverter via the bus, the delay transmission duration can also be determined for each slave node inverter based on the parallel number of the slave node inverter; after the delay transmission duration is reached, the response message is sent to the master node inverter via the bus.

[0075] In this embodiment of the invention, synchronous type writes are broadcast. All slave node inverters, upon receiving the broadcast write, will execute the write and need to provide feedback on the execution result. If each slave node inverter immediately sends an acknowledgment message after completing the write, dense acknowledgment contention can easily occur on the bus side, leading to message collisions, increased arbitration delays, or repeated retransmissions, thus affecting the real-time performance and reliability of write confirmation. To mitigate these risks, slave node inverters do not immediately send acknowledgment messages after generating them. Instead, a time-division delay is introduced based on the parallel unit number, allowing multiple nodes to send acknowledgments in staggered order according to their parallel unit numbers.

[0076] The delay transmission duration is determined by the parallel node number and can be calculated linearly: the delay time equals the parallel node number minus one multiplied by the base interval time. The base interval time can be set as a preset time slice to ensure that the response transmission windows of two adjacent slave node inverters do not overlap. The delay time calculation formula can be written as: delay time equals the local parallel node number minus one multiplied by T_base, where T_base represents the preset time slice. For example, when T_base is two milliseconds, the slave node inverter with parallel node number one has a delay time of zero milliseconds and can send the response first after completing the write operation; the slave node inverter with parallel node number two has a delay time of two milliseconds and sends the response after two milliseconds; the slave node inverter with parallel node number three has a delay time of four milliseconds and sends the response after four milliseconds, and so on.

[0077] Time-division delay can be started after the slave node inverter receives the broadcast write command. The timing start point can be the message reception completion time or the write execution completion time. To ensure more stable order, the timing start point can be uniformly set to the write execution completion time, making the delay only related to the number and reducing window overlap caused by differences in write time of different nodes. When the timer reaches the delay transmission duration, the slave node inverter sends an acknowledgment message to the bus. The master node inverter receives the acknowledgment messages from each slave node inverter in sequence and completes the acknowledgment summary. Through the time-division acknowledgment mechanism based on parallel number, the acknowledgment in the multi-node synchronous write scenario changes from "simultaneous contention for the bus" to "staggered transmission by number," which can significantly reduce bus congestion and message collision probability, and improve the communication success rate and overall response time stability in the synchronous setup scenario.

[0078] Optionally, in the step of determining the yielding inverter among the first inverter and the second inverter based on the random decision value, the parallel number setting flag bit, and the update status flag bit, the first inverter can be determined as the yielding inverter when the parallel number setting flag bit of the second inverter is at a first preset value and the parallel number setting flag bit of the first inverter is not at the first preset value; and the second inverter can be determined as the yielding inverter when the parallel number setting flag bit of the first inverter is at the first preset value and the parallel number setting flag bit of the second inverter is not at the first preset value. To allow a given inverter to proceed; when the parallel number setting flag bits of the first inverter and the second inverter are the same, and the update status flag bits of the first inverter and the second inverter are different, the inverter with the update status flag bit set to the second preset value is determined to be the given inverter; when the parallel number setting flag bits of the first inverter and the second inverter are the same, and the update status flag bits of the first inverter and the second inverter are the same, the given inverter is determined based on the random decision value of the first inverter and the second inverter.

[0079] In this embodiment of the invention, when a parallel inverter number conflict occurs, in order for the parallel network to converge in a deterministic manner, a unique yielding conclusion needs to be reached between the conflicting parties. This allows one inverter to enter the parallel inverter number update process, while the other inverter retains its current parallel inverter number and continues to participate in the monitoring. The yielding conclusion is completed using a distributed adjudication method, without relying on central coordination. The adjudication criteria are composed of ID_Setting_Flg, ID_Update_Flg, and the random number carried in the matching message. The adjudication process can be understood as resolving uncertainty sequentially at three levels: authority, process state, and symmetry breaking.

[0080] ID_Setting_Flg is used to indicate the source attribute of the parallel inverter number. When ID_Setting_Flg is 1, it means that the parallel inverter number was written by the host computer through setting instructions, and has a higher retention priority. When ID_Setting_Flg is 0, it means that the parallel inverter number comes from automatic allocation or the default initial state. If one of the conflicting inverters has ID_Setting_Flg as 1 while the other does not, the arbitration result selects the inverter with ID_Setting_Flg not being 1 as the give-way inverter, thereby preventing the automatic allocation mechanism from overwriting the parallel inverter number already set by the host computer and reducing the probability of the operation and maintenance configuration being corrupted. Corresponding to the symmetrical description of the conflicting parties, when the ID_Setting_Flg of the second inverter is 1 and the ID_Setting_Flg of the first inverter is not 1, the first inverter is determined to be the yielding inverter; when the ID_Setting_Flg of the first inverter is 1 and the ID_Setting_Flg of the second inverter is not 1, the second inverter is determined to be the yielding inverter.

[0081] When the ID_Setting_Flg values ​​of the two conflicting inverters are the same, the ruling further introduces ID_Update_Flg to constrain the concurrent behavior of the parallel inverter number update process. ID_Update_Flg indicates whether the parallel inverter number is in the update process. When ID_Update_Flg is 1, it means that the inverter has entered the candidate parallel inverter number search, occupancy detection, or number switching process. When ID_Update_Flg is 0, it means that the inverter has not entered the update process or is in a stable state. When the ID_Update_Flg values ​​of the two conflicting inverters are different, the inverter with ID_Update_Flg of 1 is determined to yield, allowing it to continue to complete the cyclic increment search and occupancy detection of candidate parallel inverter numbers. The other inverter remains waiting and maintains its current parallel inverter number, thereby avoiding repeated conflicts caused by both switching numbers simultaneously. This rule ensures that only one side is allowed to advance the update action in each conflict, making the network convergence process exhibit single-threaded advancement characteristics, reducing the risk of oscillation and shortening the convergence time.

[0082] When both conflicting inverters have the same ID_Setting_Flg and ID_Update_Flg, they maintain symmetry in terms of authority and process state. This symmetry needs to be broken using a random number carried in the matching message. The random number can be a 32-bit number and written into the matching message for adjudication comparison. The two conflicting inverters compare the random numbers to reach a unique yield decision, ensuring that a unique party can be determined to perform the update in each conflict. The adjudication method can be set so that the inverter with the smaller random number retains its current parallel unit number, while the inverter with the larger random number is determined to yield and initiates an auto-incrementing process for the parallel unit number, thus forming a definite conflict resolution direction in the distributed environment.

[0083] Through the three-layer adjudication mechanism consisting of ID_Setting_Flg, ID_Update_Flg, and a 32-bit random number, conflict resolution proceeds layer by layer from the host computer setting and maintenance to the random breaking of symmetry. This enables the parallel network to stably determine the yielding inverter in scenarios such as node power-on, hot-plugging, or host computer modification of the parallel number. It also provides a clear execution entity for subsequent parallel number cyclic increment search and broadcast occupancy detection, ultimately achieving convergence of parallel number uniqueness and broadcasting of topology update information.

[0084] To further explain the inverter parallel networking method provided in this embodiment of the invention, this embodiment also provides a flowchart of the master node routing method, as shown in Figure 3, to supplement the explanation of how the master node completes routing and forwarding according to read / write type after receiving control commands from the "host computer / APP". The "host computer / APP" on the left represents the external control entry point, which sends read or write commands to the master node; the "read" and "write" in the middle represent the branching of command types.

[0085] The read command enters the "read target node" section, used to parse the target address and determine the access object. "Read master node" indicates that the target address points to a directly connected device. After the master node reads the registers locally, it responds to the host computer. "Read slave node" indicates that the target address is mapped to a slave node corresponding to a certain parallel device number. The master node encapsulates the read request into a bus message and sends it. After receiving the message, the target slave node returns an acknowledgment message. After receiving the message, the master node forwards the data to the host computer.

[0086] The write command enters a judgment box, "Does the register to be written need to be synchronized or stored?", to distinguish between synchronous and asynchronous writes. "Synchronous" enters "Broadcast Write," where the master node broadcasts the target value to all slave nodes. In the diagram, "Broadcast address is 0x00" indicates that the target parallel node number field is 0x00. All slave nodes receive and reply accordingly, and the master node ends after receiving all replies. "Maximum number of retransmissions is 10" limits the retransmission limit when data collection is incomplete. "Asynchronous" enters "Write to Target Node," where the master node unicasts according to the target parallel node number. Only the target slave node performs the write and replies, and the master node then forwards the write result "acknowledgment data to the host computer."

[0087] The arrows in the diagram represent the processing order and message flow. The core meaning is that the master node routes the target address on the modbus side to the target parallel machine number on the bus side, and organizes the sending and response transmission according to four scenarios: read, write, synchronous write, and asynchronous write.

[0088] To further explain the inverter parallel networking method provided in this embodiment of the invention, this embodiment also provides a flowchart of a response data processing method, as shown in Figure 4. Figure 4 illustrates how the master node decides whether to send a response back to the host computer / APP after receiving a response from the slave node, and how to collect and retransmit responses in a synchronous write scenario. The left box, "Master node receives slave node response data," indicates that the master node listens to the bus and receives response frames sent back by the slave nodes. The data usually comes from the data field on the CAN side. The middle box, "Determine whether to forward to the host computer," indicates that the master node classifies and judges this response. The judgment criteria are given at the top of the figure: forwarding conditions include "target ID needs to be forwarded"; while "broadcast data does not need to be forwarded." In a broadcast scenario, the focus is on collecting the response results of each slave node, without having to forward each slave node response to the host computer individually.

[0089] The arrow pointing from the middle box to the upper right, labeled "Forward," corresponds to the upper right box "Forward the CAN data of the target ID to the host computer." This means that this response belongs to a unicast target (the target ID points to a slave node), and the master node converts / encapsulates the CAN side response into data that the host computer can recognize and sends it back. The arrow pointing to the lower right, labeled "No need to forward," corresponds to the lower right box "Record the response data of the slave node." This means that this response is a retrieval after a broadcast write, and the master node stores the responses of each slave node in a buffer or a counter table to determine whether they have been "collected."

[0090] The rightmost box, "If the number of responses and timing parameters are not equal, a retransmission will be performed, with a maximum of 10 retransmissions," expresses the collection logic and retransmission limit: The master node compares the number of responses received with the expected number of responses. The expected number can be derived from the number of online slave nodes and timing / timeout parameters. If the number of responses does not reach the expected number within the timing window, a retransmission broadcast is triggered, and the retransmission frequency is limited by "maximum of 10 retransmissions" to avoid long-term bus congestion.

[0091] To further explain the inverter parallel networking method provided in this embodiment of the invention, this embodiment also provides a flowchart of a transmission frame processing method, as shown in Figure 5. Figure 5 illustrates how the slave node completes register read / write, response construction, and time-division multiplexing after receiving the transmission frame from the master node. The leftmost box, "Slave node receives CAN data from master node," indicates that the slave node listens for and receives the transmission frame sent by the master node on the bus side. The data field of the transmission frame carries the function code of the external control command after encapsulation, the register address, and read / write data, etc.

[0092] The second box, "Set or Read Corresponding Register Data," indicates the specific operation performed after parsing the data field from the node: in a read scenario, the target data is retrieved from the register area; in a write scenario, the write value is written to the target register or configuration area, and the runtime parameter cache can be updated synchronously. Here, "corresponding register" emphasizes locating the operated parameter item using the register address carried in the message as an index.

[0093] The third box, "Set the corresponding CAN extended ID based on the sender and receiver IDs," is used to construct the extended identifier for the response frame. The sender ID in the extended identifier corresponds to the local parallel node number, and the receiver ID corresponds to the master node parallel node number or the target parallel node number field. This allows the master node to correctly filter and identify the source of the response. Simultaneously, the frame type field is switched to the response type, enabling the master node to distinguish between sent frames and response frames on the receiving side.

[0094] The rightmost box, "Delayed transmission, (ID-1)*basic interval time to prevent service data frame collisions," describes the time-sharing response mechanism. ID represents the local parallel node number, and the basic interval time is a preset time slice. After completing register operations and constructing the response frame, the slave node does not send the response immediately. Instead, it sends the response after a delay of (ID-1) times the basic interval time. This ensures that multiple nodes send responses in staggered order according to their numbers in synchronous write or broadcast scenarios, reducing the probability of bus arbitration conflicts and response loss.

[0095] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0096] In one embodiment, a parallel networking device for inverters is provided, which corresponds one-to-one with the parallel networking method for inverters described in the above embodiments. As shown in Figure 6, the parallel networking device for inverters is applied to a parallel system, which includes inverters, including a master node inverter and at least one slave node inverter. The master node inverter and the slave node inverter are connected via a bus communication. The parallel networking device for inverters includes a trigger module 601, a broadcast module 602, a determination module 603, a generation module 604, and a setting module 605. The functional modules are described in detail below: Trigger module 601 is used to trigger the parallel matching process when it receives a parallel number setting command from an external device or detects a new inverter access event or a parallel number conflict event; Broadcast module 602 is used to broadcast a matching message on the bus during the parallel matching process, the matching message containing a parallel number, a random decision value, and a status flag, the status flag including a parallel number setting flag bit and an update status flag bit; Determination module 603 is used to determine the parallel matching process based on the random decision value when the parallel numbers of the first inverter and the second inverter conflict. The parallel operation number setting flag and the update status flag are used to determine the yielding inverter among the first inverter and the second inverter; the generation module 604 is used for the yielding inverter to generate a candidate parallel operation number according to a preset candidate number selection rule, and to perform occupancy detection through bus interaction to determine that the candidate parallel operation number is not occupied by other inverters; the setting module 605 is used to set the candidate parallel operation number as the parallel operation number of the yielding inverter and broadcast update information when it is determined that it is not occupied by other inverters, until there is no parallel operation number conflict, and complete the parallel matching process to obtain the parallel operation system after networking.

[0097] Optionally, the device further includes: a verification module, used by each inverter to perform validity verification on its own stored parallel operation parameters and obtain a verification result; a second determination module, used to determine candidate synchronization source nodes with synchronization qualifications based on the verification result; a third determination module, used to determine the synchronization source node based on the parallel operation number among the candidate synchronization source nodes; a second broadcast module, used by the synchronization source node to broadcast the parallel operation parameters on the bus; and a parameter update module, used by other inverter nodes besides the synchronization source node to receive the parallel operation parameters and update the parallel operation parameters stored locally, so as to achieve consistency of parallel operation parameters of the networked parallel system.

[0098] Optionally, the device further includes: a sending module, used for the master node inverter to receive control commands sent by an external device, the control commands carrying a target address, and the control commands being read or write commands; a first return module, used for the master node inverter to execute the control commands and return a response to the external device when the target address is a first preset address; a second sending module, used for the master node inverter to determine a target parallel unit number based on the target address when the target address is not the first preset address, and to encapsulate the control commands into a bus message and send it on the bus; a third sending module, used for the slave node inverter corresponding to the target parallel unit number to receive the bus message and generate a response message, and to send the response message to the master node inverter via the bus; and a second return module, used for the master node inverter to convert the response message into a response recognizable by the external device and return it.

[0099] Optionally, the second sending module is further configured to: determine the frame type, data source, sender parallel number, and target parallel number based on the control command, wherein the frame type is used to distinguish between sending messages and acknowledgment messages; generate an initial bus message, and write the frame type, data source, sender parallel number, and target parallel number into the extended identifier of the initial bus message to form the bus message and send it to the bus.

[0100] Optionally, the second sending module is further configured to: when the control instruction is the write instruction, the master node inverter determines whether the write instruction is synchronous or asynchronous based on the register address corresponding to the write instruction; if the write instruction is asynchronous, the slave node inverter corresponding to the target parallel number is a single one; if the write instruction is synchronous, the target parallel number is a broadcast value, and the corresponding slave node inverter is all the slave node inverters; when the write instruction is asynchronous, the bus message corresponding to the write instruction is sent to the single slave node inverter corresponding to the target parallel number; when the write instruction is synchronous, the bus message corresponding to the write instruction is sent to all the slave node inverters.

[0101] Optionally, when the control instruction is the write instruction and the write instruction is of the synchronous type, the third sending module is further configured to: determine the delayed sending duration for each slave node inverter based on the parallel number of the slave node inverter; and after the delayed sending duration is reached, send the response message to the master node inverter via the bus.

[0102] Optionally, the determining module 603 is further configured to: determine the first inverter as a yielding inverter when the parallel number setting flag of the second inverter is a first preset value and the parallel number setting flag of the first inverter is not a first preset value; determine the second inverter as a yielding inverter when the parallel number setting flag of the first inverter is a first preset value and the parallel number setting flag of the second inverter is not a first preset value; determine the inverter with the update status flag of the second inverter as a yielding inverter when the parallel number setting flags of the first inverter and the second inverter are the same and the update status flags of the first inverter and the second inverter are different; and determine the yielding inverter based on the random decision value of the first inverter and the second inverter when the parallel number setting flags of the first inverter and the second inverter are the same and the update status flags of the first inverter and the second inverter are the same.

[0103] Each module in the above-mentioned inverter parallel grid connection device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0104] In one embodiment, a computer device is provided, which may be a terminal device, and its internal structure diagram is shown in Figure 7. The computer device includes a processor, a memory, and a network interface connected via a system bus. The processor of the computer device provides computing and control capabilities. The memory of the computer device includes a readable storage medium. The readable storage medium stores computer-readable instructions. The network interface of the computer device is used to communicate with external terminals via a network connection. When the computer-readable instructions are executed by the processor, a parallel networking method for inverters is implemented. The readable storage medium provided in this embodiment includes non-volatile readable storage media and volatile readable storage media.

[0105] In this application embodiment, a computer device is provided, including a memory, a processor, and computer-readable instructions stored in the memory and executable on the processor. When the processor executes the computer-readable instructions, it implements the steps of the parallel networking method of the inverter described above.

[0106] In one embodiment of the application, a readable storage medium is provided, which stores computer-readable instructions. When the computer-readable instructions are executed by a processor, they implement the steps of the parallel networking method of the inverter described above.

[0107] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by instructing related hardware with computer-readable instructions. These computer-readable instructions can be stored in a non-volatile readable storage medium or a volatile readable storage medium. When executed, these computer-readable instructions can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0108] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0109] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for parallel grid connection of inverters, characterized in that, The method is applied to a parallel system, which includes an inverter, a master node inverter, and at least one slave node inverter. The master node inverter and the slave node inverter are connected via a bus. The method includes: triggering a parallel matching process when receiving a parallel number setting command from an external device or detecting a new inverter access event or a parallel number conflict event; in the parallel matching process, the inverter broadcasts a matching message on the bus, the matching message containing a parallel number, a random decision value, and a status flag, the status flag including a parallel number setting flag and an update status flag. When the parallel operation numbers of the first inverter and the second inverter conflict, the give-way inverter is determined from the first inverter and the second inverter based on the random decision value, the parallel operation number setting flag bit, and the update status flag bit. The give-way inverter generates a candidate parallel operation number according to a preset candidate number selection rule, and performs occupancy detection through bus interaction to determine that the candidate parallel operation number is not occupied by other inverters. When it is determined that it is not occupied by other inverters, the candidate parallel operation number is set as the parallel operation number of the give-way inverter and the update information is broadcast until there is no parallel operation number conflict, thus completing the parallel matching process and obtaining the parallel system after networking.

2. The method for parallel grid connection of inverters as described in claim 1, characterized in that, After completing the parallel matching process and obtaining the networked parallel system, the method further includes: each inverter performing validity verification on its stored parallel operation parameters to obtain verification results; determining candidate synchronization source nodes with synchronization qualifications based on the verification results; determining a synchronization source node based on the parallel number among the candidate synchronization source nodes; the synchronization source node broadcasting the parallel operation parameters on the bus; and other inverter nodes besides the synchronization source node receiving the parallel operation parameters and updating their locally stored parallel operation parameters to achieve consistency of parallel operation parameters in the networked parallel system.

3. The method for parallel grid connection of inverters as described in claim 1 or 2, characterized in that, After completing the parallel matching process and obtaining the networked parallel system, the method further includes: the master node inverter receiving a control command sent by an external device, the control command carrying a target address, the control command being a read command or a write command; when the target address is a first preset address, the master node inverter executing the control command and returning a response to the external device; when the target address is not the first preset address, the master node inverter determining the target parallel number based on the target address, encapsulating the control command into a bus message and sending it on the bus; the slave node inverter corresponding to the target parallel number receiving the bus message and generating a response message, and sending the response message to the master node inverter via the bus; the master node inverter converting the response message into a response recognizable by the external device and returning it.

4. The method for parallel grid connection of inverters as described in claim 3, characterized in that, The step of encapsulating the control command into a bus message and sending it on the bus includes: determining the frame type, data source, sender parallel machine number, and target parallel machine number based on the control command, wherein the frame type is used to distinguish between a sending message and a response message; generating an initial bus message, and writing the frame type, the data source, the sender parallel machine number, and the target parallel machine number into the extended identifier of the initial bus message to form the bus message and send it to the bus.

5. The method for parallel grid connection of inverters as described in claim 3, characterized in that, The master node inverter determines the target parallel inverter number based on the target address, encapsulates the control command into a bus message, and sends it on the bus, including: when the control command is the write command, the master node inverter determines whether the write command is synchronous or asynchronous based on the register address corresponding to the write command; if the write command is asynchronous, the slave node inverter corresponding to the target parallel inverter number is a single one; if the write command is synchronous, the target parallel inverter number is a broadcast value, and the corresponding slave node inverters are all the slave node inverters; when the write command is asynchronous, the bus message corresponding to the write command is sent to the single slave node inverter corresponding to the target parallel inverter number; when the write command is synchronous, the bus message corresponding to the write command is sent to all the slave node inverters.

6. The method for parallel grid connection of inverters as described in claim 5, characterized in that, When the control command is the write command and the write command is of the synchronous type, sending the response message to the master node inverter via the bus includes: determining a delay transmission duration for each slave node inverter based on the parallel number of the slave node inverter; and sending the response message to the master node inverter via the bus after the delay transmission duration is reached.

7. The method for parallel grid connection of inverters as described in claim 1, characterized in that, The step of determining the yielding inverter among the first inverter and the second inverter based on the random decision value, the parallel number setting flag, and the update status flag includes: determining the first inverter as the yielding inverter when the parallel number setting flag of the second inverter is a first preset value and the parallel number setting flag of the first inverter is not a first preset value; and determining the second inverter as the yielding inverter when the parallel number setting flag of the first inverter is a first preset value and the parallel number setting flag of the second inverter is not a first preset value. Inverter; when the parallel number setting flag bits of the first inverter and the second inverter are the same, and the update status flag bits of the first inverter and the second inverter are different, the inverter with the update status flag bit of the second inverter is determined to be the yielding inverter; when the parallel number setting flag bits of the first inverter and the second inverter are the same, and the update status flag bits of the first inverter and the second inverter are the same, the yielding inverter is determined based on the random decision value of the first inverter and the second inverter.

8. A parallel grid connection device for an inverter, characterized in that, The device is applied to a parallel system, which includes inverters, including a master node inverter and at least one slave node inverter. The master node inverter and the slave node inverter are connected via a bus. The device includes: a trigger module, used to trigger a parallel matching process when receiving a parallel number setting command from an external device or detecting a new inverter access event or a parallel number conflict event; a broadcast module, used to broadcast a matching message on the bus during the parallel matching process, the matching message including a parallel number, a random decision value, and a status flag, the status flag including a parallel number setting flag and an update status flag; and a determination module. The system is configured to: 1) determine the yielding inverter from the first inverter and the second inverter when the parallel operation numbers of the first inverter and the second inverter conflict, based on the random decision value, the parallel operation number setting flag, and the update status flag; 2) generate a candidate parallel operation number for the yielding inverter according to a preset candidate number selection rule, and perform occupancy detection through bus interaction to determine that the candidate parallel operation number is not occupied by other inverters; and 3) set the candidate parallel operation number as the parallel operation number of the yielding inverter and broadcast update information when it is determined that it is not occupied by other inverters, until there is no parallel operation number conflict, thus completing the parallel matching process and obtaining the parallel operation system after networking.

9. A computer device comprising a memory, a processor, and computer-readable instructions stored in the memory and running on the processor, characterized in that, When the processor executes the computer-readable instructions, it implements the inverter parallel networking method as described in any one of claims 1 to 7.

10. A readable storage medium having computer-readable instructions stored thereon, characterized in that, When the computer-readable instructions are executed by the processor, they implement the inverter parallel networking method as described in any one of claims 1 to 7.

Images