Common-mode resonance calibration method of voltage-controlled oscillator and related device

Abstract

The invention relates to the technical field of power electronic devices, in particular to a common-mode resonance calibration method and related device for a voltage-controlled oscillator, and the method comprises the steps: obtaining and inputting a capacitance value control code value into a common-mode capacitor array of the voltage-controlled oscillator; acquiring a target digital code corresponding to a second harmonic signal at a cross-coupled pair source node of the voltage-controlled oscillator; performing iterative optimization on the capacitance value control code value according to a comparison result of the target digital code and a pre-obtained digital code threshold value to obtain an optimal capacitance value control code value; according to the optimal capacitance value control code value, the capacitance value of the common-mode capacitor array is adjusted to the optimal capacitance value, the optimal capacitance value enables the comprehensive performance of the voltage-controlled oscillator to be optimal, and the technical problem that the comprehensive performance of the voltage-controlled oscillator becomes poor due to the fact that the common-mode resonant frequency of the voltage-controlled oscillator is difficult to calibrate in the prior art is solved.

Description

A common-mode resonance calibration method and related apparatus for a voltage-controlled oscillator Technical Field

[0001] This invention relates to the field of power electronic device technology, and in particular to a common-mode resonance calibration method and related apparatus for a voltage-controlled oscillator. Background Technology

[0002] In wireless communication, radar, and high-speed interconnect systems, the voltage-controlled oscillator (VCO) is the core module of the frequency synthesizer, and its phase noise performance directly affects the system's spectral purity and signal sensitivity. To reduce phase noise, existing technologies typically introduce a common-mode second harmonic resonant structure, which suppresses flicker noise upconversion by optimizing the impulse sensitivity function (ISF), thereby significantly improving oscillator performance. In particular, traditional VCOs with explicit common-mode resonators achieve optimal overall performance when their common-mode resonant frequency is equal to the second harmonic frequency of the oscillator's operating frequency (i.e., the common-mode resonant frequency is twice the fundamental frequency).

[0003] However, the common-mode resonant frequency of a voltage-controlled oscillator (VCO) is easily affected by variations in process technology, voltage, and temperature (PVT), making it difficult to maintain a relationship of twice the differential-mode frequency, thus degrading the overall performance of the VCO. Therefore, how to calibrate the common-mode resonant frequency of a VCO to improve its overall performance has become an urgent technical problem to be solved. Summary of the Invention

[0004] This invention provides a common-mode resonance calibration method and related apparatus for a voltage-controlled oscillator (VCO), which solves the technical problem that the difficulty in calibrating the common-mode resonance frequency of a VCO in the prior art leads to a deterioration in the overall performance of the VCO.

[0005] This invention provides a common-mode resonance calibration method for a voltage-controlled oscillator, comprising:

[0006] Obtain and input the capacitance control code value into the common-mode capacitor array of the voltage-controlled oscillator;

[0007] At the source node of the cross-coupled pair of the voltage-controlled oscillator, the target digital code corresponding to the second harmonic signal is obtained;

[0008] Based on the comparison result between the target digital code and the pre-acquired digital code threshold, the tolerance control code value is iteratively optimized to obtain the optimal tolerance control code value.

[0009] According to the optimal capacitance control code value, the capacitance value of the common-mode capacitor array is adjusted to the optimal capacitance value, which makes the overall performance of the voltage-controlled oscillator optimal.

[0010] Optionally, obtaining the target digital code corresponding to the second harmonic signal at the source node of the cross-coupled pair of the voltage-controlled oscillator includes:

[0011] The second harmonic signal is obtained at the source node of the cross-coupled pair of the voltage-controlled oscillator;

[0012] Extract the amplitude of the second harmonic signal and convert the amplitude into a target DC voltage;

[0013] Convert the target DC voltage into a target digital code.

[0014] Optionally, the step of iteratively optimizing the tolerance control code value based on the comparison result between the target digital code and a pre-acquired digital code threshold to obtain the optimal tolerance control code value includes:

[0015] Determine whether the target numeric code is consistent with the numeric code threshold. If yes, use the current tolerance control code value as the tolerance control code value. If no, determine whether the tolerance control code value has reached the predetermined maximum code value.

[0016] If it is determined that the capacitance control code value has not reached the maximum value of the code value, the capacitance control code value is updated, and the updated capacitance control code value is input into the common mode capacitor array. Then, the execution jumps to the steps from obtaining the target digital code corresponding to the second harmonic signal at the source node of the cross-coupled pair of the voltage-controlled oscillator to iteratively optimizing the capacitance control code value based on the comparison result between the target digital code and the pre-acquired digital code threshold to obtain the optimal capacitance control code value.

[0017] If it is determined that the capacitance control code value has reached the maximum value of the code value, the digital code threshold is adjusted according to the preset adjustment ratio, and the process jumps to the step of obtaining and inputting the capacitance control code value into the common mode capacitor array of the voltage-controlled oscillator, and then to the step of iteratively optimizing the capacitance control code value based on the comparison result between the target digital code and the pre-obtained digital code threshold to obtain the optimal capacitance control code value.

[0018] Optionally, updating the tolerance control code value includes:

[0019] Increment the tolerance control code by one to obtain the updated tolerance control code.

[0020] Optionally, adjusting the digital code threshold according to a preset adjustment ratio includes:

[0021] The digital code threshold is reduced according to a preset adjustment ratio.

[0022] Optionally, the target DC voltage is positively correlated with the amplitude.

[0023] In another aspect, the present invention provides a common-mode resonance calibration device for a voltage-controlled oscillator, the device comprising:

[0024] The first acquisition module is used to acquire and input the capacitance control code value into the common-mode capacitor array of the voltage-controlled oscillator;

[0025] The second acquisition module is used to acquire the target digital code corresponding to the second harmonic signal at the source node of the cross-coupled pair of the voltage-controlled oscillator.

[0026] The optimization module is used to iteratively optimize the tolerance control code value based on the comparison result between the target digital code and the pre-acquired digital code threshold, so as to obtain the optimal tolerance control code value.

[0027] The adjustment module is used to adjust the capacitance value of the common-mode capacitor array to the optimal capacitance value according to the optimal capacitance control code value, so that the overall performance of the voltage-controlled oscillator is optimized.

[0028] Optionally, the second acquisition module includes:

[0029] The acquisition unit is used to acquire the second harmonic signal at the source node of the cross-coupled pair of the voltage-controlled oscillator;

[0030] An extraction unit is used to extract the amplitude of the second harmonic signal and convert the amplitude into a target DC voltage;

[0031] A conversion unit is used to convert the target DC voltage into a target digital code.

[0032] Another aspect of the present invention provides a voltage-controlled oscillator, comprising: a common-mode resonant calibrator and a differential-mode resonant module, a negative impedance module and a common-mode resonator connected in sequence;

[0033] The common-mode resonator calibrator is connected to the common-mode resonator and is used to perform the method described above.

[0034] In another aspect, the present invention provides a computer-readable storage medium for storing program code for performing the method described above.

[0035] As can be seen from the above technical solutions, the present invention has the following advantages:

[0036] This invention provides a common-mode resonance calibration method for a voltage-controlled oscillator (VCO). The method involves acquiring and inputting a capacitance control code value into the common-mode capacitor array of the VCO; acquiring a target digital code corresponding to the second harmonic signal at the source node of the cross-coupled pair of the VCO; iteratively optimizing the capacitance control code value based on a comparison between the target digital code and a pre-acquired digital code threshold to obtain an optimal capacitance control code value; and adjusting the capacitance of the common-mode capacitor array to the optimal capacitance value based on the optimal capacitance control code value, thereby maximizing the overall performance of the VCO.

[0037] In this invention, the capacitance control code value is used to adjust the capacitance value of the voltage-controlled oscillator (VCO) connected to the common-mode capacitor array. By acquiring and inputting the capacitance control code value into the common-mode capacitor array of the VCO, this invention achieves the adjustment of the capacitance value of the common-mode capacitor array and provides data support for iterative optimization of the optimal capacitance control code value in subsequent steps. After inputting the capacitance control code value, this invention obtains the target digital code corresponding to the amplitude of the second harmonic signal at the source node of the cross-coupled pair of the VCO, thereby obtaining a digital code signal (i.e., the target digital code) that reflects the trend of the second harmonic signal amplitude change. This provides a judgment benchmark condition for subsequent iterative optimization operations. Based on the comparison result between the target digital code and the pre-acquired digital code threshold, the capacitance control code value is iteratively optimized to obtain the optimal capacitance control code value that maximizes the overall performance of the voltage-controlled oscillator (VCO). Then, based on the optimal capacitance control code value, the capacitance of the common-mode capacitor array is adjusted to the optimal value, thus calibrating the common-mode resonant frequency of the VCO. The adjusted common-mode capacitor array allows the VCO to operate near the optimal harmonic resonance point, optimizing the overall performance index (FoM) of the VCO. Therefore, the common-mode resonance calibration method for VCOs provided by this invention comprehensively solves the technical problem of existing technologies' difficulty in calibrating the common-mode resonant frequency of VCOs, which leads to a deterioration in the overall performance of the VCO. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 is a schematic flowchart of a common-mode resonance calibration method for a voltage-controlled oscillator provided in an embodiment of the present invention;

[0040] Figure 2 is a schematic diagram of one of the voltage-controlled oscillators provided in an embodiment of the present invention;

[0041] Figure 3 is a second schematic diagram of the voltage-controlled oscillator provided in an embodiment of the present invention;

[0042] Figure 4 is a third schematic diagram of the voltage-controlled oscillator provided in an embodiment of the present invention;

[0043] Figure 5 is a circuit diagram of the peak detector provided in an embodiment of the present invention;

[0044] Figure 6 shows the simulation results of the peak detector provided in the embodiment of the present invention. In Figure 6, (a) is a waveform diagram of sinusoidal second harmonic input signal with different amplitudes; and (b) is a waveform diagram of the target DC voltage.

[0045] Figure 7 shows the FoM and A of the voltage-controlled oscillator at a frequency of 3.85 GHz provided in the embodiment of the present invention. H2 A waveform diagram;

[0046] Figure 8 is a flowchart illustrating a common-mode resonance calibration method for a voltage-controlled oscillator according to another embodiment of the present invention;

[0047] Figure 9 is a schematic flowchart of a common-mode resonance calibration method for a voltage-controlled oscillator provided by an application example of the present invention;

[0048] Figure 10 shows the calibration process provided in the embodiment of the present invention. CC A schematic diagram illustrating the waveform concepts of Bsample and Bset;

[0049] Figure 11 is a schematic diagram of the PN curves before and after calibration at 3.85 GHz provided in an embodiment of the present invention;

[0050] Figure 12 is a structural block diagram of a common-mode resonance calibration device for a voltage-controlled oscillator provided in an embodiment of the present invention. Detailed Implementation

[0051] Existing technologies utilize the harmonic resonance optimization principle to reduce the phase noise of oscillators and improve their performance. However, the harmonic resonance optimization principle requires the common-mode resonant frequency of the oscillator to be optimized. With 2 Alignment, where, The fundamental frequency is used. Based on existing harmonic resonance optimization principles, current technologies have proposed low-phase-noise voltage-controlled oscillators (VCOs) based on second-harmonic tuning. However, due to the extreme sensitivity of parasitic capacitance to process, voltage, and temperature (PVT) variations, the common-mode resonant frequency... It is prone to deviation, thus disrupting its relationship with the fundamental frequency. The mismatch leads to a significant degradation in the phase noise performance of the oscillator. Therefore, the common-mode resonant frequency needs to be calibrated.

[0052] Existing technologies employ manual calibration to maintain the common-mode resonant frequency at twice the differential-mode frequency. However, this method requires pre-determining the control word during testing and cannot adaptively adjust outside the test platform, thus limiting the stability of the voltage-controlled oscillator (VCO) in broadband applications. To address this, existing technologies also use multi-cavity coupling to create a flat impedance plateau near the second harmonic, but this significantly increases the complexity of passive network design. Furthermore, existing technologies propose achieving harmonic frequency locking by simultaneously adjusting differential-mode and common-mode capacitor arrays. However, this dual-array coordinated adjustment method not only increases the complexity of digital logic design but also requires additional comparators for calibration convergence, making it difficult to maintain good system robustness. Therefore, existing calibration methods struggle to calibrate the common-mode resonant frequency of the VCO, leading to a deterioration in the overall performance of the VCO.

[0053] To address this issue, embodiments of the present invention provide a common-mode resonance calibration method and related apparatus for a voltage-controlled oscillator (VCO), which solves the technical problem that the difficulty in calibrating the common-mode resonance frequency of a VCO in the prior art leads to a deterioration in the overall performance of the VCO.

[0054] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0055] In one embodiment, the present invention provides a voltage-controlled oscillator, including a common-mode resonant calibrator and a differential-mode resonant module, a negative impedance module, and a common-mode resonator connected in sequence; the common-mode resonant calibrator is connected to the common-mode resonator and is used to perform a common-mode resonant calibration method for a voltage-controlled oscillator provided in any of the following embodiments.

[0056] In this embodiment, the voltage-controlled oscillator core adopts a Class B structure with common-mode resonance formed by NMOS cross-coupled pairs. As shown in Figures 2 and 3, the differential-mode resonant module includes a main inductor L1 and a differential-mode capacitor array. The differential-mode capacitor array includes several differential-mode capacitor units, and each differential-mode capacitor unit includes two differential-mode capacitors C. D The first switching transistor and the negative impedance module include a first MOSFET M1 and a second MOSFET M2, which are cross-coupled. The common-mode resonator includes a tail inductor L2 and a common-mode capacitor array. The common-mode capacitor array includes several common-mode capacitor units, each of which includes a common-mode capacitor C. CAnd the second switching transistor. In one example, the differential mode capacitor C in each differential mode capacitor unit D The capacitance values ​​can be different or the same. The common-mode capacitance C in each common-mode capacitor unit... C The capacitance values ​​can be different or the same. In this embodiment, a differential-mode capacitor array is used to adjust the fundamental frequency of the voltage-controlled oscillator, and a common-mode capacitor array is used to adjust the resonant frequency of the common-mode circuit of the voltage-controlled oscillator, thus achieving independent adjustment of the differential-mode and common-mode resonant frequencies.

[0057] Among them, the first MOSFET M1 and the second MOSFET M2, the first switch, and the second switch are all NMOS transistors.

[0058] In the differential mode capacitor unit, there are two differential mode capacitors C D These are respectively connected to the source and drain of the first switching transistor, and then connected to both ends of the main inductor. The gate of the first switching transistor is used to receive the differential-mode capacitor array control signal b. CD To turn the first switching transistor on or off, thereby turning the differential-mode capacitor C... D Connect or disconnect the voltage-controlled oscillator (VCO). The differential-mode capacitor units are connected in parallel, and the gate of the first switching transistor in each differential-mode capacitor unit is used to receive the differential-mode capacitor array control signal b. CD Among them, b CD Composed of multiple bits, different digital control bits control the capacitance value of the differential-mode capacitor in the circuit. A high level connects the capacitor to the circuit, while a low level disconnects it. In this invention, b CD It can be used to control the number of capacitors connected in the differential-mode capacitor array to adjust the capacitance value of the differential-mode capacitor array, thereby changing the operating frequency of the voltage-controlled oscillator and adjusting the fundamental frequency.

[0059] The sources of the first MOSFET M1 and the second MOSFET M2 are interconnected and connected to the common-mode capacitor C of each common-mode capacitor unit. C One end of the inductor is connected to one end of the tail inductor L2, and the other end of the tail inductor L2 is grounded. The first MOSFET M1 and the second MOSFET M2 are connected to the common-mode capacitor C. C The connection point of the tail inductor L2 is the source node of the cross-coupled pair in this invention, as shown in Figure 3. H2 This represents the second harmonic signal extracted from the source node in the cross-coupling.

[0060] The common-mode capacitance C of each common-mode capacitor unit C The other end is connected to the drain of the second switching transistor inside its unit. The source of the second switching transistor in each common-mode capacitor unit is grounded, and the gate of the second switching transistor in each common-mode capacitor unit is used to receive the capacitance control signal b. CC Similarly, b CD bCC Composed of multiple bits, a high level enables the capacitor under the corresponding control bit to be connected to the circuit, while a low level deactivates the capacitor. Therefore, through b... CC The control bit can control the number of common-mode capacitors connected in the common-mode capacitor array, thereby adjusting the capacitance value of the common-mode capacitor array and thus adjusting the common-mode resonant frequency. In this invention, high and low levels are represented by digital signals, i.e., high level is "1" and low level is "0". For example: assuming there are 4 groups of common-mode capacitor units, b CC If there are 4 bits, then b CC The corresponding digital control bits are 0000 to 1111 (0-15 control words), and each digital control bit controls a group of common-mode capacitor units. When b CC If the value is 0, the corresponding digital control bit is 0000, indicating that the common-mode capacitance C of each common-mode capacitor unit is 0. C None of them are connected. It is understood that the tolerance control code value in this invention is b. CC The value of .

[0061] In one embodiment, the common-mode resonant calibrator includes a peak detector, an analog-to-digital converter (ADC), and a logic comparator. The input of the peak detector is connected to the source node of a cross-coupled pair, and the output of the peak detector is connected to the input of the ADC. The output of the ADC is connected to one input of the logic comparator, and the other input of the logic comparator is used to receive a digital code threshold. The logic comparator also has a reset terminal to restart the peak detection and ADC modules when a reset signal is received. The output of the logic comparator is connected to a common-mode capacitor array to output a capacitance control signal b. CC To the common-mode capacitor array. In one example, the output of the logic comparator is connected to the gate of the second switch in the common-mode capacitor cell.

[0062] It should be noted that before starting the common-mode resonator calibrator, b can be adjusted. CD The voltage-controlled oscillator (VCO) is set to its fundamental frequency, and then the common-mode resonance calibrator is activated to adjust the common-mode resonant frequency to twice the fundamental frequency to complete the common-mode resonance calibration. Once the common-mode resonance calibration is complete, the calibrator automatically shuts down. The peak detector extracts the amplitude of the second harmonic signal and converts it into a proportionally proportional DC signal output, also providing amplification.

[0063] In one embodiment, the main inductor adopts a regular octagonal single-turn structure, and the tail inductor is set in a figure-eight shape and is located inside the main inductor.

[0064] It should be noted that, as shown in Figure 4, the main inductor adopts a regular octagonal single-turn structure to minimize the differential-mode impedance of the resonant cavity and achieve low phase noise characteristics under low supply voltage. The tail inductor adopts an 8-shaped layout and is placed inside the main inductor. This structure effectively shortens the common-mode current return path from the main inductor tap VDD to the tail inductor ground terminal, reducing the parasitic common-mode inductance L. CM This reduces the losses caused by the main inductor and the tail inductor, while also reducing the overall layout area. It has been verified that the main inductor and tail inductor structures provided in this embodiment exhibit good quality factors and stability in their operating frequency bands, which can further ensure the accuracy of the common-mode resonant frequency.

[0065] In one embodiment, as shown in FIG5, the peak detector includes a common-source buffer and an integration circuit.

[0066] A common-source buffer refers to a buffer consisting of a bias resistor R. B The common-source amplifier circuit consists of a buffer load R1 and a first transistor M3. The integrating circuit includes a second transistor M4, a third transistor M5, a first capacitor C1, a second capacitor C2, a second resistor R2, and a second capacitor C2.

[0067] In this embodiment, the common-source buffer of the peak detector provides isolation to prevent the switching activity of the peak detector from affecting the steady-state performance of the oscillator. The drain node V of the common-source buffer... buf Connected to the integrator circuit, which extracts the envelope average of the signal. During operation, the voltage drop across the buffer load resistor R1 is approximately equal to the threshold voltage of the second transistor M4, therefore it only conducts during the negative half-cycle of the buffered output voltage. At this time, the integrator circuit... buf The negative half-cycle signal is averaged and sampled to generate a DC voltage signal V that is related to the second harmonic amplitude. PD (i.e., the target DC voltage). To further improve the detection sensitivity, the amplification stage is composed of transistors and resistors to amplify the extracted signal, thereby reducing the resolution requirements of the subsequent ADC. As shown in Figure 6, simulation results show that the settling time of the integration loop is less than 20 ns. Figure (a) shows sinusoidal second harmonic input signals of different amplitudes, and Figure (b) shows the detected peak value.

[0068] The above is a description of a voltage-controlled oscillator provided by an embodiment of the present invention. The following will describe a common-mode resonance calibration method for a voltage-controlled oscillator provided by an embodiment of the present invention.

[0069] Please refer to Figure 1. An embodiment of the present invention provides a common-mode resonance calibration method for a voltage-controlled oscillator, comprising:

[0070] 101. Obtain and input the capacitance control code value into the common-mode capacitor array of the voltage-controlled oscillator.

[0071] It should be noted that the tolerance control code value is b in the aforementioned embodiment. CC In this step, the capacitance control code value is input into the common-mode capacitor array of the voltage-controlled oscillator to control the capacitance value of the common-mode capacitor array.

[0072] In one example, during the initial stage, the initial value of the capacitance control code is input into the common-mode capacitor array as the basis for initial optimization. In subsequent iterative optimizations, the capacitance control code value is accumulated sequentially according to a preset accumulation amount to facilitate subsequent optimization of the capacitance control code value. In one example, the initial value of the capacitance control code is set to 0.

[0073] 102. At the source node of the cross-coupled pair of the voltage-controlled oscillator, obtain the target digital code corresponding to the second harmonic signal.

[0074] It should be noted that, since the voltage-controlled oscillator in this embodiment includes an explicit common-mode oscillator, based on the advantageous structure of the explicit common-mode oscillator, the second harmonic signal corresponding to the oscillator operating frequency can be directly extracted at the source node of the cross-coupled pair, thereby obtaining the target digital code corresponding to the second harmonic signal.

[0075] In one example, step 102 includes the following sub-steps:

[0076] S1. Obtain the second harmonic signal at the source node of the cross-coupled pair of the voltage-controlled oscillator;

[0077] S2. Extract the amplitude of the second harmonic signal and convert the amplitude into the target DC voltage;

[0078] It should be noted that after extracting the second harmonic signal, this step extracts the amplitude A of the second harmonic signal. H2 This will be converted into the corresponding target DC voltage.

[0079] In one example, the target DC voltage is positively correlated with the amplitude.

[0080] In one example, the expression between the target DC voltage and the amplitude of the second harmonic signal is as follows:

[0081] V PD =K PD *A H2

[0082] V PD For the target DC voltage, K PD A is the voltage scaling factor. H2 This represents the amplitude of the second harmonic signal.

[0083] S3. Convert the target DC voltage into the target digital code.

[0084] It should be noted that the obtained target DC voltage is converted into a digital signal, thus forming an S-bit digital signal (i.e., target digital code B). Sample Where S represents the total number of bits in the digital signal, and its specific value can be determined after conversion based on the value of the target DC voltage.

[0085] In one example, the target DC voltage can be converted into the corresponding target digital code using an analog-to-digital converter (ADC). For instance, a successive approximation register ADC (SAR ADC) with 6-bit resolution and a sampling rate of 250MHz can be used. Its sampling settling time is less than 10ns at 300KHz, which meets the system's dynamic range, resolution, and speed requirements. In this example, the SAR ADC can quantize the target DC voltage into a 6-bit digital code B. Sample .

[0086] 103. Based on the comparison results between the target digital code and the pre-acquired digital code threshold, the tolerance control code value is iteratively optimized to obtain the optimal tolerance control code value.

[0087] It should be noted that, due to the principle of harmonic resonance optimization, the common-mode resonant frequency is required. Adjust to differential mode fundamental frequency twice as much as In other words, the oscillator can only operate near the optimal harmonic resonance point when the common-mode capacitance of the common-mode capacitor array, the main inductance, the tail inductance, and the differential-mode capacitance of the differential-mode capacitor array meet the above conditions. When this ratio deviates from the optimal value, the FoM (Figure of Merit, the overall performance index of the oscillator) of the voltage-controlled oscillator near the near-carrier spectrum will decrease significantly.

[0088] To this end, the inventors conducted simulation verification on common-mode capacitor arrays with different capacitance values. As shown in Figure 7, the voltage-controlled oscillator at a frequency of 3.85 GHz exhibits different capacitance values. The amplitude A of the second harmonic signal extracted from the source node of the cross-coupled pair is also measured under these different common-mode capacitor array conditions. H2 The overall performance index FoM of the oscillator shows the same trend and reaches its peak under similar capacitance conditions, indicating that the amplitude A of the second harmonic signal is... H2 The value of the second harmonic signal at the source node of the cross-coupled pair shows a near positive correlation with the overall performance index (FoM) of the oscillator. Based on this, the optimal FoM value of the oscillator can be indirectly found by detecting the peak value of the second harmonic signal at the source node of the cross-coupled pair, thereby achieving optimal oscillator performance.

[0089] Based on the above principles, this step compares the target digital code with the digital code threshold, and iteratively optimizes the capacitance control code value based on the comparison result to obtain the optimal capacitance control code value. This ensures that the capacitance of the common-mode capacitor array is optimized, maintaining its optimal ratio with the capacitance of the differential-mode capacitor array, thereby maximizing A. H2 This allows the overall performance of the oscillator to reach its optimal level.

[0090] The total number of bits in the digital code threshold is the same as the total number of bits in the target digital code.

[0091] 104. Based on the optimal capacitance control code value, adjust the capacitance value of the common-mode capacitor array to the optimal value, so that the overall performance of the voltage-controlled oscillator reaches the optimal value.

[0092] It should be noted that after determining the optimal capacitance control code value, the optimization is stopped, and the optimal capacitance control code value is latched. The optimal capacitance control code value is then input into the common-mode capacitor array, thereby adjusting the capacitance value of the common-mode capacitor array to the optimal capacitance value, so that the voltage-controlled oscillator can continuously operate in a state of optimal overall performance.

[0093] In this invention, the capacitance control code value is used to adjust the capacitance value of the voltage-controlled oscillator (VCO) connected to the common-mode capacitor array. By acquiring and inputting the capacitance control code value into the common-mode capacitor array of the VCO, this invention achieves the adjustment of the capacitance value of the common-mode capacitor array and provides data support for iterative optimization of the optimal capacitance control code value in subsequent steps. After inputting the capacitance control code value, this invention obtains the target digital code corresponding to the second harmonic signal at the source node of the VCO's cross-coupling pair, thereby obtaining a digital code signal (i.e., the target digital code) that reflects the changing trend of the second harmonic signal. This provides a benchmark condition for subsequent iterative optimization operations. Based on the comparison between the target digital code and the pre-acquired digital code threshold, the capacitance control code value is iteratively optimized to obtain the optimal capacitance control code value that maximizes the overall performance of the voltage-controlled oscillator (VCO). Then, based on the optimal capacitance control code value, the capacitance of the common-mode capacitor array is adjusted to the optimal value, thus calibrating the common-mode resonant frequency of the VCO. The adjusted common-mode capacitor array allows the VCO to operate near the optimal harmonic resonance point, optimizing the overall performance index (FoM) of the VCO. Therefore, the common-mode resonance calibration method for VCOs provided by this invention comprehensively solves the technical problem of existing technologies' difficulty in calibrating the common-mode resonant frequency of VCOs, which leads to a deterioration in the overall performance of the VCO.

[0094] Please refer to Figure 8. Another embodiment of the present invention provides a common-mode resonance calibration method for a voltage-controlled oscillator, comprising:

[0095] 201. Obtain and input the capacitance control code value into the common-mode capacitor array of the voltage-controlled oscillator.

[0096] It should be noted that the initial value of the tolerance control code is entered in this step.

[0097] 202. At the source node of the cross-coupled pair of the voltage-controlled oscillator, obtain the target digital code corresponding to the second harmonic signal.

[0098] It should be noted that step 202 can be referred to step 102, and will not be repeated here.

[0099] It is understood that the second harmonic signal in this step is the second harmonic signal extracted under the control of the capacitance control code value in the common-mode capacitor array at the current extraction time. For example, if the capacitance control code value in the common-mode capacitor array at the current extraction time is the initial value, then the second harmonic signal corresponding to the initial value is extracted. If the capacitance control code value in the common-mode capacitor array at the current extraction time is the capacitance control code value updated in step 204, then the second harmonic signal corresponding to the updated capacitance control code value is extracted.

[0100] 203. Determine whether the target numeric code is consistent with the numeric code threshold. If yes, use the current tolerance control code value as the tolerance control code value; otherwise, proceed to step 204.

[0101] It should be noted that during the initial comparison, the threshold for the numeric code is a preset threshold, which can be set by evaluating the maximum value of the target numeric code.

[0102] When the target digital code matches the pre-acquired digital code threshold, it indicates that the current target digital code has reached its maximum value, that is, the amplitude of the second harmonic signal has reached its peak value. This indicates that the overall performance of the voltage-controlled oscillator has reached its optimal value at the current moment. Therefore, the capacitance control code value corresponding to the current moment is determined as the optimal capacitance control code value, and the optimization is stopped, and the optimal capacitance control code value is latched.

[0103] When the target digital code is inconsistent with the pre-acquired digital code threshold, it means that the current target digital code has not reached the maximum value. In other words, the amplitude of the second harmonic signal corresponding to the oscillator operating frequency directly extracted at the source node of the cross-coupled pair has not reached the peak value. That is, the overall performance of the voltage-controlled oscillator has not reached the optimal value. Therefore, step 204 is executed to continue optimization.

[0104] 204. Determine whether the capacitance control code value has reached the predetermined maximum value. If not, update the capacitance control code value and input the updated capacitance control code value into the common-mode capacitor array, and jump to steps 202 to 204. If yes, adjust the digital code threshold according to the preset adjustment ratio, and jump to steps 201 to 204.

[0105] It should be noted that, as can be seen from the foregoing embodiments, the capacitance control signal b CC The number of bits is a finite value, i.e., the capacitance control signal b. CC The value (i.e., the capacitance control code value) has a maximum value, for example, the capacitance control signal b. CC Taking a 4-bit value as an example, the maximum value of the tolerance control code is 15, and the corresponding number of bits is 1111.

[0106] In this embodiment, the capacitance control signal b CC The process begins by scanning sequentially from 0. When the scanned capacitance control code value reaches its maximum value, the current scan cycle ends, and the next scan cycle begins, also starting from 0. Therefore, after step 203, it is pre-determined whether the current capacitance control code value has reached the pre-determined maximum value. If not, it indicates that the capacitance control code value has not been fully iterated. Therefore, the capacitance control code value is updated, and the updated capacitance control code value is input into the common-mode capacitor array. Then, steps 202 to 204 are executed.

[0107] If the current tolerance control code value reaches the predetermined maximum value, it means that all tolerance control code values ​​have been iterated. In this case, if the target digital code is still inconsistent with the pre-acquired digital code threshold, it indicates that the digital code threshold may be set too high and needs to be adjusted. Therefore, the digital code threshold is adjusted according to the preset adjustment ratio, and the adjusted digital code threshold is used as the judgment benchmark. Steps 201 to 204 are executed again to rescan the tolerance control code value until the tolerance control code value corresponding to the target digital code being consistent with the digital code threshold is determined as the optimal tolerance control code value.

[0108] In one embodiment, updating the tolerance control code value includes: incrementing the tolerance control code by one to obtain the updated tolerance control code.

[0109] It should be noted that when the tolerance control code value does not reach the predetermined maximum value, the current tolerance control code value is incremented by one to update the tolerance control code and obtain the updated tolerance control code.

[0110] In one embodiment, adjusting the digital code threshold according to a preset adjustment ratio includes:

[0111] The digital code threshold is reduced according to the preset adjustment ratio.

[0112] It should be noted that when adjusting the numeric code threshold, the threshold is reduced according to a preset adjustment ratio, so that the reduced threshold can be used to detect the peak value of the target numeric code. In one example, the adjustment ratio can be 1, that is, subtracting one from the original numeric code threshold to obtain the new threshold.

[0113] 205. Based on the optimal capacitance control code value, adjust the capacitance value of the common-mode capacitor array to the optimal value. The optimal capacitance value enables the voltage-controlled oscillator to achieve the best overall performance.

[0114] It should be noted that step 205 can be referred to step 104, and will not be repeated here.

[0115] This invention provides a common-mode resonance calibration method for a voltage-controlled oscillator (VCO). The method involves acquiring and inputting a capacitance control code value into the common-mode capacitor array of the VCO; acquiring a target digital code corresponding to the second harmonic signal at the source node of the VCO's cross-coupled pair; iteratively optimizing the capacitance control code value based on a comparison between the target digital code and a pre-acquired digital code threshold to obtain the optimal capacitance control code value; and adjusting the capacitance of the common-mode capacitor array to the optimal value based on the optimal capacitance control code value, thereby maximizing the overall performance of the VCO.

[0116] This embodiment achieves the adjustment of the capacitance value of the common-mode capacitor array by acquiring and inputting the capacitance control code value into the common-mode capacitor array of the voltage-controlled oscillator (VCO), and provides data support for the iterative optimization of the optimal capacitance control code value in subsequent steps. After inputting the capacitance control code value, this embodiment acquires the target digital code corresponding to the second harmonic signal at the source node of the VCO's cross-coupled pair, thereby obtaining a digital code signal (i.e., the target digital code) that reflects the trend of the second harmonic signal change, providing a judgment benchmark condition for the subsequent iterative optimization operation. Based on the comparison result between the target digital code and the pre-acquired digital code threshold, the capacitance control code value is iteratively optimized to obtain the optimal capacitance control code value that enables the VCO to achieve the best overall performance. Then, based on the optimal capacitance control code value, the capacitance value of the common-mode capacitor array is adjusted to the optimal capacitance value, realizing the calibration of the common-mode resonant frequency of the VCO. The common-mode capacitor array with the optimal capacitance value enables the VCO to operate near the optimal harmonic resonance point, making the overall performance index (FoM) of the VCO optimal. Therefore, the common-mode resonance calibration method for voltage-controlled oscillators provided in this embodiment solves the technical problem that the existing technology makes it difficult to calibrate the common-mode resonance frequency of voltage-controlled oscillators, resulting in a deterioration in the overall performance of the voltage-controlled oscillators.

[0117] In one application example, as shown in Figure 9, the process of the common-mode resonance calibration method for a voltage-controlled oscillator provided by the present invention includes:

[0118] The first step is to set the digital code threshold Bset to its maximum value. This value refers to the maximum peak value that the circuit is designed to achieve in the calibration method. In one example, Bset = 2. S -1, where S is the number of bits in the target digital code Bsample. Then b CC Set to 0. Then, as shown in Figure 3, the peak detector extracts the amplitude A of the second harmonic signal from the source node of the cross-coupled pair. H2 And converted into the target DC voltage V PD The input is then fed into an analog-to-digital converter (ADC), which converts and outputs the target digital code Bsample.

[0119] The second step involves the first round of comparison between Bsample and Bset to determine if Bsample is not equal to Bset. If Bsample is not equal to Bset, it indicates that the second harmonic peak voltage has not yet reached the preset maximum voltage value. At this point, the current Bsample value is then determined. CC Has b been achieved? CC The maximum value (i.e., the maximum value of the tolerance control code) is not reached if b is not reached. CC The maximum value of b then controls the output b. CC +1, with b CC +1 replace b CC Then, jump to the step of determining whether Bsample and Bset are consistent. When b CC continuously accumulating from 1 to b CC If, during the process of maximizing the value, Bsample cannot reach Bset, it indicates that the preset Bset is too large. In this case, subtract 1 from Bset to obtain a new Bset, and then jump to the step of setting b... CC The step of setting B to 0 is repeated for the next round of comparisons, and this process is repeated until a value is found where Bsample equals Bset. CC At this time, b CC A is possible H2 To reach its maximum value, thus enabling the voltage-controlled oscillator to achieve optimal overall performance, therefore, the value of b at this point is saved. CC and the corresponding b CC The control word is latched and output to the common-mode capacitor array to lock the common-mode resonant point, and the voltage-controlled oscillator enters the optimal FoM value operating state.

[0120] As shown in Figure 10, in this example, after two rounds of comparison, it is impossible to make Bsample = Bset. However, in the third round of comparison, during the earlier comparisons, Bsample equals Bset. At this point, the output is b. CC The control bit is what enables A H2 Set the control bit for the maximum value and save the current value of b.CC and the corresponding b CC The control word is latched and output to the common-mode capacitor array to stop the oscillator calibration. From this point on, the voltage-controlled oscillator enters the optimal FoM value operating state.

[0121] When it is necessary to change the operating frequency of the voltage-controlled oscillator, the differential-mode capacitor array can be used to control the signal b. CD Adjust the capacitance value of the differential-mode capacitor array to adjust the operating frequency of the voltage-controlled oscillator to the desired target operating frequency, and reset b. CC (For example, setting the reset signal of the logic comparator in Figure 3 to 1 restarts the peak detector and analog-to-digital converter), and re-executes the above steps to re-calibrate the common-mode resonance. Therefore, based on the closed-loop self-calibration mechanism of the present invention, the common-mode resonant frequency drift caused by PVT variation can be compensated in real time under PVT variation conditions, so that its common-mode resonant frequency is stably maintained at 2. Nearby, common-mode harmonic self-calibration is achieved, and phase noise is automatically optimized across the entire frequency tuning range.

[0122] In a simulation application example, to verify the effectiveness of the proposed self-calibration mechanism, phase noise (PN) simulations were performed with the calibration loop (i.e., the common-mode coresonator) both off and on. With calibration disabled, this application example simulated all possible b... CC With b CD An exhaustive analysis was performed to determine the oscillator's best and worst common-mode capacitance performance within the tuning range. A self-calibration loop was then activated to automatically search for the optimal common-mode capacitance configuration.

[0123] Figure 11 shows the PN curves before and after calibration at 3.85 GHz. The blue line in Figure 11 is the phase noise curve after calibration is started, and the red line is the phase noise curve without calibration. As can be seen from Figure 11, the calibration loop can automatically lock the optimal state, so that the PN at the offset of 100 kHz and 1 MHz is reduced from −97.8 dBc / Hz and −124.9 dBc / Hz to −109.7 dBc / Hz and −129.8 dBc / Hz, respectively, which greatly optimizes the phase noise performance of the oscillator.

[0124] Referring to Figure 12, an embodiment of the present invention provides a common-mode resonance calibration device for a voltage-controlled oscillator, comprising:

[0125] The first acquisition module 301 is used to acquire and input the capacitance control code value into the common mode capacitor array of the voltage-controlled oscillator;

[0126] The second acquisition module 302 is used to acquire the target digital code corresponding to the second harmonic signal at the source node of the cross-coupled pair of the voltage-controlled oscillator.

[0127] The optimization module 303 is used to iteratively optimize the tolerance control code value based on the comparison result between the target digital code and the pre-acquired digital code threshold, so as to obtain the optimal tolerance control code value.

[0128] The adjustment module 304 is used to adjust the capacitance value of the common-mode capacitor array to the optimal capacitance value according to the optimal capacitance value control code value, so that the overall performance of the voltage-controlled oscillator can reach the optimal value.

[0129] In one embodiment, the second acquisition module 302 includes:

[0130] The acquisition unit is used to acquire the second harmonic signal at the source node of the cross-coupled pair of the voltage-controlled oscillator;

[0131] The extraction unit is used to extract the amplitude of the second harmonic signal and convert the amplitude into a target DC voltage;

[0132] The conversion unit is used to convert the target DC voltage into the target digital code.

[0133] In one embodiment, the optimization module 303 includes:

[0134] The first judgment unit is used to determine whether the target digital code is consistent with the digital code threshold. If it is, the current tolerance control code value is used as the tolerance control code value; otherwise, the second judgment unit is triggered.

[0135] The second judgment unit is used to determine whether the capacitance control code value has reached the predetermined maximum value. If not, the capacitance control code value is updated and the updated capacitance control code value is input into the common-mode capacitor array, and the second acquisition module 302 and the optimization module 303 are triggered in sequence. If yes, the digital code threshold is adjusted according to the preset adjustment ratio, and the first acquisition module 301, the second acquisition module 302, and the optimization module 303 are triggered in sequence.

[0136] This invention also provides a computer-readable storage medium for storing program code for performing the methods of any of the above embodiments.

[0137] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0138] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0139] Furthermore, in the various embodiments of the present invention, the functional units can be integrated into one processing unit, or each functional unit can be a separate physical entity, or two or more functional units can be integrated into one processing unit. The integrated unit described above can be implemented in hardware or as a software functional unit.

[0140] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0141] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0142] It should also be noted that in the description of this invention, the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0143] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A common-mode resonance calibration method for a voltage-controlled oscillator, characterized in that, The method includes: acquiring and inputting a capacitance control code value into the common-mode capacitor array of a voltage-controlled oscillator; acquiring a target digital code corresponding to the second harmonic signal at the source node of the cross-coupled pair of the voltage-controlled oscillator; iteratively optimizing the capacitance control code value based on a comparison between the target digital code and a pre-acquired digital code threshold to obtain an optimal capacitance control code value; and adjusting the capacitance of the common-mode capacitor array to the optimal capacitance value based on the optimal capacitance control code value, wherein the optimal capacitance value optimizes the overall performance of the voltage-controlled oscillator.

2. The method according to claim 1, characterized in that, The step of obtaining the target digital code corresponding to the second harmonic signal at the source node of the cross-coupled pair of the voltage-controlled oscillator includes: obtaining the second harmonic signal at the source node of the cross-coupled pair of the voltage-controlled oscillator; extracting the amplitude of the second harmonic signal and converting the amplitude into a target DC voltage; and converting the target DC voltage into a target digital code.

3. The method according to claim 2, characterized in that, The step of iteratively optimizing the capacitance control code value based on the comparison result between the target digital code and the pre-acquired digital code threshold to obtain the optimal capacitance control code value includes: determining whether the target digital code is consistent with the digital code threshold; if so, using the current capacitance control code value as the capacitance control code value; if not, determining whether the capacitance control code value has reached a pre-determined maximum value; if it is determined that the capacitance control code value has not reached the maximum value, updating the capacitance control code value, inputting the updated capacitance control code value into the common-mode capacitor array, and jumping to execute the step of cross-coupling at the source node of the voltage-controlled oscillator. The process involves steps from obtaining the target digital code corresponding to the second harmonic signal to iteratively optimizing the capacitance control code value based on the comparison result between the target digital code and a pre-acquired digital code threshold to obtain the optimal capacitance control code value; if the capacitance control code value is determined to have reached the maximum value, the digital code threshold is adjusted according to a preset adjustment ratio, and the process jumps to the steps from obtaining and inputting the capacitance control code value into the common-mode capacitor array of the voltage-controlled oscillator to iteratively optimizing the capacitance control code value based on the comparison result between the target digital code and the pre-acquired digital code threshold to obtain the optimal capacitance control code value.

4. The method according to claim 3, characterized in that, Updating the tolerance control code value includes: incrementing the tolerance control code by one to obtain the updated tolerance control code.

5. The method according to claim 4, characterized in that, The step of adjusting the digital code threshold according to the preset adjustment ratio includes: reducing the digital code threshold according to the preset adjustment ratio.

6. The method according to claim 5, characterized in that, The target DC voltage is positively correlated with the amplitude.

7. A common-mode resonance calibration device for a voltage-controlled oscillator, characterized in that, include: The first acquisition module is used to acquire and input the capacitance control code value into the common-mode capacitor array of the voltage-controlled oscillator; The second acquisition module is used to acquire the target digital code corresponding to the second harmonic signal at the source node of the cross-coupled pair of the voltage-controlled oscillator. The optimization module is used to iteratively optimize the tolerance control code value based on the comparison result between the target digital code and the pre-acquired digital code threshold, so as to obtain the optimal tolerance control code value. The adjustment module is used to adjust the capacitance value of the common-mode capacitor array to the optimal capacitance value according to the optimal capacitance control code value, so that the overall performance of the voltage-controlled oscillator is optimized.

8. The common-mode resonance calibration device according to claim 7, characterized in that, The second acquisition module includes: an acquisition unit for acquiring a second harmonic signal at the source node of the cross-coupled pair of the voltage-controlled oscillator; an extraction unit for extracting the amplitude of the second harmonic signal and converting the amplitude into a target DC voltage; and a conversion unit for converting the target DC voltage into a target digital code.

9. A voltage-controlled oscillator, characterized in that, include: A common-mode resonant calibrator and a differential-mode resonant module, a negative impedance module, and a common-mode resonator connected in sequence; The common-mode resonator calibrator is connected to the common-mode resonator and is used to perform the method as described in any one of claims 1-6.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store program code for performing the method as described in any one of claims 1-6.

Images