Semiconductor device and electronic control system

Abstract

The invention relates to a semiconductor device and an electronic control system. The detection transistor is configured to be turned on when the back electromotive force voltage is generated at the power output terminal and then the source voltage varies with the back electromotive force voltage. The clamping element is configured to limit a gate voltage of the detection transistor to a predetermined clamping voltage with reference to a voltage of the power output terminal. The gate connection circuit includes a resistive element configured to connect the power output terminal to a gate of the detection transistor, and an nMOS transistor configured to apply a ground power supply voltage to the gate of the detection transistor and cut off a current in a direction from the gate of the detection transistor toward the second power supply voltage.

Description

Cross-reference to related applications

[0001] The disclosure of Japanese Patent Application No. 2024-189839, filed on October 29, 2024, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Background Technology

[0002] This invention relates to semiconductor devices and electronic control systems, for example, to semiconductor devices that supply power to loads connected to an external environment and to electronic control systems incorporating such semiconductor devices.

[0003] The publicly available technologies are listed below. [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2023-47804 [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2007-28747

[0004] Patent document 1 discloses a semiconductor device capable of preventing damage to an output transistor due to secondary breakdown. The semiconductor device includes a detection transistor, a control transistor, and an output transistor. The detection transistor allows a detection current to flow during a period when the output voltage generated at the load terminal is lower than the ground voltage. The control transistor is controlled to be turned on during the period when the detection current flows. The output transistor is controlled to be turned off during the period when the control transistor is controlled to be turned on, i.e., during the period when the output voltage is lower than the ground voltage.

[0005] Patent document 2 discloses an overvoltage protection circuit capable of preventing circuit failures caused by a set value of a dynamic clamping voltage. This overvoltage protection circuit includes an output transistor, a load, a dynamic clamping circuit, and a clamping switch. The output transistor is connected between a power supply and an output terminal. The load is connected to the output terminal. The dynamic clamping circuit limits the voltage difference between the power supply and the output terminal. The clamping switch is connected between the dynamic clamping circuit and the output terminal, and its conduction state is determined based on a comparison between a reference voltage and the voltage at the output terminal. Summary of the Invention

[0006] For example, as disclosed in Patent Documents 1 and 2, configurations are known for supplying power from an output transistor to a load via an output terminal. For instance, if the load is inductive, a back electromotive force (EMF) voltage, such as a negative voltage, may be generated at the output terminal when the output transistor is turned off. Even when the load is not inductive, the back EMF voltage may be generated at the output terminal, for example, due to the parasitic inductive component of the wiring harness. Using the configuration disclosed in Patent Document 1, such a negative voltage can be clamped by a body diode of the output transistor, which is fixed to be off. Alternatively, when using the configuration disclosed in Patent Document 2, such a negative voltage can be clamped by a dynamic clamping circuit.

[0007] However, in the configurations disclosed in Patent Document 1 and Patent Document 2, a high voltage can be applied to the detection transistor and clamping switch that detect the voltage at the output terminal. For this purpose, the detection transistor and the clamping switch, which are actually formed of transistors, need to be formed of, for example, a high-voltage metal-oxide-semiconductor field-effect transistor (MOSFET) with a thick gate oxide film. Therefore, additional manufacturing processes are required, and as a result, manufacturing costs may increase.

[0008] In view of these circumstances, embodiments described later have been made, and other issues and novel features will become clear from the description in this specification and the accompanying drawings.

[0009] A semiconductor device according to one embodiment includes an output transistor, a detection transistor, a first clamping element, and a gate connection circuit. The output transistor is connected between a first power supply terminal supplied with a first power supply voltage and a power output terminal, and when controlled to be on, the output transistor is configured to supply power to a load having a terminal supplied with a second power supply voltage via the power output terminal. The detection transistor is inserted into a path between the first power supply terminal and the power output terminal and is configured to be on when a back electromotive force voltage is generated at the power output terminal, and then the source voltage changes together with the back electromotive force voltage. The first clamping element is configured to limit the gate voltage of the detection transistor to a predetermined clamping voltage with reference to the voltage of the power output terminal. The gate connection circuit is connected to the gate of the detection transistor. The gate connection circuit includes: a first resistive element configured to connect the power output terminal to the gate of the detection transistor; and a rectifier element configured to apply the second power supply voltage to the gate of the detection transistor and to cut off current in the direction from the gate of the detection transistor toward the second power supply voltage.

[0010] According to the above embodiments, manufacturing costs can be reduced in semiconductor devices that supply power to loads and in electronic control systems in which semiconductor devices are installed. Attached Figure Description

[0011] Figure 1 This is a circuit diagram illustrating an example configuration of the main parts of a semiconductor device according to a first embodiment.

[0012] Figure 2 It is shown Figure 1 Timing diagrams illustrating the operation of semiconductor devices.

[0013] Figure 3 This is a diagram illustrating an example of the current-voltage characteristics of a Zener diode, which is... Figure 1 One of the clamping elements in it.

[0014] Figure 4 It is shown that... Figure 2 A diagram showing an example of a detailed power supply voltage waveform associated with a load drop.

[0015] Figure 5 It is shown Figure 1 A cross-sectional view of an example device structure in a semiconductor device.

[0016] Figure 6 It is shown Figure 1 The circuit block diagram shows an example configuration of an electronic control system (ECU) to which the semiconductor devices are applied.

[0017] Figure 7 It shows that it has been installed. Figure 6 A schematic diagram illustrating a vehicle configuration example with an electronic control system (ECU).

[0018] Figure 8 This is a circuit diagram illustrating an example configuration of the main parts of a semiconductor device according to a second embodiment.

[0019] Figure 9 This is a circuit diagram illustrating an example configuration of the main parts of a semiconductor device according to a third embodiment.

[0020] Figure 10 It is shown Figure 9 Timing diagrams illustrating the operation of semiconductor devices.

[0021] Figure 11 It shows how to modify Figure 9 A circuit diagram of an example configuration of a semiconductor device according to the third embodiment.

[0022] Figure 12 This is a circuit diagram illustrating an example configuration of the main parts of a semiconductor device according to a fourth embodiment.

[0023] Figure 13 It is shown Figure 12 Timing diagrams illustrating the operation of semiconductor devices.

[0024] Figure 14 It is a reference. Figure 1 The first comparative example is a circuit diagram of the configuration example of the main parts of a semiconductor device.

[0025] Figure 15 It is shown Figure 14 A cross-sectional view of an example device structure in a semiconductor device.

[0026] Figure 16 It is a reference. Figure 9 The second comparative example is a circuit diagram of the configuration example of the main parts of a semiconductor device. Detailed Implementation

[0027] In the following embodiments, for convenience, the description is divided into multiple parts or embodiments where necessary. However, unless otherwise stated, these parts or embodiments are not unrelated to each other, and one part or embodiment is related to another part or embodiment in some or all of the modifications, details, supplementary descriptions, etc. Furthermore, in the following embodiments, when referring to the quantity of elements, including numbers, values, quantities, ranges, etc., unless otherwise stated or clearly limited to a specific quantity in principle, the quantity is not limited to a specific quantity, and the quantity may be equal to or greater than the specific quantity, or may be equal to or less than the specific quantity.

[0028] Furthermore, in the following embodiments, it is self-evident that components, including element steps, are not necessarily required unless otherwise specified or deemed obviously necessary in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., those components that are substantially similar or analogous in shape are included unless otherwise specified or clearly considered otherwise in principle. This also applies to the numerical values ​​and ranges described above.

[0029] Furthermore, in the following embodiments, the p-channel MOSFET and n-channel MOSFET are referred to as pMOS transistors and nMOS transistors, respectively. In the following, embodiments of the invention will be described in detail with reference to the accompanying drawings. In all the drawings used to describe the embodiments, the same reference numerals are used in principle to denote the same parts, and repeated descriptions will be omitted.

[0030] (First embodiment)

[0031] <Circuit Configuration of Semiconductor Devices>

[0032] Figure 1 This is a circuit diagram illustrating an example configuration of the main parts of the semiconductor device 105 according to the first embodiment. Figure 1 The semiconductor device 105 shown includes a power supply terminal 1, a power output terminal 2, a ground power supply terminal 3, a control input terminal 4, a power transistor (PT) 7, and various control circuits for controlling the power transistor (PT). These control circuits include an on / off control circuit (CTL) 9, a charge pump circuit (CP) 10, a clamping element 11, a gate resistor element 12, a control switch 13, and a protection circuit 41A. Details regarding the protection circuit 41A will be described later.

[0033] Power terminal 1 receives battery voltage Vbat, for example, 12V, from external battery 6 via a power connection. As a result, a power supply voltage (first power supply voltage) VCC is supplied to power terminal 1, i.e., power node N6. Power output terminal 2 is connected to load 8. Load 8 is, for example, an inductive load. One end of load 8 is supplied with a ground power supply voltage (second power supply voltage) PGND. Furthermore, at power output terminal 2, output voltage VOUT and output current IOUT are generated.

[0034] Power transistor (PT) 7 is also an output transistor connected between power supply terminal 1 and power output terminal 2. When controlled to conduct, power transistor (PT) 7 supplies power to load 8 connected to power output terminal 2 via power output terminal 2. In this example, power transistor (PT) 7 is an nMOS transistor. The source and drain of power transistor (PT) 7 are connected to power output terminal 2 and power supply terminal 1, respectively.

[0035] The power transistor (PT) 7 includes a body diode 30 having a source and a back gate that are commonly connected as an anode, and a drain that is a cathode. A clamping element 11, specifically a Zener diode, clamps the gate-source voltage VGSo of the power transistor (PT) 7. As a result, the gate voltage of the power transistor (PT) 7 is limited to prevent excessive increase by the charge pump circuit 10.

[0036] Control input terminal 4 receives an external on / off control signal IN. On / off control circuit 9, in response to the on / off control signal IN, specifically controls charge pump circuit 10 and control switch 13. Control switch 13 is, for example, an nMOS transistor. When controlled to be on, control switch 13 short-circuit the output node N3 of charge pump circuit 10 and power output terminal 2, i.e., power output node N7.

[0037] For example, when the on / off control signal IN is at the on level, the on / off control circuit 9 activates the charge pump circuit 10. As a result, the charge pump circuit 10 generates a boost voltage Vcp higher than the power supply voltage VCC. This boost voltage Vcp is applied to the gate node N4 of the power transistor (PT) 7 via the gate resistor element 12. On the other hand, when the on / off control signal IN is at the off level, the on / off control circuit 9 controls the control switch 13 to be on. As a result, the gate and source are short-circuited via the gate resistor element 12 and the control switch 13, thereby controlling the power transistor (PT) 7 to be off.

[0038] Here, the operation without the protection circuit 41A will be described. When the turn-on / turn-off control signal IN transitions from the on level to the off level, the power transistor (PT) 7 is turned off. At this time, for example, due to the load 8, a back electromotive force voltage is generated at the power output terminal 2, which is a negative voltage lower than the 0V ground supply voltage PGND. On the other hand, since the gate and source are short-circuited through the gate resistor element 12 and the control switch 13, the power transistor (PT) 7 remains off.

[0039] As a result, the power transistor (PT) 7 can clamp the drain-source voltage based on the clamping voltage (in other words, the Zener voltage) of the body diode 30, and thus clamp the back electromotive force voltage generated at the power output terminal 2. Furthermore, the power transistor (PT) 7 can dissipate the flyback energy associated with the back electromotive force voltage via the body diode 30. This clamping operation is called avalanche clamping operation, etc.

[0040] However, a problem may occur during the period when the back electromotive force voltage is generated at the power output terminal 2, when the turn-on / off control signal IN transitions from the off level to the on level. In this case, due to the turn-off of control switch 13 and the activation of charge pump circuit 10, power transistor (PT) 7 is turned on with a high drain-source voltage applied. As a result, power transistor (PT) 7 may deviate from its safe operating area (SOA) and be damaged. Therefore, protection circuit 41A is provided to keep power transistor (PT) 7 off even in this situation.

[0041] <Protection circuit as a comparative example>

[0042] Before describing the protection circuit 41A, a protection circuit as a first comparative example will be described here. Figure 14 It is a reference. Figure 1 The first comparative example is a circuit diagram of the configuration example of the main parts of the semiconductor device 300. Figure 14 The semiconductor device 300 shown has a protection circuit 41C, which has a connection with... Figure 1 The protection circuits of the semiconductor device 105 shown have different configurations. Figure 14 The protection circuit 41C shown includes a detection transistor 15, a Zener diode 14, pMOS transistors 31 and 32, an nMOS transistor 33, and a control switch 34.

[0043] A detection transistor 15 is inserted into the path between the power supply terminal (first power supply terminal) 1 and the power output terminal 2. The detection transistor 15 is generally configured to turn on when a back electromotive force voltage is generated at the power output terminal 2, and then the source voltage changes together with the back electromotive force voltage.

[0044] Specifically, the detection transistor 15 is formed of, for example, an nMOS transistor. The source and back gate of the detection transistor 15 are connected to the power output terminal 2. The gate of the detection transistor 15 is connected to the ground power supply terminal 3. A ground power supply voltage (second power supply voltage) SGND of 0V is applied to the ground power supply terminal 3. As a result, when a negative voltage is generated at the power output terminal 2, specifically, when a gate-source voltage VGSd equal to or higher than the threshold voltage is generated due to this negative voltage, the detection transistor 15 turns on. When turned on, the detection transistor 15 causes the detection current Idet to flow.

[0045] Zener diode 14 is inserted into the path between power supply terminal 1, i.e., power node N6, and the drain of detection transistor 15. Zener diode 14 determines the upper limit of the output voltage VOUT required to enable protection circuit 41C. That is, when the output voltage VOUT drops below the Zener voltage of Zener diode 14 relative to the power supply voltage VCC, protection circuit 41C enters an enabled state. As a result, for example, when a negative voltage of noise level that is not a back EMF voltage is generated, protection circuit 41C can be kept disabled, thereby preventing protection circuit 41C from being unnecessarily enabled.

[0046] As a specific example, the clamping voltage of the body diode 30 is 40V, etc. On the other hand, the Zener voltage of the Zener diode 14 is set to 18V, etc. With the power supply voltage VCC at 12V, the protection circuit 41C enters the enabled state when the output voltage VOUT drops below -6V. Furthermore, at the moment when the detection transistor 15 enters the enabled state, the detection transistor 15 is in the on state because a gate-source voltage VGSd of 6V is applied. Note that the protection circuit 41C needs to be enabled at least before the avalanche clamping operation of the body diode 30 begins. Therefore, the Zener voltage of the Zener diode 14 is determined to be lower than the clamping voltage of the body diode 30.

[0047] pMOS transistors 31 and 32 form a current mirror circuit. pMOS transistor 31, acting as a replication source, replicates the detection current Idet flowing through detection transistor 15 to pMOS transistor 32, which acts as the replication destination. nMOS transistor 33 is connected between node N10, which serves as the drain of pMOS transistor 32, and power output node N7. nMOS transistor 33 is, for example, a depletion-type transistor, with its gate and source short-circuited, and functions as a current source or a high-resistivity element. nMOS transistor 33 also acts as a voltage converter, transforming the current replicated to node N10 into a voltage.

[0048] The control switch (first control switch) 34 is controlled to be turned on / off by the voltage converted by the nMOS transistor 33. When controlled to be on, that is, when the detection current Idet responds to a negative voltage flowing through the detection transistor 15, the control switch 34 short-circuits the gate and source of the power transistor (PT) 7. The control switch 34 is formed by an nMOS transistor, the source of which is connected to the power output node N7 and the gate node N4, respectively.

[0049] By providing such a protection circuit 41C, as described above, even during the period when the back EMF voltage is generated at the power output terminal 2, when the on / off control signal IN transitions from the off level to the on level, as long as the back EMF voltage is generated, the control switch 34 can be held in the on state. As a result, since the power transistor (PT) 7 can be held in the off state, damage to the power transistor (PT) 7 can be prevented.

[0050] However, in Figure 14 In the configuration example shown, a high gate-source voltage VGSd can be applied to the sensing transistor 15. For example, with a supply voltage VCC of 12V and a body diode clamping voltage of 40V, the output voltage VOUT is -28V during the avalanche clamping operation. In this case, the gate-source voltage VGSd is +28V. Therefore, the sensing transistor 15 needs to be formed of a high-voltage MOS transistor.

[0051] <Device structure as a comparison example>

[0052] Figure 15 It is shown Figure 14 A cross-sectional view of an example device structure in the semiconductor device 300 shown. Figure 15 The diagram shows a unit output transistor PTu, a pMOS transistor MP-L, and a low-voltage nMOS transistor MN-L, as well as a pMOS transistor MP-H2 and a high-voltage-tolerance nMOS transistor MN-H2. Specifically, the power transistor (PT) 7 is formed by multiple unit output transistors PTu connected in parallel with each other. Figure 15 One of a plurality of unit output transistors PTU is shown. Furthermore, Figure 1 The various control circuits shown are formed using pMOS transistors MP-L and MP-H2, as well as nMOS transistors MN-L and MN-H2.

[0053] exist Figure 15In this process, an N-type epitaxial layer 502 is formed on an N-type semiconductor substrate 501. Unit output transistors PTu, MP-L, and MP-H2, as well as nMOS transistors MN-L and MN-H2, are formed using a diffusion layer or similar material disposed on the surface of the epitaxial layer 502. Furthermore, the unit output transistors PTu, MP-L, and MP-H2, as well as the nMOS transistors MN-L and MN-H2, are separated from each other by a thick oxide film 503 (LOCOS).

[0054] The unit output transistor PTu is formed from a vertical nMOS transistor with the back surface of the semiconductor substrate 501 as the drain. Specifically, a P-type base diffusion layer 505 serving as the back gate (BG) is formed on the surface of the epitaxial layer 502. In the P-type base diffusion layer 505, an N-type gate for supplying power to the back gate (BG) is formed. + Type-S source (S) diffusion layer 510 and P + Type power diffusion layer 511. Epitaxial layer 502 and semiconductor substrate 501 serve as drain (D). Power supply voltage VCC is supplied to drain (D), i.e., the back surface of semiconductor substrate 501.

[0055] A trench 509 extending in the depth direction is formed in the epitaxial layer 502. A thin gate oxide film 506 and polysilicon 508, serving as the gate (G), are embedded in the trench 509. A source (S) diffusion layer 510 is formed at a location in contact with the sidewall of the trench 509. When a predetermined voltage is applied between the gate (G) and the source (S), a channel is formed at a location on the sidewall of the trench 509 located in the P-type base diffusion layer 505. As a result, a drive current flows from the back surface of the semiconductor substrate 501 to the source (S) diffusion layer 510.

[0056] In the low-voltage pMOS transistor MP-L, on the surface of the epitaxial layer 502, P + Type-type source (S) diffusion layer 511 and drain (D) diffusion layer 511 and N for back gate + A power diffusion layer 510 is formed. On the epitaxial layer 502 located between the source (S) diffusion layer 511 and the drain (D) diffusion layer 511, a polysilicon 508 serving as the gate (G) is formed via a thin gate oxide film 506.

[0057] In the low-voltage specification nMOS transistor MN-L, P - A deep diffusion layer 504, i.e., a p-well, is formed from the surface of the epitaxial layer 502. - In the type diffusion layer 504, N + Type-s 510 source (S) diffusion layer and drain (D) diffusion layer 510, and P for back gate+ A power diffusion layer 511 is formed. On the epitaxial layer 502 located between the source (S) diffusion layer 510 and the drain (D) diffusion layer 510, a polysilicon 508 serving as the gate (G) is formed via a thin gate oxide film 506. Note that the low-voltage pMOS transistor MP-L and nMOS transistor MN-L have a withstand voltage of, for example, about 6V.

[0058] In the high-voltage pMOS transistor MP-H2, the P-type gate is used for the back gate. + Type-3 source (S) diffusion layer 511 and N + A power diffusion layer 510 is formed on the surface of the epitaxial layer 502. On the other hand, on the drain (D) side, P... - A deep diffusion layer 512 is formed from the surface of the epitaxial layer 502. + Type D drain (D) diffusion layer 511 in P - It is formed in the diffusion layer 512.

[0059] On the epitaxial layer 502 located between the source (S) diffusion layer 511 and the drain (D) diffusion layer 511, a polysilicon 508 serving as the gate (G) is formed via a thick gate oxide film 507. In this manner, the thickness TH2 of the gate oxide film 507 used in the high-voltage specification is greater than the thickness TH1 of the gate oxide film 506 used in the low-voltage specification. Furthermore, unlike the low-voltage specification, the gate oxide film 507 and the polysilicon 508 near the drain (D) are formed on a thick oxide film 503 to achieve high withstand voltage.

[0060] In the high-voltage specification nMOS transistor MN-H2, P - A deep diffusion layer 504 (i.e., a p-well) is formed from the surface of the epitaxial layer 502. - In the type diffusion layer 504, N + Type source (S) diffusion layer 510 and P for back gate + A type power diffusion layer 511 is formed. On the other hand, on the drain (D) side, N... - A deep diffusion layer 513 is formed from the surface of the epitaxial layer 502. + Type D drain (D) diffusion layer 510 in N - It is formed in the diffusion layer 513.

[0061] On the epitaxial layer 502 located between the source (S) diffusion layer 510 and the drain (D) diffusion layer 510, a polysilicon 508 serving as the gate (G) is formed via a thick gate oxide film 507. Similar to the pMOS transistor MP-H2, the thickness TH2 of the gate oxide film 507 is greater than the thickness TH1 used in the low-voltage specification. Furthermore, the polysilicon 508 near the gate oxide film 507 and the drain (D) is formed on a thick oxide film 503 to achieve high withstand voltage.

[0062] Note that, as Figure 15 As shown, the NPN parasitic bipolar transistor 50 can be formed within the nMOS transistor MN-H2. The parasitic bipolar transistor 50 uses N... + Type D drain (D) diffusion layer 510 and N - Type 513 deep diffusion layer as emitter, P + Type 511 power diffusion layer and P - A deep-diffused 504 layer serves as the base, and N... - The semiconductor substrate 501 and epitaxial layer 502 operate as collectors. Although not shown, parasitic bipolar transistors can also be formed in nMOS transistors MN-L.

[0063] In the device structure described above, the detection transistor 15 needs to be formed from, for example, a high-voltage nMOS transistor M-H2. Furthermore, most other transistors can be formed from low-voltage pMOS transistors MP-L and nMOS transistors MN-L. Therefore, during manufacturing, the steps of forming a gate oxide film 506 with a thin film thickness TH1 and forming a gate oxide film 507 with a thick film thickness TH2 are required separately. As a result, manufacturing costs may increase.

[0064] <Protection circuit according to the embodiment>

[0065] Therefore, it provides Figure 1 The protection circuit 41A is shown. Besides being related to... Figure 14 In addition to the same components as the protection circuit 41C shown, the protection circuit 41A also includes a clamping element 16, a gate connection circuit 42, and a clamping element 35. The clamping element (first clamping element) 16, specifically a Zener diode, limits the gate voltage of the detection transistor 15 to a predetermined clamping voltage referenced to the output voltage VOUT. That is, the clamping element 16 clamps the gate-source voltage VGSd and the gate-back gate voltage of the detection transistor 15.

[0066] Clamping element (second clamping element) 35, specifically a Zener diode, limits the gate-source voltage VGSc2 of control switch (first control switch) 34 to a predetermined clamping voltage. That is, when a back electromotive force voltage is generated at power output terminal 2, a high voltage may be generated not only in detection transistor 15 but also between the gate and source of control switch 34. Therefore, clamping element 35 is provided. Note that the voltage of clamping element 16 and the clamping voltage of clamping element 35, i.e., the Zener voltage, are, for example, 6V, etc.

[0067] A gate connection circuit 42 is connected to the gate of the detection transistor 15. The gate connection circuit 42 includes two resistive elements 17 and 18 and an nMOS transistor 19 as a rectifier. The resistive element (first resistive element) 18 connects the power output terminal 2 to the gate of the detection transistor 15. The nMOS transistor 19 applies a ground supply voltage (second supply voltage) SGND to the gate of the detection transistor 15 and cuts off the current flowing from the gate of the detection transistor 15 towards the ground supply voltage SGND.

[0068] In this example, the gate and source of nMOS transistor 19 are short-circuited. Furthermore, the source and back gate of nMOS transistor 19 are connected together. As a result, nMOS transistor 19 functions as a diode with its source and back gate as anodes and its drain as cathode.

[0069] Specifically, nMOS transistor 19 is a diode element that uses a body diode between the back gate and the drain, and it is also a diode-connected transistor, such that the source is replaced by the drain. The nMOS transistor 19, acting as a diode, applies the ground supply voltage SGND, which has been input to the anode, from the cathode to the gate of the detection transistor 15. Furthermore, the nMOS transistor 19, acting as a diode, interrupts the current flowing from the cathode to the anode.

[0070] A resistive element (second resistive element) 17 is connected in series with the nMOS transistor 19. Specifically, the resistive element 17 is connected between the drain of the nMOS transistor 19 and node N8, which serves as the gate of the detection transistor 15. Although described in detail later, the resistive element 17 is provided to limit the current flowing from the ground supply voltage SGND through the gate of the detection transistor 15 to the clamping element 16.

[0071] In the above configuration, firstly, a clamping element 16 is provided such that the upper limit of the gate-source voltage VGSd and the upper limit of the gate-back gate voltage of the detection transistor 15 can be limited to 6V, etc. As a result, the detection transistor 15 can be formed from an nMOS transistor with a thin gate oxide film. However, for example, simply adding the clamping element 16... Figure 14The construction example shown may not cause problems in avalanche clamping operations, but rather problems in normal operations.

[0072] That is, during normal operation, when the power transistor (PT) 7 is controlled to be turned on, the path current flows from the power output terminal 2, where the actual power supply voltage VCC is applied, through the positive clamping element 16 to the ground power supply terminal 3, where the ground power supply voltage SGND is applied. In response to this, Figure 1 In this configuration, an nMOS transistor 19 is provided that functions as a diode. This prevents the current from flowing through the diode. Note that a standard diode can be used instead of the nMOS transistor 19.

[0073] On the other hand, the nMOS transistor 19, which functions as a diode, is reverse-biased during the period when no negative voltage is generated at the power output terminal 2. During this period, node N8, which serves as the gate of the detection transistor 15, can be maintained at a voltage higher than the ground supply voltage SGND, such as the actual supply voltage VCC, via the forward clamping element 16. As a result, even during the period when no negative voltage is generated at the power output terminal 2, such as during the period when the power transistor (PT) 7 is in the on state, the detection transistor 15 can still be turned on.

[0074] Therefore, in Figure 1 The circuit includes a resistor 18 connecting the power output terminal 2 and node N8. This allows the power output terminal 2 and node N8 to be short-circuited during periods when no negative voltage is generated at the power output terminal 2, i.e., during periods when the nMOS transistor 19, which acts as a diode, is reverse-biased. As a result, the detection transistor 15 can be kept off.

[0075] <Operation of Semiconductor Devices>

[0076] Figure 2 It is shown Figure 1 A timing diagram illustrating an example of the operation of semiconductor device 105. Figure 2 In the middle, for comparison, it is also shown when using Figure 14 The gate-source voltages VGSd and VGSc2 are shown in the configuration example. Furthermore, Figure 2 Four time periods, T1 to T4, are shown. Time period T1 is the period when power transistor (PT) 7 is in the off state. Time period T2 is the period after power transistor (PT) 7 is turned on. Time period T3 is the period after power transistor (PT) 7 is turned off. Time period T4 is the period when a load drop occurs.

[0077] [Time period T1 (PT: Off)]

[0078] Control input terminal 4 receives an "L" level, i.e., an on / off control signal IN, which is at the off level. In response, the on / off control circuit 9 controls the control switch 13 to turn on by outputting an "H" level (i.e., gate-source voltage VGSc1) to node N5. Furthermore, the on / off control circuit 9 controls the charge pump circuit 10 to remain inactive by outputting an "L" level to node N2. When the gate-source voltage VGSo becomes 0V, the power transistor (PT) 7 turns off in response to the on of control switch 13.

[0079] On the other hand, in response to the power transistor (PT) 7 being turned off, the output voltage VOUT generated at the power output node N7 becomes the ground supply voltage PGND. At this time, the gate voltage of the detection transistor 15, i.e., the voltage at node N8, becomes equal to the voltage at the power output node N7 via the resistor element 18. As a result, when the gate-source voltage VGSd becomes 0V, the detection transistor 15 is brought into the off state.

[0080] [Time Period T2 (PT): Conduction Phase and Conduction Status]

[0081] Control input terminal 4 receives an "H" level, i.e., an on / off control signal IN at the conduction level. In response, the on / off control circuit 9 controls the control switch 13 to turn off by outputting an "L" level (i.e., gate-source voltage VGSc1) to node N5. Furthermore, the on / off control circuit 9 controls the charge pump circuit 10 to be active by outputting an "H" level to node N2. As a result, a boost voltage Vcp is applied to the gate node N4 of the power transistor (PT) 7. When the gate-source voltage VGSo at the conduction level is applied, the power transistor (PT) 7 turns on.

[0082] The output voltage VOUT is made to a level substantially the same as the supply voltage VCC by the power transistor (PT) 7, which is in the on state. At this time, the gate voltage of the detection transistor 15, i.e., the voltage at node N8, is made equal to the voltage at the power output node N7 via the resistor element 18. As a result, when the gate-source voltage VGSd becomes 0V, the detection transistor 15 is turned off. On the other hand, when Figure 14 When the configuration example shown is used, the gate-source voltage VGSd becomes the turn-off voltage with the same magnitude as the output voltage VOUT (i.e., the supply voltage VCC).

[0083] In addition, such as Figure 1As shown, when an nMOS transistor 19 is provided as a diode, no particular problem occurs even if the output voltage VOUT becomes substantially the same level as the power supply voltage VCC in this way. That is, the current flowing from the power output terminal 2 toward the ground power supply terminal 3 via the clamping element 16 or via the resistive elements 18 and 17 can be cut off by the nMOS transistor 19, which acts as a diode.

[0084] [Time Period T3 (PT: Shutdown Phase and Shutdown State)]

[0085] Control input terminal 4 again receives the on / off control signal IN at the "L" level. In response, as in time period T1, control switch 13 is turned on, and charge pump circuit 10 enters an inactive state, causing power transistor (PT) 7 to turn off. At this time, the flyback energy accumulated in load 8 is released. Due to the back electromotive force voltage at this time, the output voltage VOUT becomes negative. As a result, avalanche clamping operation is performed.

[0086] Based on the clamping voltage Vclp (i.e., Zener voltage Vz30) of the body diode 30 of the power transistor (PT) 7, the output voltage VOUT is clamped to prevent it from falling below a predetermined negative voltage Vn. Avalanche clamping operation is maintained as long as the power transistor (PT) 7 is in the off state. During avalanche clamping operation, flyback energy is released through the body diode 30. Then, when the flyback energy is fully released, the output voltage VOUT becomes the ground supply voltage PGND.

[0087] However, as Figure 2 As shown, when the on / off control signal IN becomes "H" level during avalanche clamping operation, control switch 13 is turned off, and charge pump circuit 10 is brought into an active state. As a result, if power transistor (PT) 7 is turned on, avalanche clamping operation cannot be maintained. Furthermore, since power transistor (PT) 7 is turned on when a high drain-source voltage is applied, power transistor (PT) 7 has an operating point outside its safe operating area (SOA). In this situation, power transistor (PT) 7 may be damaged due to thermal runaway.

[0088] On the other hand, when the protection circuit 41A is provided, even in this case of avalanche clamping operation, i.e., the off state of the power transistor (PT) 7 can be maintained. Specifically, firstly, when the output voltage VOUT becomes negative, current flows from the ground power supply terminal 3 through the power output node N7 and the load 8. As a result, the gate voltage of the detection transistor 15, i.e., the voltage of node N8, becomes the voltage obtained when the ground power supply voltage SGND (0V) drops below the forward voltage of the body diode of the nMOS transistor 19, for example, 0.6V.

[0089] As a result, the detection transistor 15 is brought into the on state because the gate-source voltage VGSd becomes the on level. At this time, the gate-source voltage VGSd of the detection transistor 15 is limited by the clamping voltage of the clamping element 16, i.e., the 6V Zener voltage Vz16. On the other hand, when Figure 14 When the configuration example shown is used, the gate-source voltage VGSd becomes a turn-on voltage with the magnitude of the negative voltage Vn generated at the power output node N7, such as 28V.

[0090] When the detection transistor 15 is brought to the ON state, node N10, which serves as the replication destination for the current mirror circuit, becomes "H" level. As a result, the gate-source voltage VGSc2 of the control switch 34 becomes ON level. At this time, the gate-source voltage VGSc2 is limited by the clamping voltage of the clamping element 35 (i.e., a Zener voltage Vz35 of 6V, etc.). On the other hand, when Figure 14 When the configuration example shown is used, the gate-source voltage VGSc2 can be a turn-on voltage greater than the negative voltage Vn.

[0091] When the gate-source voltage VGSc2 becomes on, the control switch 34 is turned on. As long as the detection transistor 15 is on, the control switch 34 remains on, and therefore the output voltage VOUT is negative. As long as the control switch 34 is on, the gate-source voltage VGSo of the power transistor (PT) 7 is 0V. Consequently, as long as the output voltage VOUT is negative, the power transistor (PT) 7 remains off independently of the on / off control signal IN and maintains avalanche clamp operation.

[0092] Here, when the output voltage VOUT becomes negative, the current path from the ground power supply terminal 3 to the power output terminal 2 includes a path via the resistive element 18 and a path via the clamping element 16. At this time, if the current flowing through the clamping element 16 increases, the clamping voltage may increase due to the operating resistance.

[0093] Figure 3 This is a diagram illustrating an example of the current-voltage characteristics of a Zener diode, which is... Figure 1 One of the clamping elements in [the system]. For example... Figure 3 As shown, when the Zener current Iz flowing through the Zener diode increases from "IzA" to "IzB", the Zener voltage Vz also increases from "VzA" to "VzB". In this way, when the clamping voltage of the clamping element 16 increases, the gate-source voltage VGSd of the detection transistor 15 may exceed its withstand voltage. Therefore, in Figure 1 A resistor element 17 is provided. As a result, the Zener current Iz flowing through the clamping element 16 can be limited, and fluctuations in the clamping voltage can be suppressed.

[0094] [Time Period T4 (Sudden Load Drop)]

[0095] During time period T4, when power transistor (PT) 7 is in the off state, a high-voltage surge occurs at power terminal 1 (i.e., power node N6). One type of power surge is known as a load sag high-voltage surge. Figure 4 It is an explanation and Figure 2 A diagram illustrating a detailed power supply voltage waveform associated with a load sag. (See diagram for example.) Figure 4 As shown, due to a load drop, the power supply voltage VCC increases from 12V to a predetermined load drop voltage VLD, and then returns to approximately 12V after a time constant τ of approximately 400ms.

[0096] Similarly, when a load sag occurs, a high voltage is applied between the drain and source of power transistor (PT) 7, as if a back electromotive force voltage were generated. However, if power transistor (PT) 7 also performs avalanche clamping operation during a load sag, it may be damaged due to the high energy. Therefore, by... Figure 1 The circuitry, not shown, employs countermeasures to handle load drops. In parallel, the detection transistor 15 needs to be kept off to respond to load drops. Figure 1 The detection transistor 15 shown is configured to remain off when there is a positive voltage fluctuation at power node N6.

[0097] <Device structure according to the embodiment>

[0098] Figure 5 It is shown Figure 1 A cross-sectional view of an example device structure in the semiconductor device 105 shown. Figure 5 The structures of the high-voltage pMOS transistor MP-H1 and nMOS transistor MN-H1 shown are similar to... Figure 15 The differences are shown. Specifically, the high-voltage pMOS transistor MP-H1 and nMOS transistor MN-H1 include a thin gate oxide film 506 with a film thickness TH1, instead of... Figure 15 The thick gate oxide film 507 shown has a film thickness TH2.

[0099] That is, a clamping element 16 is provided so that the gate-source voltage VGSd and the gate-back gate voltage of the detection transistor 15 can be detected as follows: Figure 2The constraint shown is that the gate-source voltage VGSc2 and the gate-back gate voltage of the control switch 34 can be constrained. Therefore, the detection transistor 15 and the control switch 34 can be implemented using an nMOS transistor MN-H1 with a thin gate oxide film 506. As a result, with... Figure 15 In different cases, the step of forming a gate oxide film 507 with a thick film thickness TH2 during the manufacturing process is not required, thereby reducing manufacturing costs.

[0100] <Application Examples of Electronic Control Systems (ECUs)>

[0101] Figure 6 It is shown Figure 1 The circuit block diagram shown is an example of a configuration in which semiconductor devices are applied to an electronic control system (ECU). Besides... Figure 1 In addition to the semiconductor device 105 shown, Figure 6 The illustrated electronic control system (ECU) 401 includes a power regulator 404 and a diode 403, as well as an ECU control unit 402 (here, a microcontroller unit (MCU)). The electronic control system (ECU) 401 may include a terminal block, etc., for mounting these components.

[0102] Furthermore, the electronic control system (ECU) 401 includes a power supply terminal 1A, a ground power supply terminal 3A, and a power output terminal 2A. The battery 6 is connected between the power supply terminal 1A and the ground power supply terminal 3A. A load is connected to the power output terminal 2A. In this example, the loads are the headlight loads 8a to 8c. Loads 8a to 8c have another end supplied with the ground power supply voltage PGND.

[0103] Power terminal 1A receives the battery voltage Vbat. Power regulator 404 receives the power supply voltage VCC obtained at power terminal 1A and generates a low-voltage power supply voltage for ECU control unit 402. The generated power supply voltage is supplied to ECU control unit 402 via diode 403. Furthermore, the ground power supply voltage SGND of battery 6 is supplied to one end of ECU control unit 402 via ground power terminal 3A. Diode 403 serves to protect ECU control unit 402 and prevents reverse current from flowing through ECU control unit 402 when battery 6 is reverse-connected or otherwise.

[0104] The power supply voltage VCC from the power supply terminal 1A of the electronic control system (ECU) 401 is supplied to the power supply terminal 1 of the semiconductor device 105. The power output terminal 2 of the semiconductor device 105 is connected to the power output terminal 2A of the electronic control system (ECU) 401. In addition, the ground power supply voltage SGND is supplied to the ground power supply terminal 3 of the semiconductor device 105 via the ground power supply terminal 3A of the electronic control system (ECU) 401.

[0105] The output port of the ECU control unit 402 is connected to the control input terminal 4 of the semiconductor device 105. The ECU control unit 402 outputs an on / off control signal IN to the semiconductor device 105 to indicate the on / off state of the power transistor (PT) 7. The semiconductor device 105 controls the power supply to the lamp loads 8a to 8c based on the on / off control signal IN from the control input terminal 4. Here, for example, when the back electromotive force voltage is generated at the power output terminal 2A and the power supply to the lamp loads 8a to 8c is stopped, the semiconductor device 105 performs an avalanche clamping operation.

[0106] Then, even during avalanche clamping operation, when the on / off control signal IN becomes "H", the semiconductor device 105 can maintain avalanche clamping operation, that is, the power transistor (PT) 7 is turned off. As a result, the power transistor (PT) 7 can be properly protected within the safe operating area (SOA). Therefore, the reliability of the electronic control system (ECU) 401 can be improved.

[0107] Figure 7 It shows that it has been installed. Figure 6 This is a schematic diagram illustrating an example configuration of the electronic control system (ECU) 401 in vehicle 109. Vehicle 109 is, for example, an automobile. Figure 7 The vehicle 109 shown is equipped with battery 6, electronic control system 401, and such as Figure 6 The lamp loads 8a to 8c are shown. For example, the rated power of lamp loads 8a, 8b, and 8c are 21W, 5W, and 21W, respectively.

[0108] The electronic control system 401 and the lamp loads 8a to 8c are connected via a wiring harness. More specifically, two sets of lamp loads 8a to 8c are provided for right turn and left turn. Accordingly, the electronic control system (ECU) 401 can be configured such that one ECU controller 402 controls two semiconductor devices 105. Figure 6 The grounding power supply voltage PGND shown is connected to the housing of vehicle 109, for example.

[0109] <Main Effects of the First Embodiment>

[0110] As described above, the semiconductor device 105 according to the first embodiment includes a detection transistor 15 for detecting the back electromotive force voltage from the load 8, a clamping element 16 for clamping the gate-source voltage VGSd, and a gate connection circuit 42 connected to the gate of the detection transistor 15. This allows avalanche clamping operation to be achieved without damaging the output transistor while the detection transistor 15 is formed using a thin gate oxide film 506. As a result, manufacturing costs can be reduced.

[0111] (Second Embodiment)

[0112] <Circuit Configuration of Semiconductor Devices>

[0113] Figure 8 This is a circuit diagram illustrating an example configuration of the main parts of the semiconductor device 106 according to the second embodiment. Figure 8 In the semiconductor device 106 shown, the configuration of the protection circuit 41B (specifically, the gate connection circuit 43) differs from that of the other devices. Figure 1 The configuration is shown. In the gate connection circuit 43, more specifically, the nMOS transistor 19 includes a configuration as shown... Figure 15 The vertically structured NPN parasitic bipolar transistor 50 uses the drain of an nMOS transistor 19 as its emitter, and the source and back gate as... Figure 8 The base of the parasitic bipolar transistor 50 is used for operation. The collector of the parasitic bipolar transistor 50 is connected to the power supply node N6.

[0114] Here, for example, suppose in Figure 2 The operation was performed during the time period T3 shown, i.e., the negative voltage period, provided that... Figure 1 The configuration example shown includes a parasitic bipolar transistor 50. In this case, forward current flows through the body diode of nMOS transistor 19 using the source and back gate as anodes and the drain as cathode. As a result, parasitic bipolar transistor 50 can turn on. Then, the drain voltage of nMOS transistor 19 rises towards the supply voltage VCC. Consequently, the gate-source voltage VGSd of detection transistor 15 may become too high due to the increased current flowing through clamping element 16.

[0115] In response to this issue, Figure 8 In this configuration, the resistive element (third resistive element) 21 and the clamping element 20 are connected to the nMOS transistor 19. (As shown in...) Figure 1 In this case, the ground supply voltage SGND is applied to the gate of nMOS transistor 19. However, with Figure 1In the opposite case, the ground supply voltage SGND is applied to the source of the nMOS transistor 19 via resistor element 21. Resistor element 21 can be made of, for example, polysilicon. Furthermore, clamping element 20 (specifically, Zener diode) limits the gate-source voltage of the nMOS transistor 19 to a predetermined clamping voltage.

[0116] In this configuration, when the output voltage VOUT becomes negative due to the back electromotive force, current flows from the ground power supply terminal 3 sequentially through resistor 21, the body diode of nMOS transistor 19, and resistors 17 and 18 to the power output node N7. At this time, a voltage drop occurs in resistor 21. When this voltage drop exceeds the threshold voltage of nMOS transistor 19, nMOS transistor 19 turns on. The drain-source voltage of the nMOS transistor decreases due to conduction. As a result, the parasitic bipolar transistor 50 can remain off with a relatively small base-emitter voltage.

[0117] <Main Effects of the Second Embodiment>

[0118] As described above, by using the semiconductor device 106 according to the second embodiment, the same effects as those described in the first embodiment can also be obtained. Furthermore, when a back electromotive force voltage is generated at the power output terminal 2, the parasitic bipolar transistor 50 of the nMOS transistor 19 can remain in the off state. As a result, problems related to the conduction of the parasitic bipolar transistor 50 can be prevented. Specifically, it is possible to prevent a breach in the withstand voltage of the detection transistor 15 due to an increase in the clamping voltage of the clamping element 16.

[0119] (Third embodiment)

[0120] <Circuit Configuration of Semiconductor Devices>

[0121] Figure 9 This is a circuit diagram illustrating an example configuration of the main parts of the semiconductor device 205 according to the third embodiment. Figure 16 This is shown as a reference. Figure 9 The second comparative example is a circuit diagram illustrating the configuration of the main parts of the semiconductor device 305. First, to facilitate understanding of the invention, Figure 16 In Figure 9 Previously described. As Figure 16 The semiconductor device 305 in the second comparative example shown includes a dynamic clamping circuit 40D, instead of Figure 1 The protection circuit 41A is shown. Other configurations are the same as... Figure 1 The configuration is the same as in [the other section], so a detailed description is omitted.

[0122] here, Figure 1The protection circuit 41A shown is used to prevent problems when the semiconductor device 105 performs an avalanche clamping operation, that is, when in situations such as Figure 2 The circuit shown addresses the problem when the on / off control signal IN changes to "H" level during the negative voltage period. On the other hand, the dynamic clamping circuit 40D is used to enable the semiconductor device 305 to perform a dynamic clamping operation different from avalanche clamping operation.

[0123] The dynamic clamping circuit 40D includes a clamping element 64 and a detection transistor 65. (As in...) Figure 1 In this case, the detection transistor 65 is inserted into the path between power supply terminal 1 (i.e., power node N6) and power output terminal 2 (i.e., power output node N7). The detection transistor 65 is configured to turn on when a back electromotive force voltage is generated at power output terminal 2, and then the source voltage changes together with the back electromotive force voltage. Specifically, the detection transistor 65 is formed of an nMOS transistor with a gate to which the ground supply voltage SGND is applied.

[0124] However, with Figure 1 In this case, the source of the detection transistor 65 is connected to the gate node N4 of the power transistor (PT) 7. The back gate of the detection transistor 65 is connected to the power output terminal 2 (i.e., the power output node N7), as shown below. Figure 1 In this case, a clamping element (third clamping element) 64 is inserted into the path between the power supply node N6 and the drain of the detection transistor 65. The clamping element 64, specifically a Zener diode, is provided to limit the back electromotive force voltage generated at the power output terminal 2 to a predetermined clamping voltage.

[0125] In dynamic clamping operation, the back electromotive force voltage is not clamped by the body diode of power transistor (PT) 7, but by the clamping voltage of clamping element 64 and the gate-source voltage VGSo of power transistor (PT) 7 in a weakly conducting state. The flyback energy associated with the back electromotive force voltage is dissipated due to the on-resistance of power transistor (PT) 7 in a weakly conducting state.

[0126] Here, the gate-source voltage VGSo of the power transistor (PT) 7 is determined by the gate resistor element 12 and the control switch (second control switch) 13. Specifically, when the control switch 13 is turned on in response to the on / off control signal IN transitioning to the off level, the control switch 13 connects the gate node N4 of the power transistor (PT) 7 to the power output node N7 via the gate resistor element 12. In this state, a voltage drop occurs when current flows through the gate resistor element 12. The gate-source voltage VGSo is determined by this voltage drop.

[0127] As a concrete example, assume the power supply voltage VCC is 12V and the clamping voltage of clamping element 64 (i.e., Zener voltage Vz64) is 33.5V. First, when power transistor (PT) 7 is turned off, a back electromotive force (i.e., a negative voltage) is generated at power output terminal 2. At this time, due to gate resistor element 12 and the control switch 13 being in the on state, the gate voltage of power transistor (PT) 7 decreases along with the decrease in output voltage VOUT.

[0128] Here, when the gate voltage of power transistor (PT) 7 drops to -21.5V with reference to the 12V supply voltage VCC and a Zener voltage Vz64 of 33.5V, the gate voltage is clamped to -21.5V by clamping element 64 and the detection transistor 65 in the on-state. At this time, a voltage drop of approximately 1.5V occurs at the gate resistor element 12, for example, due to the current flowing through the detection transistor 65. As a result, the output voltage VOUT is clamped to -23V. For example, power transistor (PT) 7 is brought into a weak on-state by applying a gate-source voltage VGSo of approximately 1.5V relative to a threshold voltage of approximately 1.0V.

[0129] In the configuration and operation described above, as in the first embodiment, a high voltage can be applied between the gate and back gate of the detection transistor 65. In response, a high voltage can also be applied between the gate and source of the detection transistor 65. For example, the gate-back gate voltage VGBd can be 23V. Furthermore, the gate-source voltage VGSd can be 21.5V. As a result, as in the first embodiment, a step of forming a thick gate oxide film during manufacturing is required, which may increase manufacturing costs.

[0130] In response to this issue, the following was provided: Figure 9 The dynamic clamping circuit shown is 40A. Besides... Figure 16 In addition to the same clamping element 64 and detection transistor 65, the dynamic clamping circuit 40A also includes... Figure 1 The same clamping element 16 and gate connection circuit 42 are used. In short, clamping element 16 limits the gate voltage of detection transistor 65 to a predetermined clamping voltage, such as 6V, based on the output voltage VOUT of power output terminal 2. As a result, the gate-back gate voltage VGBd of detection transistor 65 is clamped, and consequently, the gate-source voltage VGSd is also clamped.

[0131] The gate connection circuit 42 includes resistor elements 17 and 18, and an nMOS transistor 19 as a rectifier. The nMOS transistor 19 applies the ground supply voltage SGND to the gate of the detection transistor 65 and cuts off the current from the gate of the detection transistor 65 toward the ground supply voltage SGND. Therefore, when the power transistor (PT) 7 is in the on state, the current path from the power output terminal 2 to the ground supply terminal 3 via the clamping element 16 can be cut off.

[0132] Resistor 18 connects power output terminal 2 to the gate of detection transistor 65. As a result, during periods when no back EMF voltage is generated, detection transistor 65 can be kept in the off state. Resistor 17 is connected in series with nMOS transistor 19. During periods when the back EMF voltage is generated, resistor 17 limits the current flow from ground power terminal 3 through node N8 of the gate of detection transistor 65 to clamping element 16. As a result, the increase in clamping voltage at clamping element 16 can be suppressed, thereby suppressing the increase in gate-back gate voltage VGBd and gate-source voltage VGSd of detection transistor 65.

[0133] By providing this dynamic clamping circuit 40A, particularly the clamping element 16, the step of forming a thick gate oxide film during manufacturing is unnecessary, as in the first embodiment. That is, the semiconductor device 205 can be used... Figure 5 The device structure shown is used to implement this. As a result, manufacturing costs can be reduced. Furthermore, as in the first embodiment, the semiconductor device 205 can be applied to, for example... Figure 6 The electronic control system (ECU) 401 is shown. In this case, the power transistor (PT) 7 can be properly protected by performing dynamic clamping operation on the back electromotive force voltage from the lamp loads 8a to 8c. As a result, the reliability of the electronic control system (ECU) 401 can be improved.

[0134] <Operation of Semiconductor Devices>

[0135] Figure 10 It is shown Figure 9 Timing diagram of an example operation of semiconductor device 205. Figure 10 It shows the same as Figure 2 The same situation applies to operations during the same time period T1 to T4. Furthermore, in Figure 10 In the middle, for comparison, it is also shown that when Figure 16 The example configuration shown uses the gate-source voltage VGSd and gate-back gate voltage VGBd. Here, we will primarily focus on the configuration with... Figure 2 The differences in the situation are described.

[0136] During time period T2, in response to the conduction of power transistor (PT) 7, the output voltage VOUT becomes essentially the same level as the supply voltage VCC. At this time, the gate voltage of detection transistor 65 becomes equal to the output voltage VOUT via resistor element 18. The back gate voltage of detection transistor 65 is equal to the output voltage VOUT. A boost voltage Vcp is applied to the source of detection transistor 65. As a result, detection transistor 65 is turned off. Furthermore, the current generated during time period T2 from power output terminal 2 to ground power supply terminal 3 is cut off by nMOS transistor 19, which acts as a diode.

[0137] During time period T2, more specifically, the gate-back gate voltage VGBd of the detection transistor 65 becomes 0V. The gate-source voltage VGSd of the detection transistor 65 is a turn-off voltage based on the voltage difference between the boost voltage Vcp and the output voltage VOUT. The magnitude of the turn-off voltage is limited by the clamping voltage of the clamping element 11. On the other hand, when Figure 16 When the configuration example shown is used, the magnitude of the back gate voltage VGBd becomes the magnitude of the output voltage VOUT, which is essentially the magnitude of the supply voltage VCC. Furthermore, the gate-source voltage VGSd becomes the turn-off voltage with the magnitude of the boost voltage Vcp.

[0138] During time period T3, in response to the turn-off of power transistor (PT) 7, a back electromotive force voltage is generated, and then the output voltage VOUT becomes negative. Here, Figure 9 The dynamic clamping circuit 40A shown is... Figure 1 The protection circuit 41A shown has the different functions described above. Therefore, with Figure 2 The situations are different. Figure 10 This illustrates an operational example when the on / off control signal IN does not transition to the on level within time period T3.

[0139] When the output voltage VOUT becomes negative, dynamic clamping operation using dynamic clamping circuit 40A is performed. As a result, the ground supply voltage SGND is applied to the gate of detection transistor 65 via nMOS transistor 19 and resistor element 17. Furthermore, the source voltage of detection transistor 65 changes along with the negative output voltage VOUT. Consequently, detection transistor 65 is turned on. When the negative voltage reaches a predetermined value, clamping element 64 is also turned on.

[0140] The clamping voltage VCLP of the reference output voltage VOUT is determined by the sum of the Zener voltage VZ64 of the clamping element 64 and the gate-source voltage VGSo of the power transistor (PT) 7. As a result, the output voltage VOUT is clamped so as not to drop below a predetermined negative voltage Vn. The gate-source voltage VGSo of the power transistor (PT) 7 becomes the turn-on voltage with a weak conduction state amplitude. Furthermore, the gate voltage of the gate node N4 of the power transistor (PT) 7 becomes higher than the negative voltage Vn generated at the power output node N7 by the gate-source voltage VGSo of the power transistor (PT) 7.

[0141] The gate-back gate voltage VGBd of the detection transistor 65 is limited by the Zener voltage Vz16 of the clamping element 16. The gate-source voltage VGSd of the detection transistor 65 becomes the turn-on voltage based on the voltage difference between the Zener voltage Vz16 and the gate-source voltage VGSo of the power transistor (PT) 7. On the other hand, in Figure 16 In the illustrated structural example, the amplitude of the back gate voltage VGBd is equal to the amplitude of the negative voltage Vn. Furthermore, the gate-source voltage VGSd is the turn-on voltage based on the voltage difference between the negative voltage Vn of the power transistor (PT) 7 and the gate-source voltage VGSo.

[0142] During time period T3, current flows from ground power supply terminal 3 through clamping element 16 to power output terminal 2. At this time, resistor element 17 limits the current flowing through clamping element 16. Furthermore, during dynamic clamping operation, the flyback energy associated with the back electromotive force voltage is released due to the on-resistance of the power transistor (PT). When the flyback energy is completely released, the output voltage VOUT becomes the ground power supply voltage PGND.

[0143] During time period T4, a load sag occurred at power node N6. For example, in Figure 2 In this case, the detection transistor 65 is configured to remain off in response to load drops. Therefore, dynamic clamping is not performed in response to load drops.

[0144] <Circuit Configuration of Semiconductor Devices (Revised)>

[0145] Figure 11 It shows how to modify Figure 9 A circuit diagram of an example configuration of the semiconductor device 206 according to the third embodiment. Figure 11 The semiconductor device 206 shown includes and Figure 9 Different gate connection circuits 43. As described in the second embodiment, more specifically, Figure 9The nMOS transistor 19 in the gate connection circuit 42 shown includes a parasitic bipolar transistor 50. In this case, when the parasitic bipolar transistor 50 is turned on during time period T3, the drain voltage of the nMOS transistor 19 increases, and the current flowing through the clamping element 16 may increase.

[0146] To prevent this problem, Figure 11 In the gate connection circuit 43 shown, the resistive element 21 and the clamping element 20 are as follows: Figure 8 The circuit is connected to the nMOS transistor 19 as described above. The ground supply voltage SGND is applied to the source of the nMOS transistor 19 via the resistor element 21. The clamping element 20 limits the gate-source voltage of the nMOS transistor 19 to a predetermined clamping voltage.

[0147] <Main Effects of the Third Embodiment>

[0148] As described above, by using semiconductor devices 205 and 206 according to the third embodiment, the same effects as those described in the first and second embodiments can be achieved. That is, dynamic clamping operation can be realized while forming the detection transistor 65 using the thin gate oxide film 506. As a result, manufacturing costs can be reduced. Furthermore, problems related to the conduction of the parasitic bipolar transistor 50 can be prevented.

[0149] (Fourth embodiment)

[0150] <Structure of Semiconductor Devices>

[0151] Figure 12 This is a circuit diagram illustrating an example configuration of the main parts of the semiconductor device 207 according to the fourth embodiment. Figure 12 The semiconductor device 207 shown includes different Figure 9 The dynamic clamping circuit 40C is shown. Besides having the same characteristics as... Figure 9 In addition to clamping elements 16 and 64, which have the same function as the gate connection circuit 42, the system also includes two detection transistors 65A and 65B, a resistor element 22, an nMOS transistor 23 for clamping, a clamping element 24, and a resistor element 25.

[0152] The gates of the two detection transistors 65A and 65B are connected together, and their back gates are both connected to the power output terminal 2. A clamping element (first clamping element) 16 limits the gate voltages of detection transistors 65A and 65B to a predetermined clamping voltage relative to the output voltage VOUT of the reference power output terminal 2. In detection transistor 65B, the source is connected to the power output terminal 2, and the drain is connected to the power supply terminal 1 via a clamping element (third clamping element) 64. However, in this example, a resistor 22 is connected between the drain of detection transistor 65B and clamping element 64.

[0153] In the detection transistor (second detection transistor) 65A, the source is connected to the gate node N4 of the power transistor (PT) 7, and the drain is connected to the power supply terminal 1 via the clamping nMOS transistor 23. A clamping element (fourth clamping element) 24 (specifically, a Zener diode) and a resistive element (fourth resistive element) 25 are connected in parallel between the gate and source of the clamping nMOS transistor 23. Furthermore, the gate of the clamping nMOS transistor 23 is connected to the power supply terminal 1 via the clamping element 64. The back gate of the clamping nMOS transistor 23 is connected to the power output terminal 2.

[0154] Here, both detection transistors 65A and 65B function to detect the negative voltage generated at power output terminal 2, and when the negative voltage is detected, both detection transistors 65A and 65B are turned on. When the negative voltage reaches a predetermined value, clamping element 64 is turned on via the on-state detection transistor 65B. As a result, the voltage obtained when the power supply voltage VCC drops the Zener voltage Vz64 of clamping element 64 is applied to the gate of the clamping nMOS transistor 23. The clamping nMOS transistor 23 receives this gate voltage and clamps the source voltage of node N12 with its own gate-source voltage VGSm.

[0155] As a result, the gate voltage of power transistor (PT) 7 is also clamped from node N12 via the on-state detection transistor 65A. The clamping voltage at this time is determined by the sum of the Zener voltage Vz64 of clamping element 64 and the gate-source voltage VGSm of the nMOS transistor 23 used for clamping. Correspondingly, the output voltage VOUT of power output terminal 2 is also dynamically clamped. The clamping voltage at this time is determined by the sum of the Zener voltage Vz64, the gate-source voltage VGSm, and the gate-source voltage VGSo of power transistor (PT) 7.

[0156] Note that clamping element 24 limits the gate-source voltage VGSm of the nMOS transistor 23 used for clamping to a clamping voltage such as 6V. Resistor element 25 keeps the nMOS transistor 23 in the off state during the non-conducting period of clamping element 64. Resistor element 22 is provided to limit the current flowing through clamping element 64, i.e., to suppress changes in clamping voltage. However, resistor element 22 can be omitted. Furthermore, resistor element 22 can be, for example, a depletion-type MOS transistor with its gate and source short-circuited to reduce circuit area.

[0157] <Operation of Semiconductor Devices>

[0158] Figure 13 It is shown Figure 12 Timing diagram of an example operation of semiconductor device 207. Figure 12 It shows that in such Figure 10 The operations during time period T1 to time period T4 under the given circumstances. Here, we will mainly focus on the operations during time period T4. Figure 10 The differences in the situation are described.

[0159] During time period T1, in response to the off state of power transistor (PT) 7, the output voltage VOUT is the ground supply voltage PGND, i.e., 0V. In this state, due to resistor element 18, the gate-source voltage VGSd2 of detection transistor 65B is 0V. Because resistor element 18 and control switch 13 are in the on state, the gate-source voltage VGSd1 of detection transistor 65A is 0V. Furthermore, due to resistor element 25, the gate-source voltage VGSm of the clamped nMOS transistor 23 is 0V.

[0160] During time period T2, in response to the turn-on of power transistor (PT) 7, the output voltage VOUT becomes essentially the same level as the supply voltage VCC. At this time, the gate-source voltage VGSd2 of detection transistor 65B becomes 0V due to resistor element 18. On the other hand, a boost voltage Vcp is applied to the source of detection transistor 65A. As a result, the gate-source voltage VGSd1 of detection transistor 65A is the turn-off voltage based on the voltage difference between the boost voltage Vcp and the output voltage VOUT, i.e., the basic supply voltage VCC. Furthermore, due to resistor element 25, the gate-source voltage VGSm of the clamped nMOS transistor 23 is 0V.

[0161] During time period T3, in response to the turn-off of power transistor (PT) 7, a back electromotive force voltage is generated, and the output voltage VOUT becomes negative. As a result, dynamic clamping operation using dynamic clamping circuit 40C is performed. The ground supply voltage SGND is applied to the gates of detection transistors 65A and 65B via nMOS transistor 19 and resistor element 17. Furthermore, the source voltage of detection transistor 65A changes along with the negative output voltage VOUT. As a result, both detection transistors 65A and 65B are turned on. When the negative voltage reaches a predetermined value, clamping element 64 is also turned on.

[0162] The clamping voltage Vclp of the reference output voltage VOUT is determined by the sum of the Zener voltage Vz64 of the clamping element 64, the gate-source voltage VGSm of the nMOS transistor 23 used for clamping, and the gate-source voltage VGSo of the power transistor (PT) 7. As a result, the output voltage VOUT is clamped so as not to drop below a predetermined negative voltage Vn.

[0163] The gate-source voltage VGSd2 of the detection transistor 65B becomes a turn-on voltage limited by the Zener voltage Vz16 of the clamping element 16. The gate-back gate voltages of the detection transistors 65A and 65B are also limited by the Zener voltage Vz16. On the other hand, the gate-source voltage VGSd1 of the detection transistor 65A becomes a turn-on voltage based on the voltage difference between the Zener voltage Vz16 and the gate-source voltage VGSo of the power transistor (PT) 7. Furthermore, the gate-source voltage VGSm of the clamped nMOS transistor 23 becomes a turn-on voltage limited by the Zener voltage Vz24 of the clamping element 24.

[0164] <Semiconductor Devices (Revised)>

[0165] Figure 12 The dynamic clamping circuit 40C shown includes a gate connection circuit 42. However, as Figure 11 The gate connection circuit 43 shown can be provided instead of the gate connection circuit 42. As a result, problems associated with the conduction of the parasitic bipolar transistor 50 can be prevented in the nMOS transistor 19.

[0166] <Main Effects of the Fourth Embodiment>

[0167] As described above, by using the semiconductor device 207 according to the fourth embodiment, the same effects as those described in the third embodiment can also be obtained. Furthermore, the same detection transistor as in the third embodiment (i.e., the same detection transistor as in the first embodiment, but with its gate and source connected to the power output terminal 2) can be used together to achieve dynamic clamping operation. However, from the viewpoint of circuit area, the third embodiment is more desirable.

[0168] (Other embodiments)

[0169] In the first to fourth embodiments described above, the supply of power supply voltage VCC to a semiconductor device having a terminal with a supplied ground power supply voltage PGND, i.e., a high-side semiconductor device, has been described as an example. However, the method of the first to fourth embodiments can also be applied to supply power supply voltage VCC to a semiconductor device having a terminal with a supplied ground power supply voltage PGND, i.e., a low-side semiconductor device.

[0170] In this case, the back electromotive force voltage generated at power output terminal 2 is not a negative voltage but a positive voltage. In response to this, for example, the detection transistor 15 can be... Figure 1 The pMOS transistor is formed in the circuit. In addition, the nMOS transistor 19 in the gate connection circuit 42 can be replaced by a pMOS transistor in which the power supply voltage VCC is applied to the gate and the source.

[0171] Although the invention made by the inventors has been specifically described based on embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention. For example, the above embodiments explain the details of the invention in an easily understood manner and are not necessarily limited to those embodiments having all the described configurations. Furthermore, a portion of the configuration of one embodiment may be replaced by the configuration of another embodiment, and a configuration of another embodiment may be added to the configuration of one embodiment. Additionally, another configuration may be added to a portion of the configuration of each embodiment, removed from a portion of the configuration of each embodiment, or replaced by a portion of the configuration of each embodiment.

Claims

1. A semiconductor device, comprising: An output transistor is connected between a first power supply terminal supplied with a first power supply voltage and a power output terminal, and when controlled to be turned on, the output transistor is configured to supply power to a load having a terminal supplied with a second power supply voltage via the power output terminal. A detection transistor is inserted into the path between the first power supply terminal and the power output terminal, and is configured to turn on when a back electromotive force voltage is generated at the power output terminal, and then the source voltage changes together with the back electromotive force voltage; The first clamping element is configured to limit the gate voltage of the detection transistor to a predetermined clamping voltage with reference to the voltage of the power output terminal; as well as A gate connection circuit is connected to the gate of the detection transistor; The gate connection circuit includes: A first resistive element is configured to connect the power output terminal to the gate of the detection transistor; as well as A rectifier element is configured to apply the second power supply voltage to the gate of the detection transistor and to cut off the current in the direction from the gate of the detection transistor toward the second power supply voltage.

2. The semiconductor device according to claim 1, further comprising: A second resistive element, connected in series with the rectifier element, is configured to limit the current flowing from the second power supply voltage through the gate of the detection transistor to the first clamping element.

3. The semiconductor device according to claim 1, The rectifier element mentioned above includes a transistor whose gate and source are short-circuited.

4. The semiconductor device according to claim 1, The rectifier element includes a transistor and a third resistor element, and The second power supply voltage is applied to the gate of the transistor, and the second power supply voltage is applied to the source of the transistor via the third resistor element.

5. The semiconductor device according to claim 1, further comprising: A first control switch is configured to control the output transistor to turn off during the period when the detection transistor is turned on; The source of the detection transistor is connected to the power output terminal.

6. The semiconductor device according to claim 5, further comprising: A Zener diode is inserted into the path between the first power supply terminal and the drain of the detection transistor; The Zener voltage of the Zener diode is lower than the clamping voltage of the body diode of the output transistor.

7. The semiconductor device according to claim 5, further comprising: A current mirror circuit is configured to replicate the current flowing through the detection transistor; as well as A voltage conversion element is configured to convert the current flowing through the current mirror circuit to the replication destination into a voltage; The first control switch is controlled to be turned on and off by the voltage converted by the voltage conversion element, and when it is controlled to be turned on, the first control switch short-circuits the gate and the source of the output transistor.

8. The semiconductor device according to claim 7, further comprising: Second clamping element, The first control switch includes a MOS transistor, the source and gate of which are respectively connected to the power output terminal and the voltage conversion element; and The second clamping element limits the gate-source voltage of the MOS transistor to a predetermined clamping voltage.

9. The semiconductor device according to claim 1, further comprising: A third clamping element is inserted into the path between the first power supply terminal and the drain of the detection transistor, and is configured to limit the back electromotive force voltage to a predetermined clamping voltage. Gate resistor element; as well as A second control switch is configured to, when controlled to be on, connect the gate of the output transistor to the power output terminal via the gate resistor element. The source of the detection transistor is connected to the gate of the output transistor.

10. The semiconductor device according to claim 9, The back gate of the detection transistor is connected to the power output terminal.

11. The semiconductor device according to claim 9, further comprising: Transistors used for clamping; as well as A fourth clamping element and a fourth resistive element are connected in parallel between the gate and source of the clamping transistor. The detection transistor includes a first detection transistor and a second detection transistor, wherein the gates of the first detection transistor and the gates of the second detection transistor are connected together. The source of the first detection transistor is connected to the power output terminal, and the drain of the first detection transistor is connected to the first power supply terminal via the third clamping element. The source of the second detection transistor is connected to the gate of the output transistor, and the drain of the second detection transistor is connected to the first power supply terminal via the clamping transistor. The gate of the transistor used for clamping is connected to the first power supply terminal via the third clamping element.

12. An electronic control system, comprising: The first power terminal is supplied with the first power supply voltage; The power output terminal is connected to the load. Semiconductor devices are configured to supply power to the load; as well as A control device is configured to control the semiconductor device. The second power supply voltage is supplied to one end of the load. The semiconductor device includes: An output transistor is connected between the first power supply terminal and the power output terminal, and when controlled to be turned on, the output transistor is configured to supply power to the load via the power output terminal; A detection transistor is inserted into the path between the first power supply terminal and the power output terminal, and is configured to turn on when a back electromotive force voltage is generated at the power output terminal, and then the source voltage changes together with the back electromotive force voltage; A first clamping element is configured to limit the gate voltage of the detection transistor to a predetermined clamping voltage with reference to the voltage of the power output terminal; and A gate connection circuit is connected to the gate of the detection transistor; The gate connection circuit includes: A first resistive element is configured to connect the power output terminal to the gate of the detection transistor; and A rectifier element is configured to apply the second power supply voltage to the gate of the detection transistor and to cut off current in the direction from the gate of the detection transistor toward the second power supply voltage. The control device outputs an on / off control signal to the semiconductor device to indicate the on / off state of the output transistor.

13. The electronic control system according to claim 12, The semiconductor device further includes a second resistive element connected in series with the rectifier element and configured to limit the current flowing from the second power supply voltage through the gate of the detection transistor to the first clamping element.

14. The electronic control system according to claim 12, The rectifier element mentioned above includes a transistor whose gate and source are short-circuited.

15. The electronic control system according to claim 12, The rectifier element includes a transistor and a third resistor element, and The second power supply voltage is applied to the gate of the transistor, and the second power supply voltage is applied to the source of the transistor via the third resistor element.

Images