Analog digital conversion device
By using voltage divider and multiplier settings in SAR ADCs, combined with gain adjustment of buffers and amplifiers, the problem of simultaneously improving the resolution and speed of SAR ADCs is solved, achieving higher resolution and lower cost, and enhancing application flexibility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- APOLLO ENERGY TECH CO LTD
- Filing Date
- 2024-10-29
- Publication Date
- 2026-05-01
AI Technical Summary
Existing SAR ADCs have limitations in meeting the high resolution and speed requirements of certain applications, and their high cost restricts their widespread use.
By employing at least two SAR ADCs and combining voltage divider and multiplier settings, the input voltage is divided into coarse and fine-tuning voltage values through a voltage divider circuit, and the gain is adjusted using a buffer and amplifier. Finally, a digital output signal is synthesized through a digital adder synthesizer to achieve higher resolution and speed.
It significantly improves resolution, reduces costs, and makes SAR ADCs more flexible in different application scenarios, while also improving speed.
Smart Images
Figure CN121966568A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to an analog-to-digital converter, and more particularly to an analog-to-digital converter capable of improving resolution by utilizing voltage divider and magnification settings. Background Technology
[0002] For engineers today, converting signals from analog to digital or vice versa is an unavoidable task, and there are many different types of analog-to-digital converters and digital-to-analog converters on the market. Although their architectures differ, their ultimate functions are very similar.
[0003] Digital signal processing cannot be performed using analog values. Therefore, when an analog-to-digital converter (ADC) detects an analog voltage, its job is to convert the analog voltage into binary code within a specified time. This means that the ADC samples the analog voltage instantaneously and then decides how to represent it as a binary value at the ADC's output.
[0004] Using a higher sampling rate can make components more accurate, but it's not the only way to control accuracy. Because these components convert analog signals into binary code, the number of steps is limited, which can be used to represent the voltage at a specific point in time. The number of bits used to represent this number is called the resolution.
[0005] The higher the resolution of an ADC, the more discrete steps it can achieve. Since an ADC has a binary output, it represents the power supply voltage. If the power supply voltage is 10V and it has an 8-bit ADC, then it can potentially have 256 steps. Resolution is determined using 2-1... n In this equation, "2" is a constant, and n is the number of bits. If n=28, it means we will get 256 orders. Using 256 orders with a 10V power supply means each order is 39.0625 mV, and the binary code for each order is different.
[0006] There are several different types of ADC architectures. The three most common ADC architectures are successive approximation register (SAR), delta-integral (ΔΣ), and pipelined converter. Each architecture can convert analog signals into digital outputs, but there are still some differences in their implementations, which are briefly explained below: (1) SAR samples and retains the analog input, converts it into a digital signal and then sends it out.
[0007] (2) The trigonometric converter averages the samples over a period of time and converts them into digital signals.
[0008] (3) The pipeline converter divides the conversion operation into different stages to achieve ultra-fast conversion speed.
[0009] Each of the three architectures described above has its own advantages and disadvantages. The SAR architecture is quite easy to use, typically consumes less power, and offers low latency and high accuracy. The trigonometric integrator architecture provides ultra-high resolution and high stability with low power consumption and low cost, but it is much slower than the SAR and pipelined architectures. Pipeline ADCs are faster and have higher bandwidth than the previous two, but they have lower resolution and require more power to operate.
[0010] Among them, the successive approximation register analog-to-digital converter (SAR ADC) is currently the mainstream converter. Over time, this converter topology has been gradually used in various applications, including process control, medical, and early digital audio systems.
[0011] The output conversion range of SAR ADC is 8 bits to 20 bits. Although higher bit counts result in higher resolution, they also increase cost. Therefore, if at least two SAR ADCs can be used in combination with circuit design to achieve higher resolution and speed, their application will be more extensive and flexible. Thus, this invention is the best solution. Summary of the Invention
[0012] The present invention provides an analog-to-digital converter, comprising at least a voltage divider circuit for dividing an input voltage into a coarse-adjustment voltage value and a fine-adjustment voltage value by a voltage division ratio; at least one first front-end circuit electrically connected to the voltage divider circuit for receiving the coarse-adjustment voltage value, the first front-end circuit having at least one buffer having a buffer gain value, and the buffer being able to output a coarse-adjustment output voltage according to the buffer gain value; at least one second front-end circuit electrically connected to the voltage divider circuit for receiving the fine-adjustment voltage value, wherein the second front-end circuit having at least one amplifier and an adjustable gain controller, the amplifier having an amplification gain value, and the amplifier being able to output a fine-adjustment output voltage according to the amplification gain value; and a first successive approximation analog number... A first successive approximation analog-to-digital converter (ADC) is electrically connected to the first front-end circuit to receive the coarse adjustment output voltage and convert the coarse adjustment output voltage into a first digital signal; a second successive approximation analog-to-digital converter (ADC) is electrically connected to the second front-end circuit to receive the coarse adjustment output voltage and convert the fine adjustment output voltage into a second digital signal; a digital adder synthesizer (D&C) is electrically connected to the first and second successive approximation analog-to-digital converters to synthesize the first and second digital signals into a digital output signal; wherein, the adjustable gain controller is used to adjust the amplification gain value so that the voltage division ratio and the amplification gain value can be adjusted accordingly, and the value of the fine adjustment output voltage is equal to the value of the input voltage.
[0013] More specifically, the voltage divider circuit has one or more voltage divider elements for adjusting the voltage division ratio, and the voltage divider element can be a resistor, a variable resistor, or a digitally adjustable resistor.
[0014] More specifically, the adjustable gain controller has one or more gain-adjustable elements for adjusting the amplification gain value, and the gain-adjustable element can be at least one or more of a resistive element, a variable resistive element, and a digitally adjustable resistive element.
[0015] More specifically, if the gain-adjustable element uses a digitally adjustable resistor element, the voltage divider circuit and the second front-end circuit are also electrically connected to a resolution controller. The resolution controller is used to synchronously adjust the voltage division ratio and the amplification gain value so that the value of the fine-tuned output voltage is equal to the value of the input voltage.
[0016] More specifically, the buffer gain value is 1.
[0017] More specifically, the coarse adjustment voltage divider value is the input voltage minus the fine adjustment voltage divider value, and the coarse adjustment output voltage is equal to the coarse adjustment voltage divider value.
[0018] More specifically, the voltage divider ratio has a coarse voltage divider ratio value and a fine voltage divider ratio value, and the reciprocal of the amplification gain value of the amplifier of the second front-end circuit is equal to the fine voltage divider ratio value.
[0019] The beneficial effects of this invention are as follows: 1. This invention can achieve higher resolution and increased speed by using at least two SAR ADCs and matching circuit designs, thus making its application more extensive and flexible; 2. This invention uses an analog circuit architecture in combination with at least two SAR ADCs, and the final combined resolution is significantly higher than that of a single SAR ADC. In addition, it can be synchronously adjusted using variable resistors or digitally adjustable resistors, which will help users meet their needs in different situations. 3. The circuit architecture of the present invention can reduce overall cost and achieve higher performance, which is impossible to achieve by using multiple conventional SAR ADCs. Attached Figure Description
[0020] Figure 1 : A schematic diagram of the first embodiment of the present invention, analogous to a digital conversion device; Figure 2 The present invention provides a schematic diagram of the circuit connections of the voltage divider circuit, the first front-end circuit, the second front-end circuit, the first filter, and the second filter in an analog digital conversion device. Figure 3 : A schematic diagram of the second embodiment architecture of the present invention, analogous to a digital conversion device; Figure 4 This invention provides a schematic diagram of signal synthesis simulation using an analog digital conversion device.
[0021] Explanation of reference numerals in the attached figures 1: Voltage divider circuit; 2: First front-end circuit; 21: Buffer; 3: Second front-end circuit; 31: Amplifier; 32: Adjustable gain controller; 41: First filter; 42: Second filter; 51: First successive approximation analog-to-digital converter; 52: Second successive approximation analog-to-digital converter; 6: Digital adder synthesizer; 7: Resolution controller. Detailed Implementation
[0022] Other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the accompanying drawings.
[0023] Please see Figure 1 The figure shows a schematic diagram of the first embodiment of the analog-to-digital converter of the present invention. As shown in the figure, the analog-to-digital converter includes at least a voltage divider circuit 1, at least one first front-end circuit 2, at least one second front-end circuit 3, at least one first filter 41, at least one second filter 42, a first successive approximation analog-to-digital converter 51, a second successive approximation analog-to-digital converter 52, and a digital adder synthesizer 6.
[0024] The voltage divider circuit 1, at least one first front-end circuit 2, at least one second front-end circuit 3, at least one first filter 41, and at least one second filter 42 are analog circuit architectures.
[0025] The first successive approximation analog-to-digital converter 51, the second successive approximation analog-to-digital converter 52, and the digital adder synthesizer 6 are digital circuit architectures.
[0026] The voltage divider circuit 1 is used to divide an input voltage into a coarse-adjustment voltage value and a fine-adjustment voltage value by a voltage division ratio.
[0027] The voltage ratio has a coarse adjustment voltage ratio value and a fine adjustment voltage ratio value.
[0028] The voltage divider circuit 1 has one or more voltage divider elements for adjusting the voltage division ratio, and the voltage divider element is a resistor element, a variable resistor element, or a digitally adjustable resistor element.
[0029] The first front-end circuit 2 is electrically connected to the voltage divider circuit 1 to receive the coarse adjustment voltage value. The first front-end circuit 2 has at least one buffer 21, which is used to output a coarse adjustment output voltage.
[0030] The buffer 21 of the first front-end circuit 2 has a buffer gain value of 1.
[0031] The second front-end circuit 3 is electrically connected to the voltage divider circuit 1 to receive the fine-tuned voltage divider value. The second front-end circuit 3 has at least an amplifier 31 and an adjustable gain controller 32. The amplifier 31 is used to output a fine-tuned output voltage.
[0032] The amplifier 31 of the second front-end circuit 3 has an amplification gain value, wherein the reciprocal of the amplification gain value is equal to the fine-tuning voltage divider ratio value.
[0033] The coarse adjustment voltage divider value is the input voltage minus the fine adjustment voltage divider value, while the coarse adjustment output voltage is equal to the coarse adjustment voltage divider value.
[0034] The first filter 41 is electrically connected to the first front-end circuit 2 to filter out noise.
[0035] The second filter 42 is electrically connected to the second front-end circuit 3 to filter out noise.
[0036] The first successive approximation analog-to-digital converter 51 (SAR ADC) is electrically connected to the first front-end circuit 2 to receive the coarse adjustment output voltage and convert the coarse adjustment output voltage into a first digital signal.
[0037] The second successive approximation analog-to-digital converter 52 (SAR ADC) is electrically connected to the second front-end circuit 3 to receive the fine-tuned output voltage and convert the fine-tuned output voltage into a second digital signal.
[0038] The digital adder synthesizer 6 is electrically connected to the first successive approximation analog-to-digital converter 51 and the second successive approximation analog-to-digital converter 52 to synthesize the first digital signal and the second digital signal into a digital output signal.
[0039] The digital adder synthesizer 6 can be implemented by a microprocessor (MCU).
[0040] like Figure 2 The diagram shows the circuit connections of the voltage divider circuit, the first front-end circuit, the second front-end circuit, the first filter, and the second filter.
[0041] The voltage divider circuit 1 consists of general resistors (R245, R252) and a variable resistor (VRA). The variable resistor (VRA) is used to adjust the voltage division ratio of the voltage divider circuit 1, and the variable resistor (VRA) can also be replaced with a general resistor.
[0042] The voltage divider circuit 1 can divide the input voltage (Vin) into a coarse-adjusted voltage value (Vin-Vout) and a fine-adjusted voltage value (Vout).
[0043] The voltage division ratio is X:1, the coarse adjustment voltage division value is ((Vin)*(X-1 / X)), and the fine adjustment voltage division value is ((Vin)*(1 / X)), where the coarse adjustment voltage division ratio is (X-1 / X) and the fine adjustment voltage division ratio is (1 / X).
[0044] The buffer gain of the buffer 21 (U25A) of the first front-end circuit 2 is 1, so the coarse adjustment output voltage (VC) output by the buffer 21 is ((Vin-Vout)*1).
[0045] The amplification gain of amplifier 31 in the second front-end circuit 3 is A, and the reciprocal of the amplification gain (1 / A) is equal to the fine-tuning voltage divider ratio (1 / X). Therefore, the fine-tuning output voltage (VF) output by amplifier 31 is ((Vin)*(1 / X)*A), so the fine-tuning output voltage (VF) is equal to the input voltage (Vin).
[0046] The adjustable gain controller 32 has a general resistor (R252) and a variable resistor (VRB). The variable resistor (VRB) is used to adjust the amplification gain value, and the variable resistor (VRB) can also be replaced with a general resistor.
[0047] The following examples illustrate different bits, where the input voltage is an example of full-scale voltage (e.g., 3.3V). However, the implementation of this invention is not limited to full-scale voltage.
[0048] In the first example, assuming the input voltage (Vin) is 3.3V, the voltage divider ratio is 10:1, the coarse adjustment voltage divider value (Vin-Vout) is 2.97V (3.3*(9 / 10)), the fine adjustment voltage divider value (Vout) is 0.33V (3.3*(1 / 10)), and both the first and second successive approximation analog-to-digital converters have 12 bits each. The different numerical analyses are as follows: (1) The coarse adjustment output voltage (VC) is 2.97V.
[0049] (2) The fine-tuned output voltage (VF) is 0.33*10=3.3V.
[0050] (3) When coarsely adjusting to full scale (the full scale mentioned in this invention represents the highest voltage value; in the implementation of this invention, full scale refers to 3.3V), assuming the resolution bits are 2 12 =4096, while the resolution voltage is 0.7251mV (2.97V / 4096).
[0051] (4) When the full scale is fine-tuned, the resolution voltage is 0.80566mV (3.3V / 4096). Since the resolution of the fine-tuning is the result of magnification by 10 times, the resolution to be restored should be divided by 10 times again. The resolution voltage should be 80.566uV (0.80566mV / 10).
[0052] (5) Finally, by using two 12-bit SAR ADCs, the resolution is improved and the speed is increased by sampling and reusing the concept of multiplier. Therefore, after coarse adjustment and fine adjustment, the actual resolution bit count is 40963 (3.3V / 80.566uV), of which 40963 exceeds 15 bits (32768).
[0053] (6) It can be seen that the resolution can be increased from 12 bits to more than 15 bits by setting the 10:1 ratio of the present invention. Therefore, the present invention can indeed improve the resolution by setting the voltage divider and the multiplier.
[0054] In the second example, if the input voltage (Vin) is 3.3V, the voltage division ratio is 15:1, the coarse adjustment voltage division value (Vin-Vout) is 3.08V (3.3*(14 / 15)), the fine adjustment voltage division value (Vout) is 0.22V (3.3*(1 / 15)), and the first and second successive approximation analog-to-digital converters each have 12 bits. The different numerical analyses are as follows: (1) The coarse adjustment output voltage (VC) is 3.08V.
[0055] (2) The fine-tuned output voltage (VF) is 0.22*15=3.3V.
[0056] (3) When coarsely adjusting to full scale, assume the resolution bits are 2. 12 =4096, while the resolution voltage is 0.7519mV (3.08V / 4096).
[0057] (4) When the full scale is fine-tuned, the resolution voltage is 0.80566mV (3.3V / 4096). Since the resolution fine-tuned is the result of magnification by 15 times, the actual resolution needs to be divided by 15 times. The actual resolution voltage is 53.71uV (0.80566mV / 15).
[0058] (5) Finally, by using two 12-bit SAR ADCs, the resolution is improved and the speed is increased by sampling and using the concept of multiplier. Therefore, after coarse adjustment and fine adjustment, the actual resolution bits are 61441 (3.3V / 53.71uV), of which 61441 is close to 16 bits (65536).
[0059] (6) It can be seen that the 15:1 setting of the present invention can improve the resolution from 12 bits to nearly 16 bits. Therefore, the present invention can indeed improve the resolution by using the voltage divider and the multiplier setting.
[0060] The third example: assuming the input voltage (Vin) is 3.3V, the voltage division ratio is 16:1, the coarse adjustment voltage division value (Vin-Vout) is 3.09375V (3.3*(15 / 16)), and the fine adjustment voltage division value (Vout) is 0.20625V (3.3*(1 / 16)). The first and second successive approximation analog-to-digital converters each have 12 bits. The different numerical analyses are as follows: (1) The coarse adjustment output voltage (VC) is 3.09375V.
[0061] (2) The fine-tuned output voltage (VF) is 0.20625*16=3.3V.
[0062] (3) When coarsely adjusting to full scale, assume the resolution bits are 2. 12 =4096, while the resolution voltage is 0.75531mV (3.09375V / 4096).
[0063] (4) When the full scale is fine-tuned, the resolution is 0.80566mV (3.3V / 4096). Since the resolution of the fine-tuning is the result of magnification by 16, the true resolution needs to be divided by 16. The true resolution is 50.35375uV (0.80566mV / 16).
[0064] (5) Finally, by using two 12-bit SAR ADCs to sample and reuse the concept of multiplier, the resolution is improved and the speed is increased. Therefore, after coarse adjustment and fine adjustment, the actual resolution bits are 65536 (3.3V / 50.35375uV), where 65536 equals 16 bits (65536).
[0065] (6) It can be seen that the 16:1 setting of the present invention can improve the resolution from 12 bits to 16 bits. Therefore, the present invention can indeed improve the resolution by using the voltage divider and the multiplier setting.
[0066] The fourth example: Suppose the input voltage (Vin) is 3.3V, the voltage division ratio is 20:1, the coarse adjustment voltage division value (Vin-Vout) is 3.135V (3.3*(19 / 20)), the fine adjustment voltage division value (Vout) is 0.165V (3.3*(1 / 20)), and the first and second successive approximation analog-to-digital converters each have 12 bits. The different numerical analyses are as follows: (1) The coarse adjustment output voltage (VC) is 3.135V.
[0067] (2) The fine-tuned output voltage (VF) is 0.165*20=3.3V.
[0068] (3) When coarsely adjusting to full scale, assume the resolution bits are 2. 12 =4096, while the resolution voltage is 0.765mV (3.135V / 4096).
[0069] (4) When the full scale is fine-tuned, the resolution is 0.80566mV (3.3V / 4096). Since the resolution of the fine-tuning is the result of magnification by 20 times, the true resolution needs to be divided by 20 times. The true resolution is 40.283uV (0.80566mV / 16).
[0070] (5) Finally, by using two 12-bit SAR ADCs, the resolution is improved and the speed is increased by sampling and using the concept of multiplier. Therefore, after coarse adjustment and fine adjustment, the actual resolution is 81920 (3.3V / 40.283uV), where 81920 is greater than 16 bits (65536).
[0071] (6) It can be seen that the 20:1 setting of the present invention can improve the resolution from 12 bits to more than 16 bits. Therefore, the present invention can indeed improve the resolution by using the voltage divider and the multiplier setting.
[0072] In addition, the aforementioned invention can change the voltage division ratio and the amplification gain value by adjusting the variable resistor (VRA / VRB), but it cannot be adjusted in real time, and can only be adjusted at the factory or after disassembly.
[0073] Furthermore, if simultaneous and real-time adjustments are required, then... Figure 3 As shown, the variable resistor (VRA / VRB) of the voltage divider circuit 1 and the adjustable gain controller 32 is replaced with a digital adjustable resistor element. The voltage divider circuit 1 and the adjustable gain controller 32 are connected to a resolution controller 7. The resolution controller 7 is used to synchronously adjust the resistance value of the variable resistor (VRA / VRB), thereby synchronously changing the voltage division ratio and the amplification gain value, so that the value of the fine-tuned output voltage is equal to the value of the input voltage.
[0074] The voltage divider circuit 1 and the adjustable gain controller 32 are implemented by at least one digitally adjustable resistor element, or by at least one general resistor and at least one digitally adjustable resistor element. The general resistor can also be replaced by a variable resistor or a digitally adjustable resistor element.
[0075] The digital adder synthesizer 6 and the resolution controller 7 can be integrated into a single microprocessor (MCU).
[0076] This invention further uses a 10-bit simulation as an example, simulating a voltage signal over 10 seconds to illustrate the resolution change. 10 bits is equivalent to 1024; however, to present this graphically, 1024 levels would need to be drawn. Therefore, this invention... Figure 4As shown, the scale is represented by 10 orders, where the first nine orders represent nine-tenths and the last segment represents one-tenth. Nine-tenths are used to represent coarse adjustment and one-tenth represents fine adjustment. As can be seen from the figure, the last segment uses ten minor orders to replace one major order. If we assume the values are as before, after calculation, we can finally obtain 10248, which is close to 14 bits (16384).
[0077] After calculation, the digital synthesis of the present invention, taking 10 bits as an example, can reach close to 14 bits after being processed by the device of the present invention. Therefore, the digital addition synthesizer will perform digital processing based on the final calculated result and based on 14 bits. The digital logic of digital synthesis is a technology that those skilled in the art will know, so it will not be described in detail.
[0078] The analog-to-digital converter provided by this invention has the following advantages compared with other existing technologies: 1. This invention can achieve higher resolution and increased speed by using at least two SAR ADCs and matching circuit designs, thus making its application more extensive and flexible.
[0079] 2. This invention uses an analog circuit architecture in conjunction with at least two SAR ADCs, and the combined resolution is significantly higher than that of a single SAR ADC. In addition, it can be synchronously adjusted using variable resistors or digitally adjustable resistors, which will help users meet their needs in different situations.
[0080] 3. The circuit architecture of the present invention can reduce overall cost and achieve higher performance, which is impossible to achieve by using multiple conventional SAR ADCs.
[0081] The present invention has been disclosed above through the above embodiments, but it is not intended to limit the present invention. Any person skilled in the art, after understanding the foregoing technical features and embodiments of the present invention, may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of patent protection of the present invention shall be determined by the claims appended to this specification.
Claims
1. An analog-to-digital converter, characterized in that, At least including: A voltage divider circuit is used to divide an input voltage into a coarse-adjustment voltage value and a fine-adjustment voltage value by a voltage division ratio. At least one first front-end circuit is electrically connected to the voltage divider circuit to receive the coarse adjustment voltage divider value. The first front-end circuit has at least one buffer with a buffer gain value, and the buffer outputs a coarse adjustment output voltage according to the buffer gain value. At least one second front-end circuit is electrically connected to the voltage divider circuit to receive the fine-tuned voltage divider value, wherein the second front-end circuit has at least an amplifier and an adjustable gain controller, the amplifier has an amplification gain value, and the amplifier outputs a fine-tuned output voltage according to the amplification gain value. A first successive approximation analog-to-digital converter is electrically connected to the first front-end circuit to receive the coarse adjustment output voltage and convert the coarse adjustment output voltage into a first digital signal. A second successive approximation analog-to-digital converter is electrically connected to the second front-end circuit to receive the coarse-adjustment output voltage and convert the fine-adjustment output voltage into a second digital signal. A digital adder synthesizer is electrically connected to the first successive approximation analog-to-digital converter and the second successive approximation analog-to-digital converter to synthesize the first digital signal and the second digital signal into a digital output signal. The adjustable gain controller is used to adjust the amplification gain value so that the voltage division ratio is adjusted in accordance with the amplification gain value, and the value of the fine-tuned output voltage is equal to the value of the input voltage.
2. The analog-to-digital converter as described in claim 1, characterized in that, The voltage divider circuit has one or more voltage divider elements for adjusting the voltage division ratio, and the voltage divider element is a resistor element, a variable resistor element, or a digitally adjustable resistor element.
3. The analog-to-digital converter as described in claim 1, characterized in that, The adjustable gain controller has one or more gain-adjustable elements for adjusting the amplification gain value, and the gain-adjustable element is at least one or more of a resistive element, a variable resistive element, and a digitally adjustable resistive element.
4. The analog-to-digital converter as described in claim 3, characterized in that, When the gain-adjustable element uses a digitally adjustable resistor element, the voltage divider circuit and the second front-end circuit are also electrically connected to a resolution controller. The resolution controller is used to synchronously adjust the voltage division ratio and the amplification gain value so that the value of the fine-tuned output voltage is equal to the value of the input voltage.
5. The analog-to-digital converter as described in claim 1, characterized in that, The buffer gain value is 1.
6. The analog-to-digital converter as described in claim 1, characterized in that, The coarse adjustment voltage divider value is the input voltage minus the fine adjustment voltage divider value, while the coarse adjustment output voltage is equal to the coarse adjustment voltage divider value.
7. The analog-to-digital converter as described in claim 1, characterized in that, The voltage divider ratio has a coarse voltage divider ratio value and a fine voltage divider ratio value, and the reciprocal of the amplification gain value of the amplifier of the second front-end circuit is equal to the fine voltage divider ratio value.