Printed circuit board

Abstract

The present disclosure relates to a printed circuit board comprising: a glass layer; a cavity penetrating a region between an upper surface and a lower surface of the glass layer; a metal layer disposed on a wall surface of the cavity; and an electronic component disposed at least partially in the cavity and spaced apart from the metal layer, and an upper surface of the metal layer is disposed at substantially the same height as a height of the upper surface of the glass layer, or disposed below the upper surface of the glass layer, and a lower surface of the metal layer is disposed at substantially the same height as the lower surface of the glass layer, or disposed above the lower surface of the glass layer.

Description

Printed Circuit Board

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0152707, filed on October 31, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a printed circuit board. Background Technology

[0003] With the advent of the era of artificial intelligence (AI) semiconductors, development related to glass substrates is actively underway. For example, semiconductor packaging substrates formed using plastic materials may face various limitations due to the need for microfabrication during the packaging process. For instance, it may be difficult to reduce the thickness of plastic substrates, and they may warp. Therefore, glass substrates can be used as a solution to this problem. However, in the case of glass substrates, cracks may occur due to impacts on the side regions of the glass during die mounting after cavity processing. Additionally, cracks may appear in the glass substrate due to stress generated during the deposition process. Summary of the Invention

[0004] One aspect of this disclosure is to provide a printed circuit board that can prevent cracking when electronic components are disposed in a glass layer in which cavities are formed.

[0005] Another aspect of this disclosure is to provide a printed circuit board that can prevent cracks from forming in a glass layer when a deposited layer is formed on the glass layer.

[0006] One of the various solutions disclosed herein is to retain a metal layer formed by plating on the wall region of the cavity formed in the glass layer, thereby preventing microcracks that may occur due to impact during the embedding process of electronic components, and to reduce the tensile stress of the glass layer by the metal layer, thereby reducing horizontal cracks that may occur in the glass layer during the stacking process.

[0007] For example, a printed circuit board according to an example embodiment may include: a glass layer; a cavity penetrating the region between an upper surface and a lower surface of the glass layer; a metal layer disposed on a wall surface of the cavity; and electronic components disposed at least partially in the cavity and spaced apart from the metal layer, wherein the upper surface of the metal layer may be disposed at a height substantially the same as the height of the upper surface of the glass layer, or may be disposed below the upper surface of the glass layer, and the lower surface of the metal layer may be disposed at a height substantially the same as the height of the lower surface of the glass layer, or may be disposed above the lower surface of the glass layer.

[0008] For example, a printed circuit board according to another example embodiment may include: a glass layer; a cavity penetrating at least a portion of the region between an upper surface and a lower surface of the glass layer; a metal layer disposed on a wall surface of the cavity; and an electronic component disposed at least partially in the cavity and spaced apart from the metal layer, wherein the metal layer may include a first metal layer and a second metal layer, the first metal layer being disposed on the wall surface of the cavity, the second metal layer being disposed on the first metal layer, and the first metal layer may have a stacked structure of titanium and copper layers, and the second metal layer may include a copper layer.

[0009] One of the various effects of this disclosure is to provide a printed circuit board that can prevent cracking when electronic components are disposed in a glass layer in which cavities are formed.

[0010] Another effect of this disclosure is to provide a printed circuit board that can prevent cracks from forming in the glass layer when a deposited layer is formed on the glass layer. Attached Figure Description

[0011] The above and other aspects, features and advantages of this disclosure will be more clearly understood by taking into account the following specific embodiments in conjunction with the accompanying drawings, in which: FIG1 is a block diagram schematically showing an example of an electronic device system; FIG2 is a cross-sectional view schematically showing an example of a printed circuit board; FIG3 is a schematic cut plan view taken along line A-A' of the printed circuit board of FIG2; FIG4 is a cross-sectional view schematically showing another example of a printed circuit board; FIG5 is a schematic cut plan view taken along line B-B' of the printed circuit board of FIG4; and FIG6 is a process cross-sectional view schematically showing the following process: forming vias and cavities in a glass layer, forming metal vias inside the vias and forming a metal layer on the wall surface of the cavity, and placing electronic components thereon in the cavity on which the metal layer is formed. Detailed Implementation

[0012] In the following description, this disclosure will be made with reference to the accompanying drawings. In the drawings, the shape and size of the elements may be exaggerated or reduced for clarity.

[0013] Figure 1 is a block diagram schematically illustrating an example of an electronic device system.

[0014] Referring to Figure 1, a motherboard 1010 is housed in the electronic device 1000. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the motherboard 1010. These components are also connected to other electronic components, which will be described below, via various signal lines 1090.

[0015] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory), etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processing units (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, chip-related components 1020 are not limited to these and may also include other types of chip-related components. Furthermore, chip-related components 1020 may be combined with each other. Chip-related components 1020 may be in the form of a package including the aforementioned chips and / or electronic components.

[0016] Network-related components 1030 may include components compatible with or operating according to protocols such as: Wireless Fidelity (Wi-Fi) (such as the IEEE 802.11 series), Global Microwave Access Interoperability (WiMAX) (such as the IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Evolved Data Optimized (Ev-DO), High Speed ​​Packet Access+ (HSPA+), High Speed ​​Downlink Packet Access+ (HSDPA+), High Speed ​​Uplink Packet Access+ (HSUPA+), Global System for Mobile Communications (GSM), Evolution of GSM with Enhanced Data Rates (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (LAN), 3G, 4G, and 5G protocols, and any other wireless or wired standards or protocols specified after the foregoing. However, network-related components 1030 are not limited to these and may also include components compatible with or operating according to any of the various other wireless or wired standards or protocols. In addition, the network-related component 1030 can be combined with the aforementioned chip-related component 1020.

[0017] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), etc. However, other components 1040 are not limited to these and may also include passive components in the form of chip modules for various other purposes. Furthermore, other components 1040 may be combined with each other in conjunction with chip-related components 1020 and / or network-related components 1030.

[0018] Depending on the type of electronic device 1000, it may include other electronic components that are physically and / or electrically connected to the motherboard 1010 or not physically and / or electrically connected to the motherboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, these other electronic components are not limited to these and may also include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), optical disc (CD) drives, digital versatile disc (DVD) drives, etc. In addition, depending on the type of electronic device 1000, it may also include other electronic components for various purposes.

[0019] Electronic device 1000 can be a smartphone, personal digital assistant, digital video camera, digital camera, network system, computer, monitor, tablet PC, laptop PC, netbook PC, television, video game console, smartwatch, automotive component, and server. However, electronic device 1000 is not limited to these and can be any other electronic device capable of processing data.

[0020] Figure 2 is a schematic cross-sectional view of an example of a printed circuit board.

[0021] Figure 3 is a schematic cut plan view taken along line A-A' of the printed circuit board in Figure 2.

[0022] Referring to Figures 2 and 3, the printed circuit board 100A according to the example embodiment may include: a glass layer 111; a through-hole v penetrating the region between the upper and lower surfaces of the glass layer 111; a metal via 131 filling at least a portion of the through-hole v; a cavity h penetrating at least a portion of the upper surface and at least a portion of the lower surface of the glass layer 111; a metal layer 132 disposed on the wall surface of the cavity h; and an electronic component 150 at least partially disposed in the cavity h and spaced apart from the metal layer 132.

[0023] In this configuration, the upper surface of each of the metal via 131 and the metal layer 132 may be positioned at a height substantially the same as the upper surface of the glass layer 111, or may be positioned below the upper surface of the glass layer 111. Similarly, the lower surface of each of the metal via 131 and the metal layer 132 may be positioned at a height substantially the same as the lower surface of the glass layer 111, or may be positioned above the lower surface of the glass layer 111. In this example, the upper surfaces of the metal via 131 and the metal layer 132 may be substantially coplanar with the upper surface of the glass layer 111, and the lower surfaces of the metal via 131 and the metal layer 132 may be substantially coplanar with the lower surface of the glass layer 111.

[0024] In this way, in the printed circuit board 100A according to the example embodiment, a metal layer 132 may be disposed on the wall surface of the cavity h in which the electronic component 150 is disposed, and the metal layer 132 may not extend to the upper and lower surfaces of the glass layer 111. In this case, the metal layer 132 can reduce the damage that may occur when the glass layer 111 collides with the electronic component 150 during the embedding process of the electronic component 150, thereby reducing the occurrence of cracks (e.g., horizontal cracks) on the wall surface of the glass layer 111. In addition, the metal layer 132 can reduce the tensile stress near the cavity h of the glass layer 111, and therefore, reduce the occurrence of cracks on the glass layer 111 when the stacked layer is formed.

[0025] Furthermore, the metal via 131 may include: first metal layers s1-1 and s1-2 disposed on the wall surface of the via v; and a second metal layer m1 disposed on the first metal layers s1-1 and s1-2 to fill at least a portion of the via v. Additionally, metal layer 132 may include: first metal layers s1-1 and s1-2 disposed on the wall surface of the cavity h; and a second metal layer m1 disposed on the first metal layers s1-1 and s1-2. The first metal layers s1-1 and s1-2 may have a stacked structure of a first seed layer s1-1 and a second seed layer s1-2. For example, the first seed layer s1-1 may include a titanium layer, and the second seed layer s1-2 may include a copper layer. Optionally, the first seed layer s1-1 may have a stacked structure of titanium and copper layers, and the second seed layer s1-2 may also include a copper layer. For example, the first metal layers s1-1 and s1-2 may be seed layers formed by a sputtering process and / or an electroless plating process. Therefore, the titanium layer may include a sputtered titanium layer, and the copper layer may include a sputtered copper layer, a chemically plated copper layer, or a combination thereof. The second metal layer m1 may be a plating layer m1. For example, plating layer m1 may include a copper layer. For example, the second metal layer m1 may be a plating layer formed by an electrolytic plating process. Therefore, the copper layer may include an electrolytically plated copper layer. For example, when the metal via 131 is formed by a sputtering process and / or a plating process, the metal layer 132 may be formed simultaneously.

[0026] Furthermore, in metal layer 132, the thickness of the first metal layers s1-1 and s1-2 in the direction substantially perpendicular to the wall surface of cavity h can be smaller than the thickness of the second metal layer m1 in the same direction. For example, the first metal layers s1-1 and s1-2 can be seed layers formed by sputtering and / or electroless plating, and the second metal layer m1 can be a plating layer formed by electrolytic plating, such that the first metal layers s1-1 and s1-2 and the second metal layer m1 can have a significant thickness difference. Similarly, in the case of metal via 131, the thickness of the first metal layers s1-1 and s1-2 in the direction substantially perpendicular to the wall surface of via v can be smaller than the thickness of the second metal layer m1 in the same direction.

[0027] Furthermore, the cavity h can be in the form of continuously surrounding the side surface of the electronic component 150. For example, in a plane, the cavity h can have a generally rectangular shape. Therefore, the metal layer 132 can be disposed on the wall surface of the cavity h in the form of a metal plate to continuously surround the side surface of the electronic component 150. In this case, the crack prevention effect described above can be even better. The cavity h can be a through cavity, and can also be a blind cavity if required.

[0028] Furthermore, if necessary, the printed circuit board 100A according to the example embodiment may further include: a frame 105 having a through portion H in which at least a portion of the glass layer 111 is disposed; a first insulating layer 112a disposed on the upper surface of each of the frame 105 and the glass layer 111; a first wiring layer 121 disposed on the upper surface of the first insulating layer 112a; a first via layer 133 penetrating the first insulating layer 112a and connecting the first wiring layer 121 to the metal via 131 and the electronic component 150; a second insulating layer 112b disposed on the lower surface of each of the frame 105 and the glass layer 111; a second wiring layer 122 disposed on the lower surface of the second insulating layer 112b; a second via layer 134 penetrating the second insulating layer 112b and connecting the second wiring layer 122 to the metal via 131; and a third insulating layer 112c filling at least a portion of the space in the through portion H located between the frame 105 and the glass layer 111. In addition, the third insulating layer 112c can also fill at least a portion of the space g between the electronic component 150 and the metal layer 132.

[0029] In this way, the printed circuit board 100A according to the example embodiment may further include a frame 105 having a through-hole H, through which process warpage can be more easily controlled. Additionally, the frame 105 can be provided at the panel level, and in this case, the frame 105 can be used as a fixture to manufacture multiple printed circuit board 100A units in a single process, and multiple unit substrates can be obtained through a dicing process. Furthermore, stress relief can be achieved by surrounding the frame 105 and the glass layer 111 with a first insulating layer 112a, a second insulating layer 112b, and a third insulating layer 112c and filling the through-hole H. Additionally, a first wiring layer 121 and a second wiring layer 122 can be formed on the first insulating layer 112a and the second insulating layer 112b, respectively, thereby improving adhesion. Furthermore, electrical connection paths can be provided in the substrate through a first via layer 133 and a second via layer 134.

[0030] Furthermore, the connecting vias of the first via layer 133 and the second via layer 134 to the metal via 131 can contact the upper and lower surfaces of the metal via 131, respectively. For example, the connecting vias can be directly connected to the upper and lower surfaces of the metal via 131 without the need for separate via pads or separate via pads. Therefore, the overall thickness of the substrate can be reduced. In addition, the process can be simplified. Furthermore, adverse effects (such as delamination) that may occur when forming pads in the glass layer 111 can be minimized.

[0031] Furthermore, the third insulating layer 112c may have interlayer boundaries with each of the first insulating layer 112a and the second insulating layer 112b. For example, the third insulating layer 112c may include filler and may be formed separately from the first insulating layer 112a and the second insulating layer 112b. However, this disclosure is not limited thereto, and the third insulating layer 112c may be integrated with at least one of the first insulating layer 112a and the second insulating layer 112b. For example, when one or both of the first insulating layer 112a and the second insulating layer 112b are stacked, the space in the through-port H, excluding the electronic component 150, may be filled to form the third insulating layer 112c. Integration of the third insulating layer 112c with at least one of the first insulating layer 112a and the second insulating layer 112b may mean that the third insulating layer 112c forms a layer without boundaries with said at least one of the first insulating layer 112a and the second insulating layer 112b.

[0032] Furthermore, if necessary, the printed circuit board 100A according to the example embodiment may further include: a first stacked insulating layer 113 disposed on the upper surface of the first insulating layer 112a; a first stacked wiring layer 123 disposed on the upper surface of the first stacked insulating layer 113; a first stacked via layer 135 penetrating the first stacked insulating layer 113 and connecting the first stacked wiring layer 123 and the first wiring layer 121; a second stacked insulating layer 114 disposed on the lower surface of the second insulating layer 112b; a second stacked wiring layer 124 disposed on the lower surface of the second stacked insulating layer 114; and a second stacked via layer 136 penetrating the second stacked insulating layer 114 and connecting the second stacked wiring layer 124 and the second wiring layer 122.

[0033] In this way, the printed circuit board 100A according to the example embodiment may have a multilayer substrate structure in which stacked layers are further formed on the upper and / or lower sides of the glass layer 111. For example, the printed circuit board 100A according to the example may be a packaging substrate on which semiconductor chips are mounted. The packaging substrate may be a large-area substrate for servers, etc., as needed. The stacked layers may be formed only on the upper or lower sides of the glass layer 111, or the stacked layers may be formed asymmetrically on the upper and lower sides of the glass layer 111. For example, the printed circuit board 100A according to the example embodiment may be an intermediate substrate with an asymmetrical structure.

[0034] In the following description, the components of the printed circuit board 100A according to an exemplary embodiment will be described in more detail with reference to the accompanying drawings.

[0035] Frame 105 may comprise a material with excellent rigidity, such as copper-clad laminate (CCL) or bare CCL, but this disclosure is not limited thereto. For example, frame 105 may comprise other organic materials with excellent rigidity, or it may comprise various types of inorganic materials with excellent rigidity. During the process, frame 105 can be used as a fixture, thus allowing panel-level processing via frame 105. Additionally, frame 105 may be retained in the final unit after the splitting process, which can further facilitate warpage control.

[0036] Glass layer 111 may comprise glass, which is an amorphous solid. The glass may include, for example, pure silica (about 100% SiO2), soda-lime glass, borosilicate glass, and aluminosilicate glass. However, this disclosure is not limited thereto, and alternative glass materials (such as fluorine glass, phosphate glass, and chalcogenide glass) may also be used as materials for glass layer 111. Additionally, other additives may be included to form a glass with specific physical properties. These additives may include magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, antimony, and carbonates (e.g., calcium carbonate (e.g., limestone) and sodium carbonate (e.g., soda ash)) and / or oxides of these elements and other elements. Furthermore, glass layer 111 may be a layer distinct from organic insulating material layers (such as copper-clad laminate (CCL), prepreg (PPG), etc.) that include glass fibers (e.g., glass fabric, such as glass cloth). Glass layer 111 may be in the form of, for example, a glass plate.

[0037] Each of the first insulating layer 112a, the second insulating layer 112b, and the third insulating layer 112c, as well as the first stacked insulating layer 113 and the second stacked insulating layer 114, may comprise an organic insulating material. The organic insulating material may comprise a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a material prepared by impregnating inorganic fillers, organic fillers, and / or glass fibers (e.g., glass fabric, such as glass cloth) in the aforementioned resin. For example, the organic insulating material may comprise prepreg (PPG), Ajinomoto stacked film (ABF), photosensitive dielectric (PID), and bonding sheet (BS), but this disclosure is not limited thereto. The first insulating layer 112a, the second insulating layer 112b, and the third insulating layer 112c may comprise substantially the same material, but this disclosure is not limited thereto, and the first insulating layer 112a, the second insulating layer 112b, and the third insulating layer 112c may comprise different materials. The first stacked insulating layer 113 and the second stacked insulating layer 114 may comprise substantially the same material, but this disclosure is not limited thereto, and the first stacked insulating layer 113 and the second stacked insulating layer 114 may comprise different materials. The first stacked insulating layer 113 and the second stacked insulating layer 114 may be formed with more layers than shown in the figures, and one of the first stacked insulating layer 113 and the second stacked insulating layer 114 may be omitted if necessary.

[0038] Each of the first wiring layer 121, the second wiring layer 122, the first stacked wiring layer 123, and the second stacked wiring layer 124 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, each of the first wiring layer 121, the second wiring layer 122, the first stacked wiring layer 123, and the second stacked wiring layer 124 may include a chemically plated copper layer formed by an electroless plating process as a seed layer s2, and may include an electrolytically plated copper layer formed based on the seed layer s2 by an electrolytic plating process as a pattern plating layer m2. Each of the first wiring layer 121, the second wiring layer 122, the first stacked wiring layer 123, and the second stacked wiring layer 124 may perform various functions according to the design. For example, each of the first wiring layer 121, the second wiring layer 122, the first stacked wiring layer 123, and the second stacked wiring layer 124 may include signal patterns, power patterns, and ground patterns. Each of these patterns can take various forms such as lines, traces, planes, and pads. Pads can include the concept of a pad. The first stacked wiring layer 123 and the second stacked wiring layer 124 can be formed with more layers than shown in the figures, and one of the first stacked wiring layer 123 and the second stacked wiring layer 124 can be omitted if necessary.

[0039] Metal via 131 may include metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, metal via 131 may have a stacked structure of titanium and copper layers formed by sputtering and / or electroless plating processes as seed layers s1-1 and s1-2. For example, metal via 131 may include a sputtered titanium layer and a sputtered copper layer, a sputtered titanium layer and an electroless copper plating layer, or a sputtered titanium layer, a sputtered copper layer and an electroless copper plating layer. Additionally, a copper layer formed by electrolytic plating based on seed layers s1-1 and s1-2 may be included as plating layer m1. For example, metal via 131 may include an electrolytic copper plating layer. Metal via 131 may perform various functions according to the design. For example, metal via 131 may include signal vias, power vias, and ground vias. The metal via 131 may have a tapered shape (e.g., an hourglass shape), but is not limited thereto, and may have a cylindrical shape in which the side surfaces of the metal via 131 are generally vertical. The metal via 131 may be a plated through-glass via (TGV). Multiple metal vias 131 may exist, and the multiple metal vias 131 may be spaced apart from each other.

[0040] Metal layer 132 may include metals. Metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, metal layer 132 may have a stacked structure of titanium and copper layers formed by sputtering and / or electroless plating processes as seed layers s1-1 and s1-2. For example, metal layer 132 may include a sputtered titanium layer and a sputtered copper layer, a sputtered titanium layer and an electroless copper plating layer, or a sputtered titanium layer, a sputtered copper layer, and an electroless copper plating layer. Additionally, a copper layer formed based on seed layers s1-1 and s1-2 by an electrolytic plating process may be included as plating layer m1. For example, metal layer 132 may include an electrolytic copper plating layer. Metal layer 132 may be disposed in the form of a metal plate on the wall surface of cavity h to continuously surround the side surface of electronic component 150.

[0041] Each of the first via layer 133, the second via layer 134, the first stacked via layer 135, and the second stacked via layer 136 may include a metal. The metal in each of the first via layer 133, the second via layer 134, the first stacked via layer 135, and the second stacked via layer 136 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, each of the first via layer 133, the second via layer 134, the first stacked via layer 135, and the second stacked via layer 136 may include a chemically plated copper layer formed by an electroless plating process as a seed layer s2, and may include an electrolytically plated copper layer formed based on the seed layer s2 by an electrolytic plating process as a patterned plating layer m2. Each of the first via layer 133, the second via layer 134, the first stacked via layer 135, and the second stacked via layer 136 may perform various functions according to design. For example, each of the first via layer 133 and the second via layer 134, as well as the first stacked via layer 135 and the second stacked via layer 136, may include signal vias, power vias, and ground vias. Each of the first via layer 133 and the second via layer 134, as well as the first stacked via layer 135 and the second stacked via layer 136, may include a filled via in which the via is filled with metal, and may also include a conformal via in which metal is disposed along the wall surface of the via. Each of the first via layer 133 and the second via layer 134, as well as the first stacked via layer 135 and the second stacked via layer 136, may have a tapered shape. Each of the first via layer 133 and the second via layer 134, as well as the first stacked via layer 135 and the second stacked via layer 136, may include a plurality of connection vias. For example, the first via layer 133 may include a first connection via and a second connection via. The first connection via penetrates the first insulating layer 112a and connects at least a portion of the first wiring layer 121 to the upper surface of the metal via 131. The second connection via penetrates the first insulating layer 112a and connects at least another portion of the first wiring layer 121 to the electronic component 150. The second via layer 134 may include a third connection via. The third connection via penetrates the second insulating layer 112b and connects at least a portion of the second wiring layer 122 to the lower surface of the metal via 131. The first stacked via layer 135 and the second stacked via layer 136 may be formed with more layers than shown in the figures, and one of the first stacked via layer 135 and the second stacked via layer 136 may be omitted if necessary.

[0042] Electronic component 150 can be various types of active and / or passive components. For example, electronic component 150 may include integrated circuit devices (ICDs) and embedded passive integrated components (EPICs), but this disclosure is not limited thereto. Electronic component 150 may be disposed in cavities h on the upper and lower surfaces of the penetrating glass layer 111 and may be embedded in the substrate. Electronic component 150 may be electrically connected to the first wiring layer 121 through a second connection via of the first via layer 133. Electronic component 150 may include connection pads or connection bumps that contact the second connection via of the first via layer 133.

[0043] Figure 4 is a cross-sectional view schematically showing another example of a printed circuit board.

[0044] Figure 5 is a schematic cut plan view taken along line B-B' of the printed circuit board in Figure 4.

[0045] Referring to Figures 4 and 5, compared to the printed circuit board 100A according to the example described above, the printed circuit board 100B according to another example embodiment can be configured such that the upper surface of each of the metal via 131 and the metal layer 132 is disposed below the upper surface of the glass layer 111, and the lower surface of each of the metal via 131 and the metal layer 132 is disposed above the lower surface of the glass layer 111. For example, in another example, the upper surfaces of the metal via 131 and the metal layer 132 may have stepped portions with respect to the upper surface of the glass layer 111, and the lower surfaces of the metal via 131 and the metal layer 132 may have stepped portions with respect to the lower surface of the glass layer 111. For example, in the following process, a chemical mechanical polishing (CMP) process or the like can be used to partially remove the upper and lower surfaces of each of the metal vias 131 and the metal layer 132 during the planarization process, such that the upper and lower surfaces of each of the metal vias 131 and the metal layer 132 can respectively have stepped portions with the upper and lower surfaces of the glass layer 111.

[0046] Other descriptions are substantially the same as those in the printed circuit board 100A according to the above example embodiment, and the technical effects are also substantially the same, so their repeated descriptions will be omitted.

[0047] Figure 6 is a schematic cross-sectional view of the process of forming vias and cavities in a glass layer, forming metal vias inside the vias and forming a metal layer on the wall surface of the cavity, and placing electronic components in the cavity on which the metal layer is formed.

[0048] Referring to Figure 6, firstly, a through-hole v and a cavity h can be formed in the glass layer 111. The through-hole v and cavity h can be formed using processing techniques such as etching, sandblasting, laser processing, and plasma processing. Next, a first seed layer s1-1 can be formed on the upper and lower surfaces of the glass layer 111, the wall surface of the through-hole v, and the wall surface of the cavity h using a sputtering process. Next, a second seed layer s1-2 can be formed on the first seed layer s1-1 using a sputtering process and / or an electroless plating process. The second seed layer s1-2 can be a single layer formed by the sputtering process, or it can be multiple layers formed by an electroless plating process after the sputtering process. Next, a plating layer m1 can be formed on the second seed layer s1-2 using an electrolytic plating process. The plating layer m1 can fill the interior of the through-hole v. Next, the first seed layer s1-1, the second seed layer s1-2, and the plating layer m1, which are disposed on the upper and lower surfaces of the glass layer 111, can be removed using a planarization process such as chemical mechanical polishing (CMP). In this case, CMP process conditions can be optimized, thereby omitting the wet etching process. Therefore, a metal via 131 can be formed in the via v, and a metal layer 132 can be formed on the wall surface of the cavity h. Furthermore, during the planarization process, the upper surfaces of each of the glass layer 111, the metal via 131, and the metal layer 132 can be coplanar with each other, and the lower surfaces of each of the glass layer 111, the metal via 131, and the metal layer 132 can be coplanar with each other (e.g., a printed circuit board structure according to an example embodiment (e.g., printed circuit board 100A)). However, this disclosure is not limited to this, and the upper and lower surfaces of each of the metal via 131 and the metal layer 132 can be partially removed to have stepped portions with the upper and lower surfaces of the glass layer 111, respectively (e.g., a printed circuit board structure according to another example embodiment (e.g., printed circuit board 100B)). Next, an electronic component 150 can be embedded in the cavity h. In this case, the metal layer 132 can prevent glass cracking that occurs when the electronic component 150 collides with the glass layer 111. In addition, a stacking process can be performed thereafter, and tensile stress can be reduced by the metal layer 132 to prevent the glass from cracking.

[0049] Other descriptions are substantially the same as those in the descriptions of the printed circuit board 100A according to the example embodiment and the printed circuit board 100B according to another example embodiment, as described above, and therefore their repeated descriptions will be omitted.

[0050] In this disclosure, the term "cover" can include covering a portion or the entirety of a component, and can also include direct or indirect coverage. Furthermore, the term "fill" can include not only complete filling but also partial filling, and can also include substantially filling. For example, the term "fill" can include the presence of holes or gaps. Additionally, the term "surround" can include not only complete surrounding but also partial surrounding, and can also include substantially surrounding. Furthermore, the term "expose" can include not only complete exposure but also partial exposure, and can indicate that a feature is exposed from the component in which it is embedded. For example, exposing a pad through an opening in the resist layer can mean exposing the pad from the resist layer, and a surface treatment layer or the like can be further disposed on the exposed pad.

[0051] In this disclosure, in cross-section, the case where an object is disposed in a through portion or through hole includes not only cases where the object is completely disposed in the through portion or through hole, but also cases where the object partially protrudes upward or downward from the through portion or through hole. Furthermore, in a plane, this can be defined in a broader sense when an object is placed in a through portion or through hole.

[0052] In this disclosure, "basically" can be a concept that includes process errors, positional deviations, and measurement errors occurring during the manufacturing process. For example, "basically coplanar" can include not only cases of complete coplanarity but also cases of substantially coplanarity. Additionally, "set at substantially the same height" can include cases of being set at substantially the same height and cases of being set at exactly the same height. Furthermore, "having a substantially specific shape" can include not only cases of having exactly such a shape but also cases of having substantially such a shape. In one or more aspects, the terms "basically," "approximately," and "approximately" can provide industry-accepted tolerances for the relevance between their corresponding terms and / or items, such as tolerances of ±1%, ±5%, or ±10% of the actual value, or other suitable tolerances.

[0053] In this disclosure, "the same insulating material" can refer not only to completely identical insulating materials, but also to insulating materials of the same type. Therefore, the composition of the insulating materials can be substantially the same, but the specific composition ratios of the insulating materials can be slightly different.

[0054] In this disclosure, "section" can refer to the cross-sectional shape when an object is cut vertically or the shape when the object is viewed from a side view. Furthermore, "plane" can refer to the cross-sectional shape when an object is cut horizontally or the planar shape when the object is viewed from a top or bottom view.

[0055] In this disclosure, for convenience, the term "lower" in "lower side," "lower part," and "lower surface" refers to a downward direction relative to the cross-section of the figures, and the term "upper side," "upper part," and "upper surface" refers to a direction opposite to the downward direction. However, the above directions are defined for ease of interpretation, and the scope of the claims is not specifically limited by the description of the directions, and the concepts of upper / lower can be changed at any time.

[0056] In this disclosure, the term "connection" is meant not only to include direct connections but also to include indirect connections such as those via adhesive layers. Furthermore, expressions such as "first" and "second" are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the claims, the first component may be referred to as the second component, or similarly, the second component may be referred to as the first component.

[0057] In this disclosure, thickness, width, length, depth, linewidth, gap, pitch, spacing, surface roughness, etc., can be measured using a scanning electron microscope, optical microscope, etc., based on a cross-section obtained by polishing or cutting a printed circuit board. The cross-section can be a vertical or horizontal cross-section, and its respective values ​​can be measured based on the desired cross-section. For example, the width of the upper and / or lower portion of a via can be measured in a cross-section already cut along the central axis of the via. In this case, when the value measured for one of them is not constant, the value of said one can be determined as the average of the values ​​measured at five arbitrary points.

[0058] The term "example embodiment" as used in this disclosure does not imply the same embodiment, but is provided to explain different unique characteristics. However, the example embodiments presented above do not preclude implementation through combinations of features with other example embodiments. For example, unless there is an interpretation contrary to or contradicting that of other example embodiments, even if content described in a particular example embodiment is not described in other example embodiments, it may be understood as an interpretation relating to other example embodiments.

[0059] The terminology used in this disclosure is for describing exemplary embodiments only and is not intended to limit the disclosure. In this context, singular expressions include plural expressions unless explicitly stated otherwise in the context.

[0060] While exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: Glass layer; A cavity that penetrates the area between the upper and lower surfaces of the glass layer; A metal layer is disposed on the wall surface of the cavity; And electronic components, at least partially disposed in the cavity and spaced apart from the metal layer, wherein the upper surface of the metal layer is disposed at the same height as the upper surface of the glass layer, or below the upper surface of the glass layer, and the lower surface of the metal layer is disposed at the same height as the lower surface of the glass layer, or above the lower surface of the glass layer.

2. The printed circuit board according to claim 1, wherein, The upper surface of the metal layer is coplanar with the upper surface of the glass layer, and the lower surface of the metal layer is coplanar with the lower surface of the glass layer.

3. The printed circuit board according to claim 1, wherein, The upper surface of the metal layer and the upper surface of the glass layer have stepped portions, and the lower surface of the metal layer has a stepped portion from the lower surface of the glass layer.

4. The printed circuit board according to claim 1, wherein, The cavity continuously surrounds the side surface of the electronic component, and the metal layer is disposed on the wall surface of the cavity in the form of a metal plate to continuously surround the side surface of the electronic component.

5. The printed circuit board according to claim 1, wherein, The metal layer includes a first metal layer and a second metal layer. The first metal layer is disposed on the wall surface of the cavity, and the second metal layer is disposed on the first metal layer. The first metal layer has a stacked structure of titanium and copper layers, and the second metal layer includes a copper layer.

6. The printed circuit board according to claim 1, further comprising: A through-hole that penetrates the area between the upper and lower surfaces of the glass layer; And a metal via, filling at least a portion of the through hole, wherein the upper surface of the metal via is disposed at the same height as the upper surface of the glass layer, or below the upper surface of the glass layer, and the lower surface of the metal via is disposed at the same height as the lower surface of the glass layer, or above the lower surface of the glass layer.

7. The printed circuit board according to claim 6, wherein, The metal via includes a first metal layer and a second metal layer. The first metal layer is disposed on the wall surface of the via, and the second metal layer is disposed on the first metal layer and fills at least a portion of the via. The first metal layer has a stacked structure of titanium and copper layers, and the second metal layer includes a copper layer.

8. The printed circuit board according to claim 6, further comprising: A frame having a through portion in which at least a portion of the glass layer is disposed; A first insulating layer is disposed on the upper surface of each of the frame and the glass layer; The first wiring layer is disposed on the upper surface of the first insulating layer; A first connection via penetrates the first insulating layer and connects at least a portion of the first wiring layer to the metal via; A second connection via penetrates the first insulating layer and connects at least another portion of the first wiring layer to the electronic component; A second insulating layer is disposed on the lower surface of each of the frame and the glass layer; The second wiring layer is disposed on the lower surface of the second insulating layer; A third connection via penetrates the second insulating layer and connects at least a portion of the second wiring layer to the metal via; And a third insulating layer, filling at least a portion of the space in the through portion located between the frame and the glass layer, wherein the first connecting via contacts the upper surface of the metal via, and the third connecting via contacts the lower surface of the metal via.

9. The printed circuit board according to claim 8, wherein, The third insulating layer has an interlayer boundary with each of the first and second insulating layers.

10. The printed circuit board according to claim 8, wherein, The third insulating layer is integrated with at least one of the first insulating layer and the second insulating layer.

11. The printed circuit board according to claim 8, further comprising: A first stacked insulating layer is disposed on the upper surface of the first insulating layer; A first stacked wiring layer is disposed on the upper surface of the first stacked insulating layer; The first stacked via layer penetrates the first stacked insulating layer and connects the first stacked wiring layer and the first wiring layer; A second stacked insulating layer is disposed on the lower surface of the second insulating layer; The second stacked wiring layer is disposed on the lower surface of the second stacked insulating layer; And a second stacked via layer, which penetrates the second stacked insulating layer and connects the second stacked wiring layer and the second wiring layer.

12. A printed circuit board, comprising: Glass layer; A cavity that penetrates at least a portion of the region between the upper and lower surfaces of the glass layer; A metal layer is disposed on the wall surface of the cavity; And electronic components, at least partially disposed in the cavity and spaced apart from the metal layer, wherein the metal layer includes a first metal layer and a second metal layer, the first metal layer being disposed on the wall surface of the cavity, the second metal layer being disposed on the first metal layer, wherein the first metal layer has a stacked structure of titanium and copper layers, and the second metal layer includes a copper layer.

13. The printed circuit board according to claim 12, wherein, The thickness of the second metal layer in the direction perpendicular to the wall surface of the cavity is greater than the thickness of the first metal layer in the direction perpendicular to the wall surface of the cavity.

14. The printed circuit board according to claim 12, further comprising: A through-hole that penetrates the area between the upper and lower surfaces of the glass layer; And a metal via, filling at least a portion of the through hole, wherein the metal via includes a first metal layer and a second metal layer, the first metal layer included in the metal via is disposed on the wall surface of the through hole, and the second metal layer included in the metal via is disposed on the first metal layer included in the metal via, to further fill the at least a portion of the through hole.

15. The printed circuit board according to claim 14, wherein, The titanium layer of the first metal layer includes a sputtered titanium layer, the copper layer of the first metal layer includes at least one of a sputtered copper layer and a chemically plated copper layer, and the copper layer of the second metal layer includes an electrolytically plated copper layer.

16. The printed circuit board according to claim 12, wherein, The metal layer does not extend to the upper and lower surfaces of the glass layer.

Images