Semiconductor device and preparation method thereof, and electronic equipment

Abstract

The invention discloses a semiconductor device, a preparation method thereof and electronic equipment. The semiconductor device comprises a plurality of bit lines, a plurality of memory cell columns and a first conductive layer. The first electrode is connected with a bit line through the first conductive layer, and / or the second electrode is connected with the capacitor through the first conductive layer; a contact resistance between the active layer and the first conductive layer is set to be smaller than a contact resistance between the active layer and the capacitor and smaller than a contact resistance between the active layer and the bit line. The invention relates to the technical field of semiconductor devices, in particular to a semiconductor device, a preparation method thereof and electronic equipment, which can reduce contact resistance between a transistor and a metal structure (a bit line and a capacitor) in contact with the transistor, and improve switching speed and stability of the device.

Description

Semiconductor devices and their fabrication methods, electronic devices Technical Field

[0001] This article relates to the field of semiconductor device technology, and in particular to a semiconductor device and its fabrication method, and electronic equipment. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking daily, while the types and number of devices contained in a single chip are increasing. This means that even minor differences in the manufacturing process can affect device performance. To minimize product costs, the goal is to fabricate as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands.

[0003] As the demand for memory continues to increase, the requirements for miniaturization of memory devices are becoming increasingly stringent. However, due to limitations in existing structures and processes, miniaturization of devices faces numerous challenges, and existing fabrication processes are complex and produce products of relatively poor quality. Summary of the Invention

[0004] This application provides a semiconductor device, including:

[0005] Multiple bit lines are arranged at intervals along the direction perpendicular to the substrate;

[0006] Multiple memory cell columns, each memory cell column including multiple memory cells, the multiple memory cells are arranged along a direction perpendicular to the substrate and are connected to multiple bit lines one by one; each memory cell includes a transistor and a capacitor, the transistor includes an active layer having a first electrode region and a second electrode region, the first electrode region serving as the first electrode of the transistor, the second electrode region serving as the second electrode of the transistor, the first electrode being connected to the bit line, and the second electrode being connected to the capacitor;

[0007] A first conductive layer, wherein the first electrode is configured to connect to the bit line through the first conductive layer, and / or the second electrode is configured to connect to the capacitor through the first conductive layer;

[0008] The contact resistance between the active layer and the first conductive layer is set to be less than the contact resistance between the active layer and the capacitor, and less than the contact resistance between the active layer and the bit line.

[0009] In some exemplary embodiments, the first conductive layer is disposed on the outer surface of the active layer, or on the surface of the capacitor facing the active layer and / or the surface of the bit line facing the active layer.

[0010] In some exemplary embodiments, the transistor further includes a gate layer extending in a direction perpendicular to the substrate, the active layer surrounding the outer periphery of the gate layer and being insulated from the gate layer;

[0011] The first conductive layer is disposed on the transistor and covers the surface of the active layer away from the gate layer.

[0012] In some exemplary embodiments, the capacitor includes an outer electrode arranged in a ring, and the first conductive layer is disposed on the capacitor and covers the circumferential outer wall of the outer electrode.

[0013] In some exemplary embodiments, each bit line includes an adjacent bit line body and a connecting line, the connecting line being located on the side of the bit line body closer to the transistor, and the bit line body being connected to the transistor via the connecting line;

[0014] The first conductive layer is disposed on the bit line and covers the surface of the connection line near the transistor.

[0015] In some exemplary embodiments, the first conductive layer is configured to cover the outer surfaces of the bit line body and the connecting line.

[0016] In some exemplary embodiments, the active layer is made of indium gallium zinc oxide, and the first conductive layer is made of indium tin oxide.

[0017] In some exemplary embodiments, the bit line extends along a first direction, the transistor is located on one side of the bit line in a second direction, and the capacitor is located on the side of the transistor away from the bit line in the second direction, wherein the first direction and the second direction are perpendicular to each other and both parallel to the substrate.

[0018] This application provides a method for fabricating a semiconductor device, applicable to the aforementioned semiconductor device, comprising:

[0019] Multiple first insulating layers and multiple second insulating layers are sequentially and alternately formed on a substrate to obtain a stacked structure;

[0020] In the stacked structure, a first through-hole, a second through-hole, and a first trench are formed in a direction perpendicular to the substrate. The first trench extends in a first direction and is configured to define the position of the bit line. The first through-hole is located on one side of the first trench in a second direction, and the second through-hole is located between the first through-hole and the first trench. The first through-hole is located on one side of the second through-hole in a second direction and is configured to define the position of the capacitor. The second through-hole is configured to define the position of the transistor. The first direction and the second direction are perpendicular to and parallel to the substrate.

[0021] The first conductive layer is formed based on the stacked structure.

[0022] In some exemplary embodiments, forming the first conductive layer based on the stacked structure includes:

[0023] The trench wall of the first trench is etched, and multiple second insulating layers are etched in a direction parallel to the substrate to form multiple first transverse trenches. The multiple first transverse trenches are arranged at intervals in a direction perpendicular to the substrate, and the first transverse trenches extend from the first trench to the second through hole in the second direction.

[0024] A bit line is formed within the first transverse groove;

[0025] The wall of the first through hole is etched, and a plurality of second insulating layers are etched in a direction parallel to the substrate to form a plurality of second transverse grooves. The plurality of second transverse grooves are arranged at intervals in a direction perpendicular to the substrate, and the second transverse grooves extend to the second through hole along the second direction.

[0026] An external electrode is formed within the second transverse groove;

[0027] The wall of the second via is etched, and a plurality of the first insulating layers are etched in a direction parallel to the substrate to form a plurality of third transverse trenches. A first sacrificial layer is formed in the third transverse trenches. The plurality of third transverse trenches are arranged at intervals in a direction perpendicular to the substrate. The third transverse trenches extend from the second via to the first via and from the second via to the first trench in the second direction. The first sacrificial layer covers the sidewall of the third transverse trench.

[0028] A first conductive layer, an active layer, a gate insulating layer, and a gate layer are sequentially deposited in the second via and the third transverse groove.

[0029] In some exemplary embodiments, forming the first conductive layer based on the stacked structure includes:

[0030] The trench wall of the first trench is etched, and multiple second insulating layers are etched in a direction parallel to the substrate to form multiple first transverse trenches. The multiple first transverse trenches are arranged at intervals in a direction perpendicular to the substrate, and the first transverse trenches extend from the first trench to the second through hole in the second direction.

[0031] A first conductive layer and a bit line are formed within the first transverse groove, the first conductive layer being located between the groove wall of the first transverse groove and the bit line; and / or,

[0032] The wall of the first through hole is etched, and a plurality of second insulating layers are etched in a direction parallel to the substrate to form a plurality of second transverse grooves. The plurality of second transverse grooves are arranged at intervals in a direction perpendicular to the substrate, and the second transverse grooves extend to the second through hole along the second direction.

[0033] A first conductive layer and an outer electrode are formed within the second transverse groove, wherein the first conductive layer is located between the groove wall of the second transverse groove and the outer electrode.

[0034] In some exemplary embodiments, forming the first conductive layer based on the stacked structure includes:

[0035] The trench wall of the first trench is etched, and multiple second insulating layers are etched in a direction parallel to the substrate to form multiple first transverse trenches. The multiple first transverse trenches are arranged at intervals in a direction perpendicular to the substrate. The first transverse trenches extend from the first trench to the second via in the second direction but do not connect the first trench and the second via.

[0036] A bit line is formed within the first transverse groove;

[0037] The wall of the first through hole is etched, and multiple second insulating layers are etched in a direction parallel to the substrate to form multiple second transverse grooves. The second transverse grooves extend from the first through hole to the second through hole in the second direction but do not extend to the second through hole.

[0038] An external electrode is formed within the second transverse groove;

[0039] The wall of the second via is etched, and a plurality of second insulating layers are etched in a direction parallel to the substrate to form a plurality of third transverse grooves. The third transverse grooves extend from the second via to the bit line in the second direction and from the second via to the external electrode.

[0040] A first conductive layer, an active layer, a gate insulating layer, and a gate layer are sequentially deposited within the third transverse groove.

[0041] In some exemplary embodiments, forming the first conductive layer based on the stacked structure further includes:

[0042] The material in the first through hole and the first trench is etched to remove the first sacrificial layer, the first conductive layer and the active layer in the third transverse groove.

[0043] In some exemplary embodiments, forming a first conductive layer, an active layer, a gate insulating layer, and a gate layer within the third transverse slot includes:

[0044] A first conductive layer, an active layer, a gate insulating layer, and a gate layer are sequentially deposited in the second via and the third transverse groove;

[0045] The first conductive layer, active layer, gate insulating layer and gate layer in the second via are removed by etching, while the first conductive layer, active layer, gate insulating layer and gate layer in the third transverse groove are retained.

[0046] In some exemplary embodiments, a first through-hole, a second through-hole, and a first trench are formed in the stacked structure in a direction perpendicular to the substrate, including;

[0047] The stacked structure is etched to form a first through-hole and a second through-hole;

[0048] A second sacrificial layer is filled into the first and second through holes and then planarized.

[0049] This application provides an electronic device, including the semiconductor device described above, or a semiconductor device obtained by the method for preparing the semiconductor device described above.

[0050] The semiconductor device and its fabrication method according to embodiments of this application reduce the contact resistance between the transistor and the metal structure (bit line and capacitor) in contact with it by providing a first conductive layer between the transistor and the capacitor and / or between the transistor and the bit line, thereby improving the switching speed and stability of the device. The semiconductor device and its fabrication method of this application can effectively eliminate parasitic capacitance and avoid leakage and failure between devices.

[0051] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0052] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0053] Figure 1 is a schematic diagram of a semiconductor device according to an exemplary embodiment of this invention;

[0054] Figure 2 is a schematic diagram of the a-a' section in Figure 1;

[0055] Figure 3 is a schematic diagram of another semiconductor device according to this exemplary embodiment;

[0056] Figure 4 is a schematic diagram of the b-b' section in Figure 3;

[0057] Figure 5 is a schematic diagram of another semiconductor device according to this exemplary embodiment;

[0058] Figure 6 is a magnified view of part A in Figure 5;

[0059] Figure 7 illustrates a method for fabricating a semiconductor device according to an exemplary embodiment of this invention;

[0060] Figure 8 is a first fabrication schematic diagram of the semiconductor device in Figure 1;

[0061] Figure 9 is a second fabrication schematic diagram of the semiconductor device in Figure 1;

[0062] Figure 10 is a schematic diagram of the c-c' section in Figure 9;

[0063] Figure 11 is a third fabrication schematic diagram of the semiconductor device in Figure 1;

[0064] Figure 12 is a fourth fabrication schematic diagram of the semiconductor device in Figure 1;

[0065] Figure 13 is a fifth schematic diagram of the fabrication of the semiconductor device in Figure 1;

[0066] Figure 14 is a sixth fabrication schematic diagram of the semiconductor device in Figure 1;

[0067] Figure 15 is a schematic diagram of the seventh fabrication of the semiconductor device in Figure 1;

[0068] Figure 16 is the eighth fabrication schematic diagram of the semiconductor device in Figure 1;

[0069] Figure 17 is a schematic diagram of the ninth fabrication of the semiconductor device in Figure 1;

[0070] Figure 18 is a schematic diagram of the tenth fabrication of the semiconductor device in Figure 1;

[0071] Figure 19 is a schematic diagram of the eleventh fabrication step of the semiconductor device in Figure 1;

[0072] Figure 20 is a schematic diagram of the twelfth fabrication step of the semiconductor device in Figure 1;

[0073] Figure 21 is a schematic diagram of the thirteenth fabrication step of the semiconductor device in Figure 1;

[0074] Figure 22 illustrates another method for fabricating a semiconductor device according to this exemplary embodiment;

[0075] Figure 23 is a schematic diagram of the first fabrication of the semiconductor device in Figure 3;

[0076] Figure 24 is a second fabrication schematic diagram of the semiconductor device in Figure 3;

[0077] Figure 25 is a third fabrication schematic diagram of the semiconductor device in Figure 3;

[0078] Figure 26 is a fourth fabrication schematic diagram of the semiconductor device in Figure 3;

[0079] Figure 27 is a fifth schematic diagram of the fabrication of the semiconductor device in Figure 3;

[0080] Figure 28 illustrates another method for fabricating a semiconductor device according to this exemplary embodiment;

[0081] Figure 29 is a first fabrication schematic diagram of the semiconductor device in Figure 5;

[0082] Figure 30 is a second fabrication schematic diagram of the semiconductor device in Figure 5;

[0083] Figure 31 is a third schematic diagram of the fabrication of the semiconductor device in Figure 5;

[0084] Figure 32 is a fourth fabrication schematic diagram of the semiconductor device in Figure 5;

[0085] Figure 33 is a fifth schematic diagram of the fabrication of the semiconductor device in Figure 5;

[0086] Figure 34 is a schematic diagram of the sixth fabrication of the semiconductor device in Figure 5. Detailed Implementation

[0087] This application describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0088] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0089] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0090] Figure 1 is a schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention, and Figure 2 is a schematic cross-sectional view along a-a' in Figure 1. This exemplary embodiment provides a semiconductor device, as shown in Figures 1 and 2. The semiconductor device includes multiple bit lines 100, multiple memory cell columns 200, and a first conductive layer 300. The multiple bit lines 100 are arranged at intervals along a direction perpendicular to the substrate (not shown in the figure) (i.e., a third direction). Each memory cell column 200 may include multiple memory cells 400, which are arranged along a direction perpendicular to the substrate (i.e., a third direction) and can be connected one-to-one with the multiple bit lines 100. Each memory cell 400 may include a transistor 401 and a capacitor 402. The transistor 401 may include an active layer 401-1 having a first electrode region and a second electrode region. The first electrode region serves as the first electrode 401-1a of the transistor 401, and the second electrode region serves as the second electrode 401-1b of the transistor 401. The first electrode 401-1a is connected to the bit line 100, and the second electrode 401-1b is connected to the capacitor 402. The second electrode 401-1b can be connected to the capacitor 402 through the first conductive layer 300, and / or the first electrode 401-1a can be connected to the bit line 100 through the first conductive layer 300. Furthermore, the contact resistance between the active layer 401-1 and the first conductive layer 300 is less than the contact resistance between the active layer 401-1 and the capacitor 402, and also less than the contact resistance between the active layer 401-1 and the bit line 100. Therefore, the semiconductor device of this exemplary embodiment, by increasing the first conductive layer 300 with which the contact resistance to the active layer 401-1 is smaller, can reduce the contact resistance between the transistor and the metal structures (bit line and capacitor) in contact with it, thereby improving the switching speed of the device. In other embodiments, the second electrode 401-1b may be connected to the bit line 100, the first electrode 401-1a may be connected to the capacitor 402, the second electrode 401-1b may be connected to the bit line 100 through the first conductive layer 300, and / or the first electrode 401-1a may be connected to the capacitor 402 through the first conductive layer 300. This application does not limit this.

[0091] In some exemplary embodiments, as shown in Figures 1 and 2, the semiconductor device may include multiple arrays 200 of memory cells arranged in a row on a first plane and a second plane. The arrays 200 of memory cells may be multilayer structures, and may be composed of multiple memory cells 400 stacked in a third-order upward direction. Each memory cell 400 may include a capacitor 402 and a transistor 401, which may constitute a 1T1C structure, but is not limited thereto. For example, the memory cell 400 may be a 2T1C structure, etc.

[0092] In some exemplary embodiments, as shown in Figures 1 and 2, in a memory cell 400, a capacitor 402 is located on one side of a transistor 401 in a second direction, while the capacitors 402 in a plurality of memory cells 400 of a memory cell column 200 correspond in a third direction, and the transistors 401 also correspond in a third direction. The transistor 401 includes a gate layer 401-3, a gate insulating layer 401-2, and an active layer 401-1 extending along the third direction. The gate insulating layer 401-2 is located on the outer periphery of the gate layer 401-3 and surrounds the gate layer 401-3, while the active layer 401-1 is located on the outer periphery of the gate insulating layer 401-2, such that the gate insulating layer 401-2 is sandwiched between the active layer 401-1 and the gate layer 401-3, and the active layer 401-1 and the gate layer 401-3 are insulated from each other by the gate insulating layer 401-2. The active layer 401-1 has a first electrode region and a second electrode region at its two ends in the second direction. The first electrode region and the second electrode region constitute the first electrode 401-1a and the second electrode 401-1b of the transistor 401. The region of the active layer 401-1 between the first electrode 401-1a and the second electrode 401-1b of the transistor 401 is the channel region. In some exemplary embodiments, as shown in Figures 1 and 2, the material of the active layer 401-1 may include indium gallium zinc oxide (IGZO), but is not limited to this; for example, it may be other channel materials. The material of the gate insulating layer 401-2 may include a high dielectric constant dielectric material or a low dielectric constant dielectric material, such as aluminum oxide (AlO), but is not limited to this; it may also be a material such as hafnium dioxide. The material of the gate layer 401-3 may include titanium nitride (TiN), but is not limited to this. The material of the gate layer 401-3 may be a metal material or other conductive material, or it may be a single-layer or multi-layer structure formed by conductive materials such as metals.

[0093] In some exemplary embodiments, as shown in Figures 1 and 2, the gate layers 401-3 of transistors 401 in a plurality of memory cells 400 of a memory cell column 200 are sequentially connected to form a word line 500, that is, the gate layers 401-3 of memory cells 400 arranged in a third-order upward orientation are connected to form a word line 500. The portion of the word line 500 between the gate layers 401-3 of adjacent transistors 401 is the middle portion 501. Thus, a plurality of memory cells 400 in a memory cell column 200 share a single word line 500.

[0094] In some exemplary embodiments, as shown in Figures 1 and 2, capacitor 402 may include an outer electrode 402-1 arranged in a ring, the outer electrode 402-1 being connected to the second electrode 401-1b of transistor 401. The material of the outer electrode 402-1 may include titanium nitride (TiN), but is not limited thereto; for example, it may be a metallic material or other conductive material.

[0095] In some exemplary embodiments, as shown in Figures 1 and 2, multiple bit lines 100 extend along a first direction, and the multiple bit lines 100 may be spaced apart in a third direction. In some exemplary embodiments, each bit line 100 includes an adjacent bit line body 101 and a connecting line 102. The bit line bodies 101 may all extend along the first direction, and the connecting line 102 may be located on one side of the bit line body 101 in a second direction. A transistor 401 is located on one side of the bit line 100 in the second direction, and the bit line body 101 is connected to the first electrode 401-1a of the transistor 401 via the connecting line 102. A capacitor 402 is located on the side of the transistor 401 in the second direction away from the bit line 100, and the capacitor 402 may be connected to the second electrode 401-1b of the transistor 401. Multiple memory cells 400 of a memory cell column 200 may be correspondingly connected to the multiple bit lines 100, and the transistors 401 of the multiple memory cells 400 spaced apart in a third direction are correspondingly connected to the multiple bit lines 100. Multiple memory cell columns 200 are arranged at intervals in a first direction. Memory cells 400 in the same layer of the multiple memory cell columns 200 are connected to the same bit line 100, forming a single bit line 100 shared by multiple memory cells 400. The bit line body 101 and the connecting line 102 may be made of the same material, including titanium nitride (TiN), but are not limited to this. For example, they may be made of metallic materials or other conductive materials. Alternatively, the bit line body 101 and the connecting line 102 may be made of different conductive materials.

[0096] In some exemplary embodiments, as shown in Figures 1 and 2, a first conductive layer 300 is disposed on the outer surface of transistor 401. The first conductive layer 300 covers the surface of active layer 401-1 away from gate layer 401-3. The first conductive layer 300 does not cover the surfaces of transistor 401 at its three directional ends, nor does it cover the portion of word line 500 located between two transistors 401 (i.e., the outer wall of the middle portion 501). Thus, the first electrode 401-1a contacts bit line 100 through the first conductive layer 300, and the second electrode 401-1b contacts capacitor 402 through the first conductive layer 300. The material of the first conductive layer 300 may include indium tin oxide (ITO), but is not limited to this, and may also be other conductive materials. In this example, the active layer 401-1 may be made of indium gallium zinc oxide (IGZO), and the first conductive layer 300 may be made of indium tin oxide (IGT). The work function and bandgap of IGZO and IGT are well matched. IGZO is used as the active layer of the transistor. The contact resistance between IGZO and the metal structure is high, while the contact resistance between the first conductive layer and the active layer using IGZO is low, thereby reducing the contact resistance and improving device stability.

[0097] Figure 3 is a schematic diagram of another semiconductor device according to this exemplary embodiment, and Figure 4 is a schematic cross-sectional view along line b-b' in Figure 3. In some exemplary embodiments, as shown in Figures 3 and 4, the semiconductor device may include multiple bit lines 100, multiple memory cell columns 200, and a first conductive layer 300. The memory cell column 200 may include multiple memory cells 400, and the memory cell 400 may include a transistor 401 and a capacitor 402. The first conductive layer 300 is disposed on the outer surface of the transistor 401. The first conductive layer 300 covers the surface of the active layer 401-1 away from the gate layer 401-3, and covers the surfaces of the active layer 401-1 at its third-direction ends. The material of the first conductive layer 300 may include indium tin oxide (ITO), and the material of the active layer 401-1 may include indium gallium zinc oxide. The work function and bandgap of indium gallium zinc oxide and indium tin oxide are relatively well matched, which can reduce contact resistance and improve device stability.

[0098] Figure 5 is a schematic diagram of another semiconductor device according to this exemplary embodiment, and Figure 6 is a partially enlarged schematic diagram of point A in Figure 5. In some exemplary embodiments, as shown in Figures 5 and 6, the semiconductor device includes multiple bit lines 100, multiple memory cell columns 200, and a first conductive layer 300. The memory cell column 200 includes multiple memory cells 400, and the memory cell 400 includes a transistor 401 and a capacitor 402. The first conductive layer 300 is located on the outer surface of the capacitor 402 and / or the bit lines 100. The first conductive layer 300 may cover the circumferential outer wall of the outer electrode 402-1, and / or the first conductive layer 300 may cover the surface of the connecting line 102 near the transistor 401, and also cover the surface of the bit line body 101 near the transistor 401.

[0099] In some exemplary embodiments, as shown in Figures 5 and 6, the first conductive layer 300 outside the bit line 100 contacts the first electrode 401-1a, and the first conductive layer 300 outside the capacitor 402 contacts the second electrode 401-1b, such that the first conductive layer 300 separates the bit line 100 and the active layer 401-1, and also separates the capacitor 402 and the active layer 401-1. The material of the first conductive layer 300 may include indium tin oxide (ITO), and the material of the active layer 401-1 may include indium gallium zinc oxide. The work function and bandgap of indium gallium zinc oxide and indium tin oxide are relatively well matched, which can reduce contact resistance and improve device stability.

[0100] Figures 7 to 21 are schematic diagrams of a semiconductor device fabrication process, applicable to the fabrication of semiconductor devices as shown in Figures 1 and 2. In some exemplary embodiments, as shown in Figures 7 to 21, a method for fabricating a semiconductor device includes:

[0101] S1, multiple first insulating layers and multiple second insulating layers are sequentially and alternately formed on the substrate to obtain a stacked structure.

[0102] Figure 8 is a first fabrication schematic diagram of the semiconductor device in Figure 1. In some exemplary embodiments, as shown in Figure 8, multiple first insulating layers and multiple second insulating layers are sequentially and alternately formed on the substrate to obtain a stacked structure, including:

[0103] A first insulating layer 601 and a second insulating layer 602 are alternately deposited on a substrate 700. Specifically, the two insulating layers are deposited on the substrate 700 in a first order, where the first order is the first insulating layer 601 and the second order is the second insulating layer 602. For example, a first insulating layer 601 is deposited on the substrate 700 first, followed by a second insulating layer 602, and then the remaining first insulating layers 601 and 602 are deposited in the first order. The first insulating layer 601 and the second insulating layer 602 are made of different materials. The material of the first insulating layer 601 may include silicon dioxide (SiO2), and the material of the second insulating layer 602 may include silicon nitride (SiN), but is not limited to these. They may be two other different insulating film materials. Alternatively, the second insulating layer 602 may be deposited first, followed by the first insulating layer 601, and these alternating depositions form a stacked structure 600.

[0104] S2, forming a first through hole and a second through hole in the stacked structure.

[0105] Figure 9 is a second fabrication schematic diagram of the semiconductor device in Figure 1, and Figure 10 is a cross-sectional schematic diagram along c-c' in Figure 9. In some exemplary embodiments, as shown in Figures 8 to 10, a first through-hole and a second through-hole are formed in the stacked structure, including:

[0106] The stacked structure 600 is etched to form a first via K1 and a second via K2. Both the first via K1 and the second via K2 penetrate the stacked structure 600 in a third direction, and both the first via K1 and the second via K2 penetrate all the first insulating layers 601 and 602. The first via K1 is located on one side of the second via K2 in a second direction. The first via K1 can correspond to the position of a capacitor, and the second via K2 can correspond to the position of a transistor.

[0107] S3, fill the first through hole and the second through hole with the first sacrificial material.

[0108] Figure 11 is a third fabrication schematic diagram of the semiconductor device in Figure 1. In some exemplary embodiments, as shown in Figures 9 to 11, a first sacrificial material 801 is filled into the first via K1 and the second via K2. The first sacrificial material 801 can completely fill the first via K1 and the second via K2, thereby filling the first via K1 and the second via K2. The material of the first sacrificial material 801 may include polysilicon, but is not limited to it, and may be other insulating materials different from the first insulating layer 601 and the second insulating layer 602. After filling the first sacrificial material 801 into the first via K1 and the second via K2, planarization is performed. The first sacrificial material 801 constitutes a filling layer. In other embodiments, before filling the first sacrificial material 801 into the first via K1 and the second via K2, an insulating material with a selective etching ratio to the first insulating layer and the second insulating layer may be deposited on the sidewalls of the first via K1 and the second via K2 to form a barrier layer or stop layer, and then the first sacrificial material 801 is filled into the first via K1 and the second via K2 to form a filling layer.

[0109] S4, forming a first trench in the stacked structure, and etching the first trench to form a first transverse groove.

[0110] Figure 12 is a fourth fabrication schematic diagram of the semiconductor device in Figure 1. In some exemplary embodiments, as shown in Figures 11 and 12, a first trench is formed in the stacked structure, and a first transverse trench is formed by etching the first trench, including:

[0111] First, the stacked structure 600 is etched. According to the position of the bit line, the first trench 603 is etched from the top surface of the stacked structure 600 to the substrate 700. The first trench 603 extends along a first direction. The first via K1 is located on one side of the first trench 603 in a second direction. The second via K2 is located between the first via K1 and the first trench 603.

[0112] The trench wall of the first trench 603 is etched, and multiple second insulating layers 602 are etched in a direction parallel to the substrate 700 to form multiple first transverse trenches 604. The multiple first transverse trenches 604 extend along a first direction and are spaced apart in a direction perpendicular to the substrate 700 (i.e., a third direction). The first transverse trenches 604 extend from the first trench 603 to the second via K2 in a second direction, so that the first trench 603 is laterally etched into the first sacrificial material 801 in the second via K2.

[0113] S5, a bit line is formed in the first transverse groove 604.

[0114] Figure 13 is a fifth fabrication schematic diagram of the semiconductor device in Figure 1, and Figure 14 is a sixth fabrication schematic diagram of the semiconductor device in Figure 1. In some exemplary embodiments, as shown in Figures 12 to 14, a bit line is formed in the first transverse groove, including:

[0115] First, a conductive material is deposited in the first transverse groove 604. The deposited conductive material contacts the first sacrificial material 801 in the second through hole K2 to form a bit line 100. The material of the bit line 100 may include titanium nitride (TiN).

[0116] Subsequently, the remaining space of the first transverse groove 604 and the first trench 603 is filled and planarized. First, a second sacrificial material 802 is deposited, and then a third sacrificial material 803 is deposited. The material of the second sacrificial material 802 may be different from that of the third sacrificial material 803. The material of the second sacrificial material 802 may include silicon nitride (SiN), and the material of the third sacrificial material 803 may be polycrystalline silicon, but is not limited to this. The materials of the second sacrificial material 802 and the third sacrificial material 803 may be other materials that are different from each other.

[0117] S6, etch the wall of the first through hole K1 to form multiple second transverse grooves.

[0118] Figure 15 is a seventh fabrication schematic diagram of the semiconductor device in Figure 1. In some exemplary embodiments, as shown in Figures 13 to 15, the wall of the first through-hole is etched to form a plurality of second transverse grooves, including:

[0119] First, open the first through hole K1 and remove the first sacrificial material 801 inside the first through hole K1.

[0120] Subsequently, the wall of the first through hole K1 is etched, and multiple second insulating layers 602 are etched in a direction parallel to the substrate 700 to form multiple second transverse grooves 605. The second transverse grooves 605 can be annular. The multiple second transverse grooves 605 are arranged at intervals in a direction perpendicular to the substrate 700 (i.e., a third direction). The second transverse grooves 605 extend along the second direction to the second through hole K2 and can contact the first sacrificial material 801 in the second through hole K2.

[0121] S7 forms an external electrode within the second transverse groove.

[0122] In some exemplary embodiments, as shown in Figures 13 to 15, an external electrode is formed within the second transverse groove, including:

[0123] A layer of conductive material is deposited in the second transverse groove 605 to cover the groove wall of the second transverse groove 605, forming an external electrode 402-1. The material of the external electrode 402-1 may include titanium nitride (TiN).

[0124] Subsequently, the remaining space between the second transverse groove 605 and the first through hole K1 is filled and planarized. Specifically, a sixth sacrificial material 804 and a seventh sacrificial material 808 are sequentially filled into the second transverse groove 605. The seventh sacrificial material 808 is located at the groove opening of the second transverse groove 605, and the sixth and seventh sacrificial materials 804 together fill the second transverse groove 605. The sixth sacrificial material 804 may include polycrystalline silicon, and the seventh sacrificial material 808 may include silicon dioxide (SiO2).

[0125] Next, a fourth sacrificial material 805 is deposited in the first via K1, and then a fifth sacrificial material 806 is deposited. The material of the fourth sacrificial material 805 may be different from that of the fifth sacrificial material 806. The material of the fourth sacrificial material 805 may include silicon nitride (SiN), and the material of the fifth sacrificial material 806 may include polycrystalline silicon, but is not limited thereto. The materials of the fourth sacrificial material 805 and the fifth sacrificial material 806 may be other materials that are different from each other.

[0126] S8, etch the wall of the second through hole K2 to form multiple third transverse grooves, and form a first sacrificial layer in the third transverse grooves.

[0127] Figure 16 is an eighth fabrication schematic diagram of the semiconductor device in Figure 1, and Figure 17 is a ninth fabrication schematic diagram of the semiconductor device in Figure 1. In some exemplary embodiments, as shown in Figures 15 to 17, the wall of the second via is etched to form a plurality of third transverse grooves, and a first sacrificial layer is formed in the third transverse grooves, including:

[0128] First, open the second through hole K2 and remove the first sacrificial material 801 inside the second through hole K2.

[0129] Subsequently, the wall of the second via K2 is etched, and multiple first insulating layers 601 are etched in a direction parallel to the substrate 700 to form multiple third transverse grooves 606. The third transverse grooves 606 can be annular, and the multiple third transverse grooves 606 are spaced apart in a direction perpendicular to the substrate 700 (i.e., a third direction). The third transverse grooves 606 extend from the second via K2 to the first via K1 in a second direction, such that the third transverse grooves 606 extend into the fourth sacrificial material 805 within the first via K1. Moreover, the third transverse grooves 606 also extend from the second via K2 to the first trench 603, such that the third transverse grooves 606 extend into the second sacrificial material 802 filled within the first trench 603. At this time, the portions of the external electrode 402-1 and the bit line 100 near the second via K2 are exposed, and the exposed surfaces of the external electrode 402-1 and the bit line 100 can serve as part of the inner wall of the space formed by the combination of the second via K2 and the third transverse grooves 606.

[0130] Finally, a first sacrificial layer 807 is deposited in the third transverse groove 606. The first sacrificial layer 807 may be annular and covers the sidewall of the third transverse groove 606. The sidewall of the third transverse groove 606 may include the portion of the groove wall of the third transverse groove 606 away from the second through hole K2. Moreover, the first sacrificial layer 807 does not completely fill the third transverse groove 606, leaving some space at the groove opening near the second through hole K2. The first sacrificial layer 807 covers the groove wall of the third transverse groove 606 near the first through hole K1 and the groove wall of the third transverse groove 606 near the first trench 603, such that the first sacrificial layer 807 at one end of the third transverse groove 606 near the first through hole K1 contacts the fourth sacrificial material 805 in the first through hole K1, and the first sacrificial layer 807 at one end of the third transverse groove 606 near the first trench 603 contacts the second sacrificial material 802 filled in the first trench 603.

[0131] S9, a first conductive layer, an active layer, a gate insulating layer, and a gate layer are sequentially deposited in the second via and the third transverse slot.

[0132] Figure 18 is a tenth fabrication schematic diagram of the semiconductor device in Figure 1, and Figure 19 is an eleventh fabrication schematic diagram of the semiconductor device in Figure 1. In some exemplary embodiments, as shown in Figures 17 to 19, the wall of the second via is etched to form a plurality of third transverse trenches, and a first sacrificial layer is formed in the third transverse trenches. Then, a first conductive layer, an active layer, a gate insulating layer, and a gate layer are sequentially deposited in the second via and the third transverse trenches, including:

[0133] First, a layer of conductive material is deposited in the second through hole K2 and the third transverse groove 606. This layer of conductive material covers the hole wall of the second through hole K2. The first sacrificial layer 807 is close to the surface of the second through hole K2 and the groove wall of the third transverse groove 606 that is not covered by the first sacrificial layer 807, forming the first conductive layer 300. At this time, the hole wall of the second through hole K2 is also covered by the first conductive layer 300. The first conductive layer 300 forms contact with the external electrode 402-1 and the bit line 100 on both sides in the second direction.

[0134] Subsequently, a semiconductor material, an insulating material, and another conductive material are sequentially deposited on the first conductive layer 300 to form an active layer 401-1, a gate insulating layer 401-2, and a gate layer 401-3. At this time, part of the active layer 401-1 is located in the second via K2, and another part is located in the third transverse groove 606. This part of the active layer 401-1 covers the first conductive layer 300 located in the third transverse groove 606.

[0135] S10, etching the material in the first through hole and the first trench to remove the first sacrificial layer, the first conductive layer and the active layer in the third transverse trench.

[0136] Figure 20 is a schematic diagram of the twelfth fabrication of the semiconductor device in Figure 1, and Figure 21 is a schematic diagram of the thirteenth fabrication of the semiconductor device in Figure 1. In some exemplary embodiments, as shown in Figures 15, 18, and 20 to 21, the etching of the material in the first via and the first trench to remove the first sacrificial layer, the first conductive layer, and the active layer in the third transverse trench includes:

[0137] First, by etching, the material in the first through hole K1 and the first trench 603 is removed, so that the first sacrificial layer 807 in the third transverse groove 603 is exposed.

[0138] Subsequently, the first sacrificial layer 807 in the third transverse groove 603 is etched away, so that the first conductive layer 300 in the third transverse groove 603 can be exposed on the side of the first through hole K1 and the side of the first trench 603.

[0139] Finally, the first conductive layer 300 and the active layer 401-1 within the third transverse groove 603 are etched sequentially to avoid the problem of parasitic capacitance growth. Subsequently, the sacrificial material within the outer electrode can be removed, and dielectric and conductive materials are sequentially filled to form a dielectric structure and an inner electrode. The outer electrode surrounds the inner electrode, and the capacitor dielectric structure is located between the outer and inner electrodes. The outer electrode, dielectric structure, and inner electrode constitute a capacitor.

[0140] Figures 22 to 27 are schematic diagrams illustrating the fabrication process of another semiconductor device, applicable to the fabrication of the semiconductor devices shown in Figures 3 and 4. In some exemplary embodiments, as shown in Figures 22 to 27, a method for fabricating a semiconductor device includes:

[0141] S1, multiple first insulating layers and multiple second insulating layers are sequentially and alternately formed on the substrate to obtain a stacked structure.

[0142] In some exemplary embodiments, as shown in FIG8, a plurality of first insulating layers and a plurality of second insulating layers are sequentially and alternately formed on a substrate to obtain a stacked structure, including:

[0143] A first insulating layer 601 and a second insulating layer 602 are alternately deposited on a substrate 700. Specifically, the two insulating layers are deposited on the substrate 700 in a first order, where the first order is the first insulating layer 601 and the second order is the second insulating layer 602. For example, a first insulating layer 601 is deposited first, followed by a second insulating layer 602 on the substrate 700, and then the remaining first insulating layers 601 and 602 are deposited in the first order. The first insulating layer 601 and the second insulating layer 602 are made of different materials. The material of the first insulating layer 601 may include silicon dioxide (SiO2), and the material of the second insulating layer 602 may include silicon nitride (SiN), but is not limited to these. They may be two other different insulating film materials. Alternatively, the second insulating layer 602 may be deposited first, followed by the first insulating layer 601, and these alternating depositions form a stacked structure 600.

[0144] S2, forming a first through hole and a second through hole in the stacked structure.

[0145] In some exemplary embodiments, as shown in Figures 8 to 10, forming a first through-hole and a second through-hole in the stacked structure includes:

[0146] The stacked structure 600 is etched to form a first via K1 and a second via K2. Both the first via K1 and the second via K2 penetrate the stacked structure 600 in a third direction, and both the first via K1 and the second via K2 penetrate all the first insulating layers 601 and 602. The first via K1 is located on one side of the second via K2 in a second direction. The first via K1 can correspond to the position of a capacitor, and the second via K2 can correspond to the position of a transistor.

[0147] S3, fill the first through hole and the second through hole with the first sacrificial material.

[0148] As shown in Figures 9 to 11, a first sacrificial material 801 is filled into the first via K1 and the second via K2. The first sacrificial material 801 can completely fill the first via K1 and the second via K2, thus filling the first via K1 and the second via K2. The material of the first sacrificial material 801 may include polysilicon, but is not limited to it, and may be other insulating materials different from the first insulating layer 601 and the second insulating layer 602. After filling the first via K1 and the second via K2 with the first sacrificial material 801, planarization is performed. The first sacrificial material 801 constitutes a filling layer. In other embodiments, before filling the first via K1 and the second via K2 with the first sacrificial material 801, an insulating material with a selective etching ratio to the first insulating layer and the second insulating layer may be deposited on the sidewalls of the first via K1 and the second via K2 to form a barrier layer or stop layer, and then the first sacrificial material 801 is filled into the first via K1 and the second via K2 to form a filling layer.

[0149] S4, forming a first trench in the stacked structure, and etching the first trench to form a first transverse groove.

[0150] Figure 23 is a first fabrication schematic diagram of the semiconductor device in Figure 3. In some exemplary embodiments, as shown in Figures 10, 11, and 23, a first trench is formed in the stacked structure, and a first transverse trench is etched into the first trench, including:

[0151] First, the stacked structure 600 is etched. According to the position of the bit line, the first trench 603 is etched from the top surface of the stacked structure 600 to the substrate 700. The first trench 603 extends along a first direction. The first via K1 is located on one side of the first trench 603 in a second direction. The second via K2 is located between the first via K1 and the first trench 603.

[0152] The trench wall of the first trench 603 is etched, and multiple second insulating layers 602 are etched in a direction parallel to the substrate 700 to form multiple first transverse trenches 604. The multiple first transverse trenches 604 extend along a first direction and are spaced apart in a direction perpendicular to the substrate 700 (i.e., a third direction). The first transverse trenches 604 extend from the first trench 603 to the second via K2 in a second direction but do not extend to the second via K2. There are multiple layers of second insulating layers 602 between the second via K2 and the first trench 603, and the two are not connected.

[0153] S5 forms a bit line within the first transverse groove.

[0154] In some exemplary embodiments, as shown in FIG23, forming a bit line within the first transverse slot includes:

[0155] First, a conductive material is deposited in the first transverse groove 604 to form a bit line 100. The bit line 100 does not protrude from the first transverse groove 604. The material of the bit line 100 may include titanium nitride (TiN).

[0156] Subsequently, the remaining space in the first transverse groove 604 and the first trench 603 is filled and flattened.

[0157] S6, etch the wall of the first through hole to form multiple second transverse grooves.

[0158] Figure 24 is a second fabrication schematic diagram of the semiconductor device in Figure 3. In some exemplary embodiments, as shown in Figures 23 and 24, the wall of the first through-hole is etched to form a plurality of second transverse grooves, including:

[0159] First, open the first through hole K1 and remove the first sacrificial material inside the first through hole K1.

[0160] Subsequently, the wall of the first through hole K1 is etched, and multiple second insulating layers 602 are etched in a direction parallel to the substrate 700 to form multiple second transverse grooves 605. The second transverse grooves 605 can be annular. The multiple second transverse grooves 605 are arranged at intervals in a direction perpendicular to the substrate 700 (i.e., a third direction). The second transverse grooves 605 can extend towards the second through hole K2 along the second direction, but do not extend to the second through hole K2. There are multiple layers of second insulating layers 602 between the second through hole K2 and the first through hole K1, and the two are not connected.

[0161] S7 forms an external electrode within the second transverse groove.

[0162] In some exemplary embodiments, as shown in FIG24, an external electrode is formed within the second transverse groove, including:

[0163] A layer of conductive material is deposited in the second transverse groove 605 to cover the groove wall of the second transverse groove 605, forming an external electrode 402-1. The material of the external electrode 402-1 may include titanium nitride (TiN).

[0164] Subsequently, the remaining space in the second transverse groove 605 and the first via K1 is filled and planarized. In this example, a sixth sacrificial material and a seventh sacrificial material are sequentially filled into the second transverse groove 605. The seventh sacrificial material is located at the groove opening of the second transverse groove 605, and the sixth and seventh sacrificial materials together fill the second transverse groove 605. The sixth sacrificial material may include polysilicon, and the seventh sacrificial material may include silicon dioxide (SiO2). Next, a layer of fourth sacrificial material is deposited in the first via K1, followed by a fifth sacrificial material. The material of the fourth sacrificial material may be different from that of the fifth sacrificial material. The material of the fourth sacrificial material may include silicon nitride (SiN), and the material of the fifth sacrificial material may be polysilicon, but is not limited to these. The materials of the fourth and fifth sacrificial materials may be other materials that are different from each other.

[0165] S8, etch the wall of the second through hole to form multiple third transverse grooves.

[0166] Figure 25 is a third fabrication schematic diagram of the semiconductor device in Figure 3. In some exemplary embodiments, as shown in Figures 24 and 25, the wall of the second via is etched to form a plurality of third transverse grooves, including:

[0167] First, open the second through hole K2 and remove the first sacrificial material inside the second through hole K2.

[0168] Subsequently, the wall of the second via K2 is etched, and multiple second insulating layers 602 are etched in a direction parallel to the substrate 700 to form multiple third transverse grooves 606. The third transverse grooves 606 can be annular, and the multiple third transverse grooves 606 are spaced apart in a direction perpendicular to the substrate 700 (i.e., the third direction). The third transverse grooves 606 extend from the second via K2 to the first via K1 in a second direction, so that the third transverse grooves 606 extend to the external electrode 402-1. Moreover, the third transverse grooves 606 also extend from the second via K2 to the first trench 603, so that the third transverse grooves 606 extend to the bit line 100. At this time, the portions of the external electrode 402-1 and the bit line 100 near the second via K2 are exposed, and the exposed surfaces of the external electrode 402-1 and the bit line 100 can serve as part of the groove wall of the third transverse groove 606.

[0169] S9, a first conductive layer, an active layer, a gate insulating layer, and a gate layer are sequentially deposited in the second via and the third transverse slot.

[0170] Figure 26 is a fourth fabrication schematic diagram of the semiconductor device in Figure 3, and Figure 27 is a fifth fabrication schematic diagram of the semiconductor device in Figure 3. As shown in Figures 24 to 26, the wall of the second via is etched to form multiple third transverse trenches, and a first conductive layer, an active layer, a gate insulating layer, and a gate layer are sequentially deposited in the second via and the third transverse trenches, including:

[0171] First, a layer of conductive material is deposited in the second through hole K2 and the third transverse groove 606. The conductive material covers the hole wall of the second through hole K2 and the groove wall of the third transverse groove 606, forming a first conductive layer 300. At this time, the first conductive layer 300 is located in the hole wall of the second through hole K2 and also in the third transverse groove 606.

[0172] Subsequently, a semiconductor material, an insulating material, and another conductive material are sequentially deposited on the first conductive layer 300 to form an active layer 401-1, a gate insulating layer 401-2, and a gate layer 401-3. At this time, a portion of the active layer 401-1, the gate insulating layer 401-2, and the gate layer 401-3 are located in the second via K2, and another portion is located in the third transverse groove 606.

[0173] Finally, the first conductive layer 300, active layer 401-1, gate insulating layer 401-2, and gate layer 401-3 within the second via K2 are etched away, leaving the first conductive layer 300, active layer 401-1, gate insulating layer 401-2, and gate layer 401-3 within the third transverse slot 606. At this point, the first conductive layer 300, active layer 401-1, gate insulating layer 401-2, and gate layer 401-3 are all arranged at intervals along a third direction within the second via K2, exposing the first conductive layer 300, active layer 401-1, gate insulating layer 401-2, gate layer 401-3, and first insulating layer 601 within the second via K2.

[0174] Next, insulating material is deposited within the second via K2 to cover the exposed first conductive layer 300, active layer 401-1, gate insulating layer 401-2, gate layer 401-3, and first insulating layer 601. Then, an etch-back process is performed to expose the gate layer 401-3. Conductive material is then deposited again to form word lines extending in a third direction. Following this, the sacrificial material within the outer electrode is removed, and dielectric and conductive materials are sequentially filled to form a dielectric structure and an inner electrode. The outer electrode surrounds the inner electrode, and the dielectric structure is positioned between the outer and inner electrodes. The outer electrode, dielectric structure, and inner electrode constitute a capacitor.

[0175] Figures 28 to 34 are schematic diagrams of a semiconductor device fabrication process, applicable to the fabrication of semiconductor devices as shown in Figures 5 and 6. In some exemplary embodiments, as shown in Figures 28 to 34, a method for fabricating a semiconductor device includes:

[0176] S1, multiple first insulating layers and multiple second insulating layers are sequentially and alternately formed on the substrate to obtain a stacked structure.

[0177] In some exemplary embodiments, as shown in FIG8, a plurality of first insulating layers and a plurality of second insulating layers are sequentially and alternately formed on a substrate to obtain a stacked structure, including:

[0178] A first insulating layer 601 and a second insulating layer 602 are alternately deposited on a substrate 700. Specifically, the two insulating layers are deposited on the substrate 700 in a first order, where the first order is the first insulating layer 601 and the second order is the second insulating layer 602. For example, a first insulating layer 601 is deposited first, followed by a second insulating layer 602 on the substrate 700, and then the remaining first insulating layers 601 and 602 are deposited in the first order. The first insulating layer 601 and the second insulating layer 602 are made of different materials. The material of the first insulating layer 601 may include silicon dioxide (SiO2), and the material of the second insulating layer 602 may include silicon nitride (SiN), but is not limited to these. They may be two other different insulating film materials. Alternatively, the second insulating layer 602 may be deposited first, followed by the first insulating layer 601, and these alternating depositions form a stacked structure 600.

[0179] S2, forming a first through hole and a second through hole in the stacked structure.

[0180] In some exemplary embodiments, as shown in Figures 8 to 10, forming a first through-hole and a second through-hole in the stacked structure includes:

[0181] The stacked structure 600 is etched to form a first via K1 and a second via K2. Both the first via K1 and the second via K2 penetrate the stacked structure 600 in a third direction, and both the first via K1 and the second via K2 penetrate all the first insulating layers 601 and 602. The first via K1 is located on one side of the second via K2 in a second direction. The first via K1 can correspond to the position of a capacitor, and the second via K2 can correspond to the position of a transistor.

[0182] S3, fill the first through hole and the second through hole with the first sacrificial material.

[0183] In some exemplary embodiments, as shown in Figures 9 to 11, a first sacrificial material 801 is filled into the first via K1 and the second via K2. The first sacrificial material 801 can completely fill the first via K1 and the second via K2, thereby filling the first via K1 and the second via K2. The material of the first sacrificial material 801 may include, but is not limited to, polysilicon, and may be other insulating materials different from the first insulating layer 601 and the second insulating layer 602. After filling the first via K1 and the second via K2 with the first sacrificial material 801, planarization is performed. The first sacrificial material 801 constitutes a filling layer. In other embodiments, before filling the first via K1 and the second via K2 with the first sacrificial material 801, an insulating material with a selective etching ratio to the first insulating layer and the second insulating layer may be deposited on the sidewalls of the first via K1 and the second via K2 to form a barrier layer or stop layer, and then the first sacrificial material 801 is filled into the first via K1 and the second via K2 to form a filling layer.

[0184] S4, forming a first trench in the stacked structure, and etching the first trench to form a first transverse groove.

[0185] In some exemplary embodiments, as shown in Figures 11 and 12, forming a first trench in the stacked structure and etching the first trench to form a first transverse groove includes:

[0186] First, the stacked structure 600 is etched. According to the position of the bit line, the first trench 603 is etched from the top surface of the stacked structure 600 to the substrate 700. The first trench 603 extends along a first direction. The first via K1 is located on one side of the first trench 603 in a second direction. The second via K2 is located between the first via K1 and the first trench 603.

[0187] The trench walls of the first trench 603 are etched, and multiple second insulating layers 602 are etched in a direction parallel to the substrate 700 to form multiple first transverse trenches 604. The multiple first transverse trenches 604 are arranged at intervals in a direction perpendicular to the substrate 700 (i.e., a third direction). The first transverse trenches 604 extend from the first trench 603 to the second via K2 in a second direction, so that the sidewalls of the first trench 603 are laterally etched into the first sacrificial material 801 in the second via K2.

[0188] S5, a first conductive layer is deposited in the first trench and the first transverse groove, and the first conductive layer in the first trench is etched away.

[0189] Figure 29 is a first fabrication diagram of the semiconductor device in Figure 5, and Figure 30 is a second fabrication diagram of the semiconductor device in Figure 5. In some exemplary embodiments, as shown in Figures 11, 12, 29, and 30, a first conductive layer is deposited in the first trench and the first transverse trench, and the first conductive layer in the first trench is etched away, including:

[0190] First, a layer of conductive material is deposited in the first trench 603 and the first transverse groove 604. The conductive material covers the trench walls of the first trench 603 and the first transverse groove 604, forming a first conductive layer 300. The first conductive layer 300 in the first transverse groove 604 covers the surface of the first sacrificial material in the second through hole K2 near the first transverse groove 604.

[0191] The first conductive layer 300 in the first trench 603 is then etched away, exposing the trench wall of the first trench 603.

[0192] S6, a bit line is formed in the first transverse groove.

[0193] In some exemplary embodiments, as shown in Figures 11, 12, 29, and 30, a bit line is formed within the first transverse groove, including:

[0194] Conductive material is deposited in the first transverse groove 604 whose groove wall is covered by the first conductive layer 300, and the conductive material does not fill the first transverse groove 604. The conductive material therein forms a bit line 100, such that the first conductive layer 300 is located between the groove wall of the first transverse groove 604 and the bit line 100.

[0195] Subsequently, insulating material is filled into the first trench 603 to fill the first trench 603 and planarize it. A second sacrificial material is deposited first, and then a third sacrificial material is deposited. The material of the second sacrificial material may be different from that of the third sacrificial material. The material of the second sacrificial material may include silicon nitride (SiN), and the material of the third sacrificial material may be polycrystalline silicon, but is not limited to this. The materials of the second sacrificial material and the third sacrificial material may be other materials that are different from each other.

[0196] S7, etch the first through hole to form the second transverse groove.

[0197] Figure 31 is a third fabrication diagram of the semiconductor device in Figure 5, and Figure 32 is a fourth fabrication diagram of the semiconductor device in Figure 5. In some exemplary embodiments, as shown in Figures 31 and 32, etching the first through-hole to form the second transverse groove includes:

[0198] First, open the first through hole K1 and remove the material inside the first through hole K1.

[0199] The wall of the first through hole K1 is then etched, and multiple second insulating layers 602 are etched in a direction parallel to the substrate 700 to form multiple second transverse grooves 605. The second transverse grooves 605 can be annular. The multiple second transverse grooves 605 are arranged at intervals in a direction perpendicular to the substrate 700 (i.e., a third direction). The second transverse grooves 605 extend along the second direction to the second through hole K2, so that the second transverse grooves 605 extend into the first sacrificial material in the second through hole K2.

[0200] S8, deposit the first conductive layer in the second transverse groove.

[0201] Figure 33 is a fifth fabrication diagram of the semiconductor device in Figure 5. In some exemplary embodiments, as shown in Figures 31 to 33, a first conductive layer is deposited in the second transverse trench, including:

[0202] A conductive material is deposited on the wall of the first through hole K1 and the wall of the second transverse groove 605 to form a first conductive layer 300. At this time, the first conductive layer 300 is located both inside the second transverse groove 605 and inside the first through hole K1.

[0203] Subsequently, the first conductive layer 300 inside the first through hole K1 is etched away, leaving only the first conductive layer 300 inside the second transverse groove 605.

[0204] A first conductive layer 300 is formed within the second transverse groove 605.

[0205] S9 forms an external electrode within the second transverse groove.

[0206] In some exemplary embodiments, as shown in Figures 32 and 33, an external electrode is formed within the second transverse groove, including:

[0207] Another conductive material is deposited in the second transverse groove 605, and the conductive material covers the first conductive layer 300. This conductive material forms the outer electrode 402-1, such that the first conductive layer 300 is located between the groove wall of the second transverse groove 605 and the outer electrode 402-1.

[0208] Subsequently, insulating material is filled into the second transverse groove 605 and the first through hole K1 to fill them. In this example, a sixth sacrificial material and a seventh sacrificial material are sequentially filled into the second transverse groove 605, with the seventh sacrificial material located at the groove opening of the second transverse groove 605. The sixth and seventh sacrificial materials together fill the second transverse groove 605. The sixth sacrificial material may include polycrystalline silicon, and the seventh sacrificial material may include silicon dioxide (SiO2). Next, a layer of fourth sacrificial material is deposited in the first through hole K1, followed by a fifth sacrificial material. The materials of the fourth and fifth sacrificial materials may be different. The fourth sacrificial material may include silicon nitride (SiN), and the fifth sacrificial material may be polycrystalline silicon, but is not limited to these. The materials of the fourth and fifth sacrificial materials may be other materials that are different from each other.

[0209] S10 forms a transistor.

[0210] Figure 34 is a sixth fabrication diagram of the semiconductor device in Figure 5. In some exemplary embodiments, as shown in Figures 33 and 34, a transistor is formed, including:

[0211] First, open the second through hole K2, and etch away the filling material inside the second through hole K2, so that the first conductive layer 300 in the first horizontal groove 604 and the first conductive layer 300 in the second horizontal groove 605 are exposed and become part of the hole wall of the second through hole K2.

[0212] Subsequently, the wall of the second via K2 is etched, and multiple first insulating layers 601 are etched in a direction parallel to the substrate 700 to form multiple third transverse grooves 606. The third transverse grooves 606 may be annular. The multiple third transverse grooves 606 are spaced apart in a direction perpendicular to the substrate 700 (i.e., a third direction). The third transverse grooves 606 extend from the second via K2 to the first via K1 in a second direction, such that the third transverse grooves 606 extend into the fourth sacrificial material within the first via K1. Moreover, the second via K2 also extends from the third transverse grooves 606 to the first trench 603, such that the third transverse grooves 606 extend into the second sacrificial material filled within the first trench 603. At this time, the first conductive layer 300 covering the external electrode 402-1 and the bit line 100 can be exposed near the second via K2.

[0213] Finally, within the space formed by the second via K2 and the third transverse trench 606, semiconductor material, insulating material, and conductive material are sequentially deposited to form an active layer 401-1, a gate insulating layer 401-2, and a gate layer 401-3, forming word lines extending along the third direction. Subsequently, the first via K1 is opened, and the active layer between two adjacent external electrodes in the third direction is etched away; the first channel 603 is opened, and the active layer between two adjacent bit lines in the third direction is etched away. Next, the sacrificial material within the external electrodes can be removed, and dielectric material and conductive material are sequentially filled to form a dielectric structure and an inner electrode. The external electrode surrounds the inner electrode, and the dielectric structure is located between the external electrode and the inner electrode. The external electrode, dielectric structure, and inner electrode constitute a capacitor.

[0214] In some exemplary embodiments, a method for fabricating a semiconductor device, applied to the aforementioned semiconductor device, includes:

[0215] Multiple first insulating layers and multiple second insulating layers are sequentially and alternately formed on a substrate to obtain a stacked structure;

[0216] In the stacked structure, a first through-hole, a second through-hole, and a first trench are formed in a direction perpendicular to the substrate. The first trench extends in a first direction and is configured to define the position of the bit line. The first through-hole is located on one side of the first trench in a second direction, and the second through-hole is located between the first through-hole and the first trench. The first through-hole is located on one side of the second through-hole in a second direction and is configured to define the position of the capacitor. The second through-hole is configured to define the position of the transistor. The first direction and the second direction are perpendicular to and parallel to the substrate.

[0217] The first conductive layer is formed based on the stacked structure.

[0218] In some exemplary embodiments, the active layer 401-1 may be a wide bandgap material, such as a metal oxide material with a bandgap greater than 1.65 eV. The material of the active layer 401-1 may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as N, Si, etc.; it may also contain other small amounts of doping elements.

[0219] In some exemplary embodiments, the active layer 401-1 may contain any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW) Materials such as O, IWO, titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used. The choice of materials is simply to ensure that the transistor's leakage current meets the requirements; adjustments can be made based on specific circumstances. These materials have wide band gaps and low leakage current. For example, when the active layer 401-1 is made of IGZO, the transistor's leakage current is less than or equal to 10⁻¹⁵ A, thereby improving the performance of the dynamic memory. The above-mentioned metal oxide active layer materials only emphasize the element type, not the atomic percentage or the film quality.

[0220] In some exemplary embodiments, the material of the bit line can be selected from any one or more other metallic materials with similar properties, such as tungsten, molybdenum, and cobalt. The bit line can be a single-layer or multi-layer structure, for example, it can be a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0221] In some exemplary embodiments, the electrode material of the gate layer can be any one or more of the following different types of materials: for example, metals containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; metal alloys containing the aforementioned metals; metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), and indium oxide (InO); metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN); of course, it can also be polycrystalline silicon; it can also be a conductive material doped with a semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials exhibiting conductivity, etc.

[0222] In some exemplary embodiments, the gate insulating layer may comprise one or more Low-K and / or High-K dielectric materials, or comprise two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of this application will be illustrated exemplarily below. Low-K materials, such as silicon oxide. High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include, but is not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc., high-K materials.

[0223] In some exemplary embodiments, an electronic device includes the aforementioned semiconductor device, or includes a semiconductor device obtained by the aforementioned semiconductor device fabrication method. The electronic device can be any electronic product with storage functionality, such as a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank.

[0224] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0225] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0226] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0227] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0228] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0229] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0230] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A semiconductor device, characterized in that, include: Multiple bit lines are arranged at intervals along the direction perpendicular to the substrate; Multiple memory cell columns, each memory cell column including multiple memory cells, the multiple memory cells are arranged along a direction perpendicular to the substrate and are connected to multiple bit lines one by one; each memory cell includes a transistor and a capacitor, the transistor includes an active layer having a first electrode region and a second electrode region, the first electrode region serving as the first electrode of the transistor, the second electrode region serving as the second electrode of the transistor, the first electrode being connected to the bit line, and the second electrode being connected to the capacitor; A first conductive layer, wherein the first electrode is configured to connect to the bit line through the first conductive layer, and / or the second electrode is configured to connect to the capacitor through the first conductive layer; The contact resistance between the active layer and the first conductive layer is set to be less than the contact resistance between the active layer and the capacitor, and less than the contact resistance between the active layer and the bit line.

2. The semiconductor device according to claim 1, characterized in that, The first conductive layer is disposed on the outer surface of the active layer, or on the surface of the capacitor facing the active layer and / or the surface of the bit line facing the active layer.

3. The semiconductor device according to claim 2, characterized in that, The transistor further includes a gate layer extending in a direction perpendicular to the substrate, the active layer surrounding the outer periphery of the gate layer and being insulated from the gate layer; the first conductive layer is disposed on the transistor and covers the surface of the active layer away from the gate layer.

4. The semiconductor device according to claim 2, characterized in that, The capacitor includes an outer electrode arranged in a ring, and the first conductive layer is disposed on the capacitor and covers the circumferential outer wall of the outer electrode.

5. The semiconductor device according to claim 2, characterized in that, Each bit line includes an adjacent bit line body and a connecting line, the connecting line being located on the side of the bit line body closer to the transistor, and the bit line body being connected to the transistor via the connecting line; the first conductive layer is disposed on the bit line and covers the surface of the connecting line near the transistor.

6. The semiconductor device according to claim 5, characterized in that, The first conductive layer is configured to cover the outer surface of the bit line body and the connecting line.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, The active layer is made of indium gallium zinc oxide, and the first conductive layer is made of indium tin oxide.

8. The semiconductor device according to any one of claims 1 to 6, characterized in that, The bit line extends along a first direction, the transistor is located on one side of the bit line in a second direction, and the capacitor is located on the side of the transistor away from the bit line in the second direction. The first direction and the second direction are perpendicular to each other and are both parallel to the substrate.

9. A method for fabricating a semiconductor device, characterized in that, An application to the semiconductor device of claim 1, comprising: sequentially and alternately forming a plurality of first insulating layers and a plurality of second insulating layers on a substrate to obtain a stacked structure; forming a first via, a second via, and a first trench in the stacked structure, the first trench extending along a direction perpendicular to the substrate, the first trench being configured to define the position of the bit line; the first via being located on one side of the first trench in a second direction, the second via being located between the first via and the first trench, the first via being located on one side of the second via in the second direction, the first via being configured to define the position of the capacitor, the second via being configured to define the position of the transistor, the first direction and the second direction being perpendicular and both parallel to the substrate; and forming a first conductive layer based on the stacked structure.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The method of forming the first conductive layer based on the stacked structure includes: etching the trench walls of the first trench; etching a plurality of second insulating layers in a direction parallel to the substrate to form a plurality of first transverse trenches, wherein the plurality of first transverse trenches are spaced apart in a direction perpendicular to the substrate, and the first transverse trenches extend from the first trench to the second via in a second direction; forming bit lines within the first transverse trenches; etching the via walls of the first via; etching a plurality of second insulating layers in a direction parallel to the substrate to form a plurality of second transverse trenches, wherein the plurality of second transverse trenches are spaced apart in a direction perpendicular to the substrate, and the second transverse trenches extend along the second direction. The process extends to the second via; an external electrode is formed in the second transverse trench; the wall of the second via is etched, and multiple first insulating layers are etched in a direction parallel to the substrate to form multiple third transverse trenches, and a first sacrificial layer is formed in the third transverse trenches. The multiple third transverse trenches are arranged at intervals in a direction perpendicular to the substrate. The third transverse trenches extend from the second via to the first via and from the second via to the first trench in the second direction. The first sacrificial layer covers the sidewall of the third transverse trench. A first conductive layer, an active layer, a gate insulating layer, and a gate layer are sequentially deposited in the second via and the third transverse trenches.

11. The method for fabricating a semiconductor device according to claim 9, characterized in that, The method of forming the first conductive layer based on the stacked structure includes: etching the trench wall of the first trench; etching a plurality of second insulating layers in a direction parallel to the substrate to form a plurality of first transverse trenches, the plurality of first transverse trenches being spaced apart in a direction perpendicular to the substrate; the first transverse trenches extending from the first trench to the second via in a second direction; forming a first conductive layer and a bit line located within the first transverse trenches, the first conductive layer being located between the trench wall of the first transverse trench and the bit line; and / or etching the wall of the first via; etching a plurality of second insulating layers in a direction parallel to the substrate to form a plurality of second transverse trenches, the plurality of second transverse trenches being spaced apart in a direction perpendicular to the substrate; the second transverse trenches extending along the second direction to the second via; forming a first conductive layer and an external electrode located within the second transverse trenches, the first conductive layer being located between the trench wall of the second transverse trench and the external electrode.

12. The method for fabricating a semiconductor device according to claim 9, characterized in that, The method of forming the first conductive layer based on the stacked structure includes: etching the trench wall of the first trench; etching a plurality of second insulating layers in a direction parallel to the substrate to form a plurality of first transverse trenches, the plurality of first transverse trenches being spaced apart in a direction perpendicular to the substrate; the first transverse trenches extending from the first trench to the second via in a second direction but not connecting the first trench and the second via; forming a bit line within the first transverse trench; etching the wall of the first via; etching a plurality of second insulating layers in a direction parallel to the substrate to form a plurality of second transverse trenches, the second transverse trenches extending from the first via to the second via in the second direction but not extending to the second via; forming an external electrode within the second transverse trench; etching the wall of the second via; etching a plurality of second insulating layers in a direction parallel to the substrate to form a plurality of third transverse trenches, the third transverse trenches extending from the second via to the bit line and from the second via to the external electrode in the second direction; and sequentially depositing a first conductive layer, an active layer, a gate insulating layer, and a gate layer within the third transverse trenches.

13. The method for fabricating a semiconductor device according to claim 10, characterized in that, The process of forming the first conductive layer based on the stacked structure further includes: etching the material in the first via and the first trench to remove the first sacrificial layer, the first conductive layer and the active layer in the third transverse groove.

14. The method for fabricating a semiconductor device according to claim 12, characterized in that, The formation of a first conductive layer, an active layer, a gate insulating layer, and a gate layer within the third transverse groove includes: sequentially depositing the first conductive layer, the active layer, the gate insulating layer, and the gate layer in the second via and the third transverse groove; etching away the first conductive layer, the active layer, the gate insulating layer, and the gate layer within the second via, while retaining the first conductive layer, the active layer, the gate insulating layer, and the gate layer within the third transverse groove.

15. The method for fabricating a semiconductor device according to any one of claims 9 to 14, characterized in that, Forming a first via, a second via, and a first trench in the stacked structure along a direction perpendicular to the substrate includes: etching the stacked structure to form the first via and the second via; filling the first via and the second via with a second sacrificial layer and planarizing it.

16. An electronic device, characterized in that, It includes the semiconductor device as described in any one of claims 1 to 8, or the semiconductor device obtained by the method of preparing the semiconductor device as described in any one of claims 9 to 15.

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