A type F series resonant voltage-controlled oscillator

Abstract

This invention relates to the field of integrated circuit technology, specifically to a Class F series resonant voltage-controlled oscillator, which consists of four identical unit circuits connected end to end to form a closed loop structure. Each unit circuit includes an active circuit and an LC series resonant network. The LC series resonant network includes a main resonant cavity and an auxiliary resonant cavity. This invention achieves a systematic improvement in phase noise performance through the series resonant topology and harmonic shaping mechanism.

Description

Technical Field

[0001] This invention applies to the field of integrated circuit technology, specifically relating to a Class F series resonant voltage-controlled oscillator. Background Technology

[0002] In modern wireless communication systems, accurate clock signals are crucial for reliable data transmission. Phase-locked loops (PLLs), as key clock generation circuits, can generate high-precision clock signals with low power consumption and low noise requirements. Therefore, they are widely used in frequency synthesizers, clock generation circuits, clock data recovery circuits, and wireless transceivers. The performance of the PLL directly determines the quality of various signals in the communication system.

[0003] As a core component of a phase-locked loop (PLL), the voltage-controlled oscillator (VCO) is responsible for providing a stable local oscillation signal and performing up-conversion or down-conversion of the signal. The quality of its output signal directly affects the overall performance of the PLL. Simultaneously, the VCO is also a major source of phase noise in the PLL, and its noise characteristics significantly impact the application scenarios of the PLL. For example, in high-speed wired communication systems, PLLs are often used to provide clock signals. In this case, the phase noise of the VCO affects the out-of-band noise of the PLL, increasing clock jitter and thus affecting the sampling accuracy and signal-to-noise ratio of subsequent circuits such as analog-to-digital converters (ADCs). In wireless communication systems, the phase noise of the VCO leads to an increase in receiver noise levels, causing the local oscillator signal to down-convert interference signals along with the local oscillator signal, and introducing bit error risks during demodulation of digitally modulated signals. Furthermore, in radar systems, the noise of the VCO raises the system noise floor, reducing the ability to detect small targets. Therefore, the stability and accuracy of the clock signal are crucial in various applications.

[0004] With the continuous development of communication technology, voltage-controlled oscillators (VCOs) and high-speed phase-locked loops (PLLs) have become a research hotspot of common interest to both academia and industry. How to further reduce phase noise and expand the tuning range to provide a higher quality local oscillator signal is an important research topic in this field. Summary of the Invention

[0005] To address the aforementioned problems, this invention provides a Class F series resonant voltage-controlled oscillator, consisting of four identical unit circuits connected end-to-end to form a closed-loop structure; wherein the ports of each unit circuit include a non-inverting input terminal, an inverting input terminal, and an output terminal; in the closed-loop structure:

[0006] The non-inverting input and inverting input of the first unit circuit are respectively connected to signal V0 and signal V. 180 The output terminal of the first unit circuit outputs signal V. 270 ;

[0007] The non-inverting and inverting input terminals of the second unit circuit are respectively connected to signal V. 270 and signal V 90 The output terminal of the second unit circuit outputs signal V. 180 ;

[0008] The non-inverting and inverting input terminals of the third unit circuit are respectively connected to signal V. 180 And signal V0, the output terminal of the third unit circuit outputs signal V 90 ;

[0009] The non-inverting and inverting input terminals of the fourth unit circuit are respectively connected to signal V. 90 and signal V 270 The output terminal of the fourth unit circuit outputs signal V0.

[0010] The beneficial effects of this invention are:

[0011] This invention provides a Class F series resonant voltage-controlled oscillator. The active circuit employs an NMOS-NMOS inverter structure, which facilitates faster switching speeds and a shorter noise injection window, achieving reliable oscillation without the need for additional startup circuitry. In the circuit, MOSFETs are used as switching devices rather than transconductors, operating in the saturation region only within a very short zero-crossing window, and in the linear region for most of the oscillation cycle, effectively short-circuiting most of their generated noise to the power supply or ground. By optimizing device size and node capacitance, the noise contribution of the active core can be further suppressed to a negligible level. The circuit is based on a series resonant topology, utilizing a high-Q resonant cavity to generate a voltage amplitude on the passive devices that is much higher than the power supply voltage. This high-swing signal effectively improves the signal-to-noise ratio of the oscillation energy, thereby significantly suppressing the phase noise introduced by the inherent losses of the resonant cavity. By setting an auxiliary resonant cavity in the LC series resonant network, namely the series structure of L2 and C2, the resonant cavity forms an admittance peak at the third harmonic frequency. This structure allows the current injected into the resonant cavity to be shaped into a quasi-square wave, thus effectively converting the third harmonic current into voltage. When the fundamental and third harmonic voltages are superimposed in an appropriate ratio, a square wave voltage signal with steeper edges is formed at the switching node, and its zero-crossing slope is... The voltage waveform's zero-crossing slope increases significantly. This increase directly leads to a decrease in the peak value of the impulse sensitivity function, thus significantly reducing the mean square value of the ISF throughout the entire cycle. According to Leeson's phase noise model, phase noise and... Proportional to the phase noise performance, this invention further achieves a systematic improvement in phase noise performance through the aforementioned series resonant topology and harmonic shaping mechanism. Attached Figure Description

[0012] Figure 1 The schematic diagram of an existing basic four-phase series resonant oscillator;

[0013] Figure 2 This is a circuit diagram of the F-type series resonant voltage-controlled oscillator of the present invention;

[0014] Figure 3 This is a schematic diagram of the F-type series resonant voltage-controlled oscillator of the present invention;

[0015] Figure 4 This is a schematic diagram of the unit circuit of the present invention;

[0016] Figure 5 This is a schematic diagram of the tuning unit circuit of the present invention;

[0017] Figure 6 This is a simulation diagram of the amplitude-frequency and phase-frequency characteristics of the Y-parameter of the LC series resonant cavity in an embodiment of the present invention;

[0018] Figure 7 This is a simulation comparison diagram of the injected resonant cavity current before and after harmonic tuning in an embodiment of the present invention;

[0019] Figure 8 This is a simulation comparison diagram of the resonant cavity node voltage before and after harmonic tuning in an embodiment of the present invention;

[0020] Figure 9 This is a simulation comparison diagram of phase noise before and after harmonic tuning in an embodiment of the present invention;

[0021] Figure 10 This is a simulation diagram of phase noise in an embodiment of the present invention;

[0022] Figure 11 This is a simulation diagram of the quality factor in an embodiment of the present invention;

[0023] Figure 12 This is a simulation diagram of the tuning curve in an embodiment of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] This invention aims to further reduce the phase noise of voltage-controlled oscillators (VCOs), and a series of theoretical analyses and circuit structure designs have been carried out to achieve this goal. In the process of performance optimization, current VCO structures generally face the following key challenges:

[0026] 1. In nanometer-scale CMOS technology, to meet low power consumption requirements, the power supply voltage V...DD They are typically set at a low level. The peak single-ended output voltage of a traditional parallel resonant oscillator (Class B or Class C) can only reach a maximum of twice the supply voltage, and even with a Class D topology, the peak voltage can only be increased to about three times the supply voltage. Therefore, parallel resonant oscillators cannot effectively suppress phase noise by increasing the swing amplitude under low supply voltage conditions.

[0027] 2. Theoretically, reducing the inductance L and increasing the capacitance C can optimize phase noise. However, in the gigahertz frequency band, when the inductance value drops to tens of pichenries, a practical bottleneck is encountered: an excessively small inductance will make the effects of wiring parasitic inductance and resistance more significant, which will not only degrade the oscillator performance but also make it difficult to control the oscillator performance precisely.

[0028] 3. Class B oscillators, known for their simplicity and robustness, require an oscillation amplitude close to the supply voltage to achieve optimal performance. This causes the transconductance device to enter the deep linear region during some cycles, forming a low-resistance discharge path to ground. Simultaneously, the large tail current capacitor introduced to suppress even-order harmonic noise further exacerbates this effect, causing a periodic and severe degradation of the equivalent Q value of the resonant cavity throughout the entire oscillation cycle. Even increasing the voltage swing provides only limited improvement in phase noise, and instead leads to a sharp drop in the quality factor (FoM). This resonant cavity Q-value loss problem caused by the inherent structural characteristics is unavoidable, fundamentally limiting the potential of Class B oscillators in low-phase-noise and high-power-efficiency applications.

[0029] 4. Class C oscillators effectively prevent transconductance devices from entering the linear region, but their maximum single-ended oscillation amplitude is also strictly limited, resulting in inherent losses of 6 dB in phase noise and 3 dB in FoM. Therefore, although Class C structures exhibit advantages in power consumption by maintaining the resonant cavity Q value and optimizing the current waveform, the limitation of their output swing fundamentally restricts the lowest phase noise limit achievable by this structure, becoming a significant weakness in applications pursuing ultra-low phase noise.

[0030] To effectively avoid the above problems, a novel oscillator topology based on an LC series resonant circuit design can be adopted, such as... Figure 1 As shown. Specifically, the LC series resonant circuit in this structure is ideally driven by a voltage source with negligible series impedance. If a voltage source with a supply voltage V is used... DD If a square wave signal oscillating between the resonant and ground drives the resonant cavity, then at the resonant frequency ω0, the current amplitude I0 injected into the resonant cavity is:

[0031]

[0032] Wherein, resistance r sThis characterizes the overall equivalent loss of inductor L and capacitor C, while the voltage amplitude A0 at the node connecting inductor L and capacitor C is:

[0033]

[0034] The resonant cavity's quality factor Q can easily reach over ten, allowing for very large oscillation amplitudes even at low supply voltages. This results in excellent phase noise performance at low supply voltages, making it suitable for applications requiring extremely low phase noise. Furthermore, such high voltage swings only occur at passive device nodes capable of withstanding high voltages (such as between inductors and capacitors), and are not applied to the input or output terminals of MOS devices, thus avoiding threats to MOS device reliability. On the other hand, the contribution of the active core (MOS switch) of the series resonant oscillator to phase noise can theoretically be controlled to an extremely low level. This contrasts sharply with the mechanism in transconductance oscillators where channel noise directly degrades phase noise, providing a new and effective approach to achieving extremely low phase noise.

[0035] Meanwhile, Class F voltage-controlled oscillators can optimize phase noise performance through harmonic shaping. Their working principle involves creating an impedance peak at the third harmonic frequency using an auxiliary resonant cavity, thereby enhancing the third harmonic component of the oscillation voltage. This results in a significant third harmonic component in the oscillation voltage waveform, forcing a pseudo-square wave voltage waveform across the LC resonant cavity, thus approximating a square wave. The square wave voltage waveform exhibits ideal phase noise conversion characteristics: near the zero-crossing voltage, the waveform rate of change is high, and the corresponding impulse sensitivity function (ISF) is large, contributing significantly to phase noise; while in the voltage flat-top or flat-bottom phases, the transconductance device enters the linear region and injects a large amount of noise, causing the waveform derivative to approach zero, and the corresponding ISF value to be extremely small. Therefore, even if a large amount of noise is injected during this period, it is hardly converted into phase noise, effectively "shielding" the circuit's amplitude noise from the phase information, thus achieving superior phase noise performance. By optimizing the amplitude ratio of the third harmonic to the fundamental frequency, the root mean square value of the ISF can be reduced to a minimum, theoretically achieving an improvement of approximately 3 dB in phase noise and resulting in a corresponding improvement in the quality factor.

[0036] Based on the above analysis, the present invention provides a type F series resonant voltage-controlled oscillator, such as... Figures 2-3 As shown, the circuit consists of four identical unit circuits connected end to end in a ring-shaped closed structure; each unit circuit has an input / output port including a non-inverting input, an inverting input, and an output.

[0037] Specifically, in the ring-shaped closed structure, the non-inverting input terminal and the inverting input terminal of the first unit circuit are respectively connected to signal V0 and signal V. 180The output terminal of the first unit circuit outputs signal V. 270 The non-inverting and inverting input terminals of the second unit circuit are respectively connected to signal V. 270 and signal V 90 The output terminal of the second unit circuit outputs signal V. 180 The non-inverting and inverting input terminals of the third unit circuit are respectively connected to signal V. 180 And signal V0, the output terminal of the third unit circuit outputs signal V 90 The non-inverting and inverting input terminals of the fourth unit circuit are respectively connected to signal V. 90 and signal V 270 The output terminal of the fourth unit circuit outputs signal V0.

[0038] In some embodiments, the unit circuit includes an active circuit and an LC series resonant network;

[0039] The output terminal of the active circuit is connected to the input terminal of the LC series resonant network, providing oscillation energy to the LC series resonant network;

[0040] The output of the LC series resonant network is connected to the active circuit of the next unit circuit, providing a control signal to the active circuit of the next unit circuit.

[0041] In some embodiments, such as Figure 4 As shown, the active circuit includes NMOS transistor M1, NMOS transistor M2, capacitor C3, capacitor C4, a first resistor, and a second resistor, wherein:

[0042] One end of capacitor C3 serves as the non-inverting input of the unit circuit, and the other end of capacitor C3 is connected to one end of the first resistor and the gate of NMOS transistor M1; the other end of the first resistor is connected to the power supply voltage V. DD The drain of NMOS transistor M1 is connected to the power supply voltage V. DD One end of capacitor C4 serves as the inverting input of the unit circuit, and the other end of capacitor C4 is connected to one end of the second resistor and the gate of NMOS transistor M2; the other end of the second resistor is connected to the power supply voltage V. DD The source of NMOS transistor M2 is grounded; the source of NMOS transistor M1 is connected to the drain of NMOS transistor M2, and this connection point is the output terminal of the active circuit.

[0043] The first resistor and the second resistor have the same resistance value and are used as bias resistors, therefore in Figure 3 as well as Figure 4 China uniformly adopts R B express.

[0044] Specifically, in the active circuit, NMOS transistors M1 and M2 form an NMOS-NMOS inverter. Its core function is as a synchronous switch controlled by the resonant voltage, rather than the transconductance amplifier found in a traditional LC oscillator. The NMOS-NMOS inverter directly drives the series resonant cavity, converting DC power energy into AC oscillation energy. Its "inverter" characteristic provides the necessary 180° phase shift for the entire multiphase oscillation loop, thus satisfying the phase condition required for loop oscillation. The NMOS-NMOS inverter structure can establish oscillation in any initial state without the need for complex external startup circuitry, simplifying circuit design and improving reliability. Furthermore, at the same process node, the electron mobility of NMOS is typically higher than that of PMOS, resulting in lower on-resistance and faster switching speeds for NMOS under the same gate voltage. This characteristic helps to generate steeper transient current pulses, thereby improving noise performance.

[0045] Specifically, in the active circuit, capacitors C3 and C4 form a capacitor voltage divider network, which is used to attenuate the output signal of the previous stage unit circuit before inputting it into the NMOS-NMOS inverter.

[0046] In a preferred embodiment, NMOS transistor M1 is designed with a large size, while NMOS transistor M2 is designed with a small size.

[0047] Specifically, the drain and source of NMOS transistor M1 are connected to the power supply voltage V, respectively. DD In a resonant cavity, excessive channel on-resistance during conduction can severely deplete resonant energy, leading to a reduction in the equivalent Q value and voltage swing. By employing a large-size design (i.e., a larger aspect ratio), the channel on-resistance during conduction can be effectively reduced, thereby minimizing energy loss. The drain and source of the NMOS transistor M2 are connected to the resonant cavity and ground, respectively. A small-size design for the NMOS transistor M2 helps reduce its gate parasitic capacitance, thereby reducing the load on the drive circuit and further lowering drive power consumption and signal transmission delay.

[0048] Specifically, based on the small-size design of NMOS transistor M2, an independent bias voltage can be applied to the substrate of NMOS transistor M2. By adjusting its threshold voltage through the bias voltage, the turn-on and turn-off times of NMOS transistor M2 can be precisely controlled, thereby compressing the cross-conduction time window between NMOS transistors M2 and M1 to its limit. This cross-conduction time window is the main injection period of circuit noise. By compressing the cross-conduction time window, the noise generated by active devices can be effectively reduced. For most of the oscillation cycle, one of M1 and M2 always operates in the deep linear region, strongly pulling one end of the resonant cavity to V. DDThis allows for the establishment of a large voltage swing. Only for a very brief instant at the voltage zero-crossing point are both transistors simultaneously in the saturation region, completing current commutation. This operating mode ensures that the intrinsic noise of the transistors (thermal noise, 1 / f noise) is short-circuited by the low-resistance path for most of the cycle, effectively injected only within the cross-conduction time window, which precisely corresponds to the voltage zero-crossing point with the lowest ISF value, thus achieving natural suppression of active noise.

[0049] In some embodiments, such as Figure 3 As shown, the LC series resonant network adopts a composite resonant network structure, which includes a main resonant cavity and an auxiliary resonant cavity. The two work together to determine the overall frequency characteristics, output waveform shape and final noise performance of the circuit.

[0050] The main resonant cavity includes an inductor L1 and a tuning unit circuit; one end of the inductor L1 is connected to the output terminal of the active circuit; the other end of the inductor L1 is connected to the non-inverting output terminal of the tuning unit circuit, and this connection point serves as the output terminal of the LC series resonant network; the inverting output terminal of the tuning unit circuit is grounded.

[0051] The auxiliary resonant cavity includes an inductor L2 and a capacitor C2; one end of the inductor L2 is connected to the output terminal of the active circuit, and the other end of the inductor L2 is connected to the capacitor C2, the other end of the capacitor C2 being grounded. Specifically, the capacitor C2 is a variable capacitor.

[0052] In some embodiments, the resonant frequency of the auxiliary resonant cavity is set to the third harmonic of the fundamental frequency to shape the voltage waveform at the output of the active circuit, thereby effectively reducing the phase noise of the voltage-controlled oscillator.

[0053] In this embodiment of the invention, the core function of the main resonant cavity is to establish and maintain the fundamental frequency signal of the oscillator. Simultaneously, utilizing the series resonance characteristic, a high-swing sinusoidal voltage with an amplitude much higher than the power supply voltage and a 90-degree phase shift is generated at the output of the main resonant cavity. This high-swing sinusoidal voltage is one of the fundamental conditions for obtaining excellent phase noise performance. Since the resonant frequency of the auxiliary resonant cavity is set to three times the fundamental frequency, that is, to achieve series resonance at the third harmonic frequency, the auxiliary resonant cavity also exhibits low impedance at this specific frequency. Therefore, the effect of the auxiliary resonant cavity is to create an additional admittance peak on the input admittance-frequency curve of the entire resonant cavity. This admittance peak enables the oscillation circuit to have high energy conversion efficiency even at the third harmonic frequency.

[0054] After the circuit is powered on, the loop noise is amplified at the frequency components that meet the oscillation conditions. Since the admittance of the main resonant cavity is maximum (impedance is minimum) at f0, this frequency component quickly becomes dominant, establishing steady-state oscillation. At this time, the current flowing through the switching node is provided by the rapid switching action of M1 and M2, and its waveform is a quasi-square wave rich in the third harmonic. The third harmonic current and the fundamental current are superimposed with appropriate amplitude ratio and phase relationship, synthesizing a square wave voltage with extremely steep rising and falling edges at the switching node.

[0055] In some embodiments, such as Figure 5 As shown, the tuning unit circuit includes a first variable capacitor, a second variable capacitor, and a 6-bit switched capacitor array composed of switched capacitors N1 to N6, wherein:

[0056] One end of the first variable capacitor is connected to the non-inverting output terminal of the tuning unit circuit and one end of the switching capacitors N1~N6, and the other end of the first variable capacitor is connected to the voltage V. CTRL One end of the second variable capacitor is connected to the inverting output terminal of the tuning unit circuit and the other end of the switching capacitors N1~N6; the other end of the second variable capacitor is connected to voltage V. CTRL ;

[0057] The switched capacitor includes a first fixed capacitor, a second fixed capacitor, an NMOS transistor M0, a third resistor, a fourth resistor, and an inverter N0. One end of the first fixed capacitor is connected to the non-inverting output of the tuning unit circuit, and the other end is connected to one end of the third resistor and the drain of the NMOS transistor M0. One end of the second fixed capacitor is connected to the inverting output of the tuning unit circuit, and the other end is connected to one end of the fourth resistor and the source of the NMOS transistor M0. The other ends of the third and fourth resistors are both connected to the output of the inverter N0. The gate of the NMOS transistor M0 is connected to the input of the inverter N0, and the input of the inverter N0 is also connected to the signal CAP. BIT .

[0058] In some embodiments, the first variable capacitor and the second variable capacitor are selected from the same type of device, the first fixed capacitor and the second fixed capacitor are selected from the same type of device, and the third resistor and the fourth resistor have the same resistance value.

[0059] It should be noted that, as Figure 3 as well as Figure 4 In the circuit structure shown, capacitor C1 is used to replace the entire tuning unit circuit for a more intuitive demonstration.

[0060] This invention achieves a significant improvement in phase noise performance through systematic circuit structure optimization and harmonic shaping strategies.

[0061] First, the series resonant topology and the switching active core form the physical basis for low noise: the series resonance enables the circuit to generate a high swing oscillation at the passive component end that is several times the power supply voltage, which directly improves the signal energy and suppresses the thermal noise caused by the resonant cavity loss resistance; at the same time, the active device, as a switch, only operates in the saturation region within a very short voltage zero-crossing window, while it is in the linear region for most of the cycle, thus efficiently short-circuiting the transistor noise and greatly compressing the effective noise injection time.

[0062] Secondly, an auxiliary third harmonic resonant cavity is introduced for waveform shaping. This is key to improving the noise conversion efficiency of this invention: by setting an additional admittance peak at the third harmonic frequency, the current waveform injected into the resonant cavity is forced to be shaped from a sine wave to a quasi-square wave, thereby effectively converting the third harmonic current into voltage. When this harmonic is superimposed on the fundamental wave in an appropriate ratio, a square wave voltage with extremely steep edges is synthesized at the switching node, and this waveform has an extremely high zero-crossing slope. According to the impulse sensitivity function theory, the amplitude of the ISF is inversely proportional to the zero-crossing slope. The peak value of the ISF function corresponding to the circuit of this invention is significantly suppressed, and its root mean square value can be reduced. According to Leeson's formula, phase noise and It is directly proportional to the 1 / f noise up-conversion efficiency and the DC component of the ISF. Relatedly, this invention optimizes both parameters simultaneously, thereby systematically reducing phase noise and improving performance in both near-carrier (1 / f³ region) and far-carrier (thermal noise region).

[0063] In summary, this invention employs a series resonant architecture to construct a high-swing, low-noise circuit foundation. Based on this, an asymmetric active circuit design effectively suppresses cross-conduction, ensuring stable basic performance. A key waveform shaping is achieved through an auxiliary resonant cavity, and finally, by optimizing the noise transfer function, a significant reduction in phase noise across the entire frequency offset range is realized. The synergistic and progressively enhanced effects of these various technical measures are the key to the performance breakthrough achieved by this invention.

[0064] The structure proposed in this invention was simulated and verified. The experimental results are as follows: Figures 6-12 As shown.

[0065] exist Figure 6 In the simulation results of the amplitude-frequency and phase-frequency characteristics of the Y-parameters of the LC series resonant cavity shown, the fundamental oscillation frequency is 2.29 GHz and the third harmonic frequency is 7.58 GHz.

[0066] Figure 7 The simulation results comparing the injected current into the resonant cavity before and after harmonic tuning are shown. In the figure, the blue curve corresponds to the current simulation result without harmonic tuning, while the red curve represents the current simulation result after harmonic tuning.

[0067] Figure 8 The simulation results comparing the resonant cavity node voltages before and after harmonic tuning are shown. The blue curve represents the simulated voltage of the resonant cavity node without harmonic tuning, while the red curve represents the simulated voltage of the resonant cavity node after harmonic tuning.

[0068] Figure 9 The simulation results comparing phase noise before and after harmonic tuning are shown. The blue curve represents the simulated phase noise without harmonic tuning, while the red curve represents the simulated phase noise after harmonic tuning. At a carrier frequency of 2.4 GHz and a frequency offset of 1 MHz, harmonic tuning improved the phase noise by 1.82 dBc / Hz.

[0069] exist Figure 10 In the simulation results of phase noise shown, the lowest phase noise value of the simulation curve at a frequency offset of 1 MHz is -146.37 dBc / Hz, and it further decreases to -166.4 dBc / Hz at a frequency offset of 10 MHz.

[0070] exist Figure 11 In the simulation results of the quality factor shown, the maximum quality factor obtained when the frequency offset is 1 MHz is 202.29 dBc / Hz; while under the condition of frequency offset of 10 MHz, the corresponding maximum quality factor can reach 202.33 dBc / Hz.

[0071] exist Figure 12 The simulation results of the tuning curves shown indicate that the operating frequency range is from 1.977 GHz to 2.425 GHz, the center frequency is 2.201 GHz, and the relative tuning range reaches 20.4%.

[0072] Those skilled in the art will understand that various variations can be made without departing from the core concept of this invention:

[0073] 1. The active circuit can use a PMOS-NMOS complementary inverter.

[0074] 2. The topology of the auxiliary resonant cavity can be other resonant networks that can generate impedance or admittance peaks at the target harmonic frequency.

[0075] 3. This invention can be extended to two-phase, four-phase or more-phase oscillators to generate quadrature or multi-phase clock signals.

[0076] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A type-F series resonant voltage-controlled oscillator, characterized in that, The structure consists of four identical unit circuits connected end-to-end to form a closed loop; each unit circuit has a non-inverting input, an inverting input, and an output. Within this closed loop structure... The non-inverting input and inverting input of the first unit circuit are respectively connected to signal V0 and signal V. 180 The output terminal of the first unit circuit outputs signal V. 270 ; The non-inverting and inverting input terminals of the second unit circuit are respectively connected to signal V. 270 and signal V 90 The output terminal of the second unit circuit outputs signal V. 180 ; The non-inverting and inverting input terminals of the third unit circuit are respectively connected to signal V. 180 And signal V0, the output terminal of the third unit circuit outputs signal V 90 ; The non-inverting and inverting input terminals of the fourth unit circuit are respectively connected to signal V. 90 and signal V 270 The output terminal of the fourth unit circuit outputs signal V0.

2. The Class F series resonant voltage-controlled oscillator according to claim 1, characterized in that, The unit circuit includes an active circuit and an LC series resonant network; The output terminal of the active circuit is connected to the input terminal of the LC series resonant network, providing oscillation energy to the LC series resonant network; The output of the LC series resonant network is connected to the active circuit of the next unit circuit, providing a control signal to the active circuit of the next unit circuit.

3. The Class F series resonant voltage-controlled oscillator according to claim 2, characterized in that, The active circuit includes NMOS transistors M1 and M2, capacitor C3, capacitor C4, a first resistor, and a second resistor, wherein: One end of capacitor C3 serves as the non-inverting input of the unit circuit, and the other end of capacitor C3 is connected to one end of the first resistor and the gate of NMOS transistor M1; the other end of the first resistor is connected to the power supply voltage V. DD The drain of NMOS transistor M1 is connected to the power supply voltage V. DD One end of capacitor C4 serves as the inverting input of the unit circuit, and the other end of capacitor C4 is connected to one end of the second resistor and the gate of NMOS transistor M2; the other end of the second resistor is connected to the power supply voltage V. DD The source of NMOS transistor M2 is grounded; the source of NMOS transistor M1 is connected to the drain of NMOS transistor M2, and this connection point is the output terminal of the active circuit. The first resistor and the second resistor have the same resistance value.

4. The Class F series resonant voltage-controlled oscillator according to claim 2, characterized in that, The LC series resonant network includes a main resonant cavity and an auxiliary resonant cavity; The main resonant cavity includes an inductor L1 and a tuning unit circuit; one end of the inductor L1 is connected to the output terminal of the active circuit; the other end of the inductor L1 is connected to the non-inverting output terminal of the tuning unit circuit, and this connection point serves as the output terminal of the LC series resonant network; the inverting output terminal of the tuning unit circuit is grounded. The auxiliary resonant cavity includes an inductor L2 and a capacitor C2; one end of the inductor L2 is connected to the output terminal of the active circuit, the other end of the inductor L2 is connected to the capacitor C2, and the other end of the capacitor C2 is grounded.

5. The Class F series resonant voltage-controlled oscillator according to claim 4, characterized in that, The resonant frequency of the auxiliary resonant cavity is set to three times the fundamental frequency to shape the voltage waveform at the output of the active circuit.

6. The Class F series resonant voltage-controlled oscillator according to claim 4, characterized in that, The tuning unit circuit includes a first variable capacitor, a second variable capacitor, and switched capacitors N1 to N6, wherein: One end of the first variable capacitor is connected to the non-inverting output terminal of the tuning unit circuit and one end of the switching capacitors N1~N6, and the other end of the first variable capacitor is connected to the voltage V. CTRL One end of the second variable capacitor is connected to the inverting output terminal of the tuning unit circuit and the other end of the switching capacitors N1~N6; the other end of the second variable capacitor is connected to voltage V. CTRL ; The switched capacitor includes a first fixed capacitor, a second fixed capacitor, an NMOS transistor M0, a third resistor, a fourth resistor, and an inverter N0. One end of the first fixed capacitor is connected to the non-inverting output of the tuning unit circuit, and the other end is connected to one end of the third resistor and the drain of the NMOS transistor M0. One end of the second fixed capacitor is connected to the inverting output of the tuning unit circuit, and the other end is connected to one end of the fourth resistor and the source of the NMOS transistor M0. The other ends of the third and fourth resistors are both connected to the output of the inverter N0. The gate of the NMOS transistor M0 is connected to the input of the inverter N0, and the input of the inverter N0 is also connected to the signal CAP. BIT .

7. A Class F series resonant voltage-controlled oscillator according to claim 6, characterized in that, The first and second variable capacitors are made of the same type of components, and the third and fourth resistors have the same resistance value.

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