Semiconductor structure, manufacturing method thereof and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor structure, a manufacturing method thereof and electronic equipment, which are used for solving the technical problem of how to simplify a forming process of a bit line structure. The manufacturing method comprises the steps that a substrate is provided, the substrate comprises a plurality of semiconductor patterns arranged in the first direction, each semiconductor pattern comprises a first part extending in the second direction and a plurality of second parts arranged at intervals in the second direction and connected with the first part, and a groove is formed between every two adjacent first parts; forming a doped dielectric layer covering the groove and the first part; executing a first annealing process on the substrate on which the doped dielectric layer is formed, so that doped ions in the doped dielectric layer are diffused into the first part and the second part to respectively form a doped first part and a doped second part; removing the doped dielectric layer to expose the doped first part; based on the doped first portion, a bit line structure is formed, the bit line structure connecting the doped second portion. Therefore, the forming process of the bit line structure is simplified.

Description

Semiconductor structure and its manufacturing method, electronic equipment Technical Field

[0001] This disclosure relates to the semiconductor field, and more particularly to a semiconductor structure, a method for manufacturing the same, and an electronic device. Background Technology

[0002] With the increasing trend of high-density integration in Dynamic Random Access Memory (DRAM), bit lines (BLs), as the core interconnect structure connecting memory cell arrays and peripheral circuits, face severe challenges in their fabrication process. As the storage density of semiconductor devices continues to increase, the size of bit lines and their surrounding components is constantly shrinking, leading to a significant increase in the difficulty of bit line fabrication and a substantial impact on device read speed, signal transmission quality, and overall performance. Summary of the Invention

[0003] This disclosure provides a semiconductor structure, a method for manufacturing the same, and an electronic device.

[0004] The technical solution of this disclosure embodiment is implemented as follows: On one hand, this disclosure embodiment provides a method for manufacturing a semiconductor structure, the method comprising: providing a substrate, the substrate comprising a plurality of semiconductor patterns arranged along a first direction, wherein the semiconductor patterns comprise a first portion extending along a second direction and a plurality of second portions arranged at intervals along the second direction and all connected to the first portion, a trench being formed between adjacent first portions, the first direction intersecting the second direction; forming a doped dielectric layer covering the trenches and the first portions; performing a first annealing process on the substrate on which the doped dielectric layer is formed, so that doped ions in the doped dielectric layer diffuse into the first portion and the second portion, to form the doped first portion and the doped second portion respectively; removing the doped dielectric layer to expose the doped first portion; and forming a bit line structure based on the doped first portion, wherein the bit line structure connects the doped second portion.

[0005] In some embodiments, forming a bit line structure based on the doped first portion includes: sequentially forming a first dielectric layer and a barrier layer in the trench, wherein the first dielectric layer is located between the doped first portion and the barrier layer, and the first dielectric layer and the barrier layer fill the trench; forming a metal layer on the surface of the first dielectric layer, the barrier layer and the doped first portion; and performing a second annealing process on the substrate on which the metal layer is formed, so that the metal layer reacts with the doped first portion to form a bit line contact.

[0006] In some embodiments, the doped first portion forming a bit line structure further includes: forming a bit line extending along the second direction on the bit line contact.

[0007] In some embodiments, the manufacturing method further includes: removing the metal layer from the surfaces of the first dielectric layer and the barrier layer to expose the barrier layer; and removing the exposed barrier layer.

[0008] In some embodiments, the manufacturing method further includes forming an isolation structure at the location where the barrier layer is removed, wherein the isolation structure has an air gap extending along the second direction.

[0009] In some embodiments, providing the substrate includes: providing an initial substrate, the initial substrate including a plurality of initial semiconductor patterns arranged along a first direction, wherein the initial semiconductor patterns include an initial first portion extending along a second direction and a plurality of second portions arranged at intervals along the second direction and all connected to the initial first portions, and an initial trench is formed between adjacent initial first portions; based on the initial trench, etching the initial first portions to form the trench and the first portions respectively, wherein the size of the first portion in the first direction is smaller than the size of the initial first portion in the first direction, and the size of the trench in the first direction is larger than the size of the initial trench in the first direction.

[0010] In some embodiments, the manufacturing method further includes etching the first doped portion after removing the doped dielectric layer.

[0011] In some embodiments, the doping concentration of the doped ions in the first doped portion is greater than the doping concentration of the doped ions in the second doped portion.

[0012] In some embodiments, the first annealing process includes at least one of laser tip annealing and dynamic surface annealing.

[0013] In some embodiments, the material of the doped dielectric layer includes boron-doped silicon oxide or phosphorus-doped silicon oxide.

[0014] On the other hand, this disclosure also provides a semiconductor structure formed using the manufacturing method described in any of the above embodiments.

[0015] In another aspect, embodiments of this disclosure also provide an electronic device, which includes: a processing device; and a memory device electrically connected to the processing device, the memory device including the semiconductor structure described in the above embodiments.

[0016] In this embodiment of the present disclosure, a doped dielectric layer is formed on the surface of a first portion of a semiconductor pattern, and doped ions are diffused using a first annealing process to form a doped first portion and a doped second portion. The doped dielectric layer is then removed, and a bit line structure is formed based on the doped first portion. This simplifies the bit line structure formation process and reduces costs. Attached Figure Description

[0017] Figure 1 is a schematic diagram of a substrate after formation according to an embodiment of the present disclosure; Figure 2 is a schematic diagram of a first groove after formation according to an embodiment of the present disclosure; Figure 3 is a schematic diagram of a doped polycrystalline silicon material layer after formation according to an embodiment of the present disclosure; Figure 4 is a schematic diagram of an initial doped semiconductor layer after formation according to an embodiment of the present disclosure; Figure 5 is a schematic diagram of a doped semiconductor layer after formation according to an embodiment of the present disclosure; Figure 6 is a flowchart of a semiconductor structure manufacturing method according to an embodiment of the present disclosure; Figure 7 is another schematic diagram of a substrate after formation according to an embodiment of the present disclosure; Figure 8 is a schematic diagram of a trench after formation according to an embodiment of the present disclosure; Figure 9 is a schematic diagram of a... Figure 10 is a schematic diagram of a doped dielectric layer after formation, provided by an embodiment of the present disclosure; Figure 11 is a schematic diagram of a first doped portion and a second doped portion after formation, provided by an embodiment of the present disclosure; Figure 12 is a schematic diagram of a first dielectric material layer after formation, provided by an embodiment of the present disclosure; Figure 13 is a schematic diagram of a barrier layer after formation, provided by an embodiment of the present disclosure; Figure 14 is a schematic diagram of a bit line contact after formation and barrier layer removal, provided by an embodiment of the present disclosure; Figure 15 is a schematic diagram of an isolation structure after formation, provided by an embodiment of the present disclosure; Figure 16 is a schematic block diagram of an electronic device after an embodiment of the present disclosure. Detailed Implementation

[0018] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0019] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0020] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0021] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as a second element, component, area, layer, or part. And the discussion of a second element, component, area, layer, or part does not imply that the first element, component, area, layer, or part necessarily exists in this disclosure.

[0022] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0024] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0025] Before introducing the embodiments of this disclosure, the various directions that may be involved in the following text are defined. The direction perpendicular to the main surface of the substrate is defined as the third direction (denoted as direction D3 in the figures). In a plane parallel to the main surface of the substrate, an intersecting first direction (denoted as direction D1 in the figures) and a second direction (denoted as direction D2 in the figures) are defined. The angle between direction D1 and direction D2 can be acute, right, or obtuse. For ease of understanding, the following explanation will use the example of a right angle between direction D1 and direction D2, meaning that any two of directions D1, D2, and D3 are perpendicular to each other.

[0026] Figures 1 to 5 are schematic diagrams illustrating the manufacturing process of a semiconductor structure according to an embodiment of this disclosure. Figures 1 to 5 are partial cross-sectional views of the semiconductor structure during the manufacturing process. The manufacturing method of a semiconductor structure according to an embodiment of this disclosure will be described below with reference to Figures 1 to 5.

[0027] Referring to FIG1, a substrate 102 is provided, which includes a plurality of semiconductor patterns 104 arranged along a first direction D1. Each semiconductor pattern 104 includes a first portion 106 extending along a second direction D2 and a plurality of second portions 108 spaced apart along the second direction D2 and connected to the first portion 106. The first direction D1 intersects the second direction D2. At least a portion of the area between adjacent semiconductor patterns 104 on the first direction D1 is filled with an oxide layer 110, which serves to achieve physical isolation between adjacent semiconductor patterns 104.

[0028] In each semiconductor pattern 104, a first portion 106 extends along a second direction D2, and each second portion 108 extends along a third direction D3. Continuing to refer to FIG1, the semiconductor pattern also includes a third portion connected one-to-one with each of the plurality of second portions 108. The third portion extends along the third direction D3 and is located at the end of the second portion 108 on the third direction D3 away from the first portion 106. Each second portion 108 and its corresponding third portion form an active region of a transistor, which may include a source, a channel, and a drain arranged along the third direction D3. The second portion 108 serves as one of the source and drain, coupled to a bit line. The third portion forms the other of the source and drain, coupled to a capacitor. The third portion also forms a channel, coupled to a gate (or word line).

[0029] In some embodiments, the semiconductor pattern 104 can be formed on a substrate. Specifically, the substrate has a first surface and a second surface opposite to each other in a third direction D3. The first surface of the substrate is etched to form a plurality of semiconductor patterns 104 arranged along a first direction D1 on the first surface of the substrate. Each semiconductor pattern 104 includes a first portion 106 extending along a second direction D2, a plurality of second portions 108 spaced apart along the second direction D2 and all connected to the first portion 106, and a third portion connected to the second portions 108. After forming the semiconductor pattern 104, an oxide layer 110 is filled between adjacent semiconductor patterns 104 in the first direction D1, such that the oxide layer 110 is located at least between two adjacent first portions 106 in the first direction D1. Then, a transistor structure can be formed based on each second portion 108 and the third portion, and a capacitor correspondingly connected to each transistor structure can be formed. Each transistor structure and its corresponding capacitor constitute a memory cell, thus forming a plurality of memory cells arranged in an array along the first direction D1 and the second direction D2 on the first surface of the substrate. After forming the memory cells, the entire three-dimensional structure is flipped so that the second side of the substrate faces upward. Then, a chemical mechanical planarization (CMP) process can be used to thin the second side of the substrate until the oxide layer 110 is exposed. In this way, the remaining substrate forms a plurality of semiconductor patterns 104 arranged along the first direction. The plurality of semiconductor patterns 104 are isolated from each other by the oxide layer 110, and the top surface of the semiconductor patterns 104 is flush with the top surface of the oxide layer 110.

[0030] The substrate material may include elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art. It is understood that since the semiconductor pattern 104 is formed based on the substrate, the material of the semiconductor pattern 104 may be the same as the substrate material. For ease of understanding, silicon will be used as the material of the semiconductor pattern 104 in the following description.

[0031] The material of oxide layer 110 includes insulating materials, such as oxides; more specifically, oxide layer 110 may include silicon oxide.

[0032] The formation process of oxide layer 110 includes, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0033] Referring to Figures 1 and 2, a first portion of the semiconductor pattern 104 is etched to form a first groove 112 located between adjacent oxide layers 110 in the first direction D1. The first groove 112 extends along the second direction D2 and exposes a portion of the side surface of the oxide layer 110.

[0034] Here, the first groove 112 is used to define the formation area of ​​the bit line structure. In this embodiment of the present disclosure, the etching depth of the first groove 112 can be determined according to actual design requirements, thereby obtaining a bit line structure with the required dimensions. Specifically, in some embodiments, the entire first portion 106 of the semiconductor pattern 104 can be etched away to expose the second portion 108 of the semiconductor pattern 104 to the first groove 112. In other embodiments, a portion of the first portion 106 of the semiconductor pattern 104 can be etched away to reduce the size of the first portion 106 along the third direction D3.

[0035] The process for forming the first groove 112 includes, but is not limited to, dry etching, wet etching, or a combination thereof.

[0036] Referring to FIG3, a doped polysilicon material layer 114 is formed on the surface of oxide layer 110 and the remaining semiconductor pattern 104, and the doped polysilicon material layer 114 fills the first groove 112.

[0037] The material of the doped polycrystalline silicon material layer 114 includes doped polycrystalline silicon. Furthermore, the doping elements in the doped polycrystalline silicon material layer 114 may include N-type doping elements, such as phosphorus, arsenic, and antimony. The doping elements in the doped polycrystalline silicon material layer 114 may also include P-type doping elements, such as boron, aluminum, gallium, and indium.

[0038] The formation process of the doped polycrystalline silicon material layer 114 includes, but is not limited to, epitaxial growth, CVD, PVD, ALD, or any combination thereof.

[0039] Referring to FIG4, the polycrystalline silicon in the doped polycrystalline silicon material layer 114 is induced to transform into monocrystalline silicon using the pulsed laser annealing (PLA) process, thereby forming the initial doped semiconductor layer 116.

[0040] PLA (Plastic Argumentation) is an advanced rapid thermal annealing technology. It utilizes a high-energy pulsed laser beam (nanosecond to millisecond pulse width) to directly irradiate the wafer surface, which can heat the material on the wafer surface to the melting point or high temperature in a very short time, followed by rapid cooling to achieve non-equilibrium solid-phase or liquid-phase epitaxial recrystallization.

[0041] In this embodiment, a high-energy pulsed laser beam is used to irradiate the surface of the doped polycrystalline silicon material layer 114 with a nanosecond-level pulse width. This causes the doped polycrystalline silicon material layer 114 to absorb light energy and heat up to above its melting point in a very short time, forming a thin liquid-phase molten region. The remaining semiconductor pattern 104 located below the doped polycrystalline silicon material layer 114 is used as a seed crystal, allowing the molten silicon to recrystallize epitaxially along its original crystal direction during rapid cooling. This transforms the polycrystalline silicon in the doped polycrystalline silicon material layer 114 into high-lattice-quality single-crystal silicon, forming the initial doped semiconductor layer 116. It should be noted that since both the initial doped semiconductor layer 116 and the semiconductor pattern 104 are made of single-crystal silicon, the interface between the initial doped semiconductor layer 116 and the semiconductor pattern 104 is not distinguished in Figure 4.

[0042] Referring to FIG5, the initial doped semiconductor layer 116 located outside the first groove 112 is removed, so that the remaining initial doped semiconductor layer 116 located within the first groove 112 forms a doped semiconductor layer 118, the top surface of the doped semiconductor layer 118 being flush with the top surface of the oxide layer 110. The doped semiconductor layer 118 is used to form a bit line structure.

[0043] The removal process of the initial doped semiconductor layer 116 includes, but is not limited to, the CMP process.

[0044] However, it should be noted that the schemes shown in Figures 1 to 5 still have some drawbacks: Firstly, the process of forming the doped semiconductor layer 118 using PLA technology is quite difficult, requiring technicians to expend significant resources to adjust parameters such as energy distribution, timing, waveform, and uniformity of the PLA process. Furthermore, if the process window cannot be opened during PLA technology, single crystal formation may fail or phosphorus diffusion may occur, affecting the electrical properties and testing of subsequent devices. Secondly, since the process of forming the doped polycrystalline silicon material layer 114 is a furnace tube process, this process raises the temperature of the entire wafer. Moreover, because the memory cells have already been fabricated in previous processes, the wafer is subjected to considerable stress. Under these circumstances, the high temperature can easily lead to wafer breakage. Thirdly, the PLA process can currently only operate within a 130mm radius of the wafer, not the entire wafer. This prevents the doped polysilicon material at the wafer's edge from being converted into doped monocrystalline silicon, thus preventing the formation of effective bit line structures at the wafer's edges. (Because effective bit line structures cannot be formed at the wafer's edges, the formation of the second groove and subsequent processes are based on the wafer's central region, not the edge region. Therefore, only memory cells connected to effective bit line structures can become usable memory cells.) This affects the number of chips per wafer (Die Per Wafer, DPW), leading to increased product costs. Fourthly, the bit line structure formation process in the schemes shown in Figures 1 to 5 is relatively complex and technically challenging.

[0045] Based on at least one of the above-mentioned technical problems, this disclosure provides another method for manufacturing a semiconductor structure.

[0046] Figure 6 is a schematic flowchart of a semiconductor structure manufacturing method according to an embodiment of this disclosure. It should be noted that the steps shown in Figure 6 are not exclusive, and other steps can be performed before, after, or between any of the steps shown; the order of the steps shown in Figure 6 can be adjusted according to actual needs. Referring to Figure 6, the manufacturing method includes at least the following steps: Step S102: Providing a substrate, the substrate including a plurality of semiconductor patterns arranged along a first direction, wherein the semiconductor patterns include a first portion extending along a second direction and a plurality of second portions arranged at intervals along the second direction and all connected to the first portion, a trench is formed between adjacent first portions, and the first direction intersects the second direction; Step S104: Forming a doped dielectric layer covering the trenches and the first portions; Step S106: Performing a first annealing process on the substrate with the doped dielectric layer formed, so that doped ions in the doped dielectric layer diffuse into the first and second portions, to form the doped first portion and the doped second portion respectively; Step S108: Removing the doped dielectric layer to expose the doped first portion; Step S110: Forming a bit line structure based on the doped first portion, wherein the bit line structure connects the doped second portion.

[0047] In this embodiment of the present disclosure, a doped dielectric layer is formed on the surface (including the top and side surfaces) of a first portion of a semiconductor pattern, and doped ions are diffused using a first annealing process to form a doped first portion and a doped second portion. The doped dielectric layer is then removed, and a bit line structure is formed based on the doped first portion. This simplifies the bit line structure formation process and reduces costs.

[0048] Figures 7 to 14 are schematic diagrams illustrating the manufacturing process of another semiconductor structure provided in this disclosure. Figures 7 to 14 are partial cross-sectional views of the semiconductor structure during the manufacturing process. The manufacturing method of another semiconductor structure provided in this disclosure will be described below with reference to Figures 6 and 7 to 14.

[0049] Referring to Figures 7 and 8, step S102 is performed: a substrate 202 is provided, the substrate 202 includes a plurality of semiconductor patterns 204 arranged along a first direction, wherein the semiconductor pattern 204 includes a first portion 206 extending along a second direction D2 and a plurality of second portions 208 arranged at intervals along the second direction D2 and all connected to the first portion 206, a trench 212 is formed between adjacent first portions 206, and the first direction D1 intersects the second direction D2.

[0050] In each semiconductor pattern 204, a first portion 206 extends along a second direction D2, and each second portion 208 extends along a third direction D3. Referring again to FIG7, the semiconductor pattern 204 further includes a third portion connected to each of the plurality of second portions 208 in a one-to-one correspondence. The third portion extends along the third direction D3 and is located at the end of the second portion 208 on the third direction D3 away from the first portion 206. Each second portion 208 and its corresponding third portion form an active region of a transistor, which may include a source, a channel, and a drain arranged along the third direction D3. The second portion 208 serves as one of the source and drain, coupled to a bit line. The third portion forms the other of the source and drain, coupled to a capacitor. The third portion also forms a channel, coupled to a gate (or word line).

[0051] Semiconductor pattern 204 can be formed based on a substrate. The materials and specific formation process of semiconductor pattern 204 can be referred to the relevant description of semiconductor pattern 104 in Figure 1, which will not be repeated here.

[0052] An oxide layer 210 is filled between two adjacent semiconductor patterns 204 on the first direction D1. The oxide layer 210 is used to achieve physical isolation between adjacent semiconductor patterns 204 on the first direction D1. For the material and specific formation process of the oxide layer 210, please refer to the relevant description of the oxide layer 110 in Figure 1, which will not be repeated here.

[0053] Referring to FIG8, a portion of the oxide layer 210 is etched to form a trench 212 located between adjacent first portions 206.

[0054] Here, the groove 212 is used to define the location where the isolation structure between adjacent bit line structures is formed.

[0055] In some embodiments, the etching depth of trench 212 is greater than or equal to the dimension of the first portion 206 of semiconductor pattern 204 along the third direction D3. This can better reduce coupling between adjacent bit line structures and decrease signal crosstalk.

[0056] In this embodiment, the etching depth of the trench 212 can also be determined according to specific electrical and testing requirements. This disclosure does not impose a specific limitation on the etching depth of the trench 212.

[0057] The formation process of trench 212 includes, but is not limited to, dry etching.

[0058] It should be noted that Figure 7 above provides a substrate, and subsequent process steps can be performed based on the substrate of Figure 7. However, in another embodiment of this disclosure, another substrate is provided, and the specific steps for providing the other substrate include: step S202, providing an initial substrate, the initial substrate including a plurality of initial semiconductor patterns arranged along a first direction, wherein the initial semiconductor patterns include an initial first portion extending along a second direction and a plurality of second portions arranged at intervals along the second direction and all connected to the initial first portions, and an initial trench is formed between adjacent initial first portions; step S204, etching the initial first portions based on the initial trenches to form trenches and first portions respectively, wherein the size of the first portion in the first direction is smaller than the size of the initial first portion in the first direction, and the size of the trench in the first direction is larger than the size of the initial trench in the first direction.

[0059] Here, the initial first portion of the initial semiconductor pattern has the same dimension along the first direction D1 as the second portion of the initial semiconductor pattern. The formation process of the initial semiconductor pattern is similar to that of the semiconductor pattern, and can be referred to the relevant description in Figure 1, which will not be repeated here.

[0060] The etching process of the initial first portion can be viewed as trimming the initial first portion to reduce its size in the first direction, forming the first portion 206. At this time, the size of the first portion 206 in the first direction D1 is smaller than the size of the initial first portion in the first direction D1, and the size of the first portion 206 in the first direction D1 is smaller than the size of the second portion 208 in the first direction D1. It is understood that because the size of the first portion 206 along the first direction D1 is smaller than the size of the initial first portion along the first direction D1, the distance between adjacent first portions 206 in the first direction D1 increases accordingly. Furthermore, since the first portion 206 is used to form the bit line structure subsequently, etching the initial first portion 206 in step S204 can effectively increase the distance between adjacent bit line structures in the first direction D1, thereby reducing the coupling between adjacent bit line structures.

[0061] Referring to FIG9, step S104 is performed: forming a doped dielectric layer 214 covering the trench 212 and the first portion 206.

[0062] In some embodiments, the material of the doped dielectric layer 214 includes a doped oxide, such as a doped silicon oxide (e.g., silicon oxide).

[0063] More specifically, in some embodiments, the material of the doped dielectric layer 214 includes boron-doped silicon oxide (e.g., boron-doped silicon oxide), indium-doped silicon oxide (e.g., indium-doped silicon oxide), etc. The dopant elements in this doped dielectric layer 214 can be diffused into the first portion 206 and the second portion 208 of the semiconductor pattern 204 in subsequent processes to form a P-channel metal-oxide-semiconductor field-effect transistor (PMOS).

[0064] In other embodiments, the material of the doped dielectric layer 214 may also include phosphorus-doped silicon oxide (e.g., phosphorus-doped silicon oxide), arsenic-doped silicon oxide (e.g., arsenic-doped silicon oxide), antimony-doped silicon oxide (e.g., antimony-doped silicon oxide), etc. The dopant elements in the doped dielectric layer 214 can be diffused to the first portion 206 and the second portion 208 of the semiconductor pattern 204 in subsequent processes to form an N-channel metal-oxide-semiconductor field-effect transistor (NMOS).

[0065] The formation process of the doped dielectric layer 214 includes, but is not limited to, PVD, CVD, ALD, or any combination thereof.

[0066] Referring to FIG10, step S106 is performed: a first annealing process is performed on the substrate on which the doped dielectric layer 214 is formed, so that the doped ions in the doped dielectric layer 214 diffuse into the first part 206 and the second part 208, so as to form the doped first part 220 and the doped second part 222, respectively.

[0067] In some embodiments, the doping concentration of the doped ions in the first doped portion 220 is greater than the doping concentration of the doped ions in the second doped portion 222. Here, the first doped portion 220 is used to form a bit line structure subsequently, and the second doped portion 222 is used to form the source or drain of the transistor connected to the bit line structure.

[0068] In some embodiments, the first annealing process includes at least one of laser spike annealing (LSA) and dynamic surface annealing (DSA).

[0069] LSA is an advanced thermal processing technology that uses high-power lasers to rapidly heat the wafer surface to ultra-high temperatures within milliseconds and then rapidly cool it. It can achieve efficient activation while suppressing the diffusion of doped atoms and is a key process for forming ultra-shallow junctions and repairing ion implantation damage in advanced semiconductor manufacturing.

[0070] DSA is an advanced heat treatment technology that uses continuous wave diode laser high-speed scanning to achieve rapid surface heating and self-cooling at the millisecond level. It can effectively suppress heat diffusion while efficiently activating doped atoms, meet the requirements of ultra-shallow junctions in advanced processes, and has the characteristics of low thermal budget, good uniformity, and strong adaptability to mass production.

[0071] It should be noted that both LSA and DSA employ continuous wave laser scanning, which offers advantages over PLA in terms of more uniform energy distribution, better annealing consistency, and a wider process window. Furthermore, the millisecond-level heating time enables both sufficient doping activation and effective suppression of thermal diffusion. The scanning processing method also boasts high production efficiency, is more suitable for large-scale mass production, has a simpler equipment structure, lower maintenance costs, and causes less thermal damage to underlying devices.

[0072] In this embodiment, the more mature LSA and DSA processes are used instead of the PLA process, effectively reducing the process difficulty. Simultaneously, the formation of a doped dielectric layer 214 on the surface of the first portion 206 replaces the furnace tube process for forming a doped polysilicon material layer in Figure 3, effectively reducing wafer defects. Furthermore, the LSA and DSA processes can be applied to the entire wafer, enabling the formation of an effective bit line structure throughout the entire wafer's radius, thereby effectively improving the die wire width (DPW) and reducing production costs.

[0073] In some embodiments, after forming the trench 212 between adjacent first portions 206, no doped dielectric layer is formed on the surfaces of the trench 212 and the first portions 206; instead, ion doping is directly performed into the first portions 206 and the second portions 208 using an ion implantation process. However, with this doping method, doped ions can only be implanted from the top surface of the first portions 206 in the vertical direction, resulting in poor uniformity of ion doping in the first and second portions. In the embodiments of this disclosure, after forming the trench 212 between adjacent first portions 206, a doped dielectric layer 214 is formed covering the trench 212 and the first portions 206, and a first annealing process is performed on the substrate with the doped dielectric layer 214 to allow the doped ions in the doped dielectric layer 214 to diffuse into the first portions 206 and the second portions 208. Thus, doped ions can be implanted into the first portions 206 and the second portions 208 simultaneously from both the top surface and the sidewalls of the first portions 206. This effectively improves the uniformity of ion doping in the first doped portion 206 and the second doped portion 208.

[0074] Referring to Figures 10 and 11, step S108 is performed: the doped dielectric layer 214 is removed to expose the first doped portion 220.

[0075] The removal process of the doped dielectric layer 214 includes, but is not limited to, wet etching.

[0076] In some embodiments, the method of manufacturing a semiconductor structure further includes: after removing the doped dielectric layer 214, etching the first doped portion 220.

[0077] In other words, after removing the doped dielectric layer 214, the first doped portion 220 is trimmed to adjust its dimensions in the first direction D1, so that the dimensions and electrical parameters of the subsequently formed bitline structure meet the design requirements. Simultaneously, the sidewalls of the first doped portion 220 are repaired to facilitate the subsequent formation of the first dielectric layer on its sidewalls.

[0078] Referring to FIG14, step S110 is performed: a bit line structure is formed based on the first doped portion 220, wherein the bit line structure is connected to the second doped portion 222.

[0079] Figures 12 to 14 show the process steps for forming the bit line structure. The formation process of the bit line structure will be explained in detail below with reference to Figures 12 to 14.

[0080] Referring to Figures 12 to 14, in some embodiments, step S110 includes: step S302, forming a first dielectric layer 226 and a barrier layer 228 sequentially in the trench 212, wherein the first dielectric layer 226 is located between the doped first portion 220 and the barrier layer 228, and the first dielectric layer 226 and the barrier layer 228 fill the trench 212, as shown in Figure 13.

[0081] Specifically, referring to FIG12, a first dielectric material layer 230 is formed on the inner wall and bottom surface of the trench 212, as well as on the top and sides of the doped first portion 220. Then, a barrier material layer is formed on the surface of the first dielectric material layer 230, and the barrier material layer and the first dielectric material layer 230 fill the trench 212. Next, referring to FIG13, the first dielectric material layer 230 and the barrier material layer located outside the trench 212 are removed, so that the remaining first dielectric material layer 230 located inside the trench 212 forms the first dielectric layer 226, and the remaining barrier material layer located inside the trench 212 forms the barrier layer 228.

[0082] The formation processes of the first dielectric material layer 230 and the barrier material layer include, but are not limited to, PVD, CVD, ALD, or any combination thereof.

[0083] The material of the first dielectric layer 230 includes, but is not limited to, oxides, such as silicon oxide. The material of the first dielectric layer 230 can be the same as that of the oxide layer 210; therefore, the interface between the first dielectric layer 226 and the oxide layer 210 is not distinguished in Figure 12. It is understood that when the materials of the first dielectric layer 226 and the oxide layer 210 are different, there is a clear interface between them.

[0084] The materials used for the barrier layer include metal nitrides, such as titanium nitride.

[0085] Step S304: A metal layer (not shown in the figure) is formed on the surface of the first dielectric layer 226, the barrier layer 228 and the doped first portion.

[0086] The materials for the metal layer include, but are not limited to, nickel, cobalt, platinum, titanium, and tungsten.

[0087] The processes for forming the metal layer include, but are not limited to, PVD, CVD, ALD, or any combination thereof.

[0088] Step S306: Perform a second annealing process on the substrate with the metal layer to react the metal layer with the first doped portion 220 to generate bit line contacts 232.

[0089] Here, the bit line contact 232 is formed through a solid-phase diffusion reaction between the doped first portion 220 and the metal layer. Specifically, a second annealing process is performed on the substrate with the metal layer, causing the metal atoms of the metal layer to diffuse into and combine with the silicon atoms of the doped first portion 220 under thermal drive, forming a low-resistivity, stable metal silicide.

[0090] The second annealing process includes, but is not limited to, rapid thermal annealing (RTA) processes, such as spike RTA, millisecond annealing (MSA), and two-step RTA.

[0091] In this embodiment, the size of the bit line contact 232 can be controlled by controlling the specific parameters of the second annealing process. Specifically, in some embodiments, in the second annealing process, the metal layer reacts with all the silicon material in each doped first portion 220 to generate the bit line contact. That is, the size of the bit line contact 232 in the third direction D3 is equal to the size of the doped first portion 220 in the third direction D3. In other embodiments, in the second annealing process, the metal layer reacts with a portion of the silicon material in each doped first portion 220 to generate the bit line contact 232. That is, the size of the bit line contact 232 in the third direction D3 is smaller than the size of the doped first portion 220 in the third direction D3.

[0092] Bit line contact 232 can be used as a bit line structure or as part of a bit line structure.

[0093] In the case where the bit line contact 232 serves as a bit line structure, the semiconductor structure manufacturing method further includes, after forming the bit line contact 232, removing all the metal layer to expose the surface of the bit line contact 232. At this point, the bit line contact 232, as a bit line structure, enables the connection between the transistor and the external sensing circuit.

[0094] In some embodiments, where the bit line contact 232 is part of the bit line structure, step S110 further includes forming a bit line extending in a second direction on the bit line contact 232.

[0095] Specifically, after forming the bit line contact 232, the metal layer is removed to expose the surface of the bit line contact 232. Then, a conductive material is deposited on the surface of the bit line contact 232 to form a conductive layer covering the bit line contact 232 and extending along the second direction D2. At this point, the bit line contact 232 and the conductive layer together constitute the bit line structure, enabling the connection between the transistor and the external sensing circuit.

[0096] The conductive layer can be made of metallic materials, such as tungsten, copper, ruthenium, molybdenum, etc.

[0097] The formation process of the conductive layer includes, but is not limited to, PVD, CVD, ALD, or any combination thereof.

[0098] Referring to FIG14, in some embodiments, after forming bit line contact 232, the method of manufacturing semiconductor structure further includes: removing the metal layer on the surface of the first dielectric layer 226 and the barrier layer 228 to expose the barrier layer 228; and removing the exposed barrier layer 228.

[0099] Specifically, the unreacted metal layers located on the surfaces of the first dielectric layer 226 and the barrier layer 228 are removed, exposing the top surface of the barrier layer 228. The exposed barrier layer 228 is then etched away to reopen the trench 212.

[0100] Here, the removal processes for the metal layer and the barrier layer 228 include, but are not limited to, dry etching or wet etching processes.

[0101] It should be noted that before forming the bit line contact 232, the first dielectric layer 226 and the barrier layer 228 are filled in the trench 212 to prevent the metal material of the subsequently formed metal layer from reacting with the silicon oxide located below the trench 212, thereby affecting device performance. Furthermore, after forming the bit line contact 232, the barrier layer 228 is completely removed to reopen the trench 212. Therefore, the barrier layer 228 also serves as a sacrificial layer for intermediate auxiliary structures throughout the manufacturing process. It is evident that the material of the barrier layer 228 is not limited to the materials in the above example; any sacrificial material that meets the specific requirements of the manufacturing process can be used as the barrier layer 228.

[0102] In some embodiments, the manufacturing method further includes forming an isolation structure 233 at the removal location of the barrier layer 228, wherein the isolation structure 233 has an air gap 234 extending along the second direction D2.

[0103] Referring to FIG15, in some embodiments, the isolation structure 233 includes a second dielectric layer 235, in which an air gap 234 is formed. The second dielectric layer 235 is located between adjacent bit line structures and covers the spaces between the first dielectric layers 226. The surface of the isolation structure 233 may be flush with the surface of the bit line contact 232.

[0104] The isolation structure 233 is used to reduce the parasitic capacitance between adjacent bit line structures, while the air gap 234, as a key component of the isolation structure 233, utilizes its low dielectric constant (k approximately equal to 1) close to the theoretical limit to effectively reduce the parasitic capacitance and signal crosstalk between adjacent bit line structures, thereby improving the sensing margin and data transmission speed.

[0105] In some embodiments, the material of the isolation structure 233 includes a low dielectric constant material, such as silicon oxide.

[0106] The forming process of the isolation structure 233 includes, but is not limited to, PVD, CVD, ALD, or any combination thereof.

[0107] In this embodiment of the present disclosure, a doped dielectric layer is formed on the surface of a first portion of a semiconductor pattern, and doped ions are diffused using a first annealing process to form a doped first portion and a doped second portion. The doped dielectric layer is then removed, and a bit line structure is formed based on the doped first portion. This simplifies the bit line structure formation process and reduces costs.

[0108] Based on a concept similar to the manufacturing method described above, this disclosure provides a semiconductor structure. The semiconductor structure provided in this disclosure can constitute part or all of a semiconductor structure. The semiconductor structure can be various functional chips known in the art, such as memory chips, logic chips, interface chips, power chips, artificial intelligence chips, computing chips, and sensor chips.

[0109] In this embodiment of the disclosure, the semiconductor structure can be manufactured using the manufacturing method in any of the above embodiments. The technical effects that can be achieved by the manufacturing methods in the foregoing embodiments can also be achieved by the semiconductor structure shown in this embodiment of the disclosure, and will not be repeated here.

[0110] Based on a concept similar to the semiconductor structure described above, this disclosure provides an electronic device.

[0111] Figure 15 is a schematic block diagram of an electronic device 300 provided in an embodiment of this disclosure. Referring to Figure 15, the electronic device 300 includes a processing device 302 and a storage device 304 electrically connected to the processing device; the storage device 304 includes the semiconductor structure in any of the above embodiments.

[0112] Electronic device 300 can be a terminal or other devices besides a terminal. For example, electronic device 300 may include mobile phones, tablets, laptops, handheld computers, in-vehicle electronic devices, mobile internet devices (MIDs), augmented reality (AR) / virtual reality (VR) devices, robots, wearable devices, ultra-mobile personal computers (UMPCs), netbooks, or personal digital assistants (PDAs), etc. It can also be servers, network attached storage (NAS), personal computers (PCs), televisions (TVs), ATMs, or self-service machines, etc.

[0113] Processing device 302 typically controls the overall operation of electronic device 300. As an example, processing device 302 may include a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0114] Storage device 304 is configured to store instructions and applications executable by the processing device, and may also cache data to be processed or already processed (e.g., image data, audio data, voice communication data, and video communication data) of the processing device and various modules in the electronic device. Data can be transferred between storage device 304 and processing device 302 via a bus. As an example, storage device 304 may include DRAM, dual data rate synchronous dynamic random access memory (DDR), DDR2, DDR3, DDR4, DDR5, LP DDR, GDDR, flash memory, static random-access memory (SRAM), etc.

[0115] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0116] The products disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict.

[0117] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0118] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a plurality of semiconductor patterns arranged along a first direction, wherein the semiconductor patterns include a first portion extending along a second direction and a plurality of second portions spaced apart along the second direction and all connected to the first portion, a trench is formed between adjacent first portions, the first direction intersecting the second direction; a doped dielectric layer is formed covering the trenches and the first portions; a first annealing process is performed on the substrate on which the doped dielectric layer is formed to diffuse dopant ions in the doped dielectric layer into the first portions and the second portions to form doped first portions and doped second portions, respectively; the doped dielectric layer is removed to expose the doped first portions; a bit line structure is formed based on the doped first portions, wherein the bit line structure connects the doped second portions.

2. The manufacturing method according to claim 1, characterized in that, The first portion based on doping forms a bit line structure, comprising: sequentially forming a first dielectric layer and a barrier layer in the trench, wherein the first dielectric layer is located between the doped first portion and the barrier layer, and the first dielectric layer and the barrier layer fill the trench; forming a metal layer on the surface of the first dielectric layer, the barrier layer and the doped first portion; and performing a second annealing process on the substrate on which the metal layer is formed, so that the metal layer reacts with the doped first portion to form a bit line contact.

3. The manufacturing method according to claim 2, characterized in that, The first portion based on doping, forming a bit line structure, further includes: forming a bit line extending along the second direction on the bit line contact.

4. The manufacturing method according to claim 2, characterized in that, The manufacturing method further includes: removing the metal layer from the surfaces of the first dielectric layer and the barrier layer to expose the barrier layer; and removing the exposed barrier layer.

5. The manufacturing method according to claim 4, characterized in that, The manufacturing method further includes forming an isolation structure at the location where the barrier layer is removed, wherein the isolation structure has an air gap extending along the second direction.

6. The manufacturing method according to claim 1, characterized in that, The provision of the substrate includes: providing an initial substrate, the initial substrate including a plurality of initial semiconductor patterns arranged along a first direction, wherein the initial semiconductor patterns include an initial first portion extending along a second direction and a plurality of second portions arranged at intervals along the second direction and all connected to the initial first portions, and an initial trench is formed between adjacent initial first portions; based on the initial trench, etching the initial first portions to form the trench and the first portions respectively, wherein the size of the first portion in the first direction is smaller than the size of the initial first portion in the first direction, and the size of the trench in the first direction is larger than the size of the initial trench in the first direction.

7. The manufacturing method according to claim 1, characterized in that, The manufacturing method further includes: after removing the doped dielectric layer, etching the first doped portion.

8. The manufacturing method according to claim 1, characterized in that, The doping concentration of the doped ions in the first part is greater than the doping concentration of the doped ions in the second part.

9. The manufacturing method according to claim 1, characterized in that, The first annealing process includes at least one of laser tip annealing and dynamic surface annealing.

10. The manufacturing method according to claim 1, characterized in that, The material of the doped dielectric layer includes boron-doped silicon oxide or phosphorus-doped silicon oxide.

11. A semiconductor structure, characterized in that, The semiconductor structure is formed using the manufacturing method described in any one of claims 1 to 10.

12. An electronic device, characterized in that, include: A processing device; and a memory device electrically connected to the processing device, the memory device comprising the semiconductor structure of claim 11.

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