NORD flash memory device and manufacturing method thereof
By retaining the hard mask layer and thinning the first sidewall during the fabrication of NORD flash memory devices to form the second and third sidewalls, the problem of third sidewall breakage and exposure is solved, device failure is avoided, and the normal operation of the device is ensured.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2026-01-27
- Publication Date
- 2026-05-01
AI Technical Summary
In the manufacturing process of existing NORD flash memory devices, the small etching window of the first sidewall can cause the top of the third sidewall to break or be exposed, leading to device failure.
During the patterning of the hard mask layer, a portion of the thickness is retained, and the first sidewall is thinned to form the second and third sidewalls. This transfers the location of the defects that are prone to occur during the etching process to the top corner of the hard mask layer, thus avoiding the breakage of the control gate top corner.
The problem of breakage and exposure at the top of the third side wall was resolved, avoiding short circuits between the control grid and the word lines and ensuring normal device operation.
Smart Images
Figure CN121968582A_ABST
Abstract
Description
NORD flash memory devices and their fabrication methods Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a NORD flash memory device and its fabrication method. Background Technology
[0002] Flash memory is a type of non-volatile memory that retains data for an extended period even without a power supply, meaning data is not lost when power is off. Flash memory is primarily divided into two types: NORD and NAND, commonly referred to as NORD Flash and NAND Flash. NORD Flash, also known as coded flash memory, has become the mainstream non-volatile memory technology due to its characteristics such as direct code execution, high reliability, and fast read speed.
[0003] Figures 1A to 1F are schematic diagrams of the structure corresponding to each step in a NORD flash memory fabrication method. As shown in Figure 1A, a gate oxide layer 101, a gate stack on the gate oxide layer 101, and a hard mask layer 105 on the gate stack are sequentially formed on a substrate 100. The gate stack includes, from bottom to top, a floating gate polysilicon layer 102, an inter-gate dielectric layer, and a control gate polysilicon layer 104. The inter-gate dielectric layer includes an ONO structure composed of a first oxide layer 103a, a nitride layer 103b, and a second oxide layer 103c stacked from bottom to top. First, the hard mask layer 105 is patterned (FGSN_ET) to define a first window 110. Next, as shown in Figure 1B, a first sidewall 106 (FGSP DEP / ET) is formed on the sidewalls of the patterned hard mask layer 105 to define a second window 120. Next, as shown in Figures 1C and 1D, the control gate polysilicon layer 104 (CGPL_ET) and the inter-gate dielectric layer are etched along the second window 120. Next, as shown in Figure 1E, the second sidewall 107 and the third sidewall 108 (OFFSET OX / SIN DEP&ET) are formed along the second window 120. Next, as shown in Figure 1F, the floating gate polysilicon layer 102 and the gate oxide layer 101 (FGPL1_ET) are etched to form the word line window 130.
[0004] Referring to Figures 2A, 2B, and 2C, in the above fabrication process, during the formation of the first sidewall 106, the etching process window is relatively small. If the over-etched portion (OE amount) is too small, the third sidewall 108 (OFFSET OX SIN) is easily exposed after the subsequent chemical mechanical polishing (MPL_CMP) of the formed control gate polysilicon layer. It will be removed during the hard mask layer 105 removal (FGSN remove), as shown in Figure 2B. This can generally be improved by reducing the CMP time, but the improvement is not significant. If the over-etched portion (OE amount) is too large, the sidewall of the first sidewall (FGSP) is relatively tilted. After the second sidewall 107 (OFFSET OX_ET) is formed, the third sidewall (OFFSET OX SIN) 108 is prone to breakage, as shown in Figure 2C, leading to device failure. Summary of the Invention
[0005] The purpose of this invention is to provide a NORD flash memory device and its manufacturing method to solve the problems of the third sidewall top being broken due to the small etching process window of the first sidewall and the exposure of the third sidewall top after the polysilicon layer of the word line is ground and etched back.
[0006] To achieve the above objectives, the present invention provides a method for manufacturing a NORD flash memory device, comprising:
[0007] A semiconductor structure is provided, the semiconductor structure including a substrate, a gate stack on the substrate and a hard mask layer on the gate stack, the gate stack including a floating gate polysilicon layer, an inter-gate dielectric layer and a control gate polysilicon layer from bottom to top;
[0008] The hard mask layer is patterned to define a first window, and a portion of the thickness of the hard mask layer is retained at the location of the first window.
[0009] A first sidewall is deposited on the sidewall of the patterned hard mask layer, and the hard mask layer remaining between the first sidewalls is etched to define a second window;
[0010] The control gate polysilicon layer is etched along the second window;
[0011] The first sidewall is thinned so that the thinned first sidewall forms a step with the retained hard mask layer;
[0012] A second sidewall and a third sidewall are formed sequentially, the second sidewall at least covering the sidewall of the control gate polysilicon layer, and the third sidewall covering the second sidewall, the step, and a portion of the first sidewall; and...
[0013] The floating gate polysilicon layer is etched to define the word line window.
[0014] Optionally, the thickness of the retained portion of the hard mask layer is 200 to 300 angstroms.
[0015] Optionally, the thickness of the first sidewall thinning is 200 angstroms to 400 angstroms.
[0016] Optionally, the first sidewall can be thinned using HF wet cleaning.
[0017] Optionally, a gate oxide layer is formed on the substrate, and the gate stack is formed on the gate oxide layer.
[0018] Optionally, the inter-gate dielectric layer includes an ONO structure consisting of a first oxide layer, a nitride layer, and a second oxide layer stacked from bottom to top.
[0019] Optionally, etching the control gate polysilicon layer along the second window further includes removing the second oxide layer along the second window.
[0020] Optionally, after forming the third sidewall and before etching the floating gate polysilicon layer, the nitride layer and the first oxide layer are sequentially etched along the second window.
[0021] Optionally, the first sidewall includes an oxide layer, the second sidewall includes an oxide layer, and the third sidewall includes a nitrided layer.
[0022] Optionally, the method for fabricating the NORD flash memory device further includes, after etching the floating gate polysilicon layer:
[0023] A tunneling oxide layer is formed on the sidewall of the character line window;
[0024] A polysilicon layer for word lines is filled into the word line window;
[0025] The polysilicon layer for the word lines is subjected to chemical mechanical polishing and etch-back.
[0026] In summary, the method for fabricating a NORD flash memory device provided by this invention, when patterning the hard mask layer above the gate stack, retains a portion of the hard mask layer thickness and thins the first sidewall. This allows the location of the weak point in the third sidewall, which is prone to defects during the etching process, to be shifted to the top corner of the hard mask layer instead of the top corner of the control gate during the deposition and etching of the second and third sidewalls. This solves the problems of the third sidewall breaking at the top corner of the control gate due to the small etching process window of the first sidewall and the top of the third sidewall being exposed after the polysilicon layer of the word line is ground back. This avoids short circuits between the control gate and the word line, thereby preventing device failure. Attached Figure Description
[0027] Figures 1A to 1F are schematic diagrams of the structure corresponding to each step in the fabrication method of a NORD flash memory device;
[0028] Figures 2A to 2C are electron microscope images of the NORD flash memory device;
[0029] Figure 3 is a flowchart illustrating the method for fabricating a NORD flash memory device according to an embodiment of the present invention;
[0030] Figures 4A to 4F are schematic diagrams of the structure corresponding to each step in the fabrication method of a NORD flash memory device provided in an embodiment of the present invention. Detailed Implementation
[0031] To make the content of this invention clearer and easier to understand, the following description, in conjunction with the accompanying drawings, further illustrates the invention. Of course, this invention is not limited to this specific embodiment, and common substitutions well-known to those skilled in the art are also covered within the scope of protection of this invention.
[0032] Secondly, the present invention is described in detail using schematic diagrams. When describing the examples of the present invention in detail, for ease of explanation, the schematic diagrams are not enlarged to a certain extent according to the general proportions, and this should not be regarded as a limitation of the present invention.
[0033] For ease of description, some embodiments of the present invention may use spatially relative terms such as “above,” “below,” “top,” and “under” to describe the relationship between one element or component and another (or more) elements or components as shown in the accompanying drawings of the embodiments. It should be understood that, in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, it is described as an element or component “below” or “under” other elements or components, and will subsequently be positioned “above” or “on” other elements or components. The terms “first,” “second,” etc., used below are used to distinguish between similar elements and are not necessarily used to describe a particular order or temporal sequence.
[0034] Figure 3 is a flowchart illustrating a method for fabricating a NORD flash memory device according to an embodiment of the present invention. As shown in Figure 1, the method for fabricating a NORD flash memory device provided in this embodiment includes the following steps:
[0035] Step S01: Provide a semiconductor structure, the semiconductor structure including a substrate, a gate stack on the substrate and a hard mask layer on the gate stack, the gate stack including a floating gate polysilicon layer, an inter-gate dielectric layer and a control gate polysilicon layer from bottom to top;
[0036] Step S02: Pattern the hard mask layer, define a first window, and retain a portion of the thickness of the hard mask layer at the location of the first window;
[0037] Step S03: Deposit a first sidewall on the sidewall of the patterned hard mask layer and etch the hard mask layer between the first sidewalls to define a second window;
[0038] Step S04: Etch the control gate polysilicon layer along the second window;
[0039] Step S05: Thin the first sidewall so that the first sidewall forms a step with the retained hard mask layer;
[0040] Step S06: Sequentially form a second sidewall and a third sidewall, wherein the second sidewall at least covers the sidewall of the control gate polysilicon layer, and the third sidewall covers the second sidewall, the step, and a portion of the first sidewall; and,
[0041] Step S07: Etch the floating gate polysilicon layer to define the word line window.
[0042] Figures 4A to 4F are schematic diagrams illustrating the structural steps corresponding to each step in the fabrication method of a NORD flash memory device according to an embodiment of the present invention. Please refer to Figure 3 and, in conjunction with Figures 4A to 4F, the fabrication method of the NORD flash memory device provided by the present invention will be explained in detail.
[0043] First, referring to Figure 2A, steps S01 and S02 are performed to provide a semiconductor structure. The semiconductor structure includes a substrate 200, a gate stack on the substrate 200, and a hard mask layer 205 on top of the gate stack. The gate stack includes, from bottom to top, a floating gate polysilicon layer 202, an inter-gate dielectric layer, and a control gate polysilicon layer 204. The hard mask layer 205 (FGSN_ET) is patterned, a first window 210 is defined, and a portion of the thickness of the hard mask layer 205 is retained at the location of the first window 210.
[0044] Specifically, the substrate 200 can be a silicon substrate, and the inter-gate dielectric layer includes an ONO structure composed of a first oxide layer 203a, a nitride layer 203b, and a second oxide layer 203c stacked from bottom to top. For example, the first oxide layer 203a and the second oxide layer 203c are silicon oxide layers, and the nitride layer 203b is a silicon nitride layer. The hard mask layer 205 is located on the control gate polysilicon layer 204, and the material of the hard mask layer 205 is at least one of silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbide nitride, and silicon oxynitride.
[0045] In this embodiment of the invention, during the patterning of the hard mask layer 205, a portion of the hard mask layer 105 is etched, and the thickness of the remaining portion of the hard mask layer 205 is 200 angstroms to 300 angstroms, for example, 250 angstroms. A gate oxide layer 201 is formed on the substrate 200, and the gate stack is located on the gate oxide layer 201. The gate oxide layer 201 can be formed by methods such as low-pressure chemical vapor deposition, atomic layer deposition, thermal oxidation, or molecular beam epitaxy. The material of the gate oxide layer 201 is silicon oxide to enhance the interfacial adhesion between layers.
[0046] Next, referring to FIG4B, step S03 is performed to deposit first sidewalls 206 (FGSP DEP / ET) on the sidewalls of the patterned hard mask layer 205, and to etch the hard mask layer 205 remaining between the first sidewalls 206 to define the second window 220. The first sidewalls 206 are oxide layers, such as silicon dioxide layers.
[0047] Next, referring to FIG2C, step S04 is performed, in which the control gate polysilicon layer 204 is etched along the second window 220. The etching of the control gate polysilicon layer 204 along the second window 220 stops at the second oxide layer 203c of the inter-gate dielectric layer. The etching of the control gate polysilicon layer 204 also includes a cleaning process, in which the second oxide layer 203c exposed by the second window 220 is removed, exposing the intermediate nitride layer 203b.
[0048] Next, referring to Figure 2D, step S05 is performed to thin the first sidewall 206, so that the thinned first sidewall 206 forms a step 209 with the retained hard mask layer 205. In this embodiment, hydrofluoric acid wet etching (HF OX DIP) can be used to thin the first sidewall 206, which combines chemical wet etching and cleaning processes. It utilizes the high selectivity and isotropic etching characteristics of hydrofluoric acid on silicon oxide to thin the first sidewall 206. Optionally, the thickness of the first sidewall 206 thinned is 200 angstroms to 400 angstroms, for example, 300 angstroms.
[0049] Next, referring to Figure 2E, step S06 is performed to sequentially form a second sidewall 207 (OFFSET OX) and a third sidewall 208 (OFFSET SIN). The second sidewall 207 at least covers the sidewall of the control gate polysilicon layer 204, and the third sidewall 208 covers the second sidewall 207, the step 209, and part of the first sidewall 206.
[0050] In the above steps, when the hard mask layer of the retained portion is etched and the first sidewall 206 is thinned by HF OX DIP, and the second sidewall 207 and the third sidewall 208 are deposited and etched, the third sidewall (OFFSET SIN) 208 covers the step 209 formed by the hard mask layer of the retained portion and the thinned first sidewall 206. This shifts the location of the weak point that is prone to occur in the etching process to the top corner of the hard mask layer, rather than the top corner of the control gate 204. Even if the third sidewall 208 breaks during the subsequent grinding and etching of the word line polysilicon layer, the break point is at the top corner of the retained hard mask layer 205, rather than the top corner of the selected gate, thereby avoiding a short circuit between the control gate and the word line.
[0051] Furthermore, after forming the second sidewall 207 and the third sidewall 208, the process further includes sequentially etching the nitride layer 203b and the first oxide layer 203a along the second window 220. The second sidewall 207 is an oxide layer, such as a silicon dioxide layer, and the third sidewall 208 is a nitride layer, such as a silicon nitride layer.
[0052] Next, referring to Figure 2F, step S07 is performed to etch the floating gate polysilicon layer 202 and define the word line window 230.
[0053] Furthermore, the method for fabricating the NORD flash memory device provided in this embodiment of the invention further includes: after etching the floating gate polysilicon layer 202, forming a tunneling oxide layer on the sidewall of the word line window 230; filling the word line window with a word line polysilicon layer; and performing chemical mechanical polishing and etch-back on the word line polysilicon layer.
[0054] Because this invention shifts the location of the weak point that is prone to occur in the etching process to the top corner of the third sidewall 208 instead of the top corner of the control gate 204 when forming the second sidewall 207 and the third sidewall 208, it solves the problem of the top of the third sidewall 208 (OFFSET SIN) being exposed when the word line polysilicon layer is chemically mechanically polished and etched back when the first sidewall 206 has too little etched portion (OE amount), and the problem of the top of the third sidewall 208 (OFFSET SIN) breaking when the first sidewall 206 has too much etched portion (OE amount). In other words, it solves the problem of insufficient process window between the breakage of the OFFSET SIN top and the exposure of the OFFSET SIN top after MPL_CMP, without adding any additional process steps.
[0055] In summary, this invention provides a NORD flash memory device and its fabrication method. When patterning the hard mask layer above the gate stack, a portion of the hard mask layer thickness is retained, and the first sidewall is thinned. This allows the location of the weak point in the third sidewall, which is prone to defects during the etching process, to be shifted to the top corner of the hard mask layer instead of the top corner of the control gate during the deposition and etching of the second and third sidewalls. This solves the problems of the third sidewall breaking at the top corner of the control gate due to the small etching process window of the first sidewall and the top of the third sidewall being exposed after the polysilicon layer of the word line is ground back. This avoids short circuits between the control gate and the word line, thereby preventing device failure.
[0056] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. A method for fabricating a NORD flash memory device, characterized in that, include: A semiconductor structure is provided, the semiconductor structure including a substrate, a gate stack on the substrate and a hard mask layer on the gate stack, the gate stack including a floating gate polysilicon layer, an inter-gate dielectric layer and a control gate polysilicon layer from bottom to top; The hard mask layer is patterned to define a first window, and a portion of the thickness of the hard mask layer is retained at the location of the first window; first sidewalls are deposited on the sidewalls of the patterned hard mask layer, and the hard mask layer retained between the first sidewalls is etched to define a second window; The control gate polysilicon layer is etched along the second window; the first sidewall is thinned so that the thinned first sidewall forms a step with the remaining hard mask layer; a second sidewall and a third sidewall are formed sequentially, the second sidewall at least covering the sidewall of the control gate polysilicon layer, and the third sidewall covering the second sidewall, the step, and part of the first sidewall; and the floating gate polysilicon layer is etched to define the word line window.
2. The method for fabricating a NORD flash memory device according to claim 1, characterized in that, The thickness of the hard mask layer in the retained portion is 200 to 300 angstroms.
3. The method for fabricating a NORD flash memory device according to claim 1, characterized in that, The thickness of the first sidewall is reduced to 200 angstroms to 400 angstroms.
4. The method for fabricating a NORD flash memory device according to claim 1, characterized in that, The first sidewall was thinned using HF wet cleaning.
5. The method for fabricating a NORD flash memory device according to claim 1, characterized in that, A gate oxide layer is formed on the substrate, and the gate stack is formed on the gate oxide layer.
6. The method for fabricating a NORD flash memory device according to claim 1, characterized in that, The inter-gate dielectric layer comprises an ONO structure consisting of a first oxide layer, a nitride layer, and a second oxide layer stacked from bottom to top.
7. The method for fabricating a NORD flash memory device according to claim 6, characterized in that, Etching the control gate polysilicon layer along the second window also includes removing the second oxide layer along the second window.
8. The method for fabricating a NORD flash memory device according to claim 7, characterized in that, After the third sidewall is formed and before the floating gate polysilicon layer is etched, the nitride layer and the first oxide layer are sequentially etched along the second window.
9. The method for fabricating a NORD flash memory device according to claim 8, characterized in that, The first sidewall includes an oxide layer, the second sidewall includes an oxide layer, and the third sidewall includes a nitrided layer.
10. The method for fabricating a NORD flash memory device according to claim 9, characterized in that, After etching the floating gate polysilicon layer, the process further includes: forming a tunneling oxide layer on the sidewall of the word line window; filling the word line window with a word line polysilicon layer; and performing chemical mechanical polishing and etch-back on the word line polysilicon layer.