Semiconductor memory device and method of manufacturing semiconductor memory device

Abstract

The invention relates to a semiconductor memory device and a manufacturing method of the semiconductor memory device. A semiconductor memory device and a method of manufacturing the same are provided. The semiconductor memory device includes a cell pillar structure and a conductive layer surrounding an outer surface of the cell pillar structure. A portion of an outer surface of the unit column structure is arranged at different distances from a center point on a plurality of first axes and a plurality of second axes extending radially from the center point. The plurality of first axes and the plurality of second axes are alternately arranged in a clockwise direction, and the unit column structure includes a plurality of channel portions and an isolation structure extending between the plurality of channel portions from the center point.

Description

Semiconductor memory devices and methods for manufacturing semiconductor memory devices Technical Field

[0001] Various embodiments of this disclosure generally relate to a semiconductor memory device, and more specifically, to a semiconductor memory device including a three-dimensional memory cell array and a method of manufacturing the semiconductor memory device. Background Technology

[0002] Semiconductor memory devices are not only suitable for small electronic devices, but also for electronic systems in a wide range of fields such as automobiles, healthcare, and data centers. As a result, the demand for semiconductor memory devices is increasing.

[0003] Semiconductor memory devices include memory cell arrays, and memory cell arrays include multiple memory cells for data storage. Semiconductor memory devices are classified into two-dimensional semiconductor memory devices that include two-dimensional memory cell arrays and three-dimensional semiconductor memory devices that include three-dimensional memory cell arrays.

[0004] In a three-dimensional memory cell array, multiple memory cells are arranged along the X, Y, and Z axes. In a two-dimensional memory cell array, multiple memory cells are arranged along the X and Y axes. Due to this structural difference, three-dimensional memory cell arrays are more advantageous for increasing the capacity of semiconductor memory devices compared to two-dimensional memory cell arrays.

[0005] A three-dimensional memory cell array can be divided into multiple memory cell strings corresponding to multiple cell pillar structures. Each cell pillar structure includes a channel layer. The memory cells in each memory cell string can be connected in series through the channel layer. To improve the integration density of the memory cell string, the channel layer of the cell pillar structure can be divided into two or more channel sections. However, this may lead to a deterioration in the operational reliability of the memory cell string. Summary of the Invention

[0006] According to one embodiment, a semiconductor memory device may include: a cell pillar structure including an outer surface intersecting a plurality of first axes and a plurality of second axes, the plurality of first axes and the plurality of second axes extending radially from a center point in a first plane, the plurality of first axes and the plurality of second axes being arranged alternately in a clockwise direction, the outer surface of the cell pillar structure being spaced apart from the center point, and the cell pillar structure extending along a stacking direction intersecting the first plane; and a plurality of conductive layers, the plurality of conductive layers being spaced apart from each other in the stacking direction and surrounding the outer surface of the cell pillar structure. The cell pillar structure may include: a plurality of channel portions intersecting the plurality of first axes, each of the plurality of channel portions including a radius of curvature defined between the center point and a vertex intersecting a corresponding first axis; a plurality of memory portions, each of the plurality of memory portions disposed between the conductive layers and the channel portion; and an isolation structure disposed between the plurality of channel portions and extending toward the center point. Each of the plurality of channel portions may include an end located at a first distance from the vertex along an extension direction of the respective first axis, the first distance being 30% to 80% relative to the radius of curvature.

[0007] According to one embodiment, a method of manufacturing a semiconductor memory device may include the steps of: forming a stack comprising a plurality of material layers extending in a first plane and arranged along a stacking direction intersecting the first plane; forming a via by etching the stack, the via including a first inner wall intersecting a plurality of first axes and a plurality of second axes, the plurality of first axes and the plurality of second axes extending radially from a center point in the first plane and arranged alternately in a clockwise direction, the first inner wall being spaced apart from the center point; forming a channel layer extending on the first inner wall and including a second inner wall facing the center point; forming a plurality of seed barrier patterns extending on the second inner wall and arranged alternately with the plurality of second axes in the clockwise direction; selectively growing a plurality of growth barrier patterns from a plurality of third inner walls of the plurality of seed barrier patterns toward the center point to open a plurality of etch targets of the channel layer intersecting the plurality of second axes; and forming a plurality of openings by removing the plurality of etch targets to penetrate the channel layer. Attached Figure Description

[0008] Figure 1 is a circuit diagram showing a memory cell array of a semiconductor memory device according to an embodiment of the present disclosure;

[0009] Figures 2A and 2B are diagrams illustrating a semiconductor memory device according to an embodiment of the present disclosure;

[0010] Figure 3 is a diagram illustrating the gate stack and cell pillar structure according to an embodiment of the present disclosure;

[0011] Figures 4A, 4B and 4C are cross-sectional views illustrating doped semiconductor structures and unit pillar structures according to embodiments of the present disclosure;

[0012] Figures 5A, 5B, 6A and 6B are plan views showing the cross-section of a unit column structure according to an embodiment of the present disclosure;

[0013] Figures 7A and 7B are cross-sectional and plan views illustrating a laminate, a hole, and a layer disposed in the hole according to an embodiment of the present disclosure;

[0014] Figures 8A and 8B are plan views illustrating seed barrier patterns according to embodiments of the present disclosure;

[0015] Figures 9A, 9B, 9C, 9D, 9E and 9F are plan views illustrating the growth barrier pattern, buffer pattern, channel portion and memory portion according to embodiments of the present disclosure.

[0016] Figures 10A and 10B are cross-sectional and plan views illustrating a gate stack according to an embodiment of the present disclosure.

[0017] Figure 11 is a plan view showing a seed barrier pattern according to an embodiment of the present disclosure;

[0018] Figures 12A and 12B are cross-sectional and plan views illustrating a laminate, a hole, and a layer disposed in the hole according to an embodiment of the present disclosure;

[0019] Figures 13A, 13B, and 13C are plan views illustrating the channel portion, memory portion, and conductive layer according to embodiments of the present disclosure.

[0020] Figures 14A and 14B are cross-sectional and plan views illustrating a laminate, a hole, and a layer disposed in the hole according to an embodiment of the present disclosure;

[0021] Figures 15A, 15B and 15C are plan views showing the channel portion and opening according to an embodiment of the present disclosure;

[0022] Figure 16 is a plan view illustrating a laminate, holes, and layers disposed in the holes according to an embodiment of the present disclosure; and

[0023] Figure 17 is a block diagram illustrating an electronic system according to an embodiment of the present disclosure. Detailed Implementation

[0024] Specific structural or functional descriptions of examples of embodiments of the concepts disclosed in this specification are shown only to illustrate examples of embodiments of the concepts, and examples of embodiments of the concepts may be implemented in various forms, but the description is not limited to the examples of embodiments described in this specification.

[0025] The use of terms such as "first," "second," etc., to distinguish various elements does not imply any size, order, priority, quantity, or importance of the elements. For example, in one example, a first element may be named a second element, and in another example, a second element may be named a first element. Terms such as "top," "above," "upper," "sidewall," "upper part," "lower part," "inner," "outer," and other terms that imply relative spatial relationships or directions are used only for the purpose of facilitating description or reference to the accompanying drawings and are not intended to limit in any other way. It should be understood that when it is indicated that an element or layer is "on," "connected to," or "attached to" another element or layer, that element or layer may be directly on, directly connected to, or attached to the other element or layer, or there may be intermediate elements or layers. Conversely, when it is indicated that an element or layer is "directly on," "directly connected to," or "directly attached to" another element or layer, there are no intermediate elements or layers. Cross-shading throughout the drawings indicates corresponding or similar areas between the drawings and does not indicate material associated with these areas.

[0026] According to various embodiments of the present disclosure, a semiconductor memory device with improved integration density and operational reliability of memory cell strings, as well as a method for manufacturing the semiconductor memory device, are provided.

[0027] Figure 1 is a circuit diagram illustrating a memory cell array of a semiconductor memory device according to an embodiment of the present disclosure.

[0028] Referring to Figure 1, the memory cell array of the semiconductor memory device includes multiple memory cell strings CS1 to CSn, where n is a natural number equal to or greater than 2. The multiple memory cell strings CS1 to CSn are connected to the gate array GAR, the bit line array BAR, and the common source layer CSR.

[0029] Each of the plurality of memory cell strings CS1 to CSn includes at least one source selection transistor SST, a plurality of memory cells MC, and at least one drain selection transistor DST. The plurality of memory cells MC are stacked between the source selection transistor SST and the drain selection transistor DST. The source selection transistor SST, the plurality of memory cells MC, and the drain selection transistor DST are connected in series through corresponding channel portions (e.g., CH1 or CH2 as shown in FIG3). Multiple channel portions of the plurality of memory cell strings CS1 to CSn can be formed by separating the channel layers via an isolation structure. The cell pillar structure includes a channel layer. As one embodiment, referring to FIG3, 4A, 4B, and 4C, the channel layer CHL of the cell pillar structure CS1 can be divided by an isolation structure SS into a first channel portion CH1 of a first memory cell string and a second channel portion CH2 of a second memory cell string.

[0030] The gate array (GAR) includes a source select line (SSL), multiple word lines (WL), and a drain select line (DSL). The source select line (SSL) can be used as the gate electrode of the source select transistor (SST), each word line (WL) can be used as the gate electrode of the corresponding memory cell (MC), and the drain select line (DSL) can be used as the gate electrode of the drain select transistor (DST).

[0031] The bit line array (BAR) comprises multiple bit lines BL1 to BLn, where n is a natural number of 2 or greater. Each bit line BL1 to BLn corresponds to a memory cell string CS1 to CSn. Each bit line BL1 to BLn is connected to a channel portion of the corresponding memory cell string to selectively control that channel portion. A voltage for pre-charging the channel portion corresponding to each bit line BL1 to BLn can be applied to each of the bit lines BL1 to BLn.

[0032] Multiple memory cell strings CS1 to CSn are connected in parallel to a common source layer CSR. A voltage for discharging multiple channel portions of the multiple memory cell strings CS1 to CSn can be applied to the common source layer CSR.

[0033] Figures 2A and 2B are diagrams illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0034] Referring to Figures 2A and 2B, the semiconductor memory device includes a gate array (GAR), a bit line array (BAR), multiple cell pillar structures (CPI), a doped semiconductor structure (DPS), and a peripheral circuit structure (PCS). The gate array (GAR), bit line array (BAR), and doped semiconductor structure (DPS) are disposed above the peripheral circuit structure (PCS). The gate array (GAR) is disposed between the bit line array (BAR) and the doped semiconductor structure (DPS). The multiple cell pillar structures (CPI) pass through the gate array (GAR).

[0035] The gate array (GAR) includes multiple conductive layers CL1, CL2, and CL3. Each of the multiple conductive layers CL1, CL2, and CL3 may extend parallel to a first plane. In one embodiment, the first plane may be an XY plane. The multiple conductive layers CL1, CL2, and CL3 may be arranged to be spaced apart from each other in a stacking direction intersecting the first plane. In one embodiment, the stacking direction is the Z-axis direction intersecting the XY plane. Each of the multiple conductive layers CL1, CL2, and CL3 may include various conductive materials, such as doped semiconductor layers and metal layers. The doped semiconductor layer may include a doped silicon layer. The metal layer may include tungsten, copper, molybdenum, etc. Each of the multiple conductive layers CL1, CL2, and CL3 may also include a metal nitride layer. The metal nitride layer may include titanium nitride, tantalum nitride, etc.

[0036] The plurality of conductive layers CL1, CL2, and CL3 may include at least one first conductive layer CL1, a plurality of second conductive layers CL2, and at least one third conductive layer CL3. The plurality of second conductive layers CL2 are arranged to be spaced apart from each other along the stacking direction between the first conductive layer CL1 and the third conductive layer CL3. The first conductive layer CL1 is positioned closer to the doped semiconductor structure DPS than the plurality of second conductive layers CL2, and the third conductive layer CL3 is positioned closer to the bit line array BAR than the plurality of second conductive layers CL2. The first conductive layer CL1 can be used as the source select line SSL as shown in FIG1, the plurality of second conductive layers CL2 can be used as multiple word lines WL as shown in FIG1, and the third conductive layer CL3 can be used as the drain select line DSL as shown in FIG1.

[0037] Multiple conductive layers CL1, CL2, and CL3 may be alternately arranged with multiple insulating layers IL1, IL2, and IL3 in the stacking direction. Each of the multiple insulating layers IL1, IL2, and IL3 may include an insulating material such as a silicon oxide layer or a silicon nitride layer. The multiple insulating layers IL1, IL2, and IL3 include a first insulating layer IL1, multiple second insulating layers IL2, and a third insulating layer IL3. The first insulating layer IL1 is disposed between the doped semiconductor structure DPS and the first conductive layer CL1, the third insulating layer IL3 is disposed between the bit line array BAR and the third conductive layer CL3, and the multiple second insulating layers IL2 are arranged to be spaced apart from each other in the stacking direction between the first insulating layer IL1 and the third insulating layer IL3. The multiple conductive layers CL1, CL2, and CL3 and the multiple insulating layers IL1, IL2, and IL3 may form a gate stack GST.

[0038] Multiple cell pillar structures (CPIs) extend in the stacking direction to penetrate the gate stack (GST). Each of the multiple conductive layers CL1, CL2, and CL3 may surround the sidewall of each of the cell pillar structures (CPIs). The cell pillar structure (CPI) includes multiple memory cell string regions. The multiple memory cell string regions correspond to multiple bit lines of a bit line array (BAR), and each memory cell string region is controlled by its corresponding bit line. In one embodiment, the cell pillar structure (CPI) may include a first memory cell string region AR1 and a second memory cell string region AR2, and the bit line array (BAR) may include a first bit line BL1 corresponding to the first memory cell string region AR1 and a second bit line BL2 corresponding to the second memory cell string region AR2. Each of the multiple conductive layers CL1, CL2, and CL3 may control all of the multiple memory cell string regions of the control cell pillar structure (CPI). As one embodiment, each of the first conductive layer CL1, the second conductive layer CL2, and the third conductive layer CL3 may have an all-around structure surrounding the sidewall of the cell pillar structure (CPI) to control both the first memory cell string region AR1 and the second memory cell string region AR2.

[0039] Although not shown in Figures 2A and 2B, multiple conductive bit line connection structures can be provided between the bit line array (BAR) and the multiple cell pillar structures (CPI). Each conductive bit line connection structure can connect a corresponding bit line (e.g., BL1) to a corresponding conductive capping pattern (e.g., CAP1 as shown in Figure 3), and various structures can be designed accordingly. The conductive capping pattern can be set in the memory cell string region of the cell pillar structure (CPI), which will be described below with reference to Figure 3.

[0040] Multiple bit lines (e.g., BL1, BL2) of the bit line array (BAR) can extend in the X-axis direction and can be spaced apart in the Y-axis direction. The doped semiconductor structure (DPS) can be spaced apart from the bit line array (BAR) in the Z-axis direction. One of the doped semiconductor structure (DPS) and the bit line array (BAR) can be positioned closer to the peripheral circuit structure (PCS) than the other. In one embodiment, as shown in FIG2A, the doped semiconductor structure (DPS) can be positioned closer to the peripheral circuit structure (PCS) than the bit line array (BAR). In one embodiment, as shown in FIG2B, the bit line array (BAR) can be positioned closer to the peripheral circuit structure (PCS) than the doped semiconductor structure (DPS).

[0041] Referring to Figures 2A and 2B, a doped semiconductor structure (DPS) includes at least one doped semiconductor layer extending in the XY plane. The doped semiconductor layer of the DPS may include n-type impurities or p-type impurities. In one embodiment, the DPS may include one or both of a first conductivity-type doped semiconductor layer containing n-type impurities as majority carriers and a second conductivity-type doped semiconductor layer containing p-type impurities as majority carriers. As described with reference to Figure 1, the first conductivity-type doped semiconductor layer may serve as a common source layer (CSR), while the second conductivity-type doped semiconductor layer may serve as a well region.

[0042] The columnar unit structure (CPI) includes a contact surface that contacts the doped semiconductor structure (DPS). The contact surface may be formed on a portion of the sidewall of the columnar unit structure (CPI), an end of the columnar unit structure (CPI), or the like.

[0043] The peripheral circuit structure PCS may include input / output circuits, control circuits, voltage generation circuits, row decoders, column decoders, page buffers, etc., and may include multiple transistor PTRs that constitute at least a part of it, as well as multiple interconnect ICs connected to the multiple transistor PTRs.

[0044] Each transistor PTR is disposed in an active region of a semiconductor substrate SUB separated by an isolation layer ISO. The semiconductor substrate SUB comprises a semiconductor material. In one embodiment, the semiconductor material may include one or more of group IV semiconductors, group III-V compound semiconductors, and group II-VI compound semiconductors. Group IV semiconductors may include single-crystal silicon (Si), polycrystalline silicon, germanium (Ge), or silicon-germanium (SiGe). Group III-V compound semiconductors may include GaAs, GaN, GaP, GaAsP, GaInAsP, AlAs, AlGa, InP, InSb, and InGaAs. Group II-VI compound semiconductors may include ZnS, ZnO, and CdS.

[0045] The semiconductor substrate SUB may also include a dielectric layer. In one embodiment, the semiconductor substrate SUB may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. The semiconductor substrate SUB may also include organic materials. In one embodiment, the semiconductor substrate SUB may include graphene.

[0046] The semiconductor substrate SUB can be a bulk wafer or an epitaxial layer grown by selective epitaxial growth (SEG). Alternatively, the semiconductor substrate SUB can be a layer formed by metal-induced lateral crystallization (MILC) and may partially include metal.

[0047] The semiconductor substrate SUB can be monocrystalline, polycrystalline, or amorphous. The semiconductor substrate SUB can include Group II, III, IV, V, or VI impurities. In one embodiment, the semiconductor substrate SUB can include an n-well region doped with n-type impurities, a p-well region doped with p-type impurities, or both an n-well region and a p-well region.

[0048] The transistor PTR is covered by a peripheral insulating structure (PIS). The PIS is positioned above the semiconductor substrate (SUB). Multiple interconnects (ICs) can be formed within the PIS and include multiple conductive lines and multiple conductive contacts for electrical connections.

[0049] Referring to Figure 2A, the doped semiconductor structure DPS can be disposed on the peripheral insulating structure PIS.

[0050] Referring to FIG2B, the semiconductor memory device may further include a bonding structure BS. The bonding structure BS may be disposed between the bit line array BAR and the peripheral circuit structure PCS. The bonding structure BS includes a first intermediate insulating structure IS1, a second intermediate insulating structure IS2, a first conductive bonding pattern BDP1, and a second conductive bonding pattern BDP2. The first intermediate insulating structure IS1 is disposed between the bit line array BAR and the peripheral insulating structure PIS, and the second intermediate insulating structure IS2 is disposed between the first intermediate insulating structure IS1 and the peripheral insulating structure PIS. The first intermediate insulating structure IS1 is bonded to the second intermediate insulating structure IS2. The first conductive bonding pattern BDP1 is disposed in the first intermediate insulating structure IS1, and the second conductive bonding pattern BDP2 is disposed in the second intermediate insulating structure IS2. The first conductive bonding pattern BDP1 is bonded to the second conductive bonding pattern BDP2 and is electrically connected to the second conductive bonding pattern BDP2.

[0051] The cell column structure CPI shown in Figure 2A or Figure 2B can be configured to implement two or more memory cell strings. Hereinafter, a cell column structure according to an embodiment of the present disclosure will be described with reference to Figure 3.

[0052] Figure 3 is a diagram illustrating the gate stack (GST) and cell pillar structure (CPI) according to an embodiment of the present disclosure.

[0053] Figure 3 shows a portion of the gate layer stack GST as shown in Figure 2A or Figure 2B, and does not show the first conductive layer CL1 and the first insulating layer IL1 among the first conductive layer CL1, multiple second conductive layers CL2, third conductive layer CL3, first insulating layer IL1, multiple second insulating layers IL2 and third insulating layer IL3 shown in Figure 2A or Figure 2B.

[0054] Referring to Figure 3, the unit pillar structure CPI extends in a stacking direction intersecting the XY plane (e.g., in the Z-axis direction). The unit pillar structure CPI includes an isolation structure SS, a capping layer isolation structure CSS, a channel layer CHL separated by two or more channel portions (e.g., CH1 and CH2), two or more memory portions (e.g., ML1 and ML2) corresponding to the two or more channel portions, and two or more conductive capping patterns (e.g., CAP1 and CAP2) corresponding to the two or more channel portions.

[0055] The channel layer CHL comprises a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof. The channel layer CHL is divided into two or more channel portions by an isolation structure SS. In one embodiment, the channel layer CHL may be divided by the isolation structure SS into a first channel portion CH1 and a second channel portion CH2. Each channel portion serves as a channel region for a corresponding memory cell string. In one embodiment, the first channel portion CH1 may serve as a channel region for a first memory cell string, and the second channel portion CH2 may serve as a channel region for a second memory cell string. The channel layer CHL may extend the height of the third insulating layer IL3 of the gate layer stack GST.

[0056] The isolation structure SS comprises insulating material. The isolation structure SS may not reach the height set by the third insulating layer IL3 and may have a shorter length in the stacking direction than the channel layer CHL. As a result, the upper ends of each of the two or more channel portions may protrude further in the stacking direction than the isolation structure SS.

[0057] A buffer pattern (e.g., BU1 or BU2) may be provided between the isolation structure SS and each channel portion. In one embodiment, a first buffer pattern BU1 may be provided between the isolation structure SS and the first channel portion CH1, and a second buffer pattern BU2 may be provided between the isolation structure SS and the second channel portion CH2. Each buffer pattern may include an insulating material.

[0058] Two or more conductive capping patterns (e.g., CAP1 and CAP2) include a doped semiconductor layer. The doped semiconductor layer may include n-type impurities, or both n-type and p-type impurities. In one embodiment, the two or more conductive capping patterns may include n-type impurities as majority carriers and may be configured as drain regions. The top of the protruding channel portion may be doped with the same impurity as the corresponding conductive capping pattern.

[0059] Two or more conductive capping patterns (e.g., CAP1 and CAP2) and capping layer isolation structures CSS may overlap with isolation structures SS in the stacking direction. The capping layer isolation structures CSS comprise insulating material. The two or more conductive capping patterns are spaced apart from each other by the capping layer isolation structures CSS. In one embodiment, a doped semiconductor layer can be divided into a first conductive capping pattern CAP1 and a second conductive capping pattern CAP2 by the capping layer isolation structures CSS. Each conductive capping pattern can be coupled to a corresponding channel portion and can be integrated with the corresponding channel portion by a heat treatment such as laser annealing. In one embodiment, the first conductive capping pattern CAP1 can be coupled to and integrated with a first channel CH1, and the second conductive capping pattern CAP2 can be coupled to and integrated with a second channel CH2. Each conductive capping pattern is coupled to a corresponding bit line via a conductive bit line connection structure. In one embodiment, the first conductive capping pattern CAP1 can be connected to the first bit line BL1 of the bit line array BAR shown in FIG2A or FIG2B, and the second conductive capping pattern CAP2 can be connected to the second bit line BL2 of the bit line array BAR shown in FIG2A or FIG2B.

[0060] Each of two or more memory portions (e.g., ML1 and ML2) is disposed between a corresponding channel portion and a gate stack GST. In one embodiment, a first memory portion ML1 may be disposed between a first channel portion CH1 and a gate stack GST, and a second memory portion ML2 may be disposed between a second channel portion CH2 and a gate stack GST.

[0061] The channel layer CHL may include a contact surface that contacts the doped semiconductor structure DPS as shown in FIG. 2A or FIG. 2B. The contact surface can be designed in various ways. Hereinafter, contact surfaces according to embodiments of the present disclosure will be described with reference to FIGS. 4A, 4B, and 4C.

[0062] Figures 4A to 4C are cross-sectional views illustrating the doped semiconductor structure DPS and the single-unit pillar structure CPI according to embodiments of the present disclosure.

[0063] A portion of the gate stack GST is shown in Figures 4A to 4C, but the third conductive layer CL3 and the third insulating layer IL3 among the first conductive layer CL1, multiple second conductive layers CL2, third conductive layer CL3, first insulating layer IL1, multiple second insulating layers IL2, and third insulating layer IL3 shown in Figures 2A or 2B are not shown in Figures 4A to 4C. A portion of the cell pillar structure CPI is shown in Figures 4A to 4C.

[0064] Referring to Figures 4A to 4C, the unit pillar structure CPI can penetrate the gate stack GST to contact the doped semiconductor structure DPS. The channel layer CHL of the unit pillar structure CPI includes a contact surface CTS that contacts the doped semiconductor structure DPS.

[0065] The channel layer CHL may include two or more channel portions (e.g., CH1 and CH2) and a channel connection portion CHC connecting the channel portions. The channel connection portion CHC may form a closed end of the channel layer CHL. The channel connection portion CHC may extend to connect the two or more channel portions (e.g., CH1 and CH2) to each other. In one embodiment, the first channel portion CH1 and the second channel portion CH2 may be spaced apart from each other in the XY plane by an isolation structure SS, and the channel connection portion CHC may extend from the first channel portion CH1 toward the second channel portion CH2.

[0066] A buffer layer BUL may be disposed between the channel layer CHL and the isolation structure SS. The buffer layer BUL may include insulating material. Buffer patterns (e.g., BU1 and BU2) are part of the buffer layer BUL and extend on the inner walls of two or more channel portions (e.g., CH1 and CH2), respectively. The buffer patterns may be connected by buffer connection patterns BUC. The buffer connection pattern BUC is another part of the buffer layer BUL and extends parallel to the channel connection portion CHC of the channel layer CHL.

[0067] The doped semiconductor structure (DPS) includes at least one doped semiconductor layer. The contact surface (CTS) of the channel layer (CHL) that contacts the doped semiconductor structure (DPS) can be formed on the sidewall of each channel portion or channel connection portion (CHC).

[0068] Referring to Figure 4A, according to one embodiment, the doped semiconductor structure DPS may include a first doped semiconductor layer L1, a second doped semiconductor layer L2, and a third doped semiconductor layer L3 stacked along the Z-axis direction. The unit pillar structure CPI may penetrate the third doped semiconductor layer L3 of the doped semiconductor structure DPS and extend into the first doped semiconductor layer L1. The contact surface CTS of the channel layer CHL may be formed between the second doped semiconductor layer L2 and the channel layer CHL of the doped semiconductor structure DPS.

[0069] Each of the first doped semiconductor layer L1, the second doped semiconductor layer L2, and the third doped semiconductor layer L3 may include an n-type impurity, a p-type impurity, or a mixture thereof. In one embodiment, each of the first doped semiconductor layer L1, the second doped semiconductor layer L2, and the third doped semiconductor layer L3 may include an n-type impurity as the majority carrier. However, embodiments of the present disclosure are not limited thereto. In one embodiment, the doped semiconductor structure DPS may include an n-type impurity region containing an n-type impurity as the majority carrier and a p-type impurity region containing a p-type impurity as the majority carrier. For example, the second doped semiconductor layer L2 may constitute an n-type impurity region, and any one or both of the first doped semiconductor layer L1 and the third doped semiconductor layer L3 may constitute a p-type impurity region.

[0070] Each of two or more memory portions (e.g., ML1 and ML2) is disposed between the gate layer stack GST and the channel layer CHL, and may extend between the third doped semiconductor layer L3 and the channel layer. A dummy memory portion DML may be disposed between the first doped semiconductor layer L1 and the channel layer CHL. A second doped semiconductor layer L2 extends between each of the two or more memory portions and the dummy memory portion DML. In one embodiment, the second doped semiconductor layer L2 extends between each of the first memory portion ML1 and the second memory portion ML2 and the dummy memory portion DML.

[0071] A second doped semiconductor layer L2 may surround the sidewalls of the channel layer CHL between the first doped semiconductor layer L1 and the third doped semiconductor layer L3. A contact surface CTS may be formed on the sidewalls of the channel layer CHL. The sidewalls of the channel layer CHL may be formed from a portion of each channel portion (e.g., CH1 or CH2).

[0072] Referring to Figures 4B and 4C, in one embodiment, the doped semiconductor structure DPS may include an n-type impurity region, or may include both an n-type doped region and a p-type impurity region. The contact surface CTS of the channel layer CHL may be formed between the n-type impurity region of the doped semiconductor structure DPS and the channel layer CHL.

[0073] Referring to FIG4B, in one embodiment, the contact surface CTS of the channel layer CHL may be formed on the channel connection portion CHC of the channel layer CHL. Each of two or more memory portions (e.g., ML1 and ML2) is disposed between the gate layer stack GST and the channel layer CHL, and may be spaced apart from each other such that the channel connection portion CHC is disposed between the two or more memory portions.

[0074] Referring to FIG4C, in one embodiment, the contact surface CTS of the channel layer CHL may be formed on the trench of the doped semiconductor structure DPS. Each of the channel layer CHL, the buffer layer BUL, and the isolation structure SS may extend into the trench of the doped semiconductor structure DPS. A portion of each of two or more channel portions (e.g., CH1 and CH2) of the channel layer CHL and the channel connection portion CHC are disposed in the trench of the doped semiconductor structure DPS. A portion of each of two or more channel portions (e.g., CH1 and CH2) disposed in the trench of the doped semiconductor structure DPS and the channel connection portion CHC may form the contact surface CTS of the channel layer CHL. Each of two or more memory portions (e.g., ML1 and ML2) is disposed between the gate layer stack GST and the channel layer CHL and does not extend into the trench of the doped semiconductor structure DPS.

[0075] Referring to Figures 4A to 4C, each of two or more memory portions (e.g., ML1 and ML2) and a dummy memory portion DML includes a tunnel insulating layer TI, a data storage layer DS, and a barrier insulating layer BI. The tunnel insulating layer TI extends on the outer wall of the channel layer CHL and may include an oxide such as silicon dioxide (SiO2). The barrier insulating layer BI extends on the outer wall of the tunnel insulating layer TI and may include an oxide such as silicon dioxide (SiO2), a high-k dielectric insulating material having a higher dielectric constant than silicon dioxide, etc. The high-k dielectric insulating material may include an aluminum oxide layer, a hafnium oxide layer, etc. The data storage layer DS is disposed between the tunnel insulating layer TI and the barrier insulating layer BI.

[0076] The data storage layer DS of each of two or more memory portions (e.g., ML1 and ML2) extends continuously in the stacking direction or is divided into data storage patterns spaced apart from each other in the stacking direction. In one embodiment, as shown in Figures 4A to 4C, the data storage layer DS may extend continuously in the stacking direction on the sidewalls of multiple insulating layers IL1 and IL2 and multiple conductive layers CL1 and CL2. Although not shown, in one embodiment, the data storage layer DS may be cut at the height set by the multiple insulating layers IL1 and IL2 to separate into multiple data storage patterns. The multiple data storage patterns may be respectively set at the height set by the multiple conductive layers CL1 and CL2. In other words, each data storage pattern may be a data storage layer DS disposed between a corresponding conductive layer and a tunnel insulating layer TI. The data storage layer DS may include a material layer storing data that has been altered by using Fowler-Nordheim tunneling. In one embodiment, the data storage layer DS may include a charge trapping insulating layer, a floating gate layer, or an insulating layer comprising conductive nanodots. The charge trapping insulating layer may include a silicon nitride layer. As described above, the data storage layer formed by the floating gate layer is divided into multiple data storage patterns. As shown in Figures 4A to 4C, the data storage layer formed by the charge-trapping insulating layer or the insulating layer containing conductive nanodots is divided into multiple data storage patterns, or extends continuously in the stacking direction as in the data storage layer DS.

[0077] Considering the process of dividing the channel layer CHL into two or more channel sections, the cross-section of the unit column structure CPI, cut along a direction parallel to the XY plane, can be designed in various ways. The cross-section of the unit column structure CPI will be described below with reference to Figures 5A, 5B, 6A, and 6B.

[0078] Figures 5A, 5B, 6A, and 6B are plan views showing cross-sections of a unit column structure according to an embodiment of the present disclosure.

[0079] Figures 5A, 5B, 6A, and 6B show cross-sections of the unit column structure CPI at the height of the second conductive layer CL2, which serves as the word line. In the following description, the cross-section of the unit column structure CPI will be referenced to a plurality of first axes A1 and a plurality of second axes A2. The plurality of first axes A1 and the plurality of second axes A2 extend radially from the center point P of the unit column structure CPI in the XY plane.

[0080] Referring to Figures 5A, 5B, 6A, and 6B, the outer surface ES of the unit column structure CPI is spaced apart from the center point P. Multiple first axes A1 and multiple second axes A2 extend from the center point P towards the outer surface ES of the unit column structure CPI. The multiple first axes A1 and multiple second axes A2 are arranged alternately in a clockwise direction. Each of the multiple conductive layers CL1, CL2, and CL3 shown in Figure 2A or 2B extends in the XY plane to surround the outer surface of the unit column structure CPI.

[0081] The outer surface ES of the unit column structure CPI may include multiple protrusions P1. The multiple protrusions P1 intersect with multiple first axes A1 respectively.

[0082] The columnar unit structure CPI includes multiple channel portions (e.g., CH1, CH2, and CH3) corresponding to multiple protrusions P1. Each of the multiple channel portions intersects with multiple first axes A1. Each of the channel portions CH1, CH2, and CH3 extends clockwise and counterclockwise from a vertex V intersecting the corresponding first axis A1. In one embodiment, each channel portion CH1, CH2, or CH3 has a radius of curvature R or R′ formed between the vertex V and the center point P, and is bendable.

[0083] In the XY plane, the end E of each channel portion CH1, CH2, or CH3 is located at a first distance D1 or D1′ from the vertex V along the extension direction of the first axis A1. In one embodiment, the first distance D1 or D1′ can be controlled within 30% or more of the radius of curvature R or R′, such that channel currents formed in the channel portions CH1, CH2, or CH3 can be ensured during operation of the semiconductor memory device. In one embodiment, the first distance D1 or D1′ can be controlled within 80% or less of the radius of curvature R or R′ to suppress interference faults between multiple channel portions (e.g., CH1, CH2, and CH3).

[0084] The isolation structure SS is positioned between multiple channel sections CH1, CH2 or CH3 and extends toward the center point P.

[0085] The cell pillar structure CPI includes multiple memory portions (e.g., ML1, ML2, and ML3) corresponding to multiple protrusions P1. Each memory portion ML1, ML2, or ML3 is disposed between a conductive layer (e.g., CL2) of the gate array and a corresponding channel portion. The tunnel insulating layer TI, data storage layer DS, and barrier insulating layer BI of each of the memory portions ML1, ML2, and ML3 may extend on the outer surface ES of the cell pillar structure CPI. Some of the tunnel insulating layer TI, data storage layer DS, and barrier insulating layer BI may be penetrated by an isolation structure SS. In one embodiment, the isolation structure SS may extend from a center point P along multiple second axes A2 to penetrate the tunnel insulating layer TI and data storage layer DS, and the barrier insulating layer BI may be continuous in the XY plane on the outer surface ES of the cell pillar structure CPI without being penetrated by the isolation structure SS to be hollow. However, embodiments of the present disclosure are not limited thereto. Although not shown, in one embodiment, the isolation structure SS may penetrate the barrier insulating layer BI, and the barrier insulating layer BI may be divided into multiple portions in the XY plane. A barrier insulating layer BI is disposed between the conductive layer (e.g., CL2) of the gate array and each of the channel portions CH1, CH2, and CH3. A data storage layer DS is disposed between the barrier insulating layer BI and each of the channel portions CH1, CH2, or CH3. A tunnel insulating layer TI is disposed between the data storage layer DS and each of the channel portions CH1, CH2, and CH3.

[0086] The unit column structure CPI includes multiple buffer patterns (e.g., BU1, BU2, and BU3) corresponding to multiple protrusions P1. Each of the buffer patterns BU1, BU2, and BU3 is disposed between the inner wall IW of the corresponding channel portion and the isolation structure SS. The inner wall IW faces the center point P.

[0087] The multiple protrusions P1 of the unit column structure CPI can vary according to the cross-sectional shape of the unit column structure CPI.

[0088] Referring to Figures 5A and 5B, in one embodiment, the unit column structure CPI can have a substantially elliptical shape in the XY plane. Two first axes A1 facing opposite directions are aligned on the major axis of the ellipse defined by the unit column structure CPI, and two second axes A2 facing opposite directions are aligned on the minor axis of the ellipse. The outer surface ES of the unit column structure CPI is located at a second distance D2 from the center point P along the extension direction of the first axis A1, and at a third distance D3 from the center point P along the extension direction of the second axis A2, which is smaller than the second distance D2.

[0089] Referring to Figures 6A and 6B, in one embodiment, the outer surface ES of the unit column structure CPI may include a plurality of recesses P2. The plurality of recesses P2 intersect a plurality of second axes A2. The outer surface ES of the unit column structure CPI is located at a second distance D2′ from the center point P along the extension direction of the first axis A1, and at a third distance D3′ from the center point P along the extension direction of the second axis A2, which is smaller than the second distance D2′.

[0090] The plurality of protrusions P1 can be three or more protrusions, and the plurality of recesses P2 can also be three or more recesses. In one embodiment, the outer surface ES of the unit column structure CPI can include three protrusions P1 and three recesses P2, such that the outer surface ES can have a clover shape.

[0091] Referring to Figures 5B and 6B, the unit column structure CPI may further include multiple barrier patterns (e.g., BP1, BP2, and BP3) corresponding to multiple protrusions P1. Each of the barrier patterns BP1, BP2, and BP3 is disposed between the corresponding buffer pattern BU1, BU2, or BU3 and the isolation structure SS.

[0092] Each of the barrier patterns BP1, BP2, and BP3 may include a seed barrier pattern B1 and a growth barrier pattern B2. The seed barrier pattern B1 is disposed between the corresponding buffer pattern BU1, BU2, or BU3 and the isolation structure SS, and the growth barrier pattern B2 is disposed between the seed barrier pattern B1 and the isolation structure SS.

[0093] The thickness of each of the seed barrier pattern B1 and the growth barrier pattern B2 is a dimension along the extension direction of the corresponding first axis A1. The thickness of the seed barrier pattern B1 can decrease as it approaches the end E of the corresponding channel portion. The growth barrier pattern B2 has greater thickness uniformity than the seed barrier pattern B1. Thickness uniformity increases as the difference between the layer thicknesses measured along the first axis A1 at different locations along the second axis A2 decreases.

[0094] To increase thickness uniformity, the growth barrier pattern B2 can be formed by region-selective atomic layer deposition (AS-ALD), selective epitaxial growth (SEG), or selective polysilicon growth (SPG).

[0095] Various methods of manufacturing a semiconductor memory device according to embodiments of the present disclosure are described below.

[0096] Figures 7A and 7B are cross-sectional and plan views illustrating a laminate, holes, and layers disposed in the holes according to an embodiment of the present disclosure. Figure 7B is a plan view of the laminate 100 shown in Figure 7A taken along line II'.

[0097] Referring to Figures 7A and 7B, a laminate 100 is formed on a lower structure (not shown). The laminate 100 includes a plurality of first material layers 101 and a plurality of second material layers 103.

[0098] Although not shown, in one embodiment, the lower structure may include a semiconductor substrate SUB as shown in FIG. 2A, a peripheral circuit structure PCS as shown in FIG. 2A, and a doped semiconductor structure DPS as shown in FIG. 2A. In one embodiment, the lower structure may include the semiconductor substrate SUB as shown in FIG. 2A, the peripheral circuit structure PCS as shown in FIG. 2A, and a preliminary semiconductor structure. The preliminary semiconductor structure may include a first doped semiconductor layer L1 as shown in FIG. 4A, a third doped semiconductor layer L3 as shown in FIG. 4A, and a sacrificial structure disposed between the first doped semiconductor layer L1 and the third doped semiconductor layer L3. In subsequent processes, the sacrificial structure may be replaced by a second doped semiconductor layer L2 as shown in FIG. 4A. In one embodiment, the lower structure may be a sacrificial substrate including a silicon wafer, etc.

[0099] Each of a plurality of first material layers 101 and a plurality of second material layers 103 extends in an XY plane. The plurality of first material layers 101 and the plurality of second material layers 103 are arranged alternately in a stacking direction (e.g., the Z-axis direction) intersecting the XY plane. The plurality of first material layers 101 may include insulating materials such as silicon oxide layers and silicon oxide nitride layers. The plurality of second material layers 103 may include conductive materials, or may include sacrificial insulating materials having etch selectivity relative to the plurality of first material layers 101. In one embodiment, the sacrificial insulating material may include a silicon nitride layer. Hereinafter, a method of manufacturing a semiconductor memory device will be described based on an embodiment in which the plurality of first material layers 101 include insulating materials and the plurality of second material layers 103 include sacrificial insulating materials, but embodiments of this disclosure are not limited thereto.

[0100] Subsequently, holes 111 extending along the stacking direction are formed to penetrate multiple first material layers 101 and multiple second material layers 103. The process of forming holes 111 includes a process of forming a mask pattern (not shown) using a photolithography process and a process of using the mask pattern as an etching barrier to etch the stack 110.

[0101] Hole 111 has a first inner wall 111IW. The shape of the cross-section of hole 111 is defined by the first inner wall 111IW in the XY plane. In the XY plane, the first inner wall 111IW is spaced apart from the center point P of hole 111 and intersects with a plurality of first axes A1 and a plurality of second axes A2. The plurality of first axes A1 and the plurality of second axes A2 extend radially from the center point P and are arranged alternately in a clockwise direction. In the XY plane, the first inner wall 111IW includes a plurality of protrusions CV that intersect the plurality of first axes A1 respectively.

[0102] In one embodiment, the sidewalls of the laminate 100 adjacent to the hole 111 in the XY plane can be formed in a generally elliptical shape. Two first axes A1 facing opposite directions are aligned on the major axis of the ellipse defined by the hole 111, and two second axes A2 facing opposite directions are arranged on the minor axis of the same ellipse. Therefore, the distance d1 between the center point P and the intersection point 111IP1 between the center point P and the first inner wall 111IW of the hole 111 and each of the first axes A1 is greater than the distance d2 between the center point P and the intersection point 111IP2 between the center point P and the first inner wall 111IW of the hole 111 and each of the second axes A2.

[0103] Subsequently, a memory layer 120, a channel layer 127, a buffer oxide layer 133, a buffer nitride layer 135, and a seed barrier layer 137 can be sequentially formed in the hole 111. Each of the memory layer 120, the channel layer 127, the buffer oxide layer 133, the buffer nitride layer 135, and the seed barrier layer 137 can extend on the first inner wall 111IW of the hole 111.

[0104] The memory layer 120 may include a barrier insulating layer 121, a data storage layer 123, and a tunnel insulating layer 125 extending on the first inner wall 111IW of the via 111. The barrier insulating layer 121 may include one or both of silicon dioxide and a high-k dielectric insulating material having a higher dielectric constant than silicon dioxide. The data storage layer 123 may include a charge-trapping insulating layer such as a silicon nitride layer. The tunnel insulating layer 125 may include silicon dioxide or the like.

[0105] A channel layer 127 is formed on the surface of the tunnel insulation layer 125. The channel layer 127 may comprise silicon (Si), germanium (Ge), or a mixture thereof. The channel layer 127 has a second inner wall 127IW facing the center point P.

[0106] Each of the buffer oxide layer 133, the buffer nitride layer 135, and the seed barrier layer 137 extends on the second inner wall 127IW of the channel layer 127. The buffer oxide layer 133 has etch selectivity relative to the data storage layer 123. The buffer nitride layer 135 extends on the surface of the buffer oxide layer 133. The buffer nitride layer 135 has etch selectivity relative to the tunnel insulating layer 125.

[0107] A seed barrier layer 137 extends on the surface of a buffer nitride layer 135. The seed barrier layer 137 may have etch selectivity relative to the buffer nitride layer 135 and the buffer oxide layer 133. In one embodiment, the seed barrier layer 137 may comprise silicon.

[0108] When depositing the seed barrier layer 137, the deposition thickness is controlled to be greater in the extension direction of the first axis A1 than in the extension direction of the second axis A2 by using the cross-sectional shape of the first inner wall 111IW of the aperture 111. In one embodiment, the central region of the aperture 111 opened by the buffer nitride layer 135 may have an elliptical shape along the surface of the buffer nitride layer 135 in the XY plane. The seed barrier layer 137 may be formed to have a greater thickness in the direction of the first axis A1 than the channel layer 127, because this causes a difference in deposition thickness along the major and minor axes of the ellipse.

[0109] Figures 8A and 8B are plan views illustrating seed barrier patterns according to embodiments of the present disclosure.

[0110] Referring to Figure 8A, as shown in Figure 7B, a portion of the seed barrier layer 137 is oxidized through holes 111 to form seed oxide regions 137O. The oxidation process is controlled such that the seed oxide regions 137O can contact the portion of the buffer nitride layer 135 that intersects with the second axis A2, and are spaced apart from another portion of the buffer nitride layer 135 that intersects with the first axis A1. As shown in Figure 7B, the seed barrier layer 137 is divided into multiple seed barrier patterns 137P by the seed oxide regions 137O in the holes 111.

[0111] Referring to Figure 8B, the seed oxide region 137O shown in Figure 8A is selectively removed. Multiple seed barrier patterns 137P intersect with multiple first axes A1 and are arranged clockwise alternately with multiple second axes A2.

[0112] Figures 9A to 9F are plan views illustrating the growth barrier pattern, buffer pattern, channel portion, and memory portion according to embodiments of the present disclosure.

[0113] Referring to FIG9A, multiple growth barrier patterns 139P selectively grow from multiple third inner walls 137IW of multiple seed barrier patterns 137P toward the center point P. Multiple etch targets 127E of the channel layer 127 intersecting with multiple second axes A2 are opened between the multiple growth barrier patterns 139P.

[0114] In one embodiment, a growth barrier pattern 139P comprising silicon can be selectively grown from a seed barrier pattern 137P comprising silicon using an SPG method. The growth barrier pattern 139P grown using the SPG method has greater thickness uniformity than a growth barrier pattern 139P formed by a deposition method. The growth barrier pattern 139P grown using the SPG method can compensate for the thickness of the seed barrier pattern 137P in the direction of the first axis A1, and the growth thickness can be controlled to be spaced apart from the second axis A2. The area of ​​overlap between the etch target 127E of the channel layer 127 and the second axis A2 can be controlled according to the growth thickness of the growth barrier pattern 139P.

[0115] Referring to FIG9B, the buffer nitride layer 135 can be divided into multiple primary buffer patterns 135P by removing multiple regions of the buffer nitride layer 135 exposed between the multiple growth barrier patterns 139P shown in FIG9A. Each primary buffer pattern 135P is protected by its corresponding seed barrier pattern 137P and growth barrier pattern 139P.

[0116] Referring to Figure 9C, multiple seed barrier patterns 137P and multiple growth barrier patterns 139P, as shown in Figure 9B, are selectively removed. As a result, multiple primary buffer patterns 135P can be exposed.

[0117] Referring to FIG9D, the buffer oxide layer 133 shown in FIG9C is sequentially removed, exposing multiple regions between the multiple primary buffer patterns 135P and the multiple etch targets 127E of the channel layer 127. Therefore, the buffer oxide layer 133 shown in FIG9C can be divided into multiple secondary buffer patterns 133P. Furthermore, multiple openings OP are formed in the regions where the multiple etch targets 127E are removed as shown in FIG9C, and the channel layer 127 shown in FIG9C can be divided into multiple channel portions 127P through the multiple openings OP penetrating the channel layer.

[0118] Referring to FIG9E, multiple regions of the tunnel insulation layer 125 shown in FIG9D are removed via multiple openings OP, thus dividing the tunnel insulation layer 125 shown in FIG9D into multiple portions 125P. Multiple secondary buffer patterns 133P are protected by multiple primary buffer patterns 135P.

[0119] Referring to FIG9F, multiple regions of the data storage layer 123 shown in FIG9E are removed via multiple openings OP, and the data storage layer 123 shown in FIG9E can be divided into multiple parts 123P. The multiple primary buffer patterns 135P shown in FIG9E and the multiple regions of the data storage layer 123 shown in FIG9E can be removed together.

[0120] Subsequently, an isolation structure 141 can be formed by filling the openings OP and holes 111 as shown in FIG9E with insulating material. The isolation structure 141 extends in the space between multiple portions 125P of the tunnel insulating layer and between multiple portions 123P of the data storage layer. Multiple memory portions 120P corresponding to multiple channel portions 127P can be separated by the isolation structure 141. Each of the memory portions 120P may include a portion 125P of the tunnel insulating layer, a portion 123P of the data storage layer, and a barrier insulating layer 121.

[0121] Figures 10A and 10B are cross-sectional and plan views illustrating a gate stack 150 according to an embodiment of the present disclosure. Figure 10B is a plan view of the gate stack 150 shown in Figure 10A taken along line II'.

[0122] Referring to Figures 10A and 10B, a slit 151 is formed through the stack including the first material layer 101 and the second material layer 103 shown in Figure 7A. Subsequently, the second material layer 103 can be replaced with a conductive material through the slit 151. Therefore, a gate stack 150 comprising a plurality of first material layers 101 and a plurality of conductive layers 153 arranged alternately along the stacking direction (e.g., the Z-axis direction) can be formed. However, embodiments of the present disclosure are not limited thereto. In one embodiment, when the second material layer 103 shown in Figure 7A comprises a conductive material, the second material layer 103 can constitute the gate stack 150.

[0123] In the XY plane, each conductive layer 153 may extend to surround a plurality of memory portions 120P separated by isolation structure 141 and a plurality of channel portions 127P separated by isolation structure 141.

[0124] Figure 11 is a plan view showing a seed barrier pattern according to an embodiment of the present disclosure.

[0125] Referring to FIG11, a plurality of seed barrier patterns 137P are formed in holes 111 that pass through the plurality of first material layers 101 and the plurality of second material layers 103 shown in FIGS. 7A and 7B. The holes 111 penetrate the plurality of first material layers 101 and the plurality of second material layers 103 of the laminate 100 shown in FIGS. 7A and 7B, and have the same cross-sectional shape in the XY plane as the cross-sectional shape described with reference to FIGS. 7A and 7B. In one embodiment, the holes 111 may have an elliptical cross-section.

[0126] Before forming multiple seed barrier patterns 137P, as described with reference to Figures 7A and 7B, a barrier insulating layer 121, a data storage layer 123, a tunnel insulating layer 125, a channel layer 127, a buffer oxide layer 133, a buffer nitride layer 135, and a seed barrier layer 137 of the memory layer 120 can be formed in the via 111. The multiple seed barrier patterns 137P are some regions of the seed barrier layer 137 as shown in Figures 7A and 7B. The reference numeral "137IW" in Figure 11 indicates the inner wall of the seed barrier layer 137 as shown in Figures 7A and 7B. The seed barrier layer 137 as shown in Figures 7A and 7B can be etched from the inner wall 137IW of the seed barrier layer 137 via the via 111 using a wet etching process or the like. Through the etching process, the seed barrier layer 137 as shown in Figures 7A and 7B can be divided into multiple seed barrier patterns 137P.

[0127] After forming multiple seed barrier patterns 137P, the process described with reference to Figures 9A to 9F, as well as Figures 10A and 10B, can be performed.

[0128] Figures 12A and 12B are cross-sectional and plan views illustrating a laminate, holes, and layers disposed in the holes according to an embodiment of the present disclosure. Figure 12B is a plan view of the laminate 100 shown in Figure 12A taken along line II′.

[0129] Referring to Figures 12A and 12B, and as described with reference to Figures 7A and 7B, a laminate 100 can be formed by alternately stacking a plurality of first material layers 101 and a plurality of second material layers 103 on a lower structure (not shown). Subsequently, as described with reference to Figures 7A and 7B, a hole 111 extending in the stacking direction (e.g., the Z-axis direction) penetrates the plurality of first material layers 101 and the plurality of second material layers 103. The hole 111 has the same cross-sectional shape in the XY plane as the cross-sectional shape described with reference to Figures 7A and 7B. In one embodiment, the hole 111 may have an elliptical cross-section.

[0130] Subsequently, as described with reference to Figures 7A and 7B, the barrier insulating layer 121, data storage layer 123, tunnel insulating layer 125, channel layer 127, and buffer oxide layer 133 of the memory layer 120 can be sequentially formed in the hole 111.

[0131] Subsequently, a seed barrier layer can be formed on the surface of the buffer oxide layer 133. The seed barrier layer can be etch-selective relative to the buffer oxide layer 133. In one embodiment, the seed barrier layer may comprise silicon. As described with reference to Figures 7A and 7B, the thickness of the seed barrier layer on the first axis A1 may be greater than the thickness on the second axis A2.

[0132] Then, the seed barrier layer is divided into multiple seed barrier patterns 137P using the process described with reference to Figures 8A and 8B or the process described with reference to Figure 11. Subsequently, as described with reference to Figure 9A, multiple growth barrier patterns 139P can be grown from multiple inner walls of the multiple seed barrier patterns 137P. Multiple regions of the buffer oxide layer 133 are exposed between the multiple growth barrier patterns 139P.

[0133] Figures 13A to 13C are plan views illustrating the channel portion, memory portion, and conductive layer according to embodiments of the present disclosure.

[0134] Referring to Figure 13A, by removing the exposed areas of the buffer oxide layer 133 shown in Figure 12B, the buffer oxide layer 133 shown in Figure 12B can be divided into multiple buffer patterns 133P. Each buffer pattern 133P is protected by a seed barrier pattern 137P and a growth barrier pattern 139P.

[0135] Subsequently, multiple etch targets of the channel layer 127, as shown in FIG12B, are removed. These multiple etch targets are portions of the channel layer exposed between multiple buffer patterns 133P. When the growth barrier pattern 139P comprises silicon, a portion of the growth barrier pattern 139P can be removed while removing the multiple etch targets of the channel layer.

[0136] Multiple openings OP are formed in the regions where multiple etch targets are removed in the channel layer, and the channel layer 127 shown in FIG12B can be divided into multiple channel portions 127P through the multiple openings OP that penetrate the channel layer.

[0137] Referring to FIG13B, multiple regions of the tunnel insulating layer 125 shown in FIG13A and multiple regions of the data storage layer 123 shown in FIG13A are removed via multiple openings OP. Therefore, the memory layer 120 shown in FIG13A can be divided into multiple memory portions 120P. The multiple memory portions 120P include multiple portions 125P of the tunnel insulating layer and multiple portions 123P of the data storage layer. The barrier insulating layer 121 can be continuous in the XY plane to surround the multiple portions 123P of the data storage layer.

[0138] Referring to FIG13C, the isolation structure 141 can be formed by filling the opening OP and hole 111 shown in FIG13B with insulating material. The isolation structure 141 extends in the space between the multiple portions 125P of the tunnel insulation layer and the space between the multiple portions 123P of the data storage layer.

[0139] Subsequently, by performing the process described with reference to Figures 10A and 10B, a gate stack including a conductive layer 153 can be formed.

[0140] Figures 14A and 14B are cross-sectional and plan views illustrating a laminate, holes, and layers disposed in the holes according to an embodiment of the present disclosure. Figure 14B is a plan view of the laminate 100 shown in Figure 14A taken along line II'.

[0141] Referring to Figures 14A and 14B, and as described with reference to Figures 7A and 7B, a laminate 100 can be formed by alternately stacking a plurality of first material layers 101 and a plurality of second material layers 103 on a lower structure (not shown). Subsequently, as described with reference to Figures 7A and 7B, a hole 111 extending in the stacking direction (e.g., the Z-axis direction) penetrates the plurality of first material layers 101 and the plurality of second material layers 103. The hole 111 has the same cross-sectional shape in the XY plane as the cross-sectional shape described with reference to Figures 7A and 7B. In one embodiment, the hole 111 may have an elliptical cross-section.

[0142] Subsequently, as described with reference to Figures 7A and 7B, the barrier insulating layer 121, data storage layer 123, tunnel insulating layer 125, channel layer 127, and buffer oxide layer 133 of the memory layer 120 can be sequentially formed in the hole 111.

[0143] Subsequently, a seed barrier layer can be formed on the surface of the buffer oxide layer 133. The seed barrier layer can be etch-selective relative to the buffer oxide layer 133. In one embodiment, the seed barrier layer may include silicon nitride. As described with reference to Figures 7A and 7B, the thickness of the seed barrier layer on the first axis A1 can be greater than the thickness on the second axis A2.

[0144] Then, the seed barrier layer is divided into multiple seed barrier patterns 237P using the process described with reference to Figures 8A and 8B or the process described with reference to Figure 11. Subsequently, multiple growth barrier patterns 239P are selectively grown from multiple inner walls of the multiple seed barrier patterns 237P toward the center point P of the hole 111.

[0145] In one embodiment, a growth barrier pattern 239P comprising silicon carbide (SiOC) can be selectively grown from a seed barrier pattern 237P comprising silicon nitride using an AS-ALD method. The growth barrier pattern 239P grown by the AS-ALD method exhibits greater thickness uniformity than a growth barrier pattern 239P formed by a deposition method. The growth barrier pattern 239P grown using the AS-ALD method can compensate for the thickness of the seed barrier pattern 237P along the first axis A1, and the growth thickness of the growth barrier pattern 239P can be controlled such that the growth barrier pattern 239P can be spaced apart from the second axis A2.

[0146] Multiple etch targets 127E intersecting with multiple second axes A2 in the channel layer 127 are open between multiple growth barrier patterns 239P. The area of ​​the etch targets 127E can be controlled according to the growth thickness of the growth barrier patterns 239P.

[0147] Figures 15A to 15C are plan views showing the channel portions and openings according to embodiments of the present disclosure.

[0148] Referring to FIG15A, by removing multiple exposed areas of the buffer oxide layer 133 shown in FIG14B, the buffer oxide layer 133 shown in FIG14B can be divided into multiple buffer patterns 133P. Each buffer pattern 133P is protected by a seed barrier pattern 237P and a growth barrier pattern 239P corresponding to that buffer pattern 133P.

[0149] Subsequently, multiple etch targets 127E of the channel layer 127 as shown in FIG14B are removed. Multiple first openings OP1 are formed in the regions where the multiple etch targets of the channel layer are removed, and the channel layer 127 as shown in FIG14B can be divided into multiple channel portions 127P through the multiple first openings OP1 penetrating the channel layer. Each buffer pattern 133P is protected by a corresponding seed barrier pattern 237P and a growth barrier pattern 239P.

[0150] Referring to Figure 15B, multiple growth barrier patterns 239P shown in Figure 15A can be selectively removed. As a result, multiple seed barrier patterns 237P can be opened.

[0151] Referring to FIG15C, a plurality of second openings OP2 can be formed by etching the tunnel insulating layer 125 as shown in FIG15B through a plurality of first openings OP1. The plurality of second openings OP2 can penetrate the tunnel insulating layer 125 as shown in FIG15B and divide the tunnel insulating layer into a plurality of portions 125P. When the plurality of second openings OP2 are formed, a plurality of buffer patterns 133P are protected by a plurality of seed barrier patterns 237P.

[0152] Subsequently, by etching the data storage layer 123 through multiple second openings OP2, the data storage layer 123 can be divided into multiple portions 123P of the data storage layer as shown in FIG9F. During the etching of the data storage layer 123, multiple seed barrier patterns 237P can be removed to expose the buffer pattern 133P as shown in FIG9F.

[0153] Subsequently, the process described with reference to Figures 10A and 10B can be performed.

[0154] Figure 16 is a plan view showing a laminate, holes, and layers disposed in the holes according to an embodiment of the present disclosure.

[0155] Referring to FIG16, the laminate 100 may be penetrated by the hole 211. The laminate 100 may include a plurality of first material layers 101 and a plurality of second material layers 103 as shown in FIG7A and FIG7B.

[0156] The cross-sectional shape of the hole 211 is formed in the XY plane on the inner wall 211IW of the hole 211. In the XY plane, the inner wall 211IW is spaced apart from the center point P of the hole 211 and intersects with a plurality of first axes A1 and a plurality of second axes A2. The plurality of first axes A1 and the plurality of second axes A2 extend radially from the center point P and are arranged alternately in a clockwise direction.

[0157] In the XY plane, the inner wall 211IW includes a plurality of protrusions and a plurality of recesses. The protrusions intersect a plurality of first axes A1. The recesses intersect a plurality of second axes A2. The vertex of each protrusion is located at a first intersection point 211IP1 between the first axis A1 and the inner wall 211IW, and the inner wall 211IW extends to curve clockwise and counterclockwise from the first intersection point 211IP1. Each recess is located at a second intersection point 211IP2 between the second axis A2 and the inner wall 211IW. The distance d1′ between the center point P and the first intersection point 211IP1 is greater than the distance d2′ between the center point P and the second intersection point 211IP2. In one embodiment, the hole 211 in the XY plane may have a generally clover-like shape.

[0158] Subsequently, subsequent processes of the above-described embodiments can be performed, such as forming a barrier insulating layer 121, a data storage layer 123, and a tunnel insulating layer 125 of the memory layer 120 in the hole 211, and forming a channel layer 127 on the inner wall of the memory layer 120.

[0159] Figure 17 is a block diagram illustrating an electronic system 1000 according to an embodiment of the present disclosure.

[0160] Referring to FIG17, electronic system 1000 may include a computing system, a medical device, a communication device, a wearable device, or a memory system. Electronic system 1000 may include a host 1100 and a storage device 1200.

[0161] Host 1100 can store data in storage device 1200, or can read stored data from storage device 1200 based on an interface. The interface may include one or more of the following: Double Data Rate (DDR) interface, Universal Serial Bus (USB) interface, Multimedia Card (MMC) interface, Embedded MMC (eMMC) interface, Peripheral Component Interconnect (PCI) interface, PCI Express (PCI-E) interface, Advanced Technology Accessory (ATA) interface, Serial ATA interface, Parallel ATA interface, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Device Interface (IDE), FireWire interface, Universal Flash Memory (UFS) interface, and Non-Volatile Memory Express (NVMe) interface.

[0162] Storage device 1200 may include memory controller 1210 and semiconductor memory device 1220. According to one embodiment, storage device 1200 may be a solid-state drive (SSD), a universal serial bus (USB) memory, etc.

[0163] The memory controller 1210 can store data in the semiconductor memory device 1220 in response to control by the host 1100, or can read data stored in the semiconductor memory device 1220.

[0164] Semiconductor memory device 1220 may include a single memory chip or multiple memory chips. Semiconductor memory device 1220 may store data or output stored data in response to control by memory controller 1210.

[0165] Semiconductor memory device 1220 may be a non-volatile memory device. Semiconductor memory device 1220 may include a cell pillar structure in which the outer surface is surrounded by a conductive layer. The outer surface of the cell pillar structure may be arranged at different distances from the center point on a plurality of first axes and a plurality of second axes extending radially from the center point. The cell pillar structure includes a plurality of channel portions and an isolation structure extending from the center point between the plurality of channel portions.

[0166] According to one embodiment of this disclosure, the channel layer can extend on the inner wall of a hole formed in the laminate, and the channel layer can be divided into multiple channel portions by partially etching the channel layer. Therefore, in one embodiment, because multiple channel portions of multiple memory cell strings are disposed in a single hole, the integration level of the memory cell strings can be improved.

[0167] According to one embodiment of this disclosure, the area of ​​the etched region of the channel layer can be controlled by a growth barrier pattern grown from a seed barrier pattern. Therefore, in one embodiment, because the partitioning of each of the plurality of channel portions can be performed to ensure channel current, the operational reliability of the memory cell string can be improved.

[0168] Cross-reference to related applications

[0169] This application claims priority to Korean Patent Application No. 10-2024-0152997, filed with the Korean Intellectual Property Office on October 31, 2024, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A unit column structure includes an outer surface intersecting with a plurality of first axes and a plurality of second axes, the plurality of first axes and the plurality of second axes extending radially from a center point in a first plane, the plurality of first axes and the plurality of second axes being arranged alternately in a clockwise direction, the outer surface of the unit column structure being spaced apart from the center point, and the unit column structure extending along a stacking direction intersecting with the first plane; The unit pillar structure includes: a plurality of conductive layers spaced apart from each other in the stacking direction and surrounding the outer surface of the unit pillar structure; a plurality of channel portions intersecting a plurality of first axes, each of the channel portions including a radius of curvature defined between a center point and a vertex intersecting a corresponding first axis; a plurality of memory portions disposed between the conductive layers and the channel portions; and an isolation structure disposed between the channel portions and extending toward the center point, wherein each of the channel portions includes an end located at a first distance from the vertex along the extension direction of the corresponding first axis, the first distance being 30% to 80% relative to the radius of curvature.

2. The semiconductor memory device according to claim 1, wherein, The outer surface of the unit column structure includes a plurality of protrusions that intersect with the plurality of first axes respectively.

3. The semiconductor memory device according to claim 1, wherein, In the first plane, the unit column structure has a substantially elliptical shape.

4. The semiconductor memory device according to claim 1, wherein, The outer surface of the unit column structure includes a plurality of recesses that intersect with the plurality of second axes.

5. The semiconductor memory device according to claim 1, wherein, The outer surface of the unit column structure is disposed at a second distance from the center point along the extension direction of each of the plurality of first axes, and at a third distance from the center point along the extension direction of the plurality of second axes, wherein the third distance is less than the second distance.

6. The semiconductor memory device of claim 1, further comprising a buffer pattern disposed between the inner wall of each of the plurality of channel portions facing the center point and the isolation structure.

7. The semiconductor memory device of claim 6, further comprising a barrier pattern disposed between the buffer pattern and the isolation structure.

8. The semiconductor memory device according to claim 7, wherein, The barrier pattern includes: a seed barrier pattern disposed between the buffer pattern and the isolation structure; and a growth barrier pattern disposed between the seed barrier pattern and the isolation structure.

9. The semiconductor memory device according to claim 1, wherein, Each of the plurality of memory portions includes: a barrier insulating layer disposed between a respective channel portion of the plurality of channel portions and each of the plurality of conductive layers; a data storage layer disposed between the barrier insulating layer and the respective channel portion; and a tunnel insulating layer disposed between the data storage layer and the respective channel portion.

10. The semiconductor memory device according to claim 9, wherein, The isolation structure extends from the central point along the plurality of second axes to penetrate the data storage layer.

11. A method for manufacturing a semiconductor memory device, the method comprising the following steps: A laminate is formed comprising a plurality of material layers extending in a first plane and arranged along a stacking direction intersecting the first plane; a hole is formed by etching the laminate, the hole comprising a first inner wall intersecting a plurality of first axes and a plurality of second axes, the plurality of first axes and the plurality of second axes extending radially from a center point in the first plane and arranged alternately in a clockwise direction, the first inner wall being spaced apart from the center point; a channel layer is formed extending on the first inner wall and comprising a second inner wall facing the center point; a plurality of seed barrier patterns are formed extending on the second inner wall and arranged alternately with the plurality of second axes in a clockwise direction; a plurality of growth barrier patterns are selectively grown from a plurality of third inner walls of the plurality of seed barrier patterns toward the center point, thereby opening a plurality of etch targets of the channel layer intersecting the plurality of second axes; And to form multiple openings by removing the plurality of etched targets to penetrate the trench layer.

12. The method according to claim 11, wherein, The first inner wall includes a plurality of protrusions that intersect with the plurality of first axes respectively.

13. The method according to claim 11, wherein, In the first plane, the sidewalls of the laminate adjacent to the hole are substantially elliptical in shape.

14. The method according to claim 11, wherein, The first inner wall includes a plurality of recesses that intersect the plurality of second axes respectively.

15. The method according to claim 11, wherein, The intersection of each of the plurality of first axes with the first inner wall is set to be further away from the center point than the intersection of each of the plurality of second axes with the first inner wall.

16. The method of claim 11, further comprising the following steps: Prior to forming the trench layer, a memory layer extending on the first inner wall is formed; and multiple regions of the memory layer are etched through the plurality of openings.

17. The method according to claim 11, wherein, Each of the plurality of seed barrier patterns and the plurality of growth barrier patterns comprises silicon.

18. The method of claim 11, further comprising the following steps before forming the plurality of seed barrier patterns: A buffer oxide layer is formed on the second inner wall; The method further includes the steps of forming a buffer nitride layer on the surface of the buffer oxide layer, and prior to forming the plurality of openings: removing a plurality of regions of the buffer nitride layer exposed between the plurality of growth barrier patterns to expose a plurality of regions of the buffer oxide layer; removing the plurality of growth barrier patterns and the plurality of seed barrier patterns; and removing the plurality of exposed regions of the buffer oxide layer.

19. The method according to claim 11, further comprising the following steps: Before forming the plurality of seed barrier patterns, a buffer oxide layer is formed on the second inner wall; Prior to forming the plurality of openings, the buffer oxide layer is removed from the plurality of areas exposed between the plurality of growth barrier patterns; And to form an isolation structure to fill the space between the plurality of growth barrier patterns and the plurality of openings.

20. The method of claim 11, further comprising the following steps: Before forming the plurality of seed barrier patterns, a buffer oxide layer is formed on the second inner wall; And prior to forming the plurality of openings, remove the plurality of regions of the buffer oxide layer exposed between the plurality of growth barrier patterns; And after forming the plurality of openings, the plurality of growth barrier patterns and the plurality of seed barrier patterns are removed.

21. The method according to claim 11, wherein, Each of the plurality of seed barrier patterns comprises silicon nitride, and wherein each of the plurality of growth barrier patterns comprises silicon carbide (SiOC).

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