Gate structure and manufacturing method thereof

Abstract

The invention relates to a gate structure and a manufacturing method thereof. A method includes forming an IL at first and second device regions to surround each semiconductor channel layer; forming an HK dielectric layer over the IL; forming an adjustment layer over the HK dielectric layer, the adjustment layer including an element for a device having a first conductivity; forming a dipole layer over the adjustment layer at the first and second device regions, where the adjustment layer and the dipole layer are sequentially formed in the processing chamber without breaking the vacuum, and the dipole layer includes an element suitable for a device having the first conductivity type; removing the dipole layer above the semiconductor channel layer at the second device region; subjecting the adjustment layer to a heat treatment at the first device region to drive elements from the adjustment layer into the HK dielectric layer; removing the dipole layer and the adjusting layer above the semiconductor channel layer in the first device region; and forming gate electrode layers at the first and second device regions to surround each semiconductor channel layer.

Description

Gate structure and its manufacturing method Technical Field

[0001] This disclosure relates to gate structures and methods for manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded several generations of ICs, each featuring smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) typically increases, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) decreases. This miniaturization process generally provides benefits through increased production efficiency and reduced associated costs. However, this miniaturization also increases the complexity of processing and manufacturing ICs.

[0003] Therefore, there is a need to improve the processing and manufacturing of ICs. Summary of the Invention

[0004] According to one aspect of this disclosure, a method for forming a semiconductor device structure is provided, comprising: forming an interface layer (IL) at a first device region and a second device region to surround each of a plurality of semiconductor channel layers; forming a high-k (HK) dielectric layer over the IL; forming an adjustment layer over the HK dielectric layer, the adjustment layer including elements suitable for a device having a first conductivity type; forming a dipole layer over the adjustment layer at the first device region and the second device region, wherein the adjustment layer and the dipole layer are formed sequentially in a processing chamber without breaking a vacuum, and the dipole layer includes elements suitable for a device having a first conductivity type; removing the dipole layer over a selected semiconductor channel layer at the second device region; subjecting the adjustment layer to a thermal treatment at the first device region such that elements from the adjustment layer are driven into the HK dielectric layer; removing the dipole layer and the adjustment layer over a selected semiconductor channel layer at the first device region; and forming a gate electrode layer at the first device region and the second device region to surround each semiconductor channel layer.

[0005] According to another aspect of this disclosure, a method for forming a semiconductor device structure is provided, comprising: forming a first dipole layer over high-k (HK) dielectric layers on a first channel layer and a second channel layer, respectively; forming a second dipole layer over the first dipole layer without vacuum disruption, the second dipole layer being chemically different from the first dipole layer; removing the second dipole layer over the second channel layer; subjecting the first and second dipole layers over the first channel layer to heat treatment to form an intermixed layer in the HK dielectric layer on the first channel layer; removing the first and second dipole layers over the first channel layer; and forming a gate electrode layer over the first and second channel layers.

[0006] According to another aspect of this disclosure, a semiconductor device structure is provided, comprising: a first semiconductor channel layer at a first device region; a second semiconductor channel layer at a second device region; a first gate dielectric layer disposed on the first semiconductor channel layer, the first gate dielectric layer being doped with a first element comprising a metal and a second element comprising nitrogen; a second gate dielectric layer disposed on the second semiconductor channel layer, wherein the second gate dielectric layer has a first thickness; gate electrode layers disposed on the first gate dielectric layer and the second gate dielectric layer respectively; and an intermixing layer disposed between the gate electrode layer and the first gate dielectric layer and in contact with the gate electrode layer and the first gate dielectric layer, wherein the intermixing layer comprises the first element and the second element, and the intermixing layer and the first gate dielectric layer have a second thickness substantially the same as the first thickness. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figures 1 to 5 are perspective views of various stages in the fabrication of a semiconductor device structure according to some embodiments.

[0009] Figures 6A, 6B, and 6C are cross-sectional side views of the semiconductor device structure taken along lines AA, BB, and CC of Figure 5, respectively.

[0010] Figures 7A to 12A and 23A are cross-sectional side views taken along cross section AA of Figure 5, showing various stages of manufacturing a semiconductor device structure according to some embodiments.

[0011] Figures 7B to 12B and 23B are cross-sectional side views taken along cross section BB of Figure 5, showing various stages of manufacturing a semiconductor device structure according to some embodiments.

[0012] Figures 7C to 12C and 23C are cross-sectional side views taken along cross section CC of Figure 5, showing various stages of manufacturing a semiconductor device structure according to some embodiments.

[0013] Figures 13 to 15 and 16 to 19 are enlarged views of the region of Figure 12B, which illustrate the various stages of manufacturing alternative gate structures for semiconductor device structures according to some embodiments.

[0014] The embodiment of Figure 15-1 shows that the adjustment layer includes a first layer and a second layer.

[0015] Figure 19-1 is an enlarged view of a portion of a semiconductor device structure according to some embodiments, showing an intermixed layer in a modified HK dielectric layer.

[0016] Figures 20 and 21 are enlarged views of the region in Figure 12B, illustrating the various stages of manufacturing the replacement gate structure of a semiconductor device structure according to some embodiments.

[0017] Figure 22 shows a partial enlarged view of the semiconductor device structure of Figure 21 according to some embodiments. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. To simplify this disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, this disclosure may repeat reference numerals and / or letters in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, spatially related terms (e.g., "below," "under," "lower," "above," "above," "top," "higher," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). In addition to the orientations depicted in the figures, these spatially related terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted similarly accordingly.

[0020] This disclosure generally relates to semiconductor devices, and more specifically to field-effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), gate-all-around (GAA) devices (e.g., horizontal gate-all-around (HGAA) FETs, vertical gate-all-around (VGAA) FETs), vertical FETs, forksheet FETs, or complementary FETs (CFETs). While embodiments of this disclosure are discussed with respect to GAA devices, implementations of some aspects of this disclosure can be used in other processes and / or other devices. Those skilled in the art will readily understand that other modifications may be made within the scope of this disclosure.

[0021] For GAA devices using a high-k metal gate (HKMG) scheme, the transistor channel layer is surrounded by various layers, such as an interface layer (IL), a high-k (HK) gate dielectric, and a metal gate layer. An additional layer can be placed between the metal gate layer and the high-k gate dielectric to adjust the threshold voltage (V) of the GAA device. th For example, a dipole layer can be placed between the metal gate layer and the high-k gate dielectric to change the flat-band voltage (V) of the gate structure in the GAA device. FB This shifts the threshold voltage. However, with scaling, device size and device footprint (i.e., the physical space required by the device) are becoming smaller, which reduces the space between transistor channel layers and affects V. th The adjustment capability leads to a decrease in the effective capacitance of the GAA device due to the increased capacitance equivalent thickness (CET) value. The CET value represents the effective electrical thickness of the gate dielectric layer in the transistor. Lower CET values ​​are desirable in advanced semiconductor devices because they allow for higher capacitance, improved control of the transistor channel layer, and better device performance without increasing leakage current. Various embodiments of this disclosure provide an improvement: using an adjustment layer (formed from metal nitride) and a cluster mask layer as a double p-dipole layer to control the V of the gate structure. FB Without the cost of CET.

[0022] Figures 1 through 23C illustrate exemplary processes for manufacturing a semiconductor device structure 100 according to embodiments of the present disclosure. It should be understood that additional operations may be provided before, during, and after the processes shown in Figures 1 through 23C, and some operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes is not limiting and is interchangeable.

[0023] Figures 1 through 5 are perspective views of various stages of fabricating a semiconductor device structure 100 (e.g., a nanoFET) according to some embodiments. As shown in Figure 1, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed over the front side of a substrate 101. The substrate 101 may be a semiconductor substrate, such as a bulk semiconductor. The substrate 101 may include a single-crystal semiconductor material, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one aspect, the insulating layer is an oxygen-containing layer. Other substrates may also be used, such as single-layer, multilayer, or gradient substrates.

[0024] The substrate 101 may include various regions that have been doped with impurities (e.g., dopants with P-type or N-type conductivity). Depending on the circuit design, the dopants may be, for example, boron for P-type field-effect transistors (PFETs) and phosphorus for N-type field-effect transistors (NFETs).

[0025] Semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanosheet channels in multi-gate devices such as nanosheet channel FETs. In some embodiments, semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, semiconductor layer stack 104 includes alternating first semiconductor layer 106 and second semiconductor layer 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be made of a first semiconductor material suitable for N-type nanoFETs (such as silicon, silicon carbide, etc.), and the second semiconductor layer 108 may be made of a second semiconductor material suitable for P-type nanoFETs (such as silicon germanium, etc.). In some examples, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. Alternatively, in some embodiments, either of the semiconductor layers 106, 108 may be or may include other materials such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof. Each layer of the semiconductor layer stack 104 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), or other suitable growth processes.

[0026] Due to the high etch selectivity between the first and second semiconductor materials, the second semiconductor material of the second semiconductor layer 108 can be removed without significantly removing the first semiconductor material of the first semiconductor layer 106, thereby allowing the first semiconductor layer 106 to be patterned in a later manufacturing stage to form nanosheets or (one or more) nanostructured channels of the semiconductor device structure 100. The term nanosheet or nanostructured channel is used herein to refer to any material portion having a nanometer-scale or even micrometer-scale size and an elongated shape, regardless of the cross-sectional shape of that portion. Thus, the term refers both to elongated material portions having circular and substantially circular cross-sections and to beam-shaped or strip-shaped material portions, such as those that are cylindrical or have a substantially rectangular cross-section. One or more nanosheet channels of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include nanosheet transistors. Nanosheet transistors may be referred to as nanowire transistors, gate-all-around (GAA) transistors, multi-bridge-channel (MBC) transistors, or any transistor having a gate electrode surrounding the channel. The use of a first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0027] Each first semiconductor layer 106 may have a thickness ranging from about 5 nm to about 30 nm. Each second semiconductor layer 108 may have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness ranging from about 2 nm to about 50 nm. As shown in FIG1, three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately, which is for illustrative purposes only and is not intended to limit the scope specifically recited in the claims. It will be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels of the semiconductor device structure 100. Although the semiconductor layer stack 104 is shown to include a second semiconductor layer 108 as the bottom layer, in some embodiments, the bottom layer of the semiconductor layer stack 104 may be a first semiconductor layer 106.

[0028] In Figure 2, fin structures 112 are formed from a semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a well portion 116 formed from a substrate 101. The fin structures 112 can be formed by patterning a hard mask layer (not shown) formed on the semiconductor layer stack 104 using one or more photolithography and etching processes. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process can include a dual-patterning process or a multi-patterning process. Typically, a dual-patterning process or a multi-patterning process combines a photolithography process and a self-aligned process, thereby allowing the spacing of the patterns to be created to be smaller, for example, than that achievable using a single direct photolithography process. As an example of a multi-patterning process, a sacrificial layer can be formed on the substrate, and the sacrificial layer can be patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structures 112. In any case, one or more etching processes form trenches 114 in the unprotected area, trenches 114 passing through the hard mask layer, through the semiconductor layer stack 104, and into the substrate 101, thereby leaving a plurality of extending fin structures 112. Trenches 114 extend in the X direction.

[0029] Figure 2 also illustrates a fin structure 112 with substantially vertical sidewalls, such that the widths of the fin structures 112 are substantially similar, and each first semiconductor layer 106 and each second semiconductor layer 108 in the fin structure 112 is rectangular. In some embodiments, the fin structure 112 may have tapered sidewalls, such that the width of each fin structure 112 increases continuously in the direction toward the substrate 101. In this case, each first semiconductor layer 106 and each second semiconductor layer 108 in the fin structure 112 may have different widths and be trapezoidal.

[0030] In Figure 3, after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. A planarization operation (e.g., chemical mechanical polishing (CMP) and / or etch-back) is then performed to expose the top of the fin structure 112. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorinated silicate glass (FSG), a low-k dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0031] Subsequently, the insulating material 118 is recessed to form the isolation region 120. After the recess, portions of the fin structure 112 (e.g., the semiconductor layer stack 104) can protrude between adjacent isolation regions 120. The isolation region 120 may have a flat (as shown), raised, recessed top surface, or a combination thereof. The recess in the insulating material 118 exposes a trench 114 between adjacent fin structures 112. The isolation region 120 can be formed using a suitable process (e.g., a dry etching process, a wet etching process, or a combination thereof). In one embodiment, diluted hydrofluoric acid (dHF) is used to form the isolation region 120, a solution that is more selective for the insulating material 118 than for the semiconductor layer stack 104. After the recess is completed, the top surface of the insulating material 118 may be flush with or below the surface of the second semiconductor layer 108 that contacts the well portion 116 formed by the substrate 101.

[0032] In Figure 4, one or more sacrificial gate structures 130 are formed over a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 can be formed by sequentially depositing uniform-thickness layers of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning these layers into the sacrificial gate structure 130. Gate spacers 138 are then formed over the sidewalls of the sacrificial gate structure 130. For example, the gate spacers 138 can be formed by conformally depositing one or more layers of the gate spacers 138 and anisotropically etching the one or more layers. Although one sacrificial gate structure 130 is shown, in some embodiments two or more sacrificial gate structures 130 may be arranged along the X direction.

[0033] The sacrificial gate dielectric layer 132 may include one or more dielectric materials, such as silicon oxide-based materials. The sacrificial gate electrode layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The mask layer 136 may include more than one layer, such as an oxide layer and a nitride layer. The gate spacer 138 may be made of a dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof).

[0034] The portion of fin structure 112 covered by the sacrificial gate electrode layer 134 of sacrificial gate structure 130 serves as the channel region of semiconductor device structure 100. Fin structure 112, partially exposed on the opposite side of sacrificial gate structure 130, defines the source / drain (S / D) region of semiconductor device structure 100. In some cases, some S / D regions can be shared among individual transistors. For example, the individual regions in these S / D regions can be connected together and implemented as multiple functional transistors. It should be understood that source and drain regions can be used interchangeably because the epitaxial features to be formed in these regions are substantially the same.

[0035] In Figure 5, by removing portions of fin structure 112 not covered by sacrificial gate structure 130, portions of fin structure 112 in the S / D region (e.g., the region opposite to sacrificial gate structure 130) are recessed below the top surface of isolation region 120 (or insulating material 118). These recesses of fin structure 112 can be accomplished by an etching process (isotropic or anisotropic etching process), or further, can be selective relative to one or more crystal planes of substrate 101. The etching process can be dry etching (e.g., RIE, NBE, etc.) or wet etching (e.g., using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant). Trench 119 is formed in the S / D region due to these recesses of fin structure 112.

[0036] Figures 6A, 6B, and 6C are cross-sectional side views of the semiconductor device structure 100 taken along lines AA, BB, and CC of Figure 5, respectively. Figures 7A to 12A and 23A are cross-sectional side views of various stages of manufacturing the semiconductor device structure 100 according to some embodiments, taken along cross section AA of Figure 5. Figures 7B to 12B and 23B are cross-sectional side views of various stages of manufacturing the semiconductor device structure 100 according to some embodiments, taken along cross section BB of Figure 5. Figures 7C to 12C and 23C are cross-sectional side views of various stages of manufacturing the semiconductor device structure 100 according to some embodiments, taken along cross section CC of Figure 5. Cross section AA is in the plane along the X direction of the fin structure 112 (channel / fin cut). Cross section BB is in the plane perpendicular to cross section AA and in the sacrificial gate structure 130 (gate cut). The cross section CC lies in a plane perpendicular to the cross section AA along the Y direction and in the source / drain region (e.g., the epitaxial S / D feature 146 shown in FIG9A).

[0037] In Figures 7A to 7C, edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are removed horizontally along the X direction. The removal of the edge portions of the second semiconductor layer 108 forms cavities. In some embodiments, these portions of the second semiconductor layer 108 are removed by a selective wet etching process. When the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant (e.g., but not limited to ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution).

[0038] After removing the edge portions of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form dielectric spacers (or so-called internal spacers) 144. The dielectric spacers 144 can be made of a low-k dielectric material (e.g., SiON, SiCN, SiOC, SiOCN, or SiN). The dielectric spacers 144 can be formed by first forming a conformal dielectric layer using a conformal deposition process (e.g., ALD), followed by removing the portion of the conformal dielectric layer except for the dielectric spacers 144 by anisotropic etching. During the anisotropic etching process, the dielectric spacers 144 are protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 is capped between the dielectric spacers 144 along the X direction.

[0039] In Figures 8A-8C, epitaxial S / D features 146 are formed in the source / drain (S / D) regions. The epitaxial S / D features 146 are configured such that each sacrificial gate structure 130 is disposed between adjacent S / D region pairs. In an example shown in Figure 9A, one pair of epitaxial S / D features 146 disposed on one side of the sacrificial gate structure 130 is designated as a source feature / terminal, and the other pair of epitaxial S / D features 146 disposed on the other side of the sacrificial gate structure 130 is designated as a drain feature / terminal. The source and drain features / terminals are connected by a channel layer (e.g., a first semiconductor layer 106). The epitaxial S / D features 146 are in contact with the first semiconductor layer 106 beneath the sacrificial gate structure 130. In some cases, the epitaxial S / D feature 146 may grow beyond the topmost semiconductor channel (i.e., the first semiconductor layer 106 below the sacrificial gate structure 130) and contact the gate spacer 138. The second semiconductor layer 108 below the sacrificial gate structure 130 is separated from the epitaxial S / D feature 146 by a dielectric spacer 144.

[0040] Epitaxial S / D features 146 can be grown vertically and horizontally to form facets that can correspond to the crystal planes of the material used for substrate 101. In some cases, epitaxial S / D features 146 of fin structures can be grown and merged with epitaxial S / D features 146 of adjacent fin structures, as shown in an example in Figure 8C.

[0041] The epitaxial S / D feature 146 can be fabricated from one or more layers of Si, SiP, SiC, and SiCP for n-channel FETs or Si, SiGe, and Ge for p-channel FETs. The epitaxial S / D feature 146 can be formed using epitaxial growth methods such as CVD, ALD, or MBE. The epitaxial S / D feature 146 can be implanted with dopants and then annealed. The N-type and / or P-type impurities used for the epitaxial S / D feature 146 can be any of the dopants discussed previously.

[0042] In Figures 9A to 9C, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. CESL 162 covers the sidewalls of the sacrificial gate structure 130, the insulating material 118, the epitaxial S / D feature 146, and the exposed surface of the semiconductor layer stack 104. CESL 162 may include oxygen-containing or nitrogen-containing materials (e.g., silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbide, etc., or combinations thereof) and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162 above the semiconductor device structure 100. The material used for the first ILD layer 164 may include compounds containing Si, O, C, and / or H, such as silicon oxide, TEOS oxide, SiCOH, and SiOC. Organic materials (e.g., polymers) may also be used for the first ILD layer 164. The first ILD layer 164 can be deposited using a PECVD process or other suitable deposition techniques. In some embodiments, after the formation of the first ILD layer 164, the semiconductor device structure 100 can be subjected to a thermal process to anneal the first ILD layer 164.

[0043] In Figures 10A to 10C, after the formation of the ILD layer 164, a planarization operation (e.g., CMP) is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed.

[0044] In Figures 11A to 11C, the sacrificial gate structure 130 is removed. The first ILD layer 164 protects the epitaxial S / D features 146 during the removal of the sacrificial gate structure 130. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. For example, in the case where the sacrificial gate electrode layer 134 is polysilicon and the first ILD layer 164 is silicon oxide, a wet etchant such as tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer 134 without removing the dielectric material of the first ILD layer 164, CESL 162, and gate spacer 138. Subsequently, plasma dry etching and / or wet etching are used to remove the sacrificial gate dielectric layer 132. The removal of the sacrificial gate structure 130 (i.e., the sacrificial gate electrode layer 134 and the sacrificial gate dielectric layer 132) forms a trench 166 in the region where the sacrificial gate electrode layer 134 and the sacrificial gate dielectric layer 132 have been removed. Trench 166 exposes the top and sides of semiconductor layer stack 104 (e.g., first semiconductor layer 106 and second semiconductor layer 108).

[0045] In Figures 12A-12C, the exposed second semiconductor layer 108 is removed. Removal of the second semiconductor layer 108 exposes the dielectric spacer 144 and the first semiconductor layer 106. The removal process can be any suitable etching process, such as dry etching, wet etching, or a combination thereof. The etching process can be a selective etching process that removes the second semiconductor layer 108 but substantially does not erode the first semiconductor layer 106. In some embodiments, the etching process is an isotropic etching process using an etching gas and optionally a carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas can be an inert gas, such as Ar, He, N2, or combinations thereof. After removal of the second semiconductor layer 108, an opening 151 is formed around the first semiconductor layer 106, and the portion of the first semiconductor layer 106 not covered by the dielectric spacer 144 is exposed to the opening 151. The remaining first semiconductor layer 106 can be used as a channel region for a GAA device, which in some embodiments may include at least an NFET or a PFET. Although not specifically shown, according to some embodiments, one of the GAA devices, such as semiconductor device structure 100, may be an NFET or a PFET.

[0046] Figures 13 through 16 are enlarged views of region 147 of Figure 12B, illustrating various stages of fabricating the alternative gate structure 190 of the semiconductor device structure 100 according to some embodiments. As discussed above, substrate 101 may include various regions already doped with impurities (e.g., dopants having P-type or N-type conductivity). In one exemplary embodiment, substrate 101 has device region 153 and device region 155 adjacent to device region 153. Device region 153 may be designated as a P-type region or an N-type region, and device region 155 may be designated as an N-type region or a P-type region. Alternatively, both regions 153 and 155 may be designated as P-type or N-type regions. In one embodiment, device region 153 is a P-type region, and device region 155 is an N-type region. Although not shown to scale in some figures, device regions 153 and 155 belong to a continuous substrate 101. In some embodiments of this disclosure, P-type regions are used to form PMOS structures thereon, while N-type regions are used to form NMOS structures thereon. Depending on the circuit design, regions 153 and 155 can be used to form different types of circuits. For example, device region 153 can be used to form, for example, peripheral circuits, input / output (I / O) circuits, electrostatic discharge (ESD) circuits, and / or analog circuits, and device region 155 can be used to form logic circuits. Other regions for forming other types of circuits are considered and are intended to be included within the scope of this disclosure.

[0047] In Figure 13, an interface layer (IL) 150 is formed to surround the exposed surface of the first semiconductor layer 106. In some embodiments, the IL 150 may also be formed on the well portion 116 of the substrate 101. The IL 150 has a uniform thickness on the exposed surface of the first semiconductor layer 106 and on the well portion 116 of the substrate 101. The IL 150 may comprise an oxygen-containing material or a silicon-containing material, such as silicon oxide, silicon oxynitride, oxynitride, etc., or made of them. In one embodiment, the IL 150 is silicon oxide. The IL 150 can be formed by first subjecting the first semiconductor layer 106 and the exposed well portion 116 of the substrate 101 to a wet process. This wet process can be any suitable wet cleaning process or a self-compensating wet process. In some embodiments, the wet process is an etching process using at least ozone (O3) and / or ammonium hydroxide (NH4OH). For example, wet processes may include NH4OH, HF or diluted HF, deionized (DI) water, tetramethylammonium hydroxide (TMAH), other suitable wet etching solutions, or combinations thereof. In one embodiment, the wet process may be Standard Clean-2 (SC2) followed by Standard Clean-1 (SC1), wherein SC2 is a mixture of DI water, hydrochloric acid (HCl), and hydrogen peroxide (H2O2), and SC1 is a mixture of DI water, NH4OH, and H2O2. In some embodiments, isopropanol (IPA) may be used after SC1. Other suitable wet cleaning processes may also be used, such as the APM process which includes at least water (H2O), ammonium hydroxide (NH4OH), and hydrogen peroxide (H2O2), the HPM process which includes at least H2O, H2O2, and hydrogen chloride (HCl), the SPM process (also known as piranhaclean) which includes at least H2O2 and sulfuric acid (H2SO4), or any combination thereof.

[0048] Alternatively or additionally, the IL 150 can be formed by a wet oxidation process that oxidizes the exterior of the first semiconductor layer 106 and the exterior of the exposed well portion 116 of the substrate 101. That is, the exterior of the first semiconductor layer 106 and the exposed well portion 116 of the substrate 101 are part of the IL 150. After oxidation is complete, this exterior surrounds and contacts the well portion 116 of the first semiconductor layer 106 and the well portion 116 of the substrate 101. In some embodiments, the IL 150 can be formed using an oxidation process, such as a thermal oxidation process, a rapid thermal oxidation (RTO) process, an in-situ flow generation (ISSG) process, or an enhanced in-situ flow generation (EISSG) process. In one example, the IL 150 is formed by subjecting the first semiconductor layer 106 and the well portion 116 of the substrate 101 to rapid thermal annealing (RTA) in an oxygen-containing environment. Thermal oxidation can be performed at temperatures ranging from approximately 600°C to approximately 1100°C for a time span of approximately 10 seconds to approximately 30 seconds. The temperature and time span of this oxidation can contribute to the thickness of the IL 150. For example, higher temperatures and longer oxidation time spans can result in a thicker IL 150. Alternatively, the IL 150 can also be an oxide formed by CVD, ALD, or any suitable conformal deposition technique.

[0049] In Figure 14, a high-k (HK) dielectric layer 160 is formed on the exposed surface of the semiconductor device structure 100. In some embodiments, the HK dielectric layer 160 is in contact with IL 150. The HK dielectric layer 160 is also formed on the exposed surface of the insulating material 118. The HK dielectric layer 160 can be a single-layer or multi-layer structure. In one embodiment, the HK dielectric layer 160 is a bilayer structure including a first HK dielectric layer 160a and a second HK dielectric layer 160b. The first HK dielectric 160a and the second HK dielectric 160b can be made of materials with different chemical compositions from each other. Suitable materials for the HK dielectric layer 160 may include, but are not limited to, hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfAlO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), lanthanum oxide (LaO), aluminum oxide (AlOx), aluminum silicon oxide (AlSiO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), silicon oxynitride (SiON), etc., or any material having a dielectric constant greater than that of silicon oxide. The HK dielectric layer 160 may be a conformal layer formed by a conformal process (e.g., ALD or CVD process). The HK dielectric layer 160 may have a thickness in the range of about 10 angstroms to about 50 angstroms.

[0050] In Figure 15, a conditioning layer 156 is formed on the HK dielectric 160. The conditioning layer 156 can be used as a dipole layer for Vth conditioning. If the HK dielectric layer 160 is a multilayer structure, the conditioning layer 156 can be deposited on the first HK dielectric 160a. In some embodiments, the conditioning layer 156 contains a Vth suitable for a P-type device. th A dielectric material of one or more adjusted elements. The adjustment layer 156 can be a nitride-based or oxide-based dielectric material. In some embodiments, the adjustment layer 156 is a metal nitride material, wherein the metal may include, but is not limited to, aluminum (Al), titanium (Ti), hafnium (Hf), tantalum (Ta), zirconium (Zr), gallium (Ga), or combinations thereof. Exemplary metal nitrides for the adjustment layer 156 may include AlN, TiN, HfN, TaN, ZrN, GaN, etc. The thickness of the adjustment layer 156 serves as a key parameter for adjusting the nitrogen doping amount in the HK dielectric 160, thereby controlling V. FB The offset minimizes CET loss. As will be discussed in more detail below, the total thickness of the adjustment layer 156 and the dipole layer 157 affects the concentration of metals and nitrogen within the adjustment layer 156. This, in turn, affects the metal and nitrogen content in the HK dielectric layer 160, ultimately affecting the flat-band voltage (V) of the gate structure in the device. FB ) and threshold voltage.

[0051] In some embodiments, the adjustment layer 156 is a metal oxide material, wherein the metal may include, but is not limited to, Al, gallium (Ga), indium (In), zinc (Zn), germanium (Ge), Ti, or combinations thereof. Exemplary metal oxides used for the adjustment layer 156 may include AlOx, GaO, InO, ZnO, GeO, TiO, etc.

[0052] In some embodiments, the adjustment layer 156 is a metal oxynitride, wherein the metal may be Al, Hf, Ti, Zr, lanthanum (La), or a combination thereof. Exemplary metal oxynitrides used for the adjustment layer 156 may include AlON, HfON, TiON, ZrON, LaON, etc.

[0053] In some embodiments, the adjustment layer 156 may be a multilayer structure comprising two or more materials discussed herein. For example, the adjustment layer 156 may be a bilayer structure comprising AlN and AlON. Figure 15-1 illustrates an embodiment in which the adjustment layer 156 comprises a first layer 156a (comprising, for example, AlN) and a second layer 156b (comprising, for example, AlON).

[0054] In any case, conformal deposition processes (such as ALD) can be used to form the conditioning layer 156. Other suitable deposition techniques, such as CVD, MOCVD, or PECVD, can also be used.

[0055] When the adjustment layer 156 includes AlN, the chemical precursors used to form AlN may include aluminum-containing precursors and nitrogen-containing precursors. Exemplary aluminum-containing precursors may include, but are not limited to, alkylaluminum (e.g., trimethylaluminum (TMA, Al(CH3)3)), aluminum hydroxide (Al(OH)3) or aluminum oxide (Al2O3), aluminum chloride (AlCl3), etc. Exemplary nitrogen-containing precursors may include, but are not limited to, ammonia (NH3), nitrogen (N2), hydrazine (N2H4), trimethylamine (N(CH3)3).

[0056] When the adjustment layer 156 includes AlON, the chemical precursors used to form AlON may include aluminum-containing precursors, oxygen-containing precursors, and nitrogen-containing precursors. Exemplary oxygen-containing precursors may include, but are not limited to, water (H2O), oxygen (O2), nitrogen oxides (N2O), etc. Oxygen-containing organic compounds, such as methanol (CH3OH), ethanol (C2H5OH), and propanol (C3H7OH), may also be used. Exemplary aluminum-containing and nitrogen-containing precursors may be precursors for forming AlN as described above.

[0057] Alternatively, the adjustment layer 156 may be a dielectric material comprising one or more elements suitable for Vth adjustment in N-type devices. In this case, the adjustment layer 156 may be an oxide-based dielectric material. In some embodiments, the adjustment layer 156 is a metal oxide material, wherein the metal may include, but is not limited to, lanthanum (La), lutetium (Lu), scandium (Sc), yttrium (Y), thulium (Tm), gadolinium (Gd), magnesium (Mg), or combinations thereof. Exemplary metal oxides for the adjustment layer 156 may include La₂O₃, LuO₂, etc. x ScO x , Y2O3, Tm2O3, Gd2O3, MgO, etc.

[0058] As will be discussed below, the adjustment layer 156 works in conjunction with the dipole layer 157 (Figure 16), and the thickness of the adjustment layer 156 can increase or compensate for the flat-band voltage (V) required by the P-type or N-type transistor device. FB The adjustment layer 156 can have a thickness ranging from about 1 angstrom to about 15 angstroms (e.g., from about 5 angstroms to about 10 angstroms). If the thickness of the adjustment layer 156 is less than 1 angstrom, the adjustment layer 156 may not be usable for effective V. FB and V th Adjustment. On the other hand, if the thickness of the adjustment layer 156 is greater than about 15 angstroms, the gate fill window for subsequent layers (e.g., dipole layer 157) may be negatively affected, and the manufacturing cost increases without any significant advantage.

[0059] In Figure 16, a dipole layer 157 is formed on the exposed surface of the adjustment layer 156. Depending on the conductivity type of the nanosheet transistor, the dipole layer 157 can be configured to include positive or negative polarity. The materials of the dipole layer 157 and the adjustment layer 156 are selected and used together as a bilayer P-dipole. The dipole layer 157 can also be used as a patterning mask and to prevent oxidation of the adjustment layer 156 (e.g., AlN or AlON). In cases where the nanosheet transistor at device region 153 is designated as a p-type FET and the nanosheet transistor at device region 155 is designated as an N-type FET, the dipole layer 157 can be a positive dipole (p-dipole) layer formed of a material that inherently includes positive polarity. For example, the dipole layer 157 can be an oxide-based dielectric material, such as a metal oxide material. In this case, the metal can include, but is not limited to, Al, Ga, In, Zn, Ge, Ti, vanadium (V), etc., or combinations thereof. An exemplary metal oxide for the dipole layer 157 can include AlO. x GaO x InO x ZnO x GeO x TiO x VO x wait.

[0060] Dipole layer 157 includes AlO x In the case of forming AlO x The chemical precursors may include aluminum-containing precursors and oxygen-containing precursors. Exemplary aluminum-containing and oxygen-containing precursors may be precursors for forming AlON as described above. The dipole layer 157 can be formed using a conformal deposition process (e.g., ALD process). Other suitable deposition techniques may also be used, such as CVD, MOCVD, or PECVD. In some embodiments, the dipole layer 157 and the conditioning layer 156 may be deposited in the same processing chamber without breaking the vacuum.

[0061] Since the dipole layer 157 also serves as a mask, the total thickness of the adjustment layer 156 and the dipole layer 157 is set to a fixed value. In various embodiments, the dipole layer 157 and the adjustment layer 156 may have a total thickness of about 30 angstroms, and the thickness of the dipole layer 157 will vary depending on the thickness of the adjustment layer 156. For example, if the adjustment layer 156 has a thickness of about 10 angstroms, then the dipole layer 157 may have a thickness of about 20 angstroms. Therefore, the thicker the dipole layer 157, the thinner the adjustment layer 156, and vice versa. It has been observed that as the thickness of the adjustment layer 156 increases, a greater amount of nitrogen (in the case where the adjustment layer 156 includes AlN or AlON) is driven into the HK dielectric layer 160 after heat treatment. Due to the stronger bonding properties and interactions between nitrogen and the metal elements in the HK dielectric layer 160, the increased nitrogen doping in the HK dielectric layer 160 enhances the blocking effect on the metal elements (e.g., aluminum) in the adjustment layer 156. Therefore, most of the metal (e.g., Al) is prevented from entering or penetrating deeper into the HK dielectric layer 160, resulting in a lower concentration of metal (e.g., Al) in the HK dielectric layer 160. Conversely, as the thickness of the dipole layer 157 increases, the thickness of the adjustment layer 156 decreases. Therefore, after heat treatment, less nitrogen is driven into the HK dielectric layer 160, resulting in a higher concentration of metal (e.g., Al) in the HK dielectric layer 160. By adjusting the thickness ratio between the adjustment layer 156 and the dipole layer 157, the concentrations of Al and N in the HK dielectric layer 160 can be changed, thereby allowing a flat-band voltage (V0) of the gate structure. FB The CET increases to the expected value, while the CET increases very little.

[0062] In Figure 17, a patterned mask layer 154 is formed to at least cover the nanosheet transistors at device region 153, which are designated as P-type FETs in some embodiments. The mask layer 154 may initially fill the opening 151 (Figure 16) to such that the nanosheet transistors at regions 153, 155 are immersed in the mask layer 154. The mask layer 154 may be any suitable masking material (e.g., a photoresist layer, a BARC (bottom antireflective coating) layer, an SOG (spin-on glass) layer, or a SOC (spin-on carbon) layer) and may be deposited by spin coating or any suitable deposition technique. Next, the mask layer 154 is patterned and etched to expose the nanosheet transistors at device region 155, which are designated as N-type FETs in some embodiments. An ashing process and / or one or more etching processes (e.g., dry etching, wet etching, or a combination thereof) are used to remove the conditioning layer 156 and dipole layer 157 at device region 153 not covered by the mask layer 154.

[0063] In some embodiments, an etching process is performed to expose the HK dielectric layer 160 at device region 155, as shown in FIG17.

[0064] In some embodiments, an etching process is performed until the adjustment layer 156 at device region 155 is exposed, as shown in FIG18.

[0065] In some embodiments, an etching process is performed to expose the HK dielectric layer 160 at device region 155, and the semiconductor device structure 100 undergoes a thermal treatment 158, as shown in FIG19. At device region 153, the thermal treatment drives elements (e.g., Al) from conditioning layer 156 into the underlying HK dielectric layer 160. The HK dielectric layer 160 at device region 155 does not contain elements from conditioning layer 156. In some embodiments, the thermal treatment may also drive elements (e.g., Al) from dipole layer 157 into HK dielectric layer 160. In cases where conditioning layer 156 comprises AlN or AlON, elements (e.g., Al) in conditioning layer 156 are driven into and mixed with HK dielectric layer 160 due to the thermal treatment to form an intermixed layer 129. The individual intermixed layer 129 or the entire HK dielectric layer 160 can be considered as a modified HK dielectric layer 160'. As used herein, the term "intermixed layer" refers to the reaction product of HK dielectric layer 160 and conditioning layer 156, which may be a compound, composition, or mixture, depending on the heat treatment used. In some embodiments, intermixed layer 129 may be HK dielectric layer 160 doped with an element from conditioning layer 156 (e.g., Al).

[0066] Figure 19-1 is an enlarged view of a portion of a semiconductor device structure 100, showing an intermixed layer 129 located at and / or near the interface defined by the modified HK dielectric layer 160' and the conditioning layer 156 within a modified HK dielectric layer 160'. The intermixed layer 129 may contain element A (e.g., Al) and element B (e.g., N), the concentration distribution of which changes gradient-wise and continuously along the thickness of the intermixed layer 129. In one embodiment, the intermixed layer 129 has a first concentration of Al and N at the interface between the intermixed layer 129 and the conditioning layer 156, and a second concentration of Al and N at the interface between the intermixed layer 129 and the modified HK dielectric layer 160', wherein the first concentration is greater than the second concentration. In some embodiments, Al may have a higher concentration than N at the interface between the intermixed layer 129 and the conditioning layer 156, possibly due to its larger atomic radius compared to N, which may affect its diffusion and distribution characteristics.

[0067] The heat treatment can be performed in situ or in situ, and can be any type of annealing, such as rapid thermal annealing, spike annealing, immersion annealing, laser annealing, furnace annealing, etc. The heat treatment can be performed over a temperature range of approximately 450°C to approximately 1200°C for approximately 0.05 seconds to approximately 60 minutes (e.g., approximately 10 seconds to approximately 30 seconds). The heat treatment can be performed in a gaseous environment (e.g., oxygen-containing gas, hydrogen-containing gas, argon-containing gas, helium-containing gas, or any combination thereof). Exemplary gases may include, but are not limited to, N2, NH3, O2, N2O, Ar, He, H, etc.

[0068] In Figure 20, a mask layer 154' (e.g., mask layer 154) is formed to at least cover the nanosheet transistor at device region 155, which is designated as an N-type FET in some embodiments. The mask layer 154' protects the HK dielectric layer 160 and IL 150 at device region 155 during a subsequent etching process. Next, the mask layer 154 at device region 153 is patterned and etched to expose the nanosheet transistor, which is designated as a P-type FET in some embodiments. An ashing process and / or one or more etching processes (such as dry etching, wet etching, or a combination thereof) are used to remove the dipole layer 157 and conditioning layer 156 at device region 153 that are not covered by the mask layer 154. The etching process exposes the surface of the HK dielectric layer 160 at device region 153.

[0069] Depending on the application, the threshold voltage of the N-type and / or P-type FETs in regions 153 and 155 can be adjusted by forming and varying the thickness of one or more dipole layers 157 and adjustment layers 156, as described above, to achieve different elemental concentrations. Additionally, the etching process discussed above with respect to Figures 17 through 19 can be configured to provide different arrangements of the dipole layers 157 and adjustment layers 156 in regions 153 and 155, respectively. Integrated circuit devices, such as semiconductor device structures 100, can include various transistors with different threshold voltages based on their function in the IC device. For example, input / output (IO) transistors may have the highest threshold voltage because they require high current handling. Core logic transistors may have the lowest threshold voltage to achieve higher switching speeds at lower operating power. A third threshold voltage, between the threshold voltage of the IO transistors and the threshold voltage of the core logic transistors, can be used for other functional transistors, such as static random access memory (SRAM) transistors. By retaining and / or removing the dipole layers / adjustment layers in different regions, nanosheet FETs in different regions of the semiconductor device structure can operate at different threshold voltages required for different applications.

[0070] In Figure 21, mask layer 154' is removed, and gate electrode layer 165 is formed on modified HK dielectric layer 160' at device region 153 and HK dielectric layer 160 at device region 155. Gate electrode layer 165 surrounds each first semiconductor layer 106 and fills opening 151 at device regions 153, 155 (Figures 19 and 20). Gate electrode layer 165 can be deposited such that at least the nanosheet transistors at regions 153, 155 are immersed in gate electrode layer 165. In some embodiments, gate electrode layer 165 is deposited to a height above the top surface of HK dielectric layers 160, 160' above the topmost first semiconductor layer 106. In some embodiments, multiple layers can be used to form gate electrode layer 165, with each layer deposited sequentially adjacent to each other using a highly conformal deposition process such as ALD. Other deposition techniques, such as PVD, CVD, or electroplating, can also be used. Although not shown, the gate electrode layer 165 may include a cap layer, a barrier layer, an n-metal work function layer, a p-metal work function layer, and a filler material. The cap layer and barrier layer may be metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, or combinations thereof. The barrier layer may be formed of a material different from that of the cap layer. The n-metal work function layer may be formed of metallic materials (e.g., W, Cu, AlCu, TiAlC, TiAlN, Ti, TiN, Ta, TaN, Co, Ni, Ag, Al, TaAl, TaAlC, TaC, TaCN, TaSiN, Mn, Zr), other suitable n-type work function materials, or combinations thereof. The p-metal work function layer can be formed of metallic materials, such as W, Al, Cu, TiN, Ti, TiAlN, Ta, TaN, Co, Ni, TaC, TaCN, TaSiN, TaSi2, NiSi2, Mn, Zr, ZrSi2, TaN, Ru, AlCu, Mo, MoSi2, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, and combinations thereof. Once the n-metal work function layer and the p-metal work function layer are formed, a filler material is deposited to fill the remaining portion of opening 151. The filler material can be materials such as W, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, and combinations thereof.

[0071] While the various processes described in Figures 17 through 20 depict schemes for selectively removing the conditioning layer 156 and dipole layer 157 from the nanosheet transistor at device region 155 using mask layer 154, in some embodiments, the dipole layer 157 at device region 155 is removed to expose the conditioning layer 156, and then the dipole layer 157 at device region 153 is used as a patterning mask to further remove the conditioning layer 156 at device region 155. Next, the dipole layer 157 and conditioning layer 156 at device region 153 are thermally treated to form an intermixed layer 129 in the modified HK dielectric layer 160'. The dipole layer 157 and conditioning layer 156 at device region 153 are then removed, followed by the formation of the gate electrode layer 165 to produce the structure shown in Figure 21.

[0072] Figure 22 shows an enlarged view of a portion of the semiconductor device structure 100 of Figure 21 according to some embodiments. As discussed above, a first semiconductor layer 106 at device region 153 is sequentially surrounded by IL 150, a modified HK dielectric layer 160', an intermix layer 129, and a gate electrode layer 165. The first semiconductor layer 106 at device region 155 is sequentially surrounded by IL 150, an HK dielectric layer 160, and a gate electrode layer 165. The modified HK dielectric layer 160' and the intermix layer 129 at device region 153 may have a thickness T1, and the HK dielectric layer 160 at device region 155 may have a thickness T2 that is substantially the same as the thickness T1.

[0073] In Figures 23A-23C, contact openings are formed through ILD layers 164 and CESL 162 to expose the epitaxial S / D feature 146. A silicide layer 178 is then formed on the epitaxial S / D feature 146 to electrically couple the epitaxial S / D feature 146 to the subsequently formed S / D contact 176. The silicide layer 178 can be formed by depositing a metal source layer on the epitaxial S / D feature 146 and performing a rapid thermal annealing process. The metal source layer includes a metal layer selected from W, Co, Ni, Ti, Mo, and Ta, or a metal nitride layer selected from tungsten nitride, cobalt nitride, nickel nitride, titanium nitride, molybdenum nitride, and tantalum nitride. During the rapid annealing process, the portion of the metal source layer above the epitaxial S / D feature 146 reacts with silicon in the epitaxial S / D feature 146 to form the silicide layer 178. The unreacted portion of the metal source layer is then removed.

[0074] After the silicide layer 178 is formed, a conductive material is formed in the contact opening to form an S / D contact 176. This conductive material can be made of one or more of the following: Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, and TaN. Although not shown, a barrier layer (e.g., TiN, TaN, etc.) can be formed on the sidewalls of the contact opening before forming the S / D contact 176. A planarization process (e.g., CMP) is then performed to remove excess deposited contact material and expose the top surface of the gate electrode layer 165.

[0075] It should be understood that the semiconductor device structure 100 may undergo further complementary metal-oxide-semiconductor (CMOS) and / or back-end processing (BEOL) processes. For example, gate contacts may be formed to electrically couple to the gate electrode layer 165. Interconnect structures may be formed on the S / D contact 176 and the gate contact. The interconnect structures may include multiple dielectric layers and metallic features, including conductive traces and conductive vias embedded in the dielectric layers, which form electrical connections between various devices on the substrate 101. The semiconductor device structure 100 may also include back contact (not shown) on the back side of the substrate 101, implemented by flipping the semiconductor device structure 100, removing the substrate 101, and selectively connecting the source or drain features / terminals of the epitaxial S / D feature 146 to a back power rail (e.g., a positive voltage VDD or a negative voltage VSS) via the back contact. Depending on the application, the source or drain features / terminals of the epitaxial S / D feature 146 and the gate electrode layer 172 may be connected to a front power supply.

[0076] Various embodiments of this disclosure provide an improvement: using an adjustment layer (formed of a metal nitride) and a dipole layer (cluster mask layer) as a bilayer p-dipole layer to control the V of the gate structure. FB The thickness of the adjustment layer (e.g., adjustment layer 156) is used as a key parameter to adjust the amount of nitrogen doping in the HK dielectric (e.g., HK dielectric layer 160), thereby controlling V. FB The offset minimizes CET loss. The total thickness of the tuning layer and dipole layer (e.g., dipole layer 157) affects the concentration of metals and nitrogen within the tuning layer. This, in turn, affects the metal and nitrogen content in the HK dielectric layer 160, ultimately influencing the flat-band voltage (V0) of the gate structure in the device. FB ) and threshold voltage.

[0077] One embodiment is a method for forming a semiconductor device structure. The method includes: forming an interface layer (IL) at a first device region and a second device region to surround each of a plurality of semiconductor channel layers; forming a high-k (HK) dielectric layer over the IL; forming an adjustment layer over the HK dielectric layer, the adjustment layer including elements suitable for a device having a first conductivity type; forming a dipole layer over the adjustment layer at the first device region and the second device region, wherein the adjustment layer and the dipole layer are formed sequentially in a processing chamber without breaking a vacuum, and the dipole layer includes elements suitable for a device having a first conductivity type; removing the dipole layer over a selected semiconductor channel layer at the second device region; subjecting the adjustment layer to a thermal treatment at the first device region such that elements from the adjustment layer are driven into the HK dielectric layer; removing the dipole layer and the adjustment layer over a selected semiconductor channel layer at the first device region; and forming a gate electrode layer at the first device region and the second device region to surround each semiconductor channel layer.

[0078] Another embodiment is a method for forming a semiconductor device structure. The method includes: forming a first dipole layer on a first channel layer and a second channel layer, respectively, over a high-k (HK) dielectric layer; forming a second dipole layer on the first dipole layer, the second dipole layer being chemically different from the first dipole layer; removing the second dipole layer over the second channel layer; subjecting the first and second dipole layers over the first channel layer to a thermal treatment to form an intermixed layer in the HK dielectric layer on the first channel layer; removing the first and second dipole layers over the first channel layer; and forming a gate electrode layer on the first channel layer and the second channel layer.

[0079] Another embodiment is a semiconductor device structure. The structure includes: a first semiconductor channel layer at a first device region; a second semiconductor channel layer at a second device region; a first gate dielectric layer disposed above the first semiconductor channel layer, the first gate dielectric layer being doped with a first element comprising a metal and a second element comprising nitrogen; a second gate dielectric layer disposed above the second semiconductor channel layer, wherein the second gate dielectric layer has a first thickness; gate electrode layers disposed above the first gate dielectric layer and the second gate dielectric layer respectively; and an intermixing layer disposed between the gate electrode layer and the first gate dielectric layer and in contact with the gate electrode layer and the first gate dielectric layer, wherein the intermixing layer comprises the first element and the second element, and the intermixing layer and the first gate dielectric layer have a second thickness substantially the same as the first thickness.

[0080] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0081] Example 1. A method for forming a semiconductor device structure, comprising: forming an interface layer (IL) at a first device region and a second device region to surround each of a plurality of semiconductor channel layers; forming a high-k (HK) dielectric layer over the IL; forming an adjustment layer over the HK dielectric layer, the adjustment layer including elements suitable for a device having a first conductivity type; forming a dipole layer over the adjustment layer at the first device region and the second device region, wherein the adjustment layer and the dipole layer are formed sequentially in a processing chamber without breaking a vacuum, and the dipole layer includes elements suitable for a device having the first conductivity type; removing the dipole layer over a selected semiconductor channel layer at the second device region; subjecting the adjustment layer to a thermal treatment at the first device region such that elements from the adjustment layer are driven into the HK dielectric layer; removing the dipole layer and the adjustment layer over a selected semiconductor channel layer at the first device region; and forming a gate electrode layer at the first device region and the second device region to surround each semiconductor channel layer.

[0082] Example 2. The method according to Example 1 further includes: after removing the dipole layer over the selected semiconductor channel layer in the second device region, removing the adjustment layer over the selected semiconductor channel layer in the second device region.

[0083] Example 3. The method according to Example 1, wherein the adjustment layer comprises a nitride-based or oxide-based dielectric material.

[0084] Example 4. The method according to Example 3, wherein the adjustment layer is a metal nitride and / or a metal oxynitride.

[0085] Example 5. The method according to Example 4, wherein the metal is aluminum (Al), titanium (Ti), hafnium (Hf), tantalum (Ta), zirconium (Zr), or gallium (Ga), etc.

[0086] Example 6. The method according to Example 4, wherein the adjustment layer is aluminum nitride (AlN).

[0087] Example 7. The method according to Example 4, wherein the adjustment layer is aluminum oxynitride (AlON).

[0088] Example 8. The method according to Example 4, wherein the adjustment layer has a thickness of about 1 angstrom to about 15 angstroms.

[0089] Example 9. The method according to Example 8, wherein the adjustment layer and the dipole layer have a total thickness of about 30 angstroms.

[0090] Example 10. A method for forming a semiconductor device structure, comprising: forming a first dipole layer over high-k (HK) dielectric layers on a first channel layer and a second channel layer, respectively; forming a second dipole layer over the first dipole layer without vacuum disruption, the second dipole layer being chemically different from the first dipole layer; removing the second dipole layer over the second channel layer; subjecting the first dipole layer and the second dipole layer over the first channel layer to a thermal treatment to form an intermixed layer in the HK dielectric layer over the first channel layer; removing the first dipole layer and the second dipole layer over the first channel layer; and forming a gate electrode layer over the first channel layer and the second channel layer.

[0091] Example 11. The method according to Example 10 further includes: after removing the second dipole layer above the second channel layer, removing the first dipole layer above the second channel layer.

[0092] Example 12. The method according to Example 11, wherein the second dipole layer above the first channel layer is used as a mask to remove the first dipole layer above the second channel layer.

[0093] Example 13. The method according to Example 10, wherein the first dipole layer and the second dipole layer have a total thickness of about 30 angstroms.

[0094] Example 14. The method according to Example 10, wherein the intermixed layer is the reaction product of the HK dielectric layer and the first dipole layer.

[0095] Example 15. The method according to Example 14, wherein the first dipole layer is a metal nitride and / or a metal oxynitride.

[0096] Example 16. A semiconductor device structure comprising: a first semiconductor channel layer at a first device region; a second semiconductor channel layer at a second device region; a first gate dielectric layer disposed above the first semiconductor channel layer, the first gate dielectric layer being doped with a first element comprising a metal and a second element comprising nitrogen; a second gate dielectric layer disposed above the second semiconductor channel layer, wherein the second gate dielectric layer has a first thickness; gate electrode layers disposed above the first gate dielectric layer and the second gate dielectric layer, respectively; and an intermixing layer disposed between the gate electrode layer and the first gate dielectric layer and in contact with the gate electrode layer and the first gate dielectric layer, wherein the intermixing layer comprises the first element and the second element, and the intermixing layer and the first gate dielectric layer have a second thickness substantially the same as the first thickness.

[0097] Example 17. The semiconductor device structure according to Example 16, wherein the first element and the second element in the intermixed layer have a first concentration, and the first element and the second element in the first gate dielectric layer have a second concentration lower than the first concentration.

[0098] Example 18. A semiconductor device structure according to Example 16, wherein the intermixed layer is a reaction product of the first gate dielectric layer and a metal nitride or a metal oxynitride.

[0099] Example 19. A semiconductor device structure according to Example 16, wherein the intermixed layer is a reaction product of the first gate dielectric layer with a metal nitride and a metal oxynitride.

[0100] Example 20. A semiconductor device structure according to Example 16, wherein the intermixed layer is a reaction product of the first gate dielectric layer and the metal oxide.

Claims

1. A method for forming a semiconductor device structure, comprising: An interface layer IL is formed at the first device region and the second device region to surround each of the plurality of semiconductor channel layers. A high-k HK dielectric layer is formed on the IL; An adjustment layer is formed on the HK dielectric layer, the adjustment layer including elements suitable for a device having a first conductivity type; a dipole layer is formed on the adjustment layer at the first device region and the second device region, wherein the adjustment layer and the dipole layer are formed sequentially in a processing chamber without breaking the vacuum, and the dipole layer includes elements suitable for a device having the first conductivity type; the dipole layer on a selected semiconductor channel layer at the second device region is removed; the adjustment layer is subjected to heat treatment at the first device region such that elements from the adjustment layer are driven into the HK dielectric layer; the dipole layer and the adjustment layer on a selected semiconductor channel layer at the first device region are removed; and a gate electrode layer is formed at the first device region and the second device region to surround each semiconductor channel layer.

2. The method according to claim 1, further comprising: After removing the dipole layer above the selected semiconductor channel layer in the second device region, the adjustment layer above the selected semiconductor channel layer in the second device region is removed.

3. The method according to claim 1, wherein, The adjustment layer comprises a nitride-based or oxide-based dielectric material.

4. The method according to claim 3, wherein, The adjustment layer is a metal nitride and / or a metal oxynitride.

5. The method according to claim 4, wherein, The metal is aluminum (Al), titanium (Ti), hafnium (Hf), tantalum (Ta), zirconium (Zr), or gallium (Ga).

6. The method according to claim 4, wherein, The adjustment layer is aluminum nitride (AlN).

7. The method according to claim 4, wherein, The adjustment layer is aluminum oxynitride (AlON).

8. The method according to claim 4, wherein, The adjustment layer has a thickness of 1 to 15 angstroms.

9. A method for forming a semiconductor device structure, comprising: A first dipole layer is formed on top of the high-k HK dielectric layer on the first channel layer and the second channel layer, respectively; A second dipole layer is formed on top of the first dipole layer without vacuum disruption, and the second dipole layer is chemically different from the first dipole layer. Remove the second dipole layer above the second channel layer; subject the first dipole layer and the second dipole layer above the first channel layer to heat treatment to form an intermixed layer in the HK dielectric layer on the first channel layer. Remove the first dipole layer and the second dipole layer above the first channel layer; and form a gate electrode layer above the first channel layer and the second channel layer.

10. A semiconductor device structure, comprising: The first semiconductor channel layer at the first device region; The second semiconductor channel layer at the second device region; A first gate dielectric layer is disposed above the first semiconductor channel layer, the first gate dielectric layer being doped with a first element comprising a metal and a second element comprising nitrogen; a second gate dielectric layer is disposed above the second semiconductor channel layer, wherein the second gate dielectric layer has a first thickness; gate electrode layers are disposed above the first gate dielectric layer and the second gate dielectric layer, respectively; and an intermixing layer is disposed between the gate electrode layer and the first gate dielectric layer and in contact with the gate electrode layer and the first gate dielectric layer, wherein the intermixing layer comprises the first element and the second element, and the intermixing layer and the first gate dielectric layer have a second thickness substantially the same as the first thickness.

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