Asymmetric GCT chip

Abstract

The invention belongs to the field of power semiconductors, and particularly relates to an asymmetric GCT chip which comprises a P + transparent emission anode, an N-base region, a P base region, a P + base region and an N + emission region partially embedded in the P + base region, or an N'buffer layer is arranged between the P + transparent emitting anode region and the N-base region; the center of the N + emitter region is provided with a groove, and the groove is filled with a cathode metal layer and is led out. According to the asymmetric GCT chip provided by the invention, a comb structure with a groove is adopted, under the same chip size, the effective area of a cathode is increased, the doping concentration of a P + base region below an N + emitter region is reduced, the opening performance of the chip is improved, the junction depth of a J3 junction is basically kept unchanged, and the turn-off capability is not reduced while the through-current capability is improved.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductors, and specifically relates to an asymmetric GCT chip. Background Technology

[0002] As a fully controllable power semiconductor device, IGCT devices have broad application prospects in the power grid field due to their large power capacity, low on-state loss, and robust short-circuit failure mode.

[0003] The existing vertical structure of asymmetric GCT chips is mainly composed of P, depending on the doping intensity. + 、N′、N - P, P + N + It consists of six layers, each corresponding to P. + Transparent emitting anode, N′ buffer layer, N - base region, P base region, P + short base region and N + Emitter region (also called cathode comb). There are three PN junctions inside the chip, from anode to cathode: J1 junction (anode transparent junction), J2 junction (blocking voltage main junction), and J3 junction (gate cathode junction). The cathode and gate are connected by a trench forming a step. Looking at the GCT chip laterally, N... + The emitter area is arranged in a sector arc or circumference evenly on a wafer.

[0004] With the expanding applications of IGCT devices in the power grid field, IGCTs continue to develop towards higher voltage, higher current carrying capacity, and higher turn-off capability. Based on the traditional trench gate GCT structure, the current carrying capacity and turn-off capability of IGCT devices are limited by the N-axis of the GCT. + The current processing capability of the emitter region is limited by the N of the GCT. + Launch area design. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an asymmetric GCT chip that increases the effective cathode area and further enhances the chip's current carrying capacity.

[0006] This invention provides an asymmetric GCT chip, comprising P layers stacked sequentially from bottom to top. + Transparent emitting anode, N - base region, P base region and P + Base region and partially embedded P + N in the base region + Launch area; or P + Transparent emitting anode with N - An N′ buffer layer is provided between the base regions; The N+ The center of the emission area is provided with a groove, and the groove contains a cathode metal layer that is led out.

[0007] Optionally, the planar shape of the groove is a rounded rectangle. A rounded rectangle is a special rectangle whose four corners are rounded.

[0008] Optionally, the two ends of the groove are arc-shaped structures, the length of the groove is 50μm~6mm, the width is 10μm~500μm, and the depth is 2μm~50μm.

[0009] Optionally, the width of the groove is 80μm~120μm and the depth is 5μm~10μm.

[0010] Optionally, the N + The doping concentration of the emitter region is 1E22~5E17 cm⁻¹ -3 Its diffusion depth is 2~50μm.

[0011] Optionally, the doping concentration of the P-based region is 2E16~1E13 cm⁻¹. -3 The diffusion depth is 60μm~200μm.

[0012] Optionally, the P + The doping concentration of the transparent emitting anode is 1E15~5E18cm. -3 The diffusion depth is 0.5μm~80μm.

[0013] Optionally, the P + The base region doping concentration is 2E18~1E17cm. -3 Its diffusion depth is typically 40μm~80μm.

[0014] Optionally, the N + The emission area is a rounded rectangular strip with multiple N-shaped sections. + The emission areas are arranged radially on the cathode surface.

[0015] Optionally, the P + A gate metal layer is connected to the top of the base region, and N + The top surface of the launch area and P + The height difference of the top surface of the base region does not exceed 30 μm.

[0016] Optionally, P + The bottom surface of the transparent emitting anode is connected to an anode metal layer; there are three PN junctions inside the device, which, from the anode to the cathode, are the J1 junction (anode transparent junction), the J2 junction (blocking voltage main junction), and the gate cathode junction (J3 junction). Among them, the J1 junction exists in the P... + Transparent emitting anode with N′ buffer layer or N -Between the base regions, the J2 junction exists in N. - Between the base region and the P base region, the J3 junction exists in the N region. + Launch area and P + Between the base regions, and the J3 junction forms with N. + The recessed area of ​​the emitter region is adapted to the concave shape. The concave J3 junction increases the current gain of the GCT equivalent npn equivalent transistor, thereby enhancing the carrier emission capability and improving the carrier conductance modulation effect in the on-state of the device, thus improving the current carrying capacity of the device.

[0017] The beneficial effects of this invention are that the asymmetric GCT chip provided by this invention adopts a comb structure with grooves, which increases the effective cathode area and reduces N under the same chip size. + P below the launch area + By adjusting the base region doping concentration and introducing a concave comb structure, the effective cathode area is increased within the same chip size, thereby improving the chip's current carrying capacity. Furthermore, the junction depth of the J3 junction remains essentially unchanged, thus enhancing the current carrying capacity without reducing the turn-off capability. Attached Figure Description

[0018] Figure 1 This is a schematic longitudinal section of the asymmetric GCT chip of the present invention; Figure 2 N is the GCT chip of this invention. + Schematic diagram of the longitudinal section of the launch area; Figure 3 N is the GCT chip of this invention. + A top-down view of the launch area; Figure 4 N is the GCT chip of this invention. + Schematic diagram of the distribution structure of the launch area; Figure 5 This is a simulation diagram illustrating the doping depth of the asymmetric GCT chip of the present invention. Figure 6 For the present invention N + Curves showing the influence of different groove widths in the emitter region on the GCT on-state characteristics; Figure 7 For the present invention N + The effect curves of different groove depths in the emitter region on the GCT on-state characteristics.

[0019] In the diagram: 1, P + 1. Transparent emitting anode; 2. N′ buffer layer; 3. N - 4. P base region; 5. P base region + Base region; 6, N + Emitter region; 61, Groove; 7, Anode metal layer; 8, Gate metal layer; 9, Cathode metal layer; 10, J1 junction; 11, J2 junction; 12, J3 junction. Detailed Implementation

[0020] like Figure 1 As shown, the present invention provides an asymmetric GCT chip, comprising P layers stacked sequentially from bottom to top. + Transparent emitting anode 1, N - Base region 3, P base region 4 and P + Base region 5 and partially embedded P + N in base region 5 + Launch area 6; or P + Transparent emitting anode 1 and N - An N′ buffer layer 2 is provided between the base regions 3; N + The center of the emission area 6 is provided with a groove 61, and the groove 61 contains a cathode metal layer 9 which is led out.

[0021] Compared with the prior art, the asymmetric GCT chip provided by the present invention uses an N-type GCT chip with a groove 61. + Emitter region 6: Under the same chip size, increasing the effective cathode area reduces No. + Below launch area 6, P + The base region has a doping concentration of 5. A concave comb structure is introduced to increase the effective cathode area within the same chip size, thereby improving the chip's current carrying capacity. Furthermore, the junction depth of J3 junction 12 remains essentially unchanged, thus enhancing the current carrying capacity without reducing the turn-off capability.

[0022] like Figure 2 As shown, the present invention N + The width x1 of the recess 61 in emitter region 6 is 10μm~500μm, the length y1 is 50μm~6mm, and the depth h is 2μm~50μm. The on-state voltage drop of the device typically decreases with increasing recess width / length and recess depth, as shown in the subsequent simulation. Figure 5 Considering the trade-off design between device turn-off and on-state characteristics, preferably, the width x1 of the groove 61 is 80~120μm and the depth h is 5~10μm.

[0023] The N of GCT described in this invention + Emitter region 6, with a doping concentration of X jN+ 1E22~5E17cm -3 Its diffusion depth is 2μm~50μm, and the diffusion depth X in the concave region is... jN+ Also ranging from 2μm to 50μm, the specific design depends on the trade-off requirements between device turn-off and current-carrying capabilities.

[0024] like Figure 3 and Figure 4 As shown, the GCT chip N of the present invention +The emission area 6 is typically designed as a rounded rectangular strip with multiple N-shaped sections. + The emission region 6 is arranged in a circular pattern on the cathode surface. Considering the utilization rate of the chip cathode area and the device turn-off characteristics, the cathode is typically designed with a strip-shaped shape, with a width x0 of 40μm to 600μm and a length y0 of 200μm to 6mm.

[0025] GCT's P + The doping concentration of the short base region is 2E18~1E17 cm⁻¹ -3 Its diffusion depth is typically 40μm~80μm, depending on the trade-off requirements of the device's trigger, on-state and turn-off characteristics.

[0026] like Figure 2 As shown, the peak doping concentration of the P-based region 4 of GCT is 2E16~1E13 cm⁻¹. -3 Its diffusion depth X jP The value ranges from 60μm to 200μm, depending on the trade-off between blocking voltage and on-state loss.

[0027] GCT's N - The base region 3 (or containing N′ buffer layer 2), its doping concentration and its width depend on the blocking voltage design.

[0028] GCT's P + Transparent emitting anode 1, with a doping concentration of 5E18~1E15cm⁻¹ -3 The diffusion depth is approximately 0.5 μm to 80 μm, depending on the device design characteristics.

[0029] P + The base region 5 is typically led out through one or more stacked gate metal layers 8, and N + The top surface of launch area 6 and P + The height difference h of the top surface of base region 5 does not exceed 30μm. The height difference depends on the device's trigger and turn-off characteristics design. When the height difference is 0, the GCT is a planar GCT design.

[0030] N + The recess 61 of the emission area 6 is filled by one or more stacked cathode metal layers 9, N + The emitter layer is typically led out through one or more stacked cathode metal layers 9.

[0031] P + The transparent emitting anode 1 is typically led out through one or more stacked gate metal layers 8.

[0032] P +The bottom surface of the transparent emitting anode 1 is connected to an anode metal layer 7; there are three PN junctions inside the device, which are J1 junction 10 (anode transparent junction), J2 junction 11 (blocking voltage main junction), and J3 junction 13 (gate cathode junction) from the anode to the cathode. Among them, the J1 junction 10 exists in the P + Transparent emitting anode 1 and N′ buffer layer 2 or N - Between base region 3, J2 junction 11 exists in N. - Between base region 3 and base region 4, junction J312 exists in N. + Launch Zone 6 and P + Between base region 5, and J3 junction 12 is formed with N. + The recess 61 of the emitter region 6 is adapted to the concave shape. The concave J3 junction 12 increases the current gain of the GCT equivalent npn equivalent transistor, thereby enhancing the carrier emission capability and improving the carrier conductance modulation effect in the on-state of the device, thus improving the current carrying capacity of the device.

[0033] like Figure 6 As shown, the groove is a rounded rectangle with rounded ends. For a 4-inch GCT comb structure, keeping the comb length design constant and the groove depth 10μm, the on-state current-voltage characteristic curves of the GCT chip under different groove widths (61) are as follows: Compared to the standard structure, for a current of 4000A, N + After the emitter region 6 has a groove 61 structure, the on-state voltage drop of the GCT chip is reduced from 2.1V to 1.8V, a reduction of 14%.

[0034] like Figure 7 As shown, the groove is a rounded rectangle with rounded ends. For a 4-inch GCT comb structure, keeping the comb length design constant and the groove width 120μm, the on-state current-voltage characteristic curves of the GCT chip at different groove depths of 61 are as follows: Compared to the standard structure, for a current of 4000A, N + After the emitter region 6 incorporates the groove 61 structure, the on-state voltage drop of the GCT chip decreases from 2.0V to 1.7V, a reduction of 15%. The results show that N + The emitter region 6 has a groove 61 structure, which increases the effective cathode area and improves the current carrying capacity of the chip under the same chip size.

[0035] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of protection of this application is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of one or more embodiments of this application as described above, which are not provided in detail for the sake of brevity.

[0036] One or more embodiments in this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of this application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments in this application should be included within the protection scope of this application.

Claims

1. An asymmetric GCT chip, characterized in that, Including P arranged in layers from bottom to top + Transparent emitting anode (1), N - Base region (3), P base region (4) and P + Base region (5) and partially embedded P + N in base region (5) + Launch area (6); The N + The center of the emission area (6) is provided with a groove (61), and the groove (61) contains a cathode metal layer (9) which is led out.

2. The asymmetric GCT chip according to claim 1, characterized in that, The P + Transparent emitting anode (1) and N - An N′ buffer layer (2) is provided between the base regions (3).

3. The asymmetric GCT chip according to claim 1, characterized in that, The planar shape of the groove (61) is a rounded rectangle.

4. The asymmetric GCT chip according to claim 3, characterized in that, The groove (61) has arc-shaped structures at both ends. The length of the groove (61) is 50μm~6mm, the width is 10μm~500μm, and the depth is 2μm~50μm.

5. The asymmetric GCT chip according to claim 4, characterized in that, The groove (61) has a width of 80μm~120μm and a depth of 5μm~10μm.

6. The asymmetric GCT chip according to any one of claims 1-5, characterized in that, The N + The doping concentration of the emitter region (6) is 1E22~5E17 cm⁻¹ -3 Its diffusion depth is 2~50μm.

7. The asymmetric GCT chip according to any one of claims 1-5, characterized in that, The doping concentration of the P-based region (4) is 2E16~1E13 cm⁻¹ -3 The diffusion depth is 60μm~200μm.

8. The asymmetric GCT chip according to any one of claims 1-5, characterized in that, The P + The doping concentration of the transparent emitting anode (1) is 1E15~5E18 cm⁻¹ -3 The diffusion depth is 0.5μm~80μm.

9. The asymmetric GCT chip according to any one of claims 1-5, characterized in that, The P + The doping concentration of the base region (5) is 2E18~1E17 cm⁻¹ -3 Its diffusion depth is typically 40μm~80μm.

10. The asymmetric GCT chip according to any one of claims 1-5, characterized in that, The P + The top surface of the base region (5) is connected to a gate metal layer (8), and N + The top surface of the launch area (6) and P + The height difference of the top surface of the base region (5) does not exceed 30 μm.

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