Semiconductor device and forming method thereof

Abstract

The embodiment of the invention discloses a semiconductor device and a forming method thereof. The semiconductor device in the embodiment of the invention comprises a semiconductor substrate, a doped region, a deep termination structure and at least one source electrode region and drain electrode region. Wherein the doped region is formed on the semiconductor substrate, the doped region comprises a deep terminal groove, the deep terminal groove extends into the doped region from the upper surface of the doped region, the deep terminal structure is formed in the deep terminal groove, and the source region and the drain region are respectively formed in the doped region at two sides of the deep terminal structure. Therefore, the deep terminal structure is formed in the doped region, and the source region and the drain region are respectively formed in the doped regions on the two sides of the deep terminal structure, so that the gate charge of the planar architecture device can be reduced, and the power density of the planar architecture device can be improved.

Description

[0001] This application claims priority to Chinese Patent Application No. 202512059113.X, filed on December 31, 2025, entitled "Semiconductor Device and Method of Forming Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for forming the same. Background Technology

[0003] Currently, due to limitations in device spacing (e.g., field plate and drift region dimensions), planar architecture devices typically suffer from high gate charge and low power density. Therefore, there is an urgent need for a planar architecture device design scheme with low gate charge and high power density. Summary of the Invention

[0004] In view of this, the object of the present invention is to provide a semiconductor device and a method for forming the same, so as to reduce the gate charge of the planar architecture device and improve the power density of the planar architecture device.

[0005] In a first aspect, embodiments of the present invention aim to provide a semiconductor device, the semiconductor device comprising: Semiconductor substrate; A doped region is formed on the semiconductor substrate, the doped region including a deep termination trench extending from the upper surface of the doped region into the doped region; A deep terminal structure is formed within the deep terminal trench; and At least one source region and one drain region are formed on both sides of the deep terminal structure.

[0006] Furthermore, the semiconductor device further includes: At least one gate structure for modulating charge carriers in a semiconductor channel located below or to the side thereon, wherein the deep termination structure is located between the gate structure and the drain region for optimizing the electric field distribution near the drain region.

[0007] Furthermore, the doped region also includes a gate trench, which is formed on one side of the deep termination structure and extends from the upper surface of the doped region into the doped region; The gate structure includes: A vertical gate structure, formed within the gate trench, is used to regulate charge carriers in the vertical semiconductor channel located to its side.

[0008] Furthermore, the depth of the deep terminal structure is greater than the depth of the vertical gate structure.

[0009] Furthermore, the vertical gate structure includes a first shielding dielectric layer, a first shielding gate, a first gate dielectric layer, and a first control gate, wherein the first shielding dielectric layer is located at the bottom and lower sidewall of the gate trench and isolates the first shielding gate from the doped region; the first gate dielectric layer is located at the upper sidewall of the gate trench and isolates the first control gate from the doped region; and the first gate dielectric layer is also located between the first shielding gate and the first control gate and isolates the first shielding gate from the first control gate.

[0010] Furthermore, the semiconductor device further includes: A buried layer is formed between the semiconductor substrate and the doped region; At least one body region is formed within the doped region, and the at least one body region is located on one or both sides of the vertical gate structure, and each of the source regions is formed within the corresponding body region; The sinking region is located below the drain region and is in contact with the drain region and the buried layer.

[0011] Furthermore, a Schottky diode is formed at the contact position between the sunken area and the buried layer.

[0012] Furthermore, the doped region is a deep well region, the buried layer and the doped region are of the first doping type, and the bulk region is of the second doping type.

[0013] Furthermore, the body region includes a first body region, wherein, between the vertical gate structure and the deep terminal structure, the first body region is formed in a first region near the vertical gate structure and is spaced apart from the deep terminal structure.

[0014] Furthermore, the gate structure also includes: A planar gate structure is formed on the doped region. The first body region includes a first source region, a body contact region, and a second source region in sequence along the direction towards the drain region. The planar gate structure covers the region between the second source region and the deep termination structure in the vertical spatial direction, and is used to regulate the carriers in the horizontal semiconductor channel located below it.

[0015] Furthermore, when the semiconductor device is in operation, each of the source regions except the second source region forms a first carrier path, and the second source region forms a second carrier path. The first carrier path includes a longitudinal path portion that extends through the doped region to the buried layer and a transport path portion that extends through the buried layer and the sinked region to the drain region. The second carrier path includes a transverse path portion that extends across the doped region, a longitudinal path portion that extends through the doped region to the buried layer, and a transport path portion that extends through the buried layer and the sinked region to the drain region.

[0016] Furthermore, the body region includes a first body region, which is formed between the vertical gate structure and the deep terminal structure, and has its two sides in contact with the vertical gate structure and the deep terminal structure, respectively.

[0017] Furthermore, the first body region includes, in sequence, a first source region, a body contact region, and a second source region along the direction toward the drain region. The first source region is in contact with the vertical gate structure, and the second source region is in contact with the deep termination structure.

[0018] Furthermore, the first body region includes a first source region and a body contact region in sequence along the direction towards the drain region, and the first source region is in contact with the vertical gate structure.

[0019] Furthermore, the deep terminal structure is reused as a gate structure to regulate charge carriers in the vertical semiconductor channel located on its side.

[0020] Furthermore, the deep termination structure includes a second shielding dielectric layer, a second shielding gate, a second gate dielectric layer, and a second control gate. The second shielding dielectric layer is located at the bottom and lower sidewall of the deep termination trench and isolates the second shielding gate from the doped region. The second gate dielectric layer is located at the upper sidewall of the deep termination trench and isolates the second control gate from the doped region. The second shielding dielectric layer is also located between the second shielding gate and the second control gate and isolates the second shielding gate from the second control gate.

[0021] Furthermore, when the semiconductor device is in operation, each of the source regions forms a first carrier path, the first carrier path including a longitudinal path portion that extends longitudinally through the doped region to the buried layer and a transport path portion that extends through the buried layer and the sinking region to the drain region.

[0022] Furthermore, the second control gate is an offset gate, and the offset direction of the second control gate is closer to the direction where the first body region is located.

[0023] Furthermore, the semiconductor device further includes: A buried layer is formed between the semiconductor substrate and the doped region; A body region is located on one side of the deep terminal structure. The body region is formed on the upper surface of the semiconductor substrate. The source region is formed within the body region. The body region is adjacent to the doped region. A planar gate structure is formed on the doped region, the planar gate structure covering the region between the source region and the deep termination structure in the vertical spatial direction, for regulating the carriers in the horizontal semiconductor channel located below it.

[0024] Furthermore, the body region is in contact with the buried layer.

[0025] Furthermore, the semiconductor device further includes: The sink region is located below the drain region and extends from the upper surface of the doped region into the doped region.

[0026] Furthermore, when the semiconductor device is in operation, a third carrier path is formed in the source region. The third carrier path includes a lateral path portion that crosses the doped region, a longitudinal path portion that crosses the doped region, and a transport path portion that reaches the drain region via the sinking region.

[0027] Furthermore, the doped region is a drift region, the doping type of the doped region is a first doping type, and the doping type of the body region is a second doping type.

[0028] Furthermore, the deep termination structure includes an isolation conductor layer and a third shielding dielectric layer, wherein the third shielding dielectric layer is formed at the bottom and sidewalls of the deep termination trench and isolates the isolation conductor layer from the doped region.

[0029] Furthermore, the doped region also includes a first trench, and the sinking region includes a conductive material filling the first trench.

[0030] Secondly, embodiments of the present invention aim to provide a method for forming a semiconductor device, the method comprising: Provide semiconductor substrates; A doped region is formed on the semiconductor substrate, the doped region including a deep termination trench extending from the upper surface of the doped region into the doped region; A deep terminal structure is formed within the deep terminal trench; and At least one source region and one drain region are formed on both sides of the deep terminal structure.

[0031] Furthermore, the method also includes: A gate trench is formed in the doped region, extending from the upper surface of the doped region into the doped region. The gate trench and the deep termination trench are formed simultaneously. A vertical gate structure is formed in the gate trench.

[0032] Furthermore, the method also includes: A planar gate structure is formed on the upper surface of the doped region.

[0033] Furthermore, the method also includes: At least one body region is formed within the doped region, the at least one body region being located on one or both sides of the vertical gate structure, or located below a portion of the planar gate structure, and each source region is formed within the corresponding body region.

[0034] Furthermore, the method also includes: A sinking region is formed, which is located below the drain region; The method for forming the sinking zone includes: A first trench is formed in the doped region, and The first trench is filled with conductive material.

[0035] Furthermore, the deep terminal structure is adjacent to the drain region.

[0036] The semiconductor device in this embodiment of the invention includes a semiconductor substrate, a doped region, a deep termination structure, and at least one source region and a drain region. The doped region is formed on the semiconductor substrate and includes a deep termination trench extending from the upper surface of the doped region into the doped region. The deep termination structure is formed within the deep termination trench, and the source and drain regions are respectively formed within the doped regions on both sides of the deep termination structure. Therefore, by forming a deep termination structure within the doped region and forming the source and drain regions within the doped regions on both sides of the deep termination structure, this embodiment of the invention can reduce the gate charge of the planar architecture device and increase the power density of the planar architecture device. Attached Figure Description

[0037] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 3 This is a schematic diagram of another semiconductor device according to an embodiment of the present invention; Figure 4This is a schematic diagram of another semiconductor device according to an embodiment of the present invention; Figure 5 This is a schematic diagram of another semiconductor device according to an embodiment of the present invention; Figure 6 This is a flowchart of a semiconductor device formation method according to an embodiment of the present invention; Figures 7 to 15 This is a schematic diagram illustrating the formation process of a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0038] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0039] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0040] Unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0041] For ease of explanation, spatially related terms such as “inside,” “outside,” “below,” “below,” “lower,” “above,” “upper,” etc., are used herein to describe the relationship between one element or feature illustrated in the figure and another. It will be understood that spatially related terms may be intended to encompass different orientations of the device in use or operation besides those depicted in the figure. For example, if the device in the figure is flipped, an element described as “below” or “below” another element or feature would then be positioned “above” that other element or feature. Thus, the exemplified term “below” can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptive terms used herein should be interpreted accordingly.

[0042] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0043] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0044] In this embodiment of the invention, the semiconductor device may include a semiconductor substrate, a doped region, a deep termination structure, and at least one source region and a drain region. The semiconductor substrate may be located at the bottom layer of the semiconductor device. The semiconductor substrate serves as the carrier of the entire semiconductor device, providing necessary physical support during device fabrication and after device formation. The doped region may be formed on the semiconductor substrate. The doped region serves as the core carrier region of the semiconductor device, supporting the formed core structure of the device. The doped region may include a deep termination trench extending from its upper surface into its interior. The deep termination structure may be formed within the deep termination trench. The source region and drain region may be formed within the doped regions on either side of the deep termination structure, respectively. The deep termination structure, source region, and drain region serve as the core structure of the semiconductor device, realizing the electrical characteristics exhibited by the semiconductor device. The source region and drain region can be formed by implanting corresponding types of dopant ions into corresponding regions within the doped region. Therefore, by forming a deep termination structure within the doped region and forming the source and drain regions within the doped regions on both sides of the deep termination structure, the embodiments of the present invention can reduce the gate charge of planar architecture devices and increase the power density of planar architecture devices.

[0045] Optionally, in addition to the semiconductor substrate, doped region, deep termination structure, source region, and drain region, the semiconductor device may also include at least one gate structure. The gate structure can be used to modulate carriers in the semiconductor channel below it, or to modulate carriers in the semiconductor channel to its side; this application is not limited in this regard. Furthermore, the deep termination structure may specifically be located between the gate structure and the drain region to optimize the electric field distribution near the drain region.

[0046] Optionally, in embodiments of the present invention, the gate structure may include a planar gate structure, a vertical gate structure, or a gate structure formed by multiplexing a deep termination structure; this application does not impose any limitations on this. By forming different gate structures, embodiments of the present invention can obtain different types of semiconductor devices. For ease of understanding, various types of semiconductor devices will be described separately below.

[0047] Figure 1 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention. It is intended to be noted that... Figure 1 The semiconductor device shown can be obtained by forming a planar gate structure on a doped region. For example... Figure 1 As shown, the semiconductor device 1 includes a semiconductor substrate 11, a doped region 12, a deep termination structure 13, a source region 14, and a drain region 15.

[0048] exist Figure 1 In the semiconductor device 1 shown, the semiconductor substrate 11 may be located at the bottom layer of the semiconductor device 1. A doped region 12 may be formed on the semiconductor substrate 11. The doped region 12 may include a deep termination trench extending from its upper surface into its interior. A deep termination structure 13 may be formed within the deep termination trench. A source region 14 and a drain region 15 may be formed on both sides of the deep termination structure 13, respectively, with the deep termination structure 13 adjacent to the drain region 15, and further, the deep termination structure 13 in contact with the drain region 15.

[0049] Optionally, in the semiconductor device 1, the deep termination structure 13 may include an isolation conductor layer 131 and a third shielding dielectric layer 132, wherein the third shielding dielectric layer 132 may be formed on the bottom and sidewalls of the deep termination trench and isolates the isolation conductor layer 131 from the doped region 12. As one implementation, the isolation conductor layer 131 may be a polysilicon layer or other suitable conductive material. The third shielding dielectric layer 132 may be a shielding oxide layer. The deep termination structure 13 can be formed by sequentially depositing a shielding oxide layer and a polysilicon layer in the deep termination trench. Thus, by configuring the deep termination structure 13 to include an isolation conductor layer 131 and a third shielding dielectric layer 132, embodiments of the present invention can reuse the deep termination structure 13 as a shielding gate to reduce Cgd (Gate-to-Drain Capacitance) in the semiconductor device 1 during high-speed applications.

[0050] Optionally, in semiconductor device 1, the gate structure may include a planar gate structure 16. The planar gate structure 16 may be formed on the doped region 12. The planar gate structure 16 can be used to modulate carriers in the horizontal semiconductor channel located below it (specifically, in the region below the body region of the planar gate structure 16, close to the planar gate structure 16). It is worth noting that, to ensure that the modulating range of the planar gate structure 16 covers the horizontal semiconductor channel located below it, the planar gate structure 16 may cover the region between the source region 14 and the deep termination structure 13 in the vertical spatial direction. Furthermore, as one implementation, the planar gate structure 16 may include a gate oxide 161 and a gate conductor 162. The gate oxide 161 may be a very thin layer of silicon dioxide (SiO2) or other high-k dielectric material, which can be used to isolate the gate conductor from the underlying semiconductor channel. The gate conductor 162 can be used to apply a control voltage to modulate the carrier concentration in the channel. The gate conductor 162 may be a polysilicon layer or other suitable conductive material. Furthermore, the planar gate structure 16 may also include sidewalls 163 covering both sides of the gate conductor, which is not a limitation of this application.

[0051] Optionally, the semiconductor device 1 may further include a buried layer 17 and a body region 18. The buried layer 17 may be formed between the semiconductor substrate 11 and the doped region 12. The body region 18 may be located on one side of the deep termination structure 13 and is separated from the deep termination structure 13. The body region 18 may be located on the upper surface of the semiconductor substrate 11 and adjacent to the doped region 12. A source region 14 may be formed within the body region 18, and a drain region 15 may be formed within the doped region 12. It is worth noting that in this embodiment of the invention, the body region 18 may extend downwards and contact the semiconductor substrate 11. Thus, by contacting the body region 18 with the semiconductor substrate 11, this embodiment of the invention can achieve charge balance and pinch-off the channel to protect the gate oxide layer under high voltage. However, it should be understood that in some embodiments, the body region may not contact the buried layer, and this application does not impose limitations on this.

[0052] Optionally, the semiconductor device 1 may further include a sunken region 19. The sunken region 19 may be located below the drain region 15 and extend from the upper surface of the doped region 12 into the interior of the doped region 12. The sunken region 19 is not in contact with the buried layer 17. In this embodiment, the sunken region 19 can be considered as a low-resistance vertical lead structure, which can provide a low-resistance path for charge carriers to move to the drain region. Furthermore, as an implementation, the sunken region 19 may be a metal pillar or a doped region with a high doping concentration; this application is not limited in this regard. Thus, by forming the sunken region 19 within the doped region, this embodiment of the invention can provide a low-resistance path for charge carriers to move to the drain region, thereby reducing the on-resistance of the semiconductor device 1.

[0053] Alternatively, in the semiconductor device 1, the source region 14 may have a corresponding body contact region 110. The body contact region 110 may be formed side by side with the corresponding source region 14 within the body region 18.

[0054] Optionally, in the semiconductor device 1, the doped region 12 can be a drift region. The doping type of the doped region 12 can be a first doping type, and the doping type of the bulk region 18 can be a second doping type. Furthermore, the semiconductor substrate 11 can be of the second doping type, and the doping type of the buried layer 17 can also be of the second doping type. The first and second doping types can be opposite. Thus, by setting the doped region 12 and the buried layer 17 to different doping types, embodiments of the present invention can use the buried layer 17 as a RESURF (Reduced Surface Field) layer to introduce impact ionization into the bulk, thereby enhancing the robustness of the semiconductor device 1.

[0055] It is worth noting that when the semiconductor device 1 is in operation, a third carrier path can be formed from the source region 14 to the drain region 15. The third carrier path may include a lateral path portion L11 that crosses the doped region 12 below the planar gate structure 16, a longitudinal path portion L12 that crosses the doped region 12, and a transport path portion L13 that reaches the drain region 15 via the sink region 19.

[0056] It is worth noting that, in this embodiment of the invention, the semiconductor device 1 can be a low-side field-effect transistor (FET), which has a low overall figure of merit for switching (i.e., the product of on-resistance and gate charge. On-resistance directly affects conduction losses, while gate charge determines switching speed, thus affecting switching losses. The lower the product, the better the overall performance of the device in reducing conduction and switching losses). Furthermore, as a low-side FET, the body region 18 of the semiconductor device 1 and the substrate 11 can be connected to the same potential.

[0057] Optionally, for Figure 1 The semiconductor device shown is designed to enable its application as a low-side field-effect transistor.

[0058] Figure 2 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 2 As shown, a deep well region 12' can be formed on the semiconductor substrate 11'. Furthermore, a body region 13', a buried layer 15', and a doped region 14' can be formed on the deep well region 12'. It is worth noting that, in addition to the additional formation of the deep well region, Figure 2 The structures of the semiconductor device 1' shown are similar to Figure 1The semiconductor devices shown are all identical in structure, therefore, they will not be described further here. Figure 2 The other structures of the semiconductor device 1' shown will be described in detail. It should be understood that the semiconductor device 1' can be a high-side field-effect transistor with a low gate charge (Qg). Also, as a high-side field-effect transistor, the body region 13' of the semiconductor device 1' and the substrate 11' can be connected to different potentials.

[0059] It should be noted that, in the embodiments of the present invention, the drift region and the deep well region can refer to two doped regions with different doping concentrations. The implantation energy of the deep well region is greater than that of the drift region, and the doping concentration of the deep well region is less than that of the drift region. The specific doping concentrations can be set by those skilled in the art according to actual needs, and this application does not impose excessive limitations. Furthermore, in the embodiments of the present invention, the semiconductor substrate may include a substrate. Alternatively, the semiconductor substrate may also include a substrate and an epitaxial layer located on the substrate. When the semiconductor substrate includes a substrate, the body region and the drift region can be formed in the substrate. When the semiconductor substrate includes a substrate and an epitaxial layer located on the substrate, the body region and the drift region can be formed in the epitaxial layer.

[0060] Figure 3 This is a schematic diagram of another semiconductor device according to an embodiment of the present invention. It is intended to illustrate that... Figure 3 The semiconductor device shown can be obtained by forming a vertical gate structure within a doped region. For example... Figure 3 As shown, the semiconductor device 2 includes a semiconductor substrate 21, a doped region 22, a deep termination structure 23, a source region 24, and a drain region 25.

[0061] exist Figure 3 In the semiconductor device 2 shown, the semiconductor substrate 21 may be located at the bottom layer of the semiconductor device 2. A doped region 22 may be formed on the semiconductor substrate 21. The doped region 22 may include a deep termination trench extending from its upper surface into its interior. A deep termination structure 23 may be formed within the deep termination trench. A source region 24 and a drain region 25 may be formed in the doped region 22 on both sides (or one side) of the deep termination structure 23, respectively.

[0062] Optionally, in the semiconductor device 2, the deep termination structure 23 may include an isolation conductor layer 231 and a third shielding dielectric layer 232, wherein the third shielding dielectric layer 232 may be formed at the bottom and sidewalls of the deep termination trench, and isolates the isolation conductor layer 231 from the doped region 22. As one implementation, the isolation conductor layer 231 may be a polysilicon layer or other suitable conductive material. The third shielding dielectric layer 232 may be a shielding oxide layer. The deep termination structure 23 can be formed by sequentially depositing a shielding oxide layer and a polysilicon layer in the deep termination trench. Thus, by configuring the deep termination structure 23 to include an isolation conductor layer 231 and a third shielding dielectric layer 232, embodiments of the present invention can reuse the deep termination structure 23 as a shielding gate to reduce Cgd (Gate-to-Drain Capacitance) in high-speed applications of the semiconductor device 2.

[0063] Optionally, in semiconductor device 2, the gate structure may include a vertical gate structure 26. The doped region 22 may further include a gate trench extending from the upper surface of the doped region 22 into the interior of the doped region 22, the gate trench being formed on the side of the deep termination structure 23 away from the drain region 25. The vertical gate structure 26 may be formed within the gate trench. It is intended that the vertical gate structure 26 can be used to modulate carriers in the vertical semiconductor channels located to its side (specifically, in the regions located on both sides of the vertical gate structure 26, close to the vertical gate structure 26).

[0064] Alternatively, in the semiconductor device 2, the depth of the deep termination structure 23 is greater than the depth of the vertical gate structure 26.

[0065] Optionally, in the semiconductor device 2, the vertical gate structure 26 may include a first shielding dielectric layer 261, a first shielding gate 262, a first gate dielectric layer 263, and a first control gate 264. The first shielding dielectric layer 261 may be located at the bottom and lower sidewall of the gate trench, isolating the first shielding gate 262 from the doped region 22. The first gate dielectric layer 263 may be located at the upper sidewall of the gate trench, isolating the first control gate 264 from the doped region 22. The first gate dielectric layer 263 also includes a portion located between the first shielding gate 262 and the first control gate 264, isolating the first shielding gate 262 from the first control gate 264. As one implementation, the first shielding dielectric layer 261 and the first gate dielectric layer 263 may be shielding oxide layers. The first shielding gate 262 and the first control gate 264 may be polysilicon layers or other suitable conductive materials. In an alternative embodiment, the first shielding gate 262 may be configured in a stepped shape, with its width gradually increasing from bottom to top, thereby better optimizing the electric field on its sides and below.

[0066] Optionally, the semiconductor device 2 may further include a buried layer 27, a body region 28, and a subsided region 29. The buried layer 27 may be formed between the semiconductor substrate 21 and the doped region 22. The body region 28 may be formed within the doped region 22 and may be located on both sides (or one side) of the vertical gate structure 26. Each source region 24 may be formed within its respective body region 28. The subsided region 29 may be located below the drain region 25. The subsided region 29 may contact the drain region 25 and the buried layer 27. In this embodiment, the buried layer 27 can be considered as a carrier collection structure that can collect carriers. The subsided region 29 can be considered as a low-resistance vertical lead structure that can provide a low-resistance path for carriers to move from the buried layer 27 to the drain region. Furthermore, as an implementation, the subsided region 29 may be a metal pillar or a doped region with a high doping concentration; this application is not limited in this regard. Therefore, by forming a buried layer 27 and a submerged region 29 in the doped region, the embodiments of the present invention can provide a low-resistance channel for charge carriers to move to the drain region, thereby reducing the on-resistance of the semiconductor device 2.

[0067] Alternatively, in the semiconductor device 2, each source region 24 may have a corresponding body contact region 210. The body contact region 210 may be formed side by side with the corresponding source region 24 within the body region 28.

[0068] Optionally, in the semiconductor device 2, the body region 28 may include a first body region A1. The first body region A1 may be formed between the vertical gate structure 26 and the deep termination structure 23, and its two sides may be in contact with the vertical gate structure 26 and the deep termination structure 23, respectively. The first body region A1 may sequentially include a first source region A2 and a body contact region A3 along the direction towards the drain region 25, and the first source region A2 may be in contact with the vertical gate structure 26.

[0069] Alternatively, a Schottky diode can be formed at the contact site between the sunken region 29 and the buried layer 27 in the semiconductor device 2. Therefore, by forming a Schottky diode at the contact site between the sunken region 29 and the buried layer 27, embodiments of the present invention can reduce the reverse recovery charge Qrr in high-speed applications.

[0070] Optionally, in semiconductor device 2, the doped region 22 can be a deep well region. The doping type of the buried layer 27 and the doped region 22 can be a first doping type. The doping type of the body region 28 can be a second doping type. Furthermore, the semiconductor substrate 21 can be of the second doping type. The first and second doping types can be opposite doping types.

[0071] It should be noted that, during operation, semiconductor device 2 can form a first carrier path from each source region to the drain region. This first carrier path may include a longitudinal path portion L21 extending through the doped region to the buried layer and a transport path portion L22 extending through the buried layer and the subsided region to the drain region. It should be understood that, since the first carrier paths of each source region are similar, therefore... Figure 3 Only the first carrier path of a single first source region A2 is shown in the diagram.

[0072] It should be noted that, in this embodiment of the invention, the semiconductor device 2 can be a high-side field-effect transistor.

[0073] Figure 4 This is a schematic diagram of another semiconductor device according to an embodiment of the present invention. It is intended to illustrate that... Figure 4 The semiconductor device shown can be obtained by forming a vertical gate structure on a doped region and a planar gate structure within the doped region. Figure 4 As shown, the semiconductor device 3 includes a semiconductor substrate 31, a doped region 32, a deep termination structure 33, a source region 34, and a drain region 35.

[0074] exist Figure 4 In the semiconductor device 3 shown, the semiconductor substrate 31 may be located at the bottom layer of the semiconductor device 3. A doped region 32 may be formed on the semiconductor substrate 31. The doped region 32 may include a deep termination trench extending from its upper surface into its interior. A deep termination structure 33 may be formed within the deep termination trench. A source region 34 and a drain region 35 may be formed within the doped regions 32 on both sides of the deep termination structure 33, respectively.

[0075] Optionally, in the semiconductor device 3, the deep termination structure 33 may include an isolation conductor layer 331 and a third shielding dielectric layer 332, wherein the third shielding dielectric layer 332 may be formed at the bottom and sidewalls of the deep termination trench, and isolates the isolation conductor layer 331 from the doped region 32. As one implementation, the isolation conductor layer 331 may be a polysilicon layer or other suitable conductive material. The third shielding dielectric layer 332 may be a shielding oxide layer. The deep termination structure 33 can be formed by sequentially depositing a shielding oxide layer and a polysilicon layer in the deep termination trench. Thus, by configuring the deep termination structure 33 to include an isolation conductor layer 331 and a third shielding dielectric layer 332, embodiments of the present invention can reuse the deep termination structure 33 as a shielding gate to reduce Cgd (Gate-to-Drain Capacitance) in the semiconductor device 3 during high-speed applications.

[0076] Optionally, in the semiconductor device 3, the gate structure may include a vertical gate structure 36. The doped region 32 may further include a gate trench extending from the upper surface of the doped region 32 into the interior of the doped region 32, the gate trench being formed on one side of the deep termination structure 33. The vertical gate structure 36 may be formed within the gate trench. It is intended to illustrate that the vertical gate structure 36 can be used to modulate charge carriers in the vertical semiconductor channels located to its side (specifically, in the regions located on both sides of the vertical gate structure 36, close to the vertical gate structure 36).

[0077] Alternatively, in the semiconductor device 3, the depth of the deep termination structure 33 may be greater than the depth of the vertical gate structure 36.

[0078] Optionally, in the semiconductor device 3, the vertical gate structure 36 may include a first shielding dielectric layer 361, a first shielding gate 362, a first gate dielectric layer 363, and a first control gate 364. The first shielding dielectric layer 361 may be located at the bottom and lower sidewall of the gate trench, isolating the first shielding gate 362 from the doped region 32. The first gate dielectric layer 363 may be located at the upper sidewall of the gate trench, isolating the first control gate 364 from the doped region 32. The first gate dielectric layer 363 also includes a portion located between the first shielding gate 362 and the first control gate 364, isolating the first shielding gate 362 from the first control gate 364. As one implementation, the first shielding dielectric layer 361 and the first gate dielectric layer 363 may be shielding oxide layers. The first shielding gate 362 and the first control gate 364 may be polysilicon layers or other suitable conductive materials.

[0079] Optionally, the semiconductor device 3 may further include a buried layer 37, a body region 38, and a subsided region 39. The buried layer 37 may be formed between the semiconductor substrate 31 and the doped region 32. The body region 38 may be formed within the doped region 32 and may be located on both sides (or on one side) of the vertical gate structure 36. Each source region 34 may be formed within its respective body region 38. The subsided region 39 may be located below the drain region 35. The subsided region 39 may contact the drain region 35 and the buried layer 37. In this embodiment, the buried layer 37 can be considered as a carrier collection structure that can collect carriers. The subsided region 39 can be considered as a low-resistance vertical lead structure that can provide a low-resistance path for carriers to move from the buried layer 37 to the drain region. Furthermore, as an implementation, the subsided region 39 may be a metal pillar or a doped region with a high doping concentration; this application is not limited in this regard. Therefore, by forming a buried layer 37 and a submerged region 39 in the doped region, the embodiments of the present invention can provide a low-resistance channel for charge carriers to move to the drain region, thereby reducing the on-resistance of the semiconductor device 3.

[0080] Alternatively, in the semiconductor device 3, each source region 34 may have a corresponding body contact region 310. The body contact region 310 may be formed side by side with the corresponding source region 34 within the body region 38.

[0081] Optionally, in the semiconductor device 3, the body region 38 may include a first body region B1. Specifically, between the vertical gate structure 36 and the deep termination structure 33, the first body region B1 may be formed in a first region near the vertical gate structure 36 and spaced apart from the deep termination structure 33. The first body region B1 may sequentially include a first source region B2, a body contact region B3, and a second source region B4 along the direction towards the drain region 35.

[0082] Optionally, in the semiconductor device 3, the gate structure may further include a planar gate structure 311. The planar gate structure 311 may be formed on the doped region 32, with a first side of the planar gate structure 311 adjacent to the second source region B4, and a second side of the planar gate structure 311 opposite to the first side adjacent to the deep termination structure 33. The planar gate structure 311 can be used to modulate carriers in the horizontal semiconductor channel located below it (specifically located in the region of the first body region B1 near the planar gate structure 311). It is worth noting that, to ensure that the modulation range of the planar gate structure 311 can cover the horizontal semiconductor channel located below it, the planar gate structure 311 may cover the region between the second source region B4 and the deep termination structure 33 in the vertical spatial direction. Furthermore, as one implementation, the planar gate structure 311 may include a gate oxide 3111 and a gate conductor 3112. The gate oxide 3111 may be a very thin layer of silicon dioxide (SiO2) or other high-k dielectric material, which can be used to isolate the gate conductor from the underlying semiconductor channel. The gate conductor 3112 can be used to apply a control voltage to modulate the carrier concentration in the channel. The gate conductor 3112 can be made of a polysilicon layer or other suitable conductive material. Furthermore, the planar gate structure 311 may also include sidewalls 3113 covering both sides of the gate conductor, which is not a limitation of this application.

[0083] Optionally, in semiconductor device 3, doped region 32 can be a deep well region. The doping type of buried layer 37 and doped region 32 can be a first doping type. The doping type of body region 38 can be a second doping type. And, semiconductor substrate 31 can be a second doping type. The first doping type and the second doping type can be opposite doping types.

[0084] It should be noted that when the semiconductor device 3 is operating, each source region except the second source region B4 can form a first carrier path, and the second source region B4 can form a second carrier path. The first carrier path may include a longitudinal path portion L31 that runs vertically from each source region through the doped region 32 to the buried layer 37, and a transport path portion L32 that runs through the buried layer 37 and the sinking region 39 to the drain region 35. The second carrier path may include a lateral path portion L31' that runs horizontally across the doped region 32 below the planar gate structure 311, a longitudinal path portion L32' that runs vertically through the doped region 32 to the buried layer 37, and a transport path portion L33' that runs through the buried layer 37 and the sinking region 39 to the drain region 35. It should be understood that since the first carrier paths of each source region except the second source region B4 are similar, therefore... Figure 4 Only the first carrier path of the single first source region B2 is marked.

[0085] Alternatively, a Schottky diode may be formed at the contact site between the sunken region 39 and the buried layer 37 in the semiconductor device 3. Thus, by forming a Schottky diode at the contact site between the sunken region 39 and the buried layer 37, embodiments of the present invention can reduce the reverse recovery charge Qrr in high-speed applications.

[0086] It should be noted that, in the embodiments of the present invention, the semiconductor device 3 can be a high-side field-effect transistor.

[0087] Figure 5 This is a schematic diagram of another semiconductor device according to an embodiment of the present invention. It is intended to illustrate that... Figure 5 The semiconductor device shown can be obtained by forming a vertical gate structure on a doped region and multiplexing a deep termination structure as a gate structure. For example... Figure 5 As shown, the semiconductor device 4 includes a semiconductor substrate 41, a doped region 42, a deep termination structure 43, a source region 44, and a drain region 45.

[0088] exist Figure 5 In the semiconductor device 4 shown, the semiconductor substrate 41 may be located at the bottom layer of the semiconductor device 4. A doped region 42 may be formed on the semiconductor substrate 41. The doped region 42 may include a deep termination trench extending from its upper surface into its interior. A deep termination structure 43 may be formed within the deep termination trench. A source region 44 and a drain region 45 may be formed within the doped regions 42 on both sides of the deep termination structure 43, respectively.

[0089] Optionally, in semiconductor device 4, the gate structure may include a vertical gate structure 46. The doped region 42 may further include a gate trench extending from the upper surface of the doped region 42 into the interior of the doped region 42, the gate trench being formed on one side of the deep termination structure 43. The vertical gate structure 46 may be formed within the gate trench. It is intended that the vertical gate structure 46 can be used to modulate charge carriers in vertical semiconductor channels located to its side (specifically, in the regions located on both sides of the vertical gate structure 46, close to the vertical gate structure 46).

[0090] Optionally, in the semiconductor device 4, the depth of the deep termination structure 43 may be greater than the depth of the vertical gate structure 46.

[0091] Optionally, the vertical gate structure 46 includes a first shielding dielectric layer 461, a first shielding gate 462, a first gate dielectric layer 463, and a first control gate 464. The first shielding dielectric layer 461 may be located at the bottom and lower sidewall of the gate trench, isolating the first shielding gate 462 from the doped region 42. The first gate dielectric layer 463 may be located at the upper sidewall of the gate trench, isolating the first control gate 464 from the doped region 42. The first gate dielectric layer 463 may further include a portion between the first shielding gate 462 and the first control gate 464, isolating the first shielding gate 462 from the first control gate 464. As one implementation, the first shielding dielectric layer 461 and the first gate dielectric layer 463 may be shielding oxide layers. The first shielding gate 462 and the first control gate 464 may be polysilicon layers or other suitable conductive materials.

[0092] Optionally, the semiconductor device 4 may further include a buried layer 47, a body region 48, and a subsided region 49. The buried layer 47 may be formed between the semiconductor substrate 41 and the doped region 42. The body region 48 may be formed within the doped region 42 and may be located on both sides (or on one side) of the vertical gate structure 46. Each source region 44 may be formed within its respective body region 48. The subsided region 49 may be located below the drain region 45. The subsided region 49 may contact the drain region 45 and the buried layer 47. In this embodiment, the buried layer 47 can be considered as a carrier collection structure that can collect carriers. The subsided region 49 can be considered as a low-resistance vertical lead structure that can provide a low-resistance path for carriers to move from the buried layer 47 to the drain region. Furthermore, as one implementation, the subsided region 49 may be a metal pillar or a doped region with a high doping concentration; this application is not limited in this regard. Therefore, by forming a buried layer 47 and a submerged region 49 in the doped region, the embodiments of the present invention can provide a low-resistance channel for charge carriers to move to the drain region, thereby reducing the on-resistance of the semiconductor device 4.

[0093] Alternatively, in the semiconductor device 4, each source region 44 may have a corresponding body contact region 410. The body contact region 410 may be formed side by side with the corresponding source region 44 within the body region 48.

[0094] Optionally, in the semiconductor device 4, the body region 48 may include a first body region C1. The first body region C1 may be formed between the vertical gate structure 46 and the deep termination structure 43, and its two sides are in contact with the vertical gate structure 46 and the deep termination structure 43, respectively. The first body region C1 may sequentially include a first source region C2, a body contact region C3, and a second source region C4 along the direction towards the drain region 45. The first source region C2 is in contact with the vertical gate structure 46, and the second source region C4 is in contact with the deep termination structure 43.

[0095] Optionally, in the semiconductor device 4, the gate structure may further include a deep termination structure 43. The deep termination structure 43 may be reused as a gate structure for regulating carriers in the vertical semiconductor channel located to its side (specifically located in the region of the first body region C1 near the deep termination structure 43).

[0096] Further optionally, in the semiconductor device 4, the doped region 42 can be a deep well region. The doping type of the buried layer 47 and the doped region 42 can be a first doping type. The doping type of the body region 48 can be a second doping type. And, the semiconductor substrate 41 can be a second doping type. The first doping type and the second doping type can be opposite doping types.

[0097] Optionally, in the semiconductor device 4, the deep termination structure 43 includes a second shielding dielectric layer 431, a second shielding gate 432, a second gate dielectric layer 433, and a second control gate 434. The second shielding dielectric layer 431 may be located at the bottom and lower sidewall of the deep termination trench, isolating the second shielding gate 432 from the doped region 42. The second gate dielectric layer 433 may be located at the upper sidewall of the deep termination trench, isolating the second control gate 434 from the doped region 42. The second gate dielectric layer 433 also includes a portion located between the second shielding gate 432 and the second control gate 434, isolating the second shielding gate 432 from the second control gate 434. As one implementation, the second shielding dielectric layer 431 and the second gate dielectric layer 433 may be shielding oxide layers. The second shielding gate 432 and the second control gate 434 may be polysilicon layers or other suitable conductive materials.

[0098] Further optionally, in order to improve the control effect of the deep terminal structure 43 as a gate structure, in the semiconductor device 4, the second control gate 434 can be an offset gate (a gate structure with an offset position), and the offset direction of the second control gate 434 can be the direction close to the first body region C1.

[0099] It should be noted that when the semiconductor device 4 is operating, each source region can form a first carrier path. This first carrier path may include a longitudinal path portion L41 that runs vertically from each source region through the doped region 42 to the buried layer 47, and a transport path portion L42 that runs via the buried layer 47 and the subsided region 49 to the drain region 45. It should be understood that the first carrier paths of each source region are similar; therefore, Figure 5 Only the first carrier path of a single first source region C2 is shown in the diagram.

[0100] Alternatively, a Schottky diode may be formed at the contact site between the sunken region 49 and the buried layer 47 in the semiconductor device 4. Thus, by forming a Schottky diode at the contact site between the sunken region 49 and the buried layer 47, embodiments of the present invention can reduce the reverse recovery charge Qrr in high-speed applications.

[0101] It should be noted that, in this embodiment of the invention, the semiconductor device 4 can be a high-side field-effect transistor.

[0102] Figure 6 This is a flowchart illustrating a semiconductor device formation method according to an embodiment of the present invention. It is intended to illustrate that by performing the following... Figure 6 The semiconductor device formation method shown in the present invention can form the semiconductor device as described above. Figure 6 As shown, the semiconductor device formation method may specifically include the following steps: Step S100: Provide a semiconductor substrate.

[0103] Specifically, this embodiment can provide a semiconductor substrate. The semiconductor substrate can be located at the bottom layer of the semiconductor device. The semiconductor substrate can serve as a carrier for the entire semiconductor device, providing necessary physical support for the entire semiconductor device during device manufacturing and after device formation.

[0104] Figures 7 to 15 This is a schematic diagram illustrating the formation process of a semiconductor device according to an embodiment of the present invention. Figure 7 As shown, this embodiment can provide a semiconductor substrate 61.

[0105] Optionally, in this embodiment, a buried layer may be formed on the semiconductor substrate before proceeding to form subsequent doped regions. For example... Figure 8 As shown, in this embodiment, a buried layer 62 can be formed on the semiconductor substrate 61. Alternatively, as a formation method, the buried layer 62 can be formed by implanting dopant ions into the semiconductor substrate 61.

[0106] It should be noted that, depending on the type of semiconductor device being formed, the doping types of the buried layer 62 and the semiconductor substrate 61 can be the same or different, and this application does not impose any limitations on this. Furthermore, given that the doping type is determined, the specific dopant ions implanted into the semiconductor substrate 61 to form the buried layer 62 in this embodiment can be set by those skilled in the art according to actual needs, and this application does not impose any specific limitations on this. Simultaneously, the buried layer 62 formed in this embodiment can be formed only in a portion of the relevant area of ​​the semiconductor substrate 61. During dopant ion implantation, the remaining unrelated areas can be covered by a coated photoresist to avoid contamination by the implanted dopant ions, and the photoresist can be removed after the dopant ion implantation is completed.

[0107] Step S200: A doped region is formed on the semiconductor substrate.

[0108] Specifically, after providing the semiconductor substrate, this embodiment can form a doped region on the semiconductor substrate. The doped region may include a deep termination trench that extends from the upper surface of the doped region into the doped region.

[0109] Optionally, depending on the type of semiconductor device being formed, in addition to deep termination trenches, the doped region may also include gate trenches. The depth of the deep termination trenches can be greater than that of the gate trenches. Specifically, to form... Figure 1 or Figure 2 The semiconductor device shown in this embodiment can be formed with a doped region consisting only of deep termination trenches. However, to form... Figure 3 , 4 If the semiconductor device shown in Figure 5 is used, then this embodiment can form a doped region that simultaneously includes a deep terminal trench and a gate trench.

[0110] like Figure 9 As shown, in this embodiment, a doped region 63 can be formed on the semiconductor substrate 61. The doped region 63 can simultaneously include a deep termination trench 631 and a gate trench 632. Optionally, as one implementation, in this embodiment, the doped region 63 can be formed on the semiconductor substrate 61 first, and an irrelevant area can be covered using a hard mask. The doped region 63 can be selectively etched to form a trench of the required depth, and then the hard mask can be removed to form the deep termination trench 631 and the gate trench 632.

[0111] In the following description, the example of forming a doped region 63 that simultaneously includes a deep terminal trench 631 and a gate trench 632 will be used.

[0112] Step S300: A deep terminal structure is formed within the deep terminal trench.

[0113] Specifically, in this embodiment, a deep terminal structure can be formed within a deep terminal trench.

[0114] Optionally, depending on the type of semiconductor device formed, the deep termination structure can be reused as a shielding gate or as a gate structure including a control gate / main gate. Specifically, when reused as a shielding gate, the deep termination structure may include an isolation conductor layer and a third shielding dielectric layer. The third shielding dielectric layer may be formed at the bottom and sidewalls of the deep termination trench, isolating the isolation conductor layer from the doped region. When reused as a gate structure, the deep termination structure may include a second shielding dielectric layer, a second shielding gate, a second gate dielectric layer, and a second control gate. The second shielding dielectric layer may be located at the bottom and lower sidewalls of the deep termination trench, isolating the second shielding gate from the doped region. The second gate dielectric layer may be located at the upper sidewall of the deep termination trench, isolating the second control gate from the doped region. The second gate dielectric layer may also be located between the second shielding gate and the second control gate, isolating the second shielding gate from the second control gate.

[0115] like Figure 10 As shown, in this embodiment, a deep termination structure 64 can be formed within the deep termination trench of the doped region 63. Since it is reused as a shielding gate, the deep termination structure 64 may include an isolation conductor layer 641 and a third shielding dielectric layer 642.

[0116] Furthermore, depending on the type of semiconductor device formed, in addition to forming a deep termination structure in the deep termination trench of the doped region, this embodiment can also form a vertical gate structure in the gate trench of the doped region.

[0117] like Figure 10 As shown, in this embodiment, a vertical gate structure 65 can be formed within the gate trench of the doped region 63. The vertical gate structure 65 may include a first shielding dielectric layer 651, a first shielding gate 652, a first gate dielectric layer 653, and a first control gate 654. Optionally, as one implementation, the deep termination structure 64 and the vertical gate structure 65 can be formed separately. Alternatively, since both the deep termination structure 64 and the vertical gate structure 65 can be formed by depositing a shielding oxide layer and a polysilicon layer, as another implementation, the deep termination structure 64 and the vertical gate structure 65 can also be formed by reusing process steps. This application does not limit the specific formation method of either.

[0118] In the following description, the deep terminal structure 64 will be used as an example of a shielding barrier.

[0119] In step S400, at least one source region and one drain region are formed in the doped regions on both sides of the deep terminal structure.

[0120] Specifically, in this embodiment, at least one source region and one drain region can be formed in the doped regions on both sides of the deep terminal structure.

[0121] Optionally, in forming the source and drain regions, this embodiment may first form a body region within the doped region.

[0122] Alternatively, depending on the type of semiconductor device being formed, the body region can be formed in a corresponding region within the doped region. Specifically, to form Figure 1 or Figure 2 In the semiconductor device shown, this embodiment can form a body region within a doped semiconductor substrate on one side of the deep terminal structure, the body region being adjacent to the doped region. To form... Figure 3 or Figure 5 In the semiconductor device shown, this embodiment can form a body region within the doped regions on both sides of the vertical gate structure, and simultaneously contact the body region located between the vertical gate structure and the deep termination structure with both the vertical gate structure and the deep termination structure. To form... Figure 4 In the semiconductor device shown, in this embodiment, a body region can be formed in the doped regions on both sides of the vertical gate structure, and the body region located between the vertical gate structure and the deep terminal structure is only in contact with the vertical gate structure, while being spaced apart from the deep terminal structure.

[0123] like Figure 11 As shown, in this embodiment, a bulk region 66 can be formed within the doped region 63.

[0124] In the following description, an example will be given where a body region 66 is formed in the doped regions on both sides of the vertical gate structure 65, and the body region 66 located between the vertical gate structure 65 and the deep terminal structure 64 is in contact with both the vertical gate structure 65 and the deep terminal structure 64.

[0125] Furthermore, after forming the body region, depending on the type of semiconductor device being formed, this embodiment can selectively form a planar gate structure on the doped region 63.

[0126] like Figure 12 As shown, in this embodiment, a planar gate structure 67 can be formed on the doped region 63. In one implementation, the planar gate structure 67 may include gate oxide 671, gate conductor 672, and sidewalls 673.

[0127] In the following description, the formation of a planar gate structure 67 will be used as an example.

[0128] Furthermore, this embodiment can form a source region and a corresponding bulk contact region.

[0129] like Figure 13 As shown, this embodiment can form a source region 68 and a corresponding bulk contact region 69.

[0130] Furthermore, this embodiment can form a sunken region. Optionally, depending on the type of semiconductor device being formed, the formed sunken region may or may not contact the buried layer. Specifically, if to form Figure 1 or Figure 2 The semiconductor device shown in this embodiment can avoid contact between the submerged region and the buried layer. To form... Figure 3 , 4 In the case of the semiconductor device shown in Figure 5, this embodiment allows the submerged region to contact the buried layer. Furthermore, depending on the implementation method, the submerged region can be formed by performing an ion doping operation or by performing a metal filling process; this application is not limited in this regard. Specifically, when the submerged region is formed by performing an ion doping operation, this embodiment performs ion implantation in the corresponding region of the doped region to form the submerged region. When the submerged region is formed by performing a metal filling process, this embodiment can first form a first trench on the doped region, and then fill the first trench with conductive material to form the submerged region.

[0131] Furthermore, a drain region can be formed in this embodiment. For example... Figure 15 As shown, this embodiment can form a drain region 612. It is important to note that the method of forming the drain region can be matched with the method of forming the sink region. Specifically, when the sink region is formed by performing an ion doping operation, the drain region can also be formed by performing an ion doping operation, and the ion doping types are the same. When the sink region is formed by performing a trench filling process, the drain region can also be formed by performing a trench filling process.

[0132] Therefore, the embodiments of the present invention can obtain the following: Figure 4 The semiconductor device shown is intended to illustrate that... Figures 7 to 15 The semiconductor formation process shown is for illustrative purposes only. In actual applications, the actual process is achieved by executing... Figure 6 The semiconductor device formation method shown in the present invention can also be used to obtain other types of semiconductor devices.

[0133] It should be noted that, in the embodiments of the present invention, all material layers involved can be formed using existing semiconductor deposition processes, including but not limited to Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), Molecular Beam Epitaxy (MBE), and Liquid-Phase Deposition (LPD), etc., and this application does not impose any limitations on these processes. The groove structures involved can all be formed using existing semiconductor etching processes, including but not limited to wet etching, dry etching, and ion beam etching (IBE), etc., and this application does not impose any limitations on these processes. Furthermore, although not explicitly stated, in actual process flows, to ensure that the formed material layers meet the requirements, this embodiment may also include other operations, such as planarization operations, and this application does not impose any limitations on these operations.

[0134] The semiconductor device in this embodiment of the invention includes a semiconductor substrate, a doped region, a deep termination structure, and at least one source region and a drain region. The doped region is formed on the semiconductor substrate and includes a deep termination trench extending from the upper surface of the doped region into the doped region. The deep termination structure is formed within the deep termination trench, and the source and drain regions are respectively formed within the doped regions on both sides of the deep termination structure. Therefore, by forming a deep termination structure within the doped region and forming the source and drain regions within the doped regions on both sides of the deep termination structure, this embodiment of the invention can reduce the gate charge of the planar architecture device and increase the power density of the planar architecture device.

[0135] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: Semiconductor substrate; A doped region is formed on the semiconductor substrate, the doped region including a deep termination trench extending from the upper surface of the doped region into the doped region; A deep terminal structure is formed within the deep terminal trench; and At least one source region and one drain region are formed on both sides of the deep terminal structure.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: At least one gate structure for modulating charge carriers in a semiconductor channel located below or to the side thereon, wherein the deep termination structure is located between the gate structure and the drain region for optimizing the electric field distribution near the drain region.

3. The semiconductor device according to claim 2, characterized in that, The doped region further includes a gate trench, which is formed on one side of the deep termination structure and extends from the upper surface of the doped region into the doped region. The gate structure includes: A vertical gate structure, formed within the gate trench, is used to regulate charge carriers in the vertical semiconductor channel located to its side.

4. The semiconductor device according to claim 3, characterized in that, The depth of the deep terminal structure is greater than the depth of the vertical gate structure.

5. The semiconductor device according to claim 3, characterized in that, The vertical gate structure includes a first shielding dielectric layer, a first shielding gate, a first gate dielectric layer, and a first control gate. The first shielding dielectric layer is located at the bottom and lower sidewall of the gate trench and isolates the first shielding gate from the doped region. The first gate dielectric layer is located at the upper sidewall of the gate trench and isolates the first control gate from the doped region. The first gate dielectric layer is also located between the first shielding gate and the first control gate and isolates the first shielding gate from the first control gate.

6. The semiconductor device according to claim 3, characterized in that, The semiconductor device further includes: A buried layer is formed between the semiconductor substrate and the doped region; At least one body region is formed within the doped region, and the at least one body region is located on one or both sides of the vertical gate structure, and each of the source regions is formed within the corresponding body region; The sinking region is located below the drain region and is in contact with the drain region and the buried layer.

7. The semiconductor device according to claim 6, characterized in that, A Schottky diode is formed at the contact point between the sunken area and the buried layer.

8. The semiconductor device according to claim 6, characterized in that, The doped region is a deep well region, the buried layer and the doped region are of the first doping type, and the body region is of the second doping type.

9. The semiconductor device according to claim 6, characterized in that, The body region includes a first body region, wherein the first body region is formed in a first region near the vertical gate structure and spaced apart from the deep terminal structure, between the vertical gate structure and the deep terminal structure.

10. The semiconductor device according to claim 9, characterized in that, The gate structure further includes: A planar gate structure is formed on the doped region. The first body region includes a first source region, a body contact region, and a second source region in sequence along the direction towards the drain region. The planar gate structure covers the region between the second source region and the deep termination structure in the vertical spatial direction, and is used to regulate the carriers in the horizontal semiconductor channel located below it.

11. The semiconductor device according to claim 10, characterized in that, When the semiconductor device is in operation, each of the source regions except the second source region forms a first carrier path, and the second source region forms a second carrier path. The first carrier path includes a longitudinal path portion that runs through the doped region to the buried layer and a transport path portion that runs through the buried layer and the sinked region to the drain region. The second carrier path includes a transverse path portion that runs through the doped region, a longitudinal path portion that runs through the doped region to the buried layer, and a transport path portion that runs through the buried layer and the sinked region to the drain region.

12. The semiconductor device according to claim 6, characterized in that, The body region includes a first body region, which is formed between the vertical gate structure and the deep terminal structure, and has its two sides in contact with the vertical gate structure and the deep terminal structure, respectively.

13. The semiconductor device according to claim 12, characterized in that, The first body region includes, in sequence, a first source region, a body contact region, and a second source region along the direction toward the drain region. The first source region is in contact with the vertical gate structure, and the second source region is in contact with the deep termination structure.

14. The semiconductor device according to claim 12, characterized in that, The first body region includes a first source region and a body contact region in sequence along the direction towards the drain region, and the first source region is in contact with the vertical gate structure.

15. The semiconductor device according to claim 13, characterized in that, The deep terminal structure is reused as a gate structure to regulate charge carriers in the vertical semiconductor channel located on its side.

16. The semiconductor device according to claim 15, characterized in that, The deep termination structure includes a second shielding dielectric layer, a second shielding gate, a second gate dielectric layer, and a second control gate. The second shielding dielectric layer is located at the bottom and lower sidewall of the deep termination trench and isolates the second shielding gate from the doped region. The second gate dielectric layer is located at the upper sidewall of the deep termination trench and isolates the second control gate from the doped region. The second shielding dielectric layer is also located between the second shielding gate and the second control gate and isolates the second shielding gate from the second control gate.

17. The semiconductor device according to claim 14 or 16, characterized in that, When the semiconductor device is in operation, each of the source regions forms a first carrier path, the first carrier path including a longitudinal path portion that extends through the doped region to the buried layer and a transport path portion that extends through the buried layer and the sinking region to the drain region.

18. The semiconductor device according to claim 16, characterized in that, The second control gate is an offset gate, and the offset direction of the second control gate is closer to the direction where the first body region is located.

19. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: A buried layer is formed between the semiconductor substrate and the doped region; A body region is located on one side of the deep terminal structure. The body region is formed on the upper surface of the semiconductor substrate. The source region is formed within the body region. The body region is adjacent to the doped region. A planar gate structure is formed on the doped region, the planar gate structure covering the region between the source region and the deep termination structure in the vertical spatial direction, for regulating the carriers in the horizontal semiconductor channel located below it.

20. The semiconductor device according to claim 19, characterized in that, The body region is in contact with the buried layer.

21. The semiconductor device according to claim 19, characterized in that, The semiconductor device further includes: The sink region is located below the drain region and extends from the upper surface of the doped region into the doped region.

22. The semiconductor device according to claim 21, characterized in that, When the semiconductor device is in operation, a third carrier path is formed in the source region. The third carrier path includes a lateral path portion that crosses the doped region, a longitudinal path portion that crosses the doped region, and a transport path portion that reaches the drain region via the sinking region.

23. The semiconductor device according to claim 19, characterized in that, The doped region is a drift region, the doping type of the doped region is a first doping type, and the doping type of the body region is a second doping type.

24. The semiconductor device according to claim 1, characterized in that, The deep termination structure includes an isolation conductor layer and a third shielding dielectric layer, wherein the third shielding dielectric layer is formed at the bottom and sidewalls of the deep termination trench and isolates the isolation conductor layer from the doped region.

25. The semiconductor device according to claim 6 or 21, characterized in that, The doped region further includes a first trench, and the sinking region includes conductive material filling the first trench.

26. The semiconductor device according to claim 1, characterized in that, The deep terminal structure is adjacent to the drain region.

27. A method for forming a semiconductor device, characterized in that, The method includes: Provide semiconductor substrates; A doped region is formed on the semiconductor substrate, the doped region including a deep termination trench extending from the upper surface of the doped region into the doped region; A deep terminal structure is formed within the deep terminal trench; and At least one source region and one drain region are formed on both sides of the deep terminal structure.

28. The method according to claim 27, characterized in that, The method further includes: A gate trench is formed in the doped region, extending from the upper surface of the doped region into the doped region. The gate trench and the deep termination trench are formed simultaneously. A vertical gate structure is formed in the gate trench.

29. The method according to claim 28, characterized in that, The method further includes: A planar gate structure is formed on the upper surface of the doped region.

30. The method according to claim 29, characterized in that, The method further includes: At least one body region is formed within the doped region, the at least one body region being located on one or both sides of the vertical gate structure, or located below a portion of the planar gate structure, and each source region is formed within the corresponding body region.

31. The method according to claim 29, characterized in that, The method further includes: A body region is formed on the semiconductor substrate, a portion of the body region is located below the planar gate structure, the body region is in contact with the doped region, the source region is located in the body region, and the drain region is located in the doped region.

32. The method according to claim 27, characterized in that, The method further includes: A sinking region is formed, which is located below the drain region; The method for forming the sinking zone includes: A first trench is formed in the doped region, and The first trench is filled with conductive material.

33. The method according to claim 27, characterized in that, The deep terminal structure is adjacent to the drain region.

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