Semiconductor device

Abstract

The embodiment of the invention relates to a semiconductor device. An LDMOSFET is formed at a main surface of a semiconductor substrate. The LDMOSFET includes an n-type drain region, an n-type source region, an n-type drift region, a first p-type well region, and a second p-type well region all formed in an n-type semiconductor layer. The n-type drift region is in contact with a bottom surface of the n-type drain region, the second p-type well region is in contact with a bottom surface of the n-type source region, and the first p-type well region is in contact with a bottom surface of the n-type drift region and a bottom surface of the second p-type well region. A p-type impurity concentration in the first p-type well region is lower than a p-type impurity concentration in the second p-type well region and lower than an n-type impurity concentration in the n-type semiconductor layer.

Description

semiconductor devices Cross-reference to related applications

[0001] The disclosure of Japanese Patent Application No. 2024-189838, filed on October 29, 2024, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a semiconductor device that can be suitably used in semiconductor devices having transistors as power switching elements. Background Technology

[0003] In some cases, transistors that configure other circuits are also formed on the semiconductor substrate that forms the power switching element.

[0004] The publicly available technologies are listed below.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2015-23451

[0006] Patent document 1 discloses a technology related to a semiconductor device equipped with an output MOS transistor and a short-circuit transistor. Summary of the Invention

[0007] The goal is to improve the performance of semiconductor devices with power switching elements.

[0008] Other issues and novel features will become apparent from the description in this specification and the accompanying drawings.

[0009] According to one embodiment, a semiconductor device includes a semiconductor substrate, a first MOSFET and a second MOSFET formed on a main surface of the semiconductor substrate, and a back electrode formed on a back surface of the semiconductor substrate. The semiconductor substrate has a substrate region of a first conductivity type and a semiconductor layer of the first conductivity type formed on the substrate region. The first MOSFET includes a gate electrode formed on the semiconductor layer via a gate insulating film, a first source region and a first drain region of the first conductivity type formed in the semiconductor layer, a drift region of the first conductivity type formed in the semiconductor layer, and a first well region and a second well region of the second conductivity type formed in the semiconductor layer. The drift region is in contact with the bottom surface of the first drain region, the first well region is in contact with the bottom surface of the first source region, and the second well region is in contact with the bottom surfaces of the drift region and the first well region. The second MOSFET includes a trench gate electrode formed in a trench of the semiconductor layer via a second gate insulating film and a second source region of the first conductivity type formed in the semiconductor layer. The impurity concentration of the second conductivity type in the first well region is higher than the impurity concentration of the second conductivity type in the second well region. The impurity concentration of the second conductivity type in the second well region is lower than the impurity concentration of the first conductivity type in the semiconductor layer.

[0010] According to one embodiment, the performance of a semiconductor device can be improved. Attached Figure Description

[0011] Figure 1 is a circuit diagram showing an example of a circuit using power switching elements.

[0012] Figure 2 is a cross-sectional view of the main parts of the semiconductor device of the first embodiment.

[0013] Figure 3 is a cross-sectional view of the main parts of the semiconductor device in the first embodiment.

[0014] Figure 4 is a graph showing the p-type impurity concentration distribution in the p-type well region of the semiconductor device of the first embodiment.

[0015] Figure 5 is a graph showing the p-type impurity concentration distribution in the p-type well region of the semiconductor device of the first embodiment.

[0016] Figure 6 is a graph showing the p-type impurity concentration distribution in the p-type well region of the semiconductor device of the second embodiment.

[0017] Figure 7 is a graph showing the p-type impurity concentration distribution in the p-type well region of the semiconductor device of the second embodiment. Detailed Implementation

[0018] In the following embodiments, for convenience, the description is divided into multiple parts or embodiments where necessary. However, unless otherwise specifically stated, they are not unrelated to each other, and one part or embodiment is related to another part or embodiment as part or all of a modification example, detail, supplementary explanation, etc. Furthermore, in the following embodiments, when referring to the quantity of elements, etc. (including number, value, quantity, range, etc.), unless otherwise specifically stated and explicitly limited to a specific quantity in principle, it is not limited to that specific quantity and may be not less than or equal to that specific quantity. Furthermore, in the following embodiments, constitutive elements (including element steps, etc.) are not necessarily necessary unless otherwise specifically stated and explicitly considered necessary in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, unless otherwise specifically stated and explicitly considered not to be so in principle, it is assumed that shapes, etc., are substantially similar to or analogous to those shapes, etc. This also applies to the values ​​and ranges described above.

[0019] In the following description, embodiments will be illustrated with reference to the accompanying drawings. Throughout the drawings used to explain the embodiments, components with the same function are denoted by the same reference numerals, and repeated descriptions are omitted. Furthermore, in the following embodiments, descriptions of the same or similar components are generally not repeated unless specifically necessary.

[0020] In the accompanying drawings used in the embodiments, even in the case of cross-sectional views, the shading lines may be omitted to make the drawings easier to read. Furthermore, even in the case of plan views, the shading lines may be used to make the drawings easier to read.

[0021] Furthermore, "plan view" corresponds to a view taken from a plane substantially parallel to the main or back surface of the semiconductor substrate SUB. Additionally, "bottom surface" and "lower surface" have the same meaning.

[0022] In this application, MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or LDMOSFET (Laterally Diffused Metal-Oxide-Semiconductor Field-Effect Transistor) includes not only MOSFETs that use an oxide film as the gate insulating film, but also MOSFETs that use an insulating film other than an oxide film as the gate insulating film. LDMOSFET can also be referred to as HV-MOSFET (High Voltage Metal-Oxide-Semiconductor Field-Effect Transistor) or DEMOSET (Drain Extended Metal-Oxide-Semiconductor Field-Effect Transistor).

[0023] In this application, the n-type impurity concentration is the effective n-type impurity concentration, and the p-type impurity concentration is the effective p-type impurity concentration. In a semiconductor region containing both n-type and p-type impurities, when the majority carriers are electrons (n-type impurities), the difference between the number of n-type impurities per unit volume and the number of p-type impurities per unit volume is the effective n-type impurity concentration. In a semiconductor region containing both n-type and p-type impurities, when the majority carriers are holes (p-type impurities), the difference between the number of n-type impurities per unit volume and the number of p-type impurities per unit volume is the effective p-type impurity concentration. First embodiment circuit example.

[0024] As shown in Figure 1, power MOSFET 1 is inserted between the power supply potential VB and the load LD. The power supply potential VB is provided by a battery or the like. Specifically, the drain of power MOSFET 1 is connected to the power supply potential VB, and the source of power MOSFET 1 is connected to the load LD. The load LD is also connected to ground potential GND. The load LD is inserted between ground potential GND and power MOSFET 1.

[0025] Both the power supply potential VB and the ground potential GND are fixed potentials, with the power supply potential VB being higher than the ground potential GND. For example, the ground potential GND is 0V, and the power supply potential VB is a positive fixed potential.

[0026] Power MOSFET 1 is a transistor that configures a power switching element. When the gate voltage of power MOSFET 1 is below the threshold voltage (e.g., 0V), power MOSFET 1 is in the off state (non-conducting state), and no current flows to the load LD. When a gate voltage equal to or greater than the threshold voltage is supplied to the gate of power MOSFET 1, power MOSFET 1 is in the on state (conducting state). When power MOSFET 1 is in the on state, current flows through power MOSFET 1 to the load LD. (Semiconductor device structure)

[0027] The semiconductor device of the first embodiment will be described with reference to Figures 2 and 3. Figure 3 is an enlarged partial cross-sectional view of a portion of Figure 2. In Figure 3, the shaded lines are omitted.

[0028] As shown in Figures 2 and 3, the semiconductor device of the first embodiment includes a semiconductor substrate SUB, a power MOSFET 1, an LDMOSFET 2, an STI region 3, an insulating film IL, and a back electrode BE.

[0029] As shown in Figures 2 and 3, the semiconductor substrate SUB is an n-type semiconductor substrate and includes an n-type substrate body (substrate region) SB and an n-type semiconductor layer EP formed on the n-type substrate body SB.

[0030] The n-type substrate SB is made of n-type single-crystal silicon, in which n-type impurities such as phosphorus (P) or arsenic (As) are introduced. The thickness of the n-type substrate SB is almost uniform. The n-type semiconductor layer EP is made of n-type single-crystal silicon formed on the n-type substrate SB. The n-type impurity concentration of the n-type substrate SB is higher than that of the n-type semiconductor film EP. The n-type semiconductor layer EP and the n-type substrate SB are in contact with each other.

[0031] The main surface of the semiconductor substrate SUB is synonymous with the main surface of the n-type semiconductor layer EP. Furthermore, the back surface of the semiconductor substrate SUB is synonymous with the back surface of the n-type substrate body SB. The main and back surfaces of the semiconductor substrate SUB are located on opposite sides. A back electrode BE is formed on the back surface of the semiconductor substrate SUB. The n-type substrate body SB and the back electrode BE are in contact with each other. The thickness direction of the semiconductor substrate corresponds to the direction from one surface (main or back) of the semiconductor substrate SUB to the other surface, and is approximately perpendicular to either the main or back surface of the semiconductor substrate SUB.

[0032] The STI (Shallow Trench Insulation) region 3 is formed by an insulating film in a trench embedded in the semiconductor substrate SUB. Alternatively, the LOCOS (Local Oxidation of Silicon) region can be used instead of the STI region 3.

[0033] The main surface of the semiconductor substrate SUB includes element region 1A in which a transistor (here, power MOSFET 1) used as a power switching element is formed, and element region 1B in which an LDMOSFET 2 configured with other circuitry (e.g., control circuitry) is formed. In the plan view, element region 1A and element region 1B are separated from each other.

[0034] Next, the configuration of the power MOSFET 1 formed in component region 1A will be described. The power MOSFET 1 is a trench gate MOSFET. The power MOSFET 1 includes a trench gate electrode TG, a gate insulating film GF1, an n-type source region SR1, a p-type semiconductor region PR1, a p-type semiconductor region PR2, and a gate wiring portion TGL.

[0035] A trench gate electrode TG is formed in a trench TR, which is formed on the main surface of a semiconductor substrate SUB via a gate insulating film GF1. The trench TR extends from the main surface of the semiconductor substrate SUB to the back surface. The bottom surface of the trench TR is deeper than the bottom surface of the p-type semiconductor region PR1. The gate insulating film GF1 is formed on the bottom and side surfaces of the trench TR. The trench gate electrode TG is made of, for example, a polycrystalline silicon film in which n-type impurities are introduced.

[0036] An n-type source region SR1, a p-type semiconductor region (p-type body region) PR1, and a p-type semiconductor region PR2 are formed in an n-type semiconductor layer EP. The n-type source region SR1 and the p-type semiconductor region PR2 are formed on and in contact with the p-type semiconductor region PR1. The p-type impurity concentration in the p-type semiconductor region PR2 is higher than that in the p-type semiconductor region PR1. The n-type impurity concentration in the n-type source region SR1 is higher than that in the n-type semiconductor layer EP.

[0037] The n-type source region SR1 and the p-type semiconductor region PR1 are in contact with the gate insulating film GF1 formed on the side surface of the trench TR. The n-type source region SR1 is interposed between the p-type semiconductor region PR2 and the trench TR. The n-type source region SR1 is adjacent to the trench gate electrode TG via the gate insulating film GF. The p-type semiconductor region PR1 is located below the n-type source region SR1 and is adjacent to the trench gate electrode TG via the gate insulating film GF1. The bottom surface of the n-type source region SR1 is the boundary between the n-type source region SR1 and the p-type semiconductor region PR1. Therefore, a PN junction is formed at the bottom surface of the n-type source region SR1. Below the bottom surface of the p-type semiconductor region PR1, there is a portion of the n-type semiconductor layer EP (n-type semiconductor region). Therefore, a PN junction is formed at the bottom surface of the p-type semiconductor region PR1.

[0038] The n-type semiconductor layer EP is located below the p-type semiconductor region PR1, and the n-type substrate body SB is located below the p-type conductor region PR1, serving as the n-type drain region of power MOSFET 1. The channel of power MOSFET 1 is formed along the trench TR in the p-type semiconductor region PR1. The operating current of power MOSFET 1 flows between the n-type source region SR1 and the n-type substrate body SB through the channel formed in the p-type semiconductor region PR1 and the n-type semiconductor layer EP. Therefore, the operating current of power MOSFET 1 flows along the thickness direction of the semiconductor substrate SUB.

[0039] The back electrode BE can be used as the drain electrode for electrical connection with the drain of power MOSFET 1. The back electrode BE is formed on the entire back surface of the semiconductor substrate SUB. Power MOSFET 1 can be configured by connecting multiple unit transistor cells in parallel.

[0040] The gate wiring portion TGL is integrally formed with and electrically connected to the trench gate electrode TG. The trench gate electrode TG is formed in the trench TR. On the other hand, the gate wiring portion TG is disposed on the semiconductor substrate SUB outside the trench TR. A portion of the gate wiring portion TGL is located on STI region 3.

[0041] An insulating film IL is formed on the main surface of the semiconductor substrate SUB and covers the power MOSFET 1.

[0042] Next, the configuration of the LDMOSFET 2 formed in component region 1B will be described.

[0043] The LDMOSFET 2 includes a p-type well region PW1, a p-type well region PW2, an n-type drift region ND, an n-type drain region DR2, an n-type source region SR2, a p-type semiconductor region PC, a gate electrode GE, and a gate insulating film GF2.

[0044] The p-type well region (p-type semiconductor region) PW1, p-type well region (p-type semiconductor region) PW2, n-type drift region (n-type semiconductor region) ND, n-type drain region (n-type semiconductor region) DR2, n-type source region (n-type semiconductor region) SR2, and p-type semiconductor region (p-type semiconductor region) PC are formed in the n-type semiconductor layer EP. The gate electrode GE is formed on the n-type semiconductor layer EP via the gate insulating film GF2. The insulating film IL is formed on the main surface of the semiconductor substrate SUB and covers the LDMOSFET 2.

[0045] A p-type well region PW1 is formed on top of an n-type semiconductor layer EP. A portion of the n-type semiconductor layer EP (n-type semiconductor region) exists beneath the bottom surface 6 of the p-type well region PW1. Therefore, a PN junction is formed at the bottom surface 6 of the p-type well region PW1.

[0046] P-type well region PW1 surrounds p-type well region PW2 and n-type drift region ND. That is, in a planar view, p-type well region PW2 and n-type drift region ND are contained within p-type well region PW1. The bottom surface 7 of p-type well region PW2 is shallower than the bottom surface 6 of p-type well region PW1, and the bottom surface 5 of n-type drift region ND is shallower than the bottom surface 6 of p-type well region PW1. A portion of p-type well region PW1 exists below the bottom surface 5 of n-type drift region ND and the bottom surface 7 of p-type well region PW2. The bottom surface 7 of p-type well region PW2 contacts p-type well region PW1, and the bottom surface 5 of n-type drift region ND contacts p-type well region PW1. The p-type impurity concentration in p-type well region PW2 is higher than that in p-type well region PW1. The n-type impurity concentration in n-type drift region ND is higher than that in n-type semiconductor layer EP. The bottom surface 5 of the n-type drift region ND is the boundary between the n-type drift region ND and the p-type well region PW1. Therefore, a PN junction is formed at the bottom surface 5 of the n-type drift region ND.

[0047] The p-type well region PW2 surrounds the n-type source region SR2 and the p-type semiconductor region PC. That is, in the plan view, the n-type source region SR2 and the p-type semiconductor region PC are included within the p-type well region PW2. The bottom surface of the n-type source region SR2 is shallower than the bottom surface 7 of the p-type well region PW2, and the bottom surface of the p-type semiconductor region PC is shallower than the bottom surface 7 of the p-type well region PW2. A portion of the p-type well region PW2 exists beneath the bottom surfaces of the n-type source region SR2 and the p-type semiconductor region PC. The bottom surfaces of the n-type source region SR2 and the p-type semiconductor region PC are in contact with the p-type well region PW2. The upper surfaces of the n-type source region SR2 and the p-type semiconductor region PC reach the main surface of the semiconductor substrate SUB. The n-type impurity concentration in the n-type source region SR2 is higher than that in the n-type drift region ND. The p-type impurity concentration in the p-type semiconductor region PC is higher than that in the p-type well region PW2. The p-type semiconductor region PC can be used as the contact portion of the p-type well region PW2. The bottom surface of the n-type source region SR2 is the boundary between the n-type source region SR2 and the p-type well region PW2. Therefore, a PN junction is formed at the bottom surface of the n-type source region SR2.

[0048] The n-type drift region ND surrounds the n-type drain region DR2. That is, in a planar view, the n-type drain region DR2 is contained within the n-type drift region ND. The bottom surface of the n-type drain region DR2 is shallower than the bottom surface of the n-type drift region ND. A portion of the n-type drift region ND exists beneath the bottom surface of the n-type drain region DR2. The bottom surface of the n-type drain region DR2 is in contact with the n-type drift region ND. The upper surface of the n-type drain region DR2 reaches the main surface of the semiconductor substrate SUB. The n-type impurity concentration in the n-type drain region DR2 is higher than that in the n-type drift region ND.

[0049] The n-type drift region ND and the p-type well region PW2 are adjacent to each other along the gate length direction of LDMOSFET 2. The gate length direction of LDMOSFET 2 corresponds to the gate length direction of the gate electrode GE, and the gate width direction of LDMOSFET 2 corresponds to the gate width direction of the gate electrode GE.

[0050] The p-type well region PW2 can be used as a back gate. It can also be used as a punch-through stop to prevent the depletion layer from extending from the drain to the source of LDMOSFET2. The channel of LDMOSFET2 is formed in the upper part of the p-type well region PW2, which is located between the n-type source region SR2 and the n-type drain region DR2, and below the gate electrode GE. In the following text, the region in which the channel of LDMOSFET2 is formed is referred to as the channel formation region. The n-type source region SR2 is adjacent to the channel formation region of LDMOSFET2. The n-type drain region DR2 and the n-type source region SR2 are separated from each other along the gate length direction of LDMOSFET2.

[0051] In the cases shown in Figures 2 and 3, the p-type semiconductor region PC and the n-type source region SR2 are adjacent to each other along the gate length direction of the LDMOSFET 2. In this case, in the planar view, the n-type source region SR2 is located between the gate electrode GE and the p-type semiconductor region PC. Alternatively, the p-type semiconductor region PC and the n-type source region SR2 may not be adjacent to each other along the gate length direction of the LDMOSFET 2, and may be arranged alternately along the gate width direction of the LDMOSFET 2.

[0052] The gate electrode GE is formed on the main surface of the semiconductor substrate SUB between the n-type source region SR2 and the n-type drain region DR2 via a gate insulating film GF2. The gate insulating film GF2 is made of, for example, a silicon oxide film. The gate electrode GE is made of, for example, a single film of polysilicon (doped polysilicon film) or a stack of polysilicon and metal silicide layers. In a planar view, a portion of the gate electrode GE overlaps with the n-type drift region ND, and another portion overlaps with the p-type well region PW2.

[0053] In the planar view, the STI region 3 is disposed between the channel formation region of the LDMOSFET 2 and the n-type drain region DR2, and a portion of the gate electrode GE is located on the STI region 3. The n-type drift region ND exists below the STI region 3, which is interposed between the channel formation region of the LDMOSFET 2 and the n-type drain region DR2. The bottom surface of the n-type drain region DR2 contacts the n-type drift region ND, and the side surface of the n-type drain region DR2 contacts the STI region 3. Therefore, the n-type drift region ND below the STI region 3 can also serve as a conductive path between the channel of the LDMOSFET 2 and the n-type drain region DR2.

[0054] In Figures 2 and 3, there is a case where the gate insulating film GF2 is inserted between the STI region 3 and the gate electrode GE; however, there is also a case where the gate insulating film GF2 is not inserted between the STI region 3 and the gate electrode GE. Furthermore, sidewall spacers made of an insulating film (not shown) can be formed on the side surface of the gate electrode GE.

[0055] A portion of the p-type well region PW2 is located below the gate electrode GE, and a portion of the n-type drift region ND is also located below the gate electrode GE. A PN junction is formed at the boundary between the p-type well region PW2 and the n-type drift region ND. The boundary between the p-type well region PW2 and the n-type drift region ND is located below the gate electrode GE and extends in the gate width direction of the LDMOSFET 2.

[0056] In the planar diagram, the gate electrode GE is positioned between the n-type source region SR2 and the n-type drain region DR2. When a voltage equal to or greater than the threshold voltage is applied to the gate electrode GE, a channel is formed in the upper part of the p-type well region PW2 located below the gate electrode GE. The n-type source region SR2 and the n-type drain region DR2 are interconnected through the channel and the n-type drift region ND.

[0057] In the gate length direction of LDMOSFET 2, the n-type drift region ND is interposed between the p-type well region PW2 and the n-type drain region DR2. Therefore, the n-type drift region ND exists between the channel formation region and the n-type drain region DR2 of LDMOSFET 2. Thus, in the gate length direction of LDMOSFET 2, the channel formation region and the n-type drift region ND exist between the n-type source region SR2 and the n-type drain region DR2, wherein the channel formation region is located between the n-type source region SR2 and the n-type drift region RD.

[0058] Furthermore, metal silicide layers (not shown) can be formed on the n-type drain region DR2, the n-type source region SR2, and the p-type semiconductor region PC. These metal silicide layers can be formed using self-aligned silicide (salicide) technology.

[0059] Next, the structure on the semiconductor substrate SUB will be described.

[0060] As shown in Figures 2 and 3, the semiconductor device of the first embodiment further includes plugs (contact plugs) PG1, PG2, PGD, PGP, PGS, and wirings M1A, M1B, M1D, and M1S.

[0061] An insulating film IL is formed on the main surface of the semiconductor substrate SUB and covers the trench gate electrode TG, the gate wiring portion TGL, and the gate electrode GE. The insulating film IL includes, for example, a silicon nitride film and a silicon oxide film on the silicon nitride film. The upper surface of the insulating film IL is planarized.

[0062] Multiple contact holes (through holes) are formed in the insulating film IL, and multiple conductive plugs are formed in these contact holes. The multiple plugs include plug PG1, plug PG2, plug PGD, plug PGP, and plug PGS. Each of plugs PG1, plug PG2, plug PGD, plug PGP, and plug PGS passes through the insulating film IL.

[0063] The plug PGD is located on and electrically connected to the n-type drain region DR2. The plug PGS is located on and electrically connected to the n-type source region SR2. The plug PGP is located on and electrically connected to the p-type semiconductor region PC. Therefore, the plug PGP is electrically connected to the p-type well region PW2 via the p-type semiconductor region PC.

[0064] Plug PG1 is positioned across the p-type semiconductor region PR2 and the n-type source region SR1, and is electrically connected to both the p-type semiconductor region PR2 and the n-type source region SR1. Plug PG2 is located on the gate wiring portion TGL and is electrically connected to the gate wiring portion TG.

[0065] Although the plug is also located on the gate electrode GE, the plug on the gate electrode GE is not shown in Figures 2 and 3.

[0066] Multiple wirings are formed on the insulating film IL. The multiple wirings include wiring M1A, wiring M1B, wiring M1D, and wiring M1S.

[0067] Wiring M1A is electrically connected to both the n-type source region SR1 and the p-type semiconductor region PR2 via plug PG1. Therefore, the source potential of power MOSFET 1 is supplied from plug PG1 to the n-type source region SR1 and through p-type semiconductor region PR2 to p-type semiconductor region PR1. Wiring M1A is connected to the load LD via a conductive path outside the semiconductor device (see Figure 1).

[0068] The back electrode BE is electrically connected to the n-type substrate body SB, and through the n-type substrate body SB, it is electrically connected to the n-type semiconductor layer EP. Therefore, the drain potential of power MOSFET 1 is supplied from the back electrode BE to the drain region of power MOSFET 1 (n-type substrate body SB and n-type semiconductor layer EP). The back electrode BE is connected to the power supply potential VB via a conductive path outside the semiconductor device (see Figure 1). Therefore, the drain potential of power MOSFET 1 is the power supply potential VB.

[0069] Wiring M1B is electrically connected to the gate wiring portion TGL via plug PG2. The gate potential of power MOSFET 1 is supplied from wiring M1B through plug PG2 and gate wiring portion TGL to the trench gate electrode TG. Wiring M1B is connected to the control circuitry within the semiconductor device via wiring within the semiconductor device.

[0070] Wiring M1D is electrically connected to the n-type drain region DR2 via plug PGD. The drain potential of LDMOSFET 2 is supplied from wiring M1D to the n-type drain region DR2 via plug PGD. The drain potential of LDMOSFET 2 is, for example, the power supply potential VB.

[0071] Wiring M1S is electrically connected to the n-type source region SR2 via plug PGS, and is also electrically connected to the p-type semiconductor region PC via plug PGP. In other words, wiring M1S is electrically connected to both plug PGS disposed on the n-type source region SR2 and plug PGP disposed on the p-type semiconductor region PC.

[0072] Therefore, the potential supplied from the plug PGS to the n-type source region SR2 (the source potential of LDMOSFET 2) is the same as the potential supplied from the plug PGE to the p-type semiconductor region PC. Thus, the source potential of LDMOSFET 2 is supplied from the plug PGS to the n-type source region SR2, and from the plug PGP via the p-type semiconductor region PC to the p-type well region PW2. The source potential of LDMOSFET 2 is, for example, ground GND.

[0073] A gate wiring is formed on the insulating film IL, which is electrically connected to the gate electrode GE via a plug, but the gate wiring is not shown in Figures 2 and 3.

[0074] Wiring M1A, Wiring M1B, Wiring M1D and Wiring M1S are not connected to each other and are separate from each other.

[0075] In the cases of Figures 2 and 3, the plug PGS and plug PGP are connected to a common wiring M1S. It is also possible for the plug PGS to be connected to wiring M1S and the plug PGP to be connected to another wiring (not shown) formed on the insulating film IL. In this case, since the wiring M1S connected to the plug PGS and the wiring (not shown) connected to the plug PGP are separate from each other, the potential supplied from the plug PGS to the n-type source region SR2 and the potential supplied from the plug PGP to the p-type semiconductor region PC can be controlled independently.

[0076] Illustrations and descriptions of the structures on the insulating film IL, wiring M1A, wiring M1B, wiring M1D, and wiring M1S are omitted. Research Background

[0077] The inventors of this application have been researching semiconductor devices having a power MOSFET 1 and an LDMOSFET 2.

[0078] Power MOSFET 1 is used as a power switching element. Therefore, it is desirable to reduce the on-resistance (resistance during conduction) of power MOSFET 1.

[0079] When power MOSFET 1 is turned off, surge voltage can be superimposed on the drain voltage. Therefore, it is desirable to improve the breakdown voltage of LDMOSFET 2 so that when a voltage higher than the supply potential VB is applied to the drain of LDMOSFET 2, LDMOSFET 2 can withstand (not be damaged).

[0080] Therefore, to improve the performance of semiconductor devices with power MOSFET 1 and LDMOSFET 2, it is desirable to both reduce the on-resistance of power MOSFET 1 and improve the breakdown voltage of LDMOSFET 2. Key features and effects.

[0081] Increasing the n-type impurity concentration in the n-type semiconductor layer EP is effective in reducing the on-resistance of power MOSFET 1. The operating current (on-current) of power MOSFET 1 flows between the back electrode BE and the wiring M1A via the n-type substrate SB, the n-type semiconductor layer EP, the channel formed in the p-type semiconductor region PR1, the n-type source region SR1, and the plug PG1. Therefore, by increasing the n-type impurity concentration in the n-type semiconductor layer EP, the resistance of the n-type semiconductor layer EP can be reduced, thereby reducing the on-resistance of power MOSFET 1.

[0082] In the case of Figure 1, wiring M1A is connected to the load LD located outside the semiconductor device, and the back electrode BE is connected to the power supply potential VB. The power supply potential VB supplied to the back electrode BE is supplied to the n-type semiconductor layer EP via the n-type substrate body SB. The drain potential (power supply potential VB) of LDMOSFET 2 is supplied from wiring M1D to the n-type drain region DR2 via plug PGD, and further to the n-type drift region ND via the n-type drain region DR2. The source potential of LDMOSFET 2 is supplied to the n-type source region SR2 via plug PGS and to the p-type semiconductor region PC via plug PGP, and further to the p-type well region PW1 via the p-type semiconductor region PC and the p-type well region PW2.

[0083] Therefore, a potential difference corresponding to the difference between the drain voltage (power supply potential VB) and the source voltage (ground potential GND) appears between the p-type well region PW1 and the n-type semiconductor layer EP below PW1. Furthermore, a potential difference corresponding to the difference between the drain voltage (power supply potential VB) and the source voltage (ground potential GND) appears between the n-type drift region ND and the p-type well region PW1.

[0084] Therefore, during the turn-off period of power MOSFET 1, when a surge voltage is superimposed on the drain voltage (power supply potential VB) of LDMOSFET 2, the breakdown voltage of the LDMOSFET is determined by the breakdown voltage of the PN junction formed at the bottom surface 5 of the n-type drift region ND (the boundary between the n-type drift region ND and the p-type well region PW1) and the breakdown voltage of the PN junction formed at the bottom surface 6 of the p-type well region PW1 (the boundary between the p-type well region PW1 and the n-type semiconductor layer EP). Increasing the n-type impurity concentration of the n-type semiconductor layer EP is used to reduce the breakdown voltage of the PN junction formed at the bottom surface 6 of the p-type well region PW1.

[0085] Here, the bottom surface 6 of the p-type well region PW1 has a bottom surface 6a located below the n-type drift region ND and a bottom surface 6b located below the p-type well region PW2.

[0086] Therefore, in the first embodiment, the p-type impurity concentration in the p-type well region PW1 is reduced. That is, the n-type impurity concentration in the n-type semiconductor layer EP is increased, and the p-type impurity concentration in the p-type well region PW1 is reduced.

[0087] By reducing the p-type impurity concentration in the p-type well region PW1, the depletion layer tends to diffuse downwards from the bottom surface 5 of the n-type drift region ND and upwards from the bottom surface 6 of the p-type well region PW1. As a result, the depletion layer diffusing downwards from the bottom surface 5 of the n-type drift region ND and the depletion layer extending upwards from the bottom surface 6 of the p-type well region PW1 connect, allowing almost the entire p-type well region PW1 to be depleted under the n-type drift region ND. This prevents damage to the PN junction formed at the bottom surface 5 of the n-type drift region ND when a surge voltage is superimposed on the drain voltage (supply potential VB) of the LDMOSFET 2, and also prevents damage to the PN junction formed at the bottom surface 6a of the p-type well region PW1.

[0088] As a result, when a surge voltage is superimposed on the drain voltage (power supply potential VB) of LDMOSFET 2, the breakdown voltage of LDMOSFET 2 is not determined by the breakdown voltage of the PN junction formed at the bottom surface 5 of the n-type drift region ND, nor by the breakdown voltage of the PN junction formed at the bottom surface 6a of the p-type well region PW1, but almost entirely by the breakdown voltage of the PN junction formed at the top surface 6b of the p-type well region PW1. Since the n-type impurity concentration in the n-type drift region ND is higher than that in the n-type semiconductor layer EP, the breakdown voltage of the PN junction formed at the bottom surface 6b of the p-type well region PW1 is higher than that of the PN junction formed at the bottom surface 5 of the n-type drift region ND. Therefore, the breakdown voltage of LDMOSFET 2 is not affected by the breakdown voltage of the PN junction formed at the bottom surface 5 of the n-type drift region ND, nor by the breakdown voltage of the PN junction formed at the bottom surface 6a of the p-type well region PW1. Instead, it is determined by the breakdown voltage of the PN junction formed at the bottom surface 6b of the p-type well region PW1, thereby improving the breakdown voltage of LDMOSFET.

[0089] Therefore, the technical concept of the first embodiment is to increase the n-type impurity concentration of the n-type semiconductor layer EP and decrease the p-type impurity concentration of the p-type well region PW1. Thus, in the first embodiment, the p-type impurity concentration of the p-type well region PW1 is lower than the n-type impurity concentration of the n-type semiconductor layer EP. More specifically, the p-type impurity concentration of the p-type well region PW1 is lower than the n-type impurity concentration of the n-type semiconductor layer EP below the p-type well region PW1. This allows for both a reduction in the on-resistance of the power MOSFET 1 and an improvement in the breakdown voltage of the LDMOSFET 2, thereby improving the performance of the semiconductor device.

[0090] To accurately achieve the effect of reducing the on-resistance of power MOSFET 1, it is preferred that the n-type impurity concentration of the n-type semiconductor layer EP be 1.0E16 / cm³ or greater and 1.0E17 / cm³ or less. To accurately achieve the effect of improving the breakdown voltage of LDMOSFET 2, it is preferred that the p-type impurity concentration of the p-type well region PW1 be 1.0E16 / cm³ or greater and 1.0E17 / cm³ or less.

[0091] The p-type impurity concentration in the p-type well region PW1 is preferably set so that the entire p-type well region PW1 is depleted in the n-type drift region ND. Second embodiment

[0092] Figures 4 and 5 are graphs showing the p-type impurity concentration distribution in the p-type well region PW1 of the semiconductor device of the first embodiment, and Figures 6 and 7 are graphs showing the p-type impurity concentration distribution in the p-type well region PW1 of the semiconductor device of the second embodiment. The vertical axis of each graph indicates the p-type impurity concentration, and the horizontal axis of each graph indicates the depth position.

[0093] Note that Figures 4 and 6 show the p-type impurity concentration distribution in the p-type well region PW1 below the n-type drain region DR2. That is, Figures 4 and 6 show the p-type impurity concentration distribution in the p-type well region PW1 at the location along the dashed line L1 shown in Figure 3. Figures 5 and 7 show the p-type impurity concentration distribution in the p-type well region PW1 below the side surface 8 of the n-type drift region ND. Specifically, Figures 5 and 7 show the p-type impurity concentration distribution at the location along the dashed line L2 shown in Figure 3. The side surface (end) 8 of the n-type drift region ND overlaps with the gate electrode GE2 in the plan view and is adjacent to the channel of the LDMOSFET 2.

[0094] The difference between the semiconductor device of the first embodiment and that of the second embodiment lies in the distribution of p-type impurity concentration in the p-type well region PW1.

[0095] In the first embodiment, as shown in FIG. 4, the p-type impurity concentration in the p-type well region PW1 below the n-type drain region DR2 is almost constant, regardless of the depth position within the p-type well region PW1. In the first embodiment, as shown in FIG. 5, the p-type impurity concentration in the p-type well region PW1 below the side surface 8 of the n-type drift region ND gradually decreases with increasing depth (gradually decreasing towards the bottom surface 6). Therefore, in the first embodiment, the trend of p-type impurity concentration distribution in the p-type well region PW1 below the side surface 8 of the n-type drift region ND differs from the trend of p-type impurity concentration distribution in the p-type well region PW1 below the n-type drain region DR2. As a result, when the depletion layer diffuses downwards from the bottom surface 5 of the n-type drift region ND, the diffusion patterns of the depletion layer below the n-type drain region DR2 and below the side surface 8 of the n-type drift region ND tend to differ.

[0096] In contrast, in the second embodiment, as shown in FIG. 6, the p-type impurity concentration in the p-type well region PW1 below the n-type drain region DR2 gradually decreases with increasing depth (gradually decreasing towards the bottom surface 6). In the second embodiment, as shown in FIG. 7, the p-type impurity concentration in the p-type well region PW1 below the side surface 8 of the n-type drift region ND gradually decreases with increasing depth (gradually decreasing towards the bottom surface 6). Therefore, in the second embodiment, the trend of p-type impurity concentration distribution in the p-type well region PW1 below the side surface 8 of the n-type drift region ND is the same as the trend of p-type impurity concentration distribution in the p-type well region PW1 below the n-type drain region DR2. This allows the depletion layer to diffuse almost uniformly downwards from the bottom surface 5 of the n-type drift region ND, thereby more easily depleting the entire p-type well region PW1 below the n-type drift region ND. As a result, when a surge voltage is superimposed on the drain voltage (power supply potential VB) of LDMOSFET 2, breakdown can be accurately prevented at the PN junction formed at the bottom surface 5 of the n-type drift region ND and the PN junction formed at the bottom surface 6a of the p-type well region PW1. Therefore, the breakdown voltage of LDMOSFET 2 can be further improved.

[0097] The present invention has been described in detail above based on the embodiments, but the present invention is not limited to the above embodiments, and needless to say, various modifications can be made without departing from its spirit.

Claims

1. A semiconductor device, comprising: A semiconductor substrate having a main surface and a back surface opposite to the main surface; A first MOSFET is formed at the main surface of the semiconductor substrate; A second MOSFET is formed at the main surface of the semiconductor substrate; and a back electrode, formed on the back surface of the semiconductor substrate, wherein the semiconductor substrate includes: a substrate region of a first conductivity type; and a semiconductor layer of the first conductivity type formed on the substrate region, wherein the first MOSFET includes: a gate electrode formed on the semiconductor layer via a gate insulating film; a first source region of the first conductivity type formed in the semiconductor layer; a first drain region of the first conductivity type formed in the semiconductor layer; a drift region of the first conductivity type formed in the semiconductor layer and contacting the bottom surface of the first drain region; a first well region of a second conductivity type formed in the semiconductor layer and contacting the bottom surface of the first source region, the second conductivity type being opposite to the first conductivity type; and a second well region of the second conductivity type formed in the semiconductor layer and contacting the bottom surface of the drift region and the bottom surface of the first well region, wherein the second MOSFET includes: a trench gate electrode formed in a trench of the semiconductor layer via a second gate insulating film; the first conductivity type A second source region is formed in the semiconductor layer and adjacent to the trench gate electrode via the second gate insulating film; and a first semiconductor region of the second conductivity type is formed in the semiconductor layer, located below the second source region, and adjacent to the trench gate electrode via the second gate insulating film, wherein the bottom surface of the drift region is shallower than the bottom surface of the second well region, wherein the bottom surface of the first well region is shallower than the bottom surface of the second well region, wherein the bottom surface of the first drain region is shallower than the bottom surface of the drift region, wherein the bottom surface of the first source region is shallower than the bottom surface of the first well region, wherein the impurity concentration of the first conductivity type in the first source region is higher than the impurity concentration of the first conductivity type in the drift region, wherein the impurity concentration of the second conductivity type in the first well region is higher than the impurity concentration of the second conductivity type in the second well region, and wherein the impurity concentration of the second conductivity type in the second well region is lower than the impurity concentration of the first conductivity type in the semiconductor layer.

2. The semiconductor device of claim 1, wherein the semiconductor layer located below the first semiconductor region and the substrate region located below the first semiconductor region serve as the second drain region of the second MOSFET.

3. The semiconductor device of claim 1, wherein the first MOSFET includes a second semiconductor region of the second conductivity type formed in the semiconductor layer, wherein the impurity concentration of the second conductivity type in the second semiconductor region is higher than the impurity concentration of the second conductivity type in the first well region, and wherein the first well region is in contact with the bottom surface of the first source region and the bottom surface of the second semiconductor region.

4. The semiconductor device according to claim 3, comprising: An insulating film is formed on the main surface of the semiconductor substrate and covers the gate electrode; The first contact plug penetrates the insulating film and is electrically connected to the first drain region; The second contact plug penetrates the insulating film and is electrically connected to the first source region; And a third contact plug, which penetrates the insulating film and is electrically connected to the second semiconductor region.

5. The semiconductor device of claim 4, wherein a first fixed potential is supplied from the first contact plug to the first drain region, wherein a second fixed potential different from the first fixed potential is supplied from the second contact plug to the first source region, wherein the second fixed potential is supplied from the third contact plug to the second semiconductor region, and wherein the first fixed potential is supplied from the back electrode to the substrate region.

6. The semiconductor device of claim 5, wherein the first conductivity type is n-type, wherein the second conductivity type is p-type, and wherein the first fixed potential is higher than the second fixed potential.

7. The semiconductor device of claim 6, wherein the second MOSFET is a power switching element.

8. The semiconductor device of claim 1, wherein a portion of the gate electrode overlaps with the drift region in a plan view, and wherein another portion of the gate electrode overlaps with the first well region.

9. The semiconductor device of claim 1, wherein the impurity concentration of the first conductivity type in the drift region is higher than the impurity concentration of the first conductivity type in the semiconductor layer.

10. The semiconductor device of claim 1, wherein, under the first drain region, the impurity concentration of the second conductivity type in the second well region gradually decreases toward the bottom surface of the second well region, wherein, under the side surface of the drift region, the impurity concentration of the second conductivity type in the second well region gradually decreases toward the bottom surface of the second well region, and wherein the side surface of the drift region overlaps with the gate electrode in a plan view.

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