Image sensor and manufacturing method thereof
By introducing conductive isolation rings and filter structures into CMOS image sensors, the process complexity of pixel isolation is solved, thereby improving the reliability and signal transmission efficiency of CMOS image sensors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 合肥海图微电子有限公司
- Filing Date
- 2025-12-15
- Publication Date
- 2026-05-01
AI Technical Summary
Existing CMOS image sensors have high process complexity in pixel isolation, and require additional photomasks and different types of ion implantation regions when the transistor type is different, which increases the process complexity.
A conductive isolation ring is set in the epitaxial layer of the pixel area. The conductive isolation ring surrounds the trench isolation structure and the photodiode, and is connected to the ground layer of the through-silicon via contact or grounding area in the through-silicon via region. It suppresses leakage current and signal crosstalk by negative voltage, and combines filter structure and grid structure to improve the isolation effect.
It reduces process complexity, improves chip reliability and signal response speed, reduces signal crosstalk, and simplifies the process flow.
Smart Images
Figure CN121968757A_ABST
Abstract
Description
An image sensor and its fabrication method Technical Field
[0001] This invention belongs to the field of semiconductor technology, and specifically relates to an image sensor and its manufacturing method. Background Technology
[0002] CMOS image sensors (Complementary Metal Oxide Semiconductor Image Sensors, CIS) are widely used in consumer, surveillance, and industrial fields due to their low power consumption and low cost. During the manufacturing process of CMOS image sensors, to prevent the pixel area from being affected by peripheral circuitry, ions are typically implanted around the pixel area to form P-type or N-type isolation.
[0003] P-type or N-type isolation is required. Furthermore, at least one photomask is needed to form the isolation in the pixel area. Also, when the transistors in the pixel area are of different types, different types of ion implantation regions need to be formed to achieve pixel area isolation, further increasing the complexity of isolation formation. Summary of the Invention
[0004] The purpose of this invention is to provide an image sensor and its manufacturing method, which can achieve effective isolation of pixel areas and reduce process complexity.
[0005] To achieve the above objectives, the present invention provides an image sensor, which includes a pixel region and a junction region, or includes a pixel region, a junction region, and a through-silicon via region, and the image sensor includes at least:
[0006] The epitaxial layer of the pixel region is provided with a trench isolation structure and a photodiode;
[0007] A conductive isolation ring is disposed in the epitaxial layer, the conductive isolation ring surrounds the trench isolation structure and the photodiode, the conductive isolation ring is connected to the through-silicon via contact in the through-silicon via region or the ground layer in the ground region, and provides a negative voltage to the conductive isolation ring through the through-silicon via contact or the ground layer;
[0008] A grille is disposed on top of the trench isolation structure; and
[0009] A filter structure is disposed on top of the photodiode.
[0010] In one embodiment of the present invention, the conductive isolation ring includes:
[0011] Repair layer, covering the sidewalls of the annular groove;
[0012] A high dielectric constant layer covers the repair layer;
[0013] An adhesion layer covering the high dielectric constant layer; and
[0014] A copper metal layer covers the adhesive layer, and the copper metal layer fills the annular grooves within the adhesive layer.
[0015] In one embodiment of the present invention, when the conductive isolation ring is connected to the through-silicon via (TSV) contact of the TSV region, the image sensor further includes a conductive transition layer that covers the conductive isolation ring.
[0016] In one embodiment of the present invention, when the conductive isolation ring is connected to the through-silicon via (TSV) contact in the TSV region, the image sensor further includes a metal connection layer, the metal connection layer covers the conductive transition layer, and the metal connection layer is connected to the TSV contact.
[0017] In one embodiment of the present invention, when the conductive isolation ring is connected to the through-silicon via (TSV) contact in the TSV region, the image sensor further includes:
[0018] Contact pads, wherein the contact pads are disposed on the through-silicon via contacts, and the contact pads are connected to the top of the through-silicon via contacts; and
[0019] A metal connecting wire, one end of which is connected to a contact pad and the other end of which is connected to a metal connecting layer.
[0020] In one embodiment of the present invention, when the conductive isolation ring is connected to the through-silicon via (TSV) contact in the TSV region, the image sensor further includes a diffusion barrier layer that covers a portion of the TSV contact.
[0021] In one embodiment of the present invention, when the conductive isolation ring is connected to the grounding layer of the grounding area, one side of the conductive isolation ring is disposed within the grounding area, and the grounding layer covers a portion of the conductive isolation ring.
[0022] The present invention also provides a method for manufacturing an image sensor, the image sensor comprising a pixel area and a junction area, or comprising a pixel area, a junction area and a through-silicon via area, and the manufacturing method comprising at least the following steps:
[0023] An epitaxial layer is provided, wherein a trench isolation structure and a photodiode are disposed in the epitaxial layer of the pixel region;
[0024] A conductive isolation ring is formed in the epitaxial layer, the conductive isolation ring surrounds the trench isolation structure and the photodiode, the conductive isolation ring is connected to the through-silicon via contact in the through-silicon via region or the ground layer in the ground region, and a negative voltage is provided to the conductive isolation ring through the through-silicon via contact or the ground layer;
[0025] A grille is provided on top of the trench isolation structure; and
[0026] A filter structure is provided on the top of the photodiode.
[0027] In one embodiment of the present invention, when the conductive isolation ring is connected to the through-silicon via (TSV) contact in the TSV region, forming the conductive isolation ring includes the following steps:
[0028] A patterned photoresist layer is formed on the epitaxial layer, the patterned photoresist layer defining the positions of the through-silicon via contact and the conductive isolation ring;
[0029] Using the patterned photoresist as a mask, the epitaxial layer is etched to form through-silicon vias and annular grooves;
[0030] A repair layer, a high dielectric constant layer, an adhesion layer, and a copper metal layer are deposited sequentially in the annular groove to form a conductive isolation ring.
[0031] In one embodiment of the present invention, when the conductive isolation ring is connected to the grounding layer of the grounding area, forming the conductive isolation ring includes the following steps:
[0032] A patterned photoresist layer is formed on the epitaxial layer, and the patterned photoresist layer defines the positions of the trench isolation structure and the conductive isolation ring;
[0033] Using the patterned photoresist as a mask, the epitaxial layer is etched to form isolation trenches and annular grooves;
[0034] A repair layer, a high dielectric constant layer, an adhesion layer, and a copper metal layer are sequentially deposited in the annular groove to form a conductive isolation ring, one side of which is located within the grounding area; and
[0035] A ground layer is formed on the epitaxial layer of the grounding area, and the ground layer covers one side of the conductive isolation ring.
[0036] In summary, the image sensor and its fabrication method provided by this invention form a conductive isolation ring surrounding a photodiode and a trench isolation structure, and connect the conductive isolation ring to a through-silicon via (TSV) contact or a ground layer. During image sensor operation, negative voltage bias is used to suppress leakage current and signal crosstalk in deeper regions of the silicon substrate, improving chip reliability. Simultaneously, during the formation of the TSV or isolation trench, the epitaxial layer is etched concurrently to form the annular groove containing the conductive isolation ring, reducing process complexity while saving costs. Furthermore, the conductive isolation ring is a metal conductive isolation ring, allowing for the use of identical conductive isolation rings even when the transistor types in the pixel area differ, further reducing process complexity. Attached Figure Description
[0037] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0038] Figure 1 is a schematic diagram of the structure of an image sensor in one embodiment of the present invention.
[0039] Figure 2 is a top view of the image sensor in Figure 1.
[0040] Figure 3 is a schematic diagram of the structure of the conductive isolation ring in one embodiment of the present invention.
[0041] Figure 4 is a schematic diagram of the structure forming a photodiode and a trench isolation structure in one embodiment of the present invention.
[0042] Figure 5 is a schematic diagram of the structure forming a conductive isolation ring and a through-silicon via contact in one embodiment of the present invention.
[0043] Figure 6 is a schematic diagram of the structure forming a conductive transition layer and a diffusion barrier layer in one embodiment of the present invention.
[0044] Figure 7 is a schematic diagram of the structure forming a metal connection layer, a contact pad, a metal connection line, a grid, and a grounding layer in one embodiment of the present invention.
[0045] Figure 8 is a schematic diagram of the structure forming the filter structure in one embodiment of the present invention.
[0046] Figure 9 is a schematic diagram of the image sensor structure in another embodiment of the present invention.
[0047] Figure 10 is a top view of the image sensor in Figure 9. Detailed Implementation
[0048] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.
[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.
[0050] In the description of this invention, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," and "right," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0051] A CMOS image sensor is a typical solid-state imaging sensor, typically comprising a pixel array, row drivers, column drivers, timing control logic, and an analog-to-digital converter (AD converter). These semiconductor devices are usually integrated onto a single silicon chip and are isolated from each other. The pixel array contains multiple photodiodes arranged in an array, each forming a pixel unit. When an image is focused onto the pixel array by an imaging lens, the photodiodes convert the light signals on their surfaces into electrical signals. These electrical signals are then processed by the row drivers, column drivers, timing control logic, and AD converter, and converted into digital signals for readout.
[0052] Please refer to Figures 1 and 9. The image sensor provided in this application includes a pixel chip and a logic chip. The pixel chip is equipped with a photodiode 206 and a CMOS transistor. The photodiode 206 converts light signals into electrical signals. The CMOS transistor includes transistors such as a transmission transistor, a reset transistor, and a source follower transistor, which are responsible for regulating the stored charge. The logic chip is equipped with devices such as a row driver, a column driver, timing control logic, and an AD converter, which can convert the analog voltage signal output by the pixel into a usable digital image signal and realize system control and data transmission. When the pixel chip and the logic chip are bonded, they can be bonded by setting a bonding layer 102 between the logic substrate 101 and the pixel substrate 201, or by a hybrid bonding method. When the pixel chip and the logic chip are bonded by setting a bonding layer 102 between the logic substrate 101 and the pixel substrate 201, the image sensor includes a pixel area, a junction area, and a through-silicon via area. The photodiode 206 in the pixel area converts the light signal into an electrical signal. The grounding layer 214 in the grounding area can ground all semiconductor devices on the pixel chip that need to be grounded. The through-silicon via (TSV) contacts 209 in the through-silicon via (TSV) area electrically connect the pixel chip and the logic chip. When the pixel chip and the logic chip are bonded by hybrid bonding, the connection metal layer 103 of the logic substrate 101 and the pixel substrate 201 are in direct contact, and the TSV area is omitted in the image sensor.
[0053] Please refer to Figures 1, 2, 9, and 10. The image sensor provided in this application may include a pixel area and a junction area, or it may include a pixel area, a junction area, and a through-silicon via (TSV) area. The image sensor provided in this application includes an epitaxial layer 204, a conductive isolation ring 208, a grid 216, and a filter structure. The epitaxial layer 204 in the pixel area contains a trench isolation structure 205 and a photodiode 206. The conductive isolation ring 208 is disposed in the epitaxial layer 204, surrounding the trench isolation structure 205 and the photodiode 206. The conductive isolation ring 208 is connected to the TSV contact 209 in the TSV area or the ground layer 214 in the junction area, and provides a negative voltage to the conductive isolation ring 208 through the TSV contact 209 or the ground layer 214. The grid 216 is disposed on top of the trench isolation structure 205, and the filter structure is disposed on top of the photodiode 206.
[0054] Specifically, as shown in Figure 4, in one embodiment of the present invention, the image sensor includes a bonded pixel substrate 201 and a logic substrate 101. The logic substrate 101 contains an integrated circuit structure designed according to the functional requirements of the CMOS image sensor. The pixel substrate 201 can be a common semiconductor substrate such as silicon (Si), silicon carbide (SiC), sapphire (Al2O3), gallium arsenide (GaAs), and lithium aluminate (LiAlO2). A metal interconnect layer 202 is disposed on the surface of the pixel substrate 201 away from the logic substrate 101. Metal layers 2021 in the metal interconnect layer 202 can connect photodiodes 206 in the pixel chip through a preset circuit. Adjacent metal layers 2021 are separated, for example, by a silicon oxide dielectric layer. An epitaxial layer 204 is disposed on the surface of the metal interconnect layer 202 away from the pixel substrate 201, and the epitaxial layer 204 is, for example, a silicon epitaxial layer 204. An etch stop layer 203, for example, a silicon oxide layer, can also be disposed between the metal interconnect layer 202 and the epitaxial layer 204. In this embodiment, the pixel substrate 201 and the logic substrate 101 are bonded together by a bonding layer 102. The bonding layer 102 can be a polymer bonding layer formed by materials such as epoxy resin, polyimide resin or benzocyclobutene resin. Alternatively, the bonding layer 102 can be an inorganic insulating bonding layer formed by materials such as silicon oxide (SiO2) or silicon nitride (Si3N4).
[0055] Referring to Figure 4, in one embodiment of the present invention, an ion-doped region is provided in the epitaxial layer 204 of the pixel region. After being isolated by an isolation trench structure, the ion-doped region can be divided into multiple photodiodes 206. This application does not limit the type of ion-doped region, as long as the desired device is formed. In some embodiments, N-type ions, such as phosphorus ions or arsenic ions, can be implanted in the epitaxial layer 204 to form an N-type ion-doped region. In other embodiments, P-type ions, such as boron ions, can also be implanted in the epitaxial layer 204 to form a P-type ion-doped region.
[0056] Referring to Figures 2 and 4, in one embodiment of the present invention, a trench isolation structure 205 is provided in the epitaxial layer 204 of the pixel region. The trench isolation structure 205 surrounds the doped region and isolates the ion-doped region into multiple photodiodes 206 arranged in an array. Specifically, after bonding the pixel substrate 201 and the logic substrate 101, photoresist is coated on the surface of the epitaxial layer 204, and a patterned photoresist layer (not shown in the figures) is formed through processes such as exposure and development. This patterned photoresist layer defines the location of the isolation trench. Then, using the patterned photoresist layer as a mask, a portion of the epitaxial layer 204 located under the patterned photoresist layer is quantitatively removed using etching methods such as dry etching, wet etching, or a combination of dry and wet etching to obtain the isolation trench. After forming the isolation trench, an isolation medium is deposited in the isolation trench, and the isolation medium is, for example, an insulating material such as silicon oxide (SiO2). The top of the isolation medium is flattened by planarization processes such as chemical mechanical polishing (CMP) to form multiple groove isolation structures 205.
[0057] Referring to Figures 4 and 5, in one embodiment of the present invention, an oxide layer 207 is further disposed on the surface of the epitaxial layer 204, covering the epitaxial layer 204. Specifically, after forming the trench isolation structure 205, a layer of silicon oxide (SiO2) can be deposited on the surface of the epitaxial layer 204 as the oxide layer 207. The oxide layer 207 is dense and chemically stable, which can provide physical and chemical protection for the formed photodiode 206, while forming insulation isolation and electrical protection. Furthermore, the oxide layer 207 can form stable chemical bonds with the dangling bonds on the silicon surface, passivating the surface of the photodiode 206, thereby reducing dark current.
[0058] Referring to Figures 2 and 5, in one embodiment of the present invention, a conductive isolation ring 208 is provided in the pixel area and the epitaxial layer 204 adjacent to the pixel area. The conductive isolation ring 208 surrounds the trench isolation structure 205 and the photodiode 206, and the conductive isolation ring 208 passes through the epitaxial layer 204 and contacts the etch stop layer 203. The conductive isolation layer includes a repair layer 2081, a high dielectric constant layer 2082, an adhesion layer 2083, and a copper metal layer 2084 disposed in an annular groove. The repair layer 2081 covers the sidewalls of the annular groove, the high dielectric constant layer 2082 covers the repair layer 2081, the adhesion layer 2083 covers the high dielectric constant layer 2082, and the copper metal layer 2084 covers the adhesion layer 2083, with the copper metal layer 2084 filling the annular groove within the adhesion layer 2083.
[0059] Referring to Figure 5, in one embodiment of the present invention, a through-silicon via (TSV) contact 209 is provided in the epitaxial layer 204 of the TSV region. The TSV contact 209 includes a first TSV contact, a second TSV contact, and a third TSV contact connected in sequence. The first TSV contact passes through the epitaxial layer 204, the second TSV contact passes through the etch stop layer 203 and the metal interconnect layer 202, and the third TSV contact passes through the pixel substrate 201, the bonding layer 102, and a portion of the logic substrate 101. Electrical signals in the logic substrate 101 can be transmitted to the surface of the epitaxial layer 204 through the first, second, and third TSV contacts.
[0060] Referring to Figure 5, in one embodiment of the present invention, the epitaxial layer 204 can be simultaneously etched using the same photomask, forming a through-silicon via (TSV) while simultaneously etching the annular groove containing the conductive isolation ring 208. Thus, without adding a photomask, the TSV and the annular groove can be obtained simultaneously by modifying the photomask. Specifically, after forming the oxide layer 207, a patterned photoresist layer (not shown in the figure) is formed on the oxide layer 207 on the epitaxial layer 204. This patterned photoresist layer defines the positions of the TSV contact 209 and the conductive isolation ring 208. Then, using this patterned photoresist layer as a mask, the oxide layer 207 and the epitaxial layer 204 located under the patterned photoresist layer are quantitatively etched using etching methods such as dry etching, wet etching, or a combination of dry and wet etching to form the TSV and the annular groove. During the first etching, the annular groove passing through the epitaxial layer 204 and the TSV containing the first TSV contact can be formed. Next, two etching processes can be performed to sequentially form the third through-silicon via contact and the through-silicon via contact where the second through-silicon via contact is located.
[0061] Referring to Figures 3 and 5, in one embodiment of the present invention, after forming the through-silicon via (TSV) and the annular groove, a repair layer 2081, a high dielectric constant layer 2082, an adhesion layer 2083, and a copper metal layer 2084 are sequentially deposited in the annular groove to form a conductive isolation ring 208. Copper metal is deposited in the TSV to form the TSV contact 209. Specifically, during the first deposition, a layer of silicon oxide (SiO2) can be deposited inside the annular groove as the repair layer 2081 using deposition methods such as dielectric plasma oxidation (DPO) or in-situ steam generation (ISSG). The thickness of the formed repair layer 2081 is, for example, [missing information]. The silicon oxide (SiO2) generated at high temperature has a dense structure and strong adhesion to the surface of the epitaxial layer 204, effectively repairing silicon lattice damage caused by isolation trench etching. During the second deposition, a high-dielectric-constant layer 2082, consisting of hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), or an HfO2-SiO2 stack, can be deposited on the surface of the repair layer 2081 using methods such as atomic layer deposition (ALD). The thickness of the formed high-dielectric-constant layer 2082 is, for example, 10 nm to 40 nm. The high-dielectric-constant layer 2082 can strengthen the insulating isolation of the pixel and simultaneously regulate the parasitic capacitance between the copper metal layer 2084 and the epitaxial layer 204, preventing excessive capacitance from slowing down the pixel signal response speed and ensuring the stability of the pixel's electrical performance. During the third deposition, a titanium nitride (TiN) layer 2083 can be deposited on the surface of the high-dielectric-constant layer 2082 using methods such as atomic layer deposition or sputtering. The thickness of the formed adhesion layer 2083 is, for example, 5 nm to 20 nm. The adhesion layer 2083 enhances the adhesion between the copper metal layer 2084 and the high dielectric constant layer 2082, and titanium nitride, being a dense metal nitride, effectively blocks the migration of copper ions, preventing copper contamination. During the fourth deposition, a layer of copper (Cu) can be deposited in the annular groove within the adhesion layer 2083 to form the copper metal layer 2084 by methods such as electroplating or PVD sputtering. The thickness of the formed copper metal layer 2084 is, for example, 3.5 μm to 5 μm. Copper has a much lower resistivity than conventional aluminum; at the same linewidth, the copper metal ring has lower conductivity loss and can quickly conduct charge. Electrical isolation of the pixel is achieved by applying a fixed potential, avoiding signal crosstalk. In this embodiment, during the fourth deposition, while depositing copper in the annular groove to form the copper metal layer 2084, copper is simultaneously deposited in the through-silicon via (TSV) to form the TSV contact 209.
[0062] Referring to Figure 6, in one embodiment of the present invention, a conductive transition layer 210 is further disposed on the surface of the oxide layer 207, and the conductive transition layer 210 covers the conductive isolation ring 208. Specifically, after forming the conductive isolation ring 208 and the through-silicon via contact 209, a layer of titanium nitride (TiN) can be deposited on the conductive isolation ring 208 as the conductive transition layer 210 by methods such as atomic layer deposition or sputtering. The conductive transition layer 210 disposed on the conductive isolation ring 208 can block metal diffusion between the conductive isolation ring 208 and the subsequently formed metal interconnect layer 215, increase the adhesion between the conductive isolation ring 208 and the subsequently formed metal interconnect layer 215, and reduce the contact resistance between the two metals.
[0063] Referring to Figure 6, in one embodiment of the present invention, a diffusion barrier layer 211 is further disposed on the surface of the oxide layer 207, and the diffusion barrier layer 211 covers a portion of the through-silicon via (TSV) contact 209. Specifically, after forming the conductive isolation ring 208 and the TSV contact 209, a layer of silicon nitride (Si3N4) or silicon oxynitride (SiON) can be deposited as the diffusion barrier layer 211 by methods such as chemical vapor deposition. The diffusion barrier layer 211 disposed on the TSV contact 209 can prevent the diffusion of metallic copper in the TSV contact 209, while increasing the adhesion between the TSV contact 209 and the subsequently formed contact pad 213, and reducing the contact resistance between the TSV contact 209 and the subsequently formed contact pad 213.
[0064] Please refer to Figure 7. In one embodiment of the present invention, a dielectric layer 212 is disposed on the diffusion barrier layer 211, and the dielectric layer 212 covers the diffusion barrier layer 211. After the diffusion barrier layer 211 is formed, a layer of silicon oxide (SiO2) can be deposited on the diffusion barrier layer 211 as the dielectric layer 212.
[0065] Referring to Figure 7, in one embodiment of the present invention, a metal interconnect layer 215 is disposed on the conductive transition layer 210, covering the conductive transition layer 210, and the metal interconnect layer 215 is connected to the through-silicon via (TSV) contact 209. A contact pad 213 is disposed on the TSV contact 209, connecting the top of the TSV contact 209 and the metal interconnect layer 215. In this application, the contact pad 213 is disposed in the TSV region, and the metal interconnect layer 215 is disposed in the pixel region. To achieve the connection between the contact pad 213 and the metal interconnect layer 215, a metal interconnect line 2150 is provided. The metal interconnect layer 215 spans the contact area, and one end of the metal interconnect line 2150 is connected to any contact pad 213 within the TSV region, and the other end is connected to the metal interconnect layer 215. By providing the metal interconnect layer 215, the contact pad 213, and the metal interconnect line 2150, the TSV contact 209 and the conductive isolation ring 208 can be connected. When the image sensor is working, a negative voltage is provided to the conductive isolation ring 208 through the through-silicon via contact 209 to achieve negative voltage bias, thereby suppressing leakage and signal crosstalk in the deeper regions of the epitaxial layer 204 and improving the reliability of the chip.
[0066] Referring to Figure 7, in one embodiment of the present invention, a grid 216 is provided on the oxide layer 207, and the grid 216 is located on the oxide layer 207 at the top of the trench isolation structure 205. Specifically, the orthogonal projection of the grid 216 on the epitaxial layer 204 is located within the trench isolation structure 205, which can prevent crosstalk of incident light between adjacent photodiodes 205.
[0067] Please refer to Figure 7. In one embodiment of the present invention, a ground layer 214 is also provided on the epitaxial layer 204 of the grounding area. The ground layer 214 can realize the ground connection of all devices on the pixel chip that need to be grounded.
[0068] Referring to Figures 2 and 7, in one embodiment of the present invention, a metal interconnect layer 215, a contact pad 213, a metal interconnect line 2150, a grid 216, and a ground layer 214 can be formed simultaneously. Specifically, after forming the dielectric layer 212, the dielectric layer 212 in the through-silicon via (TSV) region is first etched to form an opening in the dielectric layer 212 above the TSV contact 209. Then, the oxide layer 207 in the ground region is etched to form an opening that contacts the epitaxial layer 204 at the location of the ground layer 214. Subsequently, using processes such as magnetron sputtering, a metal material with high light-shielding capacity, such as aluminum (Al) or tungsten (W), is deposited on the TSV contact 209, the dielectric layer 212, the epitaxial layer 204 where the ground layer 214 is located, the conductive transition layer 210, and the oxide layer 207 to form a metal material layer. Then, the metal material is etched according to the required shapes of the metal interconnect layer 215, contact pad 213, metal interconnect line 2150, grid 216 and ground layer 214. The contact pad 213 is formed in the through silicon via region, the ground layer 214 is formed on the epitaxial layer 204 in the ground region, the metal interconnect layer 215 and grid 216 are formed in the pixel region, and the metal interconnect line 2150 is formed in the through silicon via region, the ground region and the pixel region.
[0069] Please refer to Figure 8. In one embodiment of the present invention, after forming the metal connection layer 215, contact pad 213, metal connection line 2150, grid 216 and ground layer 214, a layer of silicon oxide (SiO2) or silicon oxynitride (SiON) or similar material is deposited on the metal connection layer 215, contact pad 213, metal connection line 2150, grid 216 and ground layer 214 to form a protective layer 219.
[0070] Referring to Figure 8, in one embodiment of the present invention, a filter structure is further provided on the oxide layer 207. The filter structure is disposed on the oxide layer 207 on top of the photodiode 206. Specifically, after forming the metal connection layer 215, contact pad 213, metal connection line 2150, and grid 216, a filter structure is formed on the photodiode 206 between adjacent grids 216, and the filter structure is located on the oxide layer 207 on top of the photodiode 206. The filter structure includes, for example, multiple color filters 217, which form a color filter array. Each color filter 217 corresponds to one photodiode 206. In this embodiment, the filter structure may include at least three primary color filters 217, such as a blue filter, a green filter, and a red filter, and the color filters 217 can be arranged in any suitable combination. For example, the blue filter, green filter, and red filter can be arranged alternately. Alternatively, a transparent filter can be added, with blue, green, and red filters arranged alternately with the transparent filter. The color filter 217 can be a polymer material, such as a negative photoresist based on an acrylic polymer, and may contain colored dyes. After forming the grid 216, the color filter 217 can be directly vacuum-deposited between adjacent grids 216. When light passes through the color filter 217, its color can be changed, maintaining high transmittance in a certain wavelength (color), thereby enhancing the photoelectric conversion effect.
[0071] Referring to Figure 8, in one embodiment of the present invention, the filter structure further includes a microlens 218. The microlens 218 is disposed on the color filter 217, and the top of the microlens 218 is an outwardly convex arc shape, which can focus the incident light onto the photodiode 206. The curvature of the filter structure surface can be changed according to the light-gathering requirements to improve the photosensitivity. The microlens 218 structure can be formed in any way, and the present invention does not impose any specific limitations. The number of photodiodes 206 and the filter structure can be set according to actual needs; the figure in this embodiment is only an example. When the image sensor is working, light enters the photodiode 206 through the microlens 218, the color filter 217, and the oxide layer 207.
[0072] Referring to Figures 9 and 10, in another embodiment of the present invention, the pixel chip and the logic chip are bonded using a hybrid bonding method. The connection metal layer 103 of the logic substrate 101 and the pixel substrate 201 are in direct contact, and the through-silicon via (TSV) region is omitted in the image sensor. At this time, a conductive isolation ring 208 is connected to the ground layer 214 of the grounding area. Specifically, one side of the conductive isolation ring 208 can be disposed within the grounding area, and the ground layer 214 can cover a portion of the conductive isolation ring 208. At this time, the conductive isolation ring 208 is formed simultaneously with the formation of the trench isolation structure 205. Specifically, after bonding the pixel chip and the logic chip, a patterned photoresist layer is formed on the epitaxial layer 204, defining the positions of the trench isolation structure 205 and the conductive isolation ring 208. Then, using the patterned photoresist as a mask, the epitaxial layer 204 is etched, forming isolation trenches and annular grooves in the epitaxial layer 204. A repair layer 2081, a high dielectric constant layer 2082, an adhesion layer 2083, and a copper metal layer 2084 are sequentially deposited in an annular groove to form a conductive isolation ring 208. An isolation medium is deposited in the isolation trench to form multiple trench isolation structures 205.
[0073] Referring to Figures 9 and 10, and in conjunction with Figures 4 to 8, in another embodiment of the present invention, after forming the conductive isolation ring 208 and the trench isolation structure 205, an oxide layer 207, a diffusion barrier layer 211, and a dielectric layer 212 are sequentially formed. The oxide layer 207 and the epitaxial layer 204 are then etched, and a metal material layer is deposited. The metal material layer is etched to form a solder pad 220 in the solder pad region that penetrates the epitaxial layer 204 and contacts the metal layer 2021. A ground layer 214 is formed on the epitaxial layer 204 in the grounding region, and a grid 216 is formed in the pixel region. Finally, a protective layer 219 and a filter structure are formed.
[0074] Please refer to Figures 1, 2, 9, and 10. The conductive isolation ring 208 formed in this application surrounds the photodiode 206 and the trench isolation structure 205, and connects the conductive isolation ring 208 to the through-silicon via contact 209 or the ground layer 214. During image sensor operation, negative voltage bias is used to suppress leakage current and signal crosstalk in deeper areas of the silicon substrate, improving chip reliability. Simultaneously, the epitaxial layer 204 is etched concurrently during the formation of the through-silicon via or isolation trench, forming the annular groove containing the conductive isolation ring 208, which reduces process complexity.
[0075] It should be noted that this application does not limit the shape of the conductive isolation ring 208. It can be set according to the photodiode 206 and the trench isolation structure 205, as long as the distance between the conductive isolation ring 208 and the outermost trench isolation structure 205 is greater than the minimum limited distance of the isolation ring.
[0076] In summary, the present invention provides an image sensor and its fabrication method. The image sensor includes a pixel region and a junction region, or includes a pixel region, a junction region, and a through-silicon via (TSV) region. The image sensor at least includes: an epitaxial layer, in which a trench isolation structure and a photodiode are disposed; a conductive isolation ring disposed in the epitaxial layer, surrounding the trench isolation structure and the photodiode, the conductive isolation ring being connected to the TSV contact in the TSV region or the ground layer in the junction region, and providing a negative voltage to the conductive isolation ring through the TSV contact or the ground layer; a grid disposed on top of the trench isolation structure; and a filter structure disposed on top of the photodiode. When operating, the image sensor provided by this application suppresses leakage current and signal crosstalk in deeper regions of the silicon substrate by using a negative voltage bias connection through the conductive isolation ring, thereby improving the reliability of the chip.
[0077] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims
1. An image sensor, characterized in that, The image sensor includes a pixel area and a junction area, or includes a pixel area, a junction area, and a through-silicon via (TSV) area, and the image sensor includes at least: an epitaxial layer, in which a trench isolation structure and a photodiode are disposed; a conductive isolation ring disposed in the epitaxial layer, the conductive isolation ring surrounding the trench isolation structure and the photodiode, the conductive isolation ring being connected to the TSV contact of the TSV area or the ground layer of the junction area, and providing a negative voltage to the conductive isolation ring through the TSV contact or the ground layer; a grid disposed on top of the trench isolation structure; and a filter structure disposed on top of the photodiode.
2. An image sensor according to claim 1, characterized in that, The conductive isolation ring includes: a repair layer covering the sidewalls of the annular groove; a high dielectric constant layer covering the repair layer; an adhesive layer covering the high dielectric constant layer; and a copper metal layer covering the adhesive layer, wherein the copper metal layer fills the annular groove within the adhesive layer.
3. An image sensor according to claim 1, characterized in that, When the conductive isolation ring is connected to the through-silicon via (TSV) contact in the TSV region, the image sensor further includes a conductive transition layer that covers the conductive isolation ring.
4. An image sensor according to claim 3, characterized in that, When the conductive isolation ring is connected to the through-silicon via contact in the through-silicon via region, the image sensor further includes a metal connection layer that covers the conductive transition layer and is connected to the through-silicon via contact.
5. An image sensor according to claim 4, characterized in that, When the conductive isolation ring is connected to the through-silicon via contact in the through-silicon via region, the image sensor further includes: a contact pad disposed on the through-silicon via contact and connected to the top of the through-silicon via contact; and a metal connecting wire, one end of which is connected to the contact pad and the other end of which is connected to the metal connecting layer.
6. An image sensor according to claim 5, characterized in that, When the conductive isolation ring is connected to the through-silicon via (TSV) contact in the TSV region, the image sensor further includes a diffusion barrier layer that covers a portion of the TSV contact.
7. An image sensor according to claim 1, characterized in that, When the conductive isolation ring is connected to the grounding layer of the grounding area, one side of the conductive isolation ring is disposed within the grounding area, and the grounding layer covers a portion of the conductive isolation ring.
8. A method for manufacturing an image sensor, characterized in that, The image sensor includes a pixel region and a junction region, or includes a pixel region, a junction region, and a through-silicon via (TSV) region, and the fabrication method includes at least the following steps: providing an epitaxial layer, wherein a trench isolation structure and a photodiode are disposed in the epitaxial layer of the pixel region; forming a conductive isolation ring in the epitaxial layer, the conductive isolation ring surrounding the trench isolation structure and the photodiode, the conductive isolation ring being connected to the TSV contact of the TSV region or the ground layer of the junction region, and providing a negative voltage to the conductive isolation ring through the TSV contact or the ground layer; disposing a grid on top of the trench isolation structure; and disposing a filter structure on top of the photodiode.
9. A method for manufacturing an image sensor according to claim 8, characterized in that, When the conductive isolation ring is connected to the through-silicon via (TSV) contact in the TSV region, forming the conductive isolation ring includes the following steps: forming a patterned photoresist layer on the epitaxial layer, the patterned photoresist layer defining the positions of the TSV contact and the conductive isolation ring; using the patterned photoresist as a mask, etching the epitaxial layer to form a TSV and an annular groove; and sequentially depositing a repair layer, a high dielectric constant layer, an adhesion layer, and a copper metal layer in the annular groove to form the conductive isolation ring.
10. A method for manufacturing an image sensor according to claim 8, characterized in that, When the conductive isolation ring is connected to the ground layer of the grounding region, forming the conductive isolation ring includes the following steps: forming a patterned photoresist layer on the epitaxial layer, the patterned photoresist layer defining the position of the trench isolation structure and the conductive isolation ring; using the patterned photoresist as a mask, etching the epitaxial layer to form an isolation trench and an annular groove; sequentially depositing a repair layer, a high dielectric constant layer, an adhesion layer and a copper metal layer in the annular groove to form a conductive isolation ring, one side of the conductive isolation ring being located within the grounding region; and forming a ground layer on the epitaxial layer of the grounding region, the ground layer covering one side of the conductive isolation ring.