InGaAs focal plane detector based on DTW integration and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor devices, in particular to an InGaAs focal plane detector based on DTW integration and a preparation method of the InGaAs focal plane detector, and the InGaAs focal plane detector comprises a silicon-based readout circuit wafer layer, an InGaAs detector array chip layer, N electrode metal and an optical filter film structure layer. The first indium bump array and the second indium bump array are bonded in a flip-chip manner and are filled and fixed by an organic polymer medium; the N electrode metal is respectively connected with the n-InP contact layer and the N electrode region; and the optical filter film structure layer is arranged on the back surface of the InGaAs detector array chip layer. According to the DTW integration technology based on the In salient point array, a traditional N hole structure and a preparation technology are removed, the N electrode is led out from the back face to the N electrode of the reading circuit after the substrate is removed, the technology steps can be simplified, the area of a detector array chip is reduced, a wafer-level machining platform is connected, and the condition for constructing a high-performance optical filtering structure is achieved.

Description

A DTW-based InGaAs focal plane detector and its fabrication method Technical Field

[0001] This application relates to the field of semiconductor device technology, specifically to an InGaAs focal plane detector based on DTW integration and its fabrication method. Background Technology

[0002] Near-infrared InGaAs focal plane array detectors have advantages such as near-room temperature operation, high detectivity, high uniformity, and stable performance. They also have excellent imaging capabilities through smoke, fog, and dust, playing an important role in fields such as spectral analysis, low-light night vision, military reconnaissance and surveillance, space laser detection, and aerospace remote sensing.

[0003] Traditional InGaAs PIN focal plane array detectors typically employ die-to-die flip-chip interconnect technology. However, existing technologies still face several bottlenecks: key process steps after flip-chip bonding are limited to die-level operations, resulting in low process efficiency and difficulty in meeting the demands of large-scale production; the process requirements heavily rely on manual operation, leading to significant limitations on interoperability yield due to factors such as particulate contamination and bond warpage.

[0004] Therefore, there is an urgent need for a fabrication method for InGaAs focal plane detectors with higher process efficiency and yield. Summary of the Invention

[0005] In view of this, this application discloses an InGaAs focal plane detector based on DTW integration and its fabrication method, to solve the problems of process efficiency and yield in the prior art; including:

[0006] A DTW-based InGaAs focal plane detector includes: a silicon-based readout circuit wafer layer, an InGaAs detector array chip layer, an optical filter structure layer, and an N-electrode metal.

[0007] The silicon-based readout circuit wafer layer is provided with a plurality of readout circuit chips; the readout circuit chips include: an arrayed pixel unit, an N-electrode region, and a peripheral signal processing circuit region; a first UBM layer is provided on the arrayed pixel unit, and a first indium bump array is provided on the first UBM layer;

[0008] The InGaAs detector array chip layer includes, in sequence, an n-InP contact layer, an n-InP buffer layer, an InGaAs absorption layer, and an n-InP cap layer; a P-pixel region is disposed on the n-InP cap layer, a second UBM layer is disposed on the P-pixel region, a second indium bump array is disposed on the second UBM layer, and the first indium bump array and the second indium bump array are flip-chip bonded to each other and filled with an organic polymer medium;

[0009] The optical filter film structure layer adopts an array filter film structure and is fabricated through wafer-level processes; the optical filter film structure layer is disposed on the back side of the InGaAs detector array chip layer;

[0010] The N electrode metal is connected to the n-InP contact layer and the N electrode region, respectively.

[0011] A method for fabricating an InGaAs focal plane detector based on DTW integration includes:

[0012] S1. Obtain a silicon-based wafer with integrated readout circuitry, and fabricate a first UBM layer and a first indium bump array on the silicon-based wafer;

[0013] S2. Fabricate an InGaAs detector array chip, and fabricate a second UBM layer and a second indium bump array on the detector array chip;

[0014] S3. Perform chip-to-wafer bonding on the InGaAs detector array chip and the silicon-based wafer to obtain the DTW wafer;

[0015] S4. Post-processing of DTW wafers;

[0016] S5. Prepare the optical filter film structure layer;

[0017] S6. Prepare N electrode metal.

[0018] The beneficial effects of this application include:

[0019] Since the chemical mechanical thinning and polishing process of InP substrates requires a continuously flat surface and the optical adhesive filling process is sensitive to high temperature, traditional InGaAs PIN focal plane detectors usually use die-to-die flip interconnect technology. This application adopts die-to-wafer bonding technology based on indium bumps, and then performs steps such as selective removal of discontinuous InP substrates through chemical means and bottom filling and curing of organic polymers to obtain silicon-based compound DTW wafers with flat surfaces and high temperature processing conditions.

[0020] The InGaAs focal plane detector designed in this application adopts an innovative electrode lead-out structure. After the substrate is removed, the N electrode is led out from the back to the N electrode of the readout circuit, which replaces the traditional complex process of forming N deep holes by etching the P side. This avoids the problem of controlling the etching depth of deep holes, reduces process defects, simplifies process steps, and improves the consistency of device performance and long-term working stability.

[0021] On the other hand, by simplifying the steps related to P-side metallization and N-hole electrode preparation, the electrode lead-out structure can reduce 7-10 process steps compared to the structure of forming N-holes several micrometers deep by P-side etching, effectively shortening the process cycle; the chip area is expected to be reduced by about 40%, and combined with the core factor of the high price of InP substrate material, it is expected to reduce the manufacturing cost of detector array chips by about 15%;

[0022] In the method designed in this application, various processes such as bonding, substrate removal, electrode extraction, and spectral filter film deposition can be unified on a wafer-level processing platform. This can shorten the modular process chain, enhance the compatibility of process solutions, reduce chip-level manual operations, and improve the overall process integration. At the same time, the wafer-level optical filter structure processing conditions can improve the uniformity and repeatability of the spectral imaging system, and promote the development of such devices towards higher performance and larger-scale applications. Attached Figure Description

[0023] Figure 1 is a cross-sectional schematic diagram of the InGaAs focal plane detector based on DTW integration in the embodiments of this application;

[0024] Figure 2 is an enlarged schematic diagram of the silicon-based readout circuit wafer layer in an embodiment of this application;

[0025] Figure 3 is an enlarged schematic diagram of the InGaAs detector array chip layer in an embodiment of this application;

[0026] Figure 4 is a top view of the DTW wafer in an embodiment of this application;

[0027] Figure 5 shows the intermediate device 1 in the fabrication process of the InGaAs focal plane detector in the embodiments of this application;

[0028] Figure 6 shows the intermediate device 2 in the fabrication process of the InGaAs focal plane detector in the embodiments of this application;

[0029] Figure 7 is a schematic diagram of the InGaAs focal plane detector in an embodiment of this application;

[0030] Figure reference numerals: 1-Silicon-based readout circuit wafer layer, 11-First UBM layer, 12-N electrode region, 2-InGaAs detector array chip layer, 21-InP substrate, 22-InGaAs etching stop layer, 23-n-InP contact layer, 24-n-InP buffer layer, 25-InGaAs absorption layer, 26-n-InP cap layer, 27-P pixel region, 28-Second UBM layer, 29-Second indium bump array, 210-Passivation film, 3-Optical filter film structure, 4-N electrode metal, 5-Bonded indium bumps, 6-Organic polymer dielectric, 7-Silicon oxide layer. Detailed Implementation

[0031] To make the objectives, technical solutions, features, and advantages of this application clearer and to enable those skilled in the art to better understand the technical solutions of this application, the following detailed description of this application is provided in conjunction with the accompanying drawings and embodiments.

[0032] Example 1:

[0033] This embodiment includes an InGaAs focal plane detector based on DTW integration, as shown in Figure 1, comprising: a silicon-based readout circuit wafer layer 1, an InGaAs detector array chip layer 2, an optical filter structure layer 3, and an N-electrode metal layer 4.

[0034] The silicon-based readout circuit wafer layer has several readout circuit chips; the readout circuit chips include: arrayed pixel units, N-electrode regions, peripheral signal processing circuits, etc.; as shown in Figure 2, a first UBM layer 11 is disposed on the arrayed pixel units, and a first indium bump array is disposed on the first UBM layer. A silicon oxide layer 7 is also disposed on the silicon-based readout circuit wafer layer 1 to protect the wafer.

[0035] The InGaAs detector array chip layer, as shown in Figure 3, includes the following layers stacked sequentially: an InGaAs etching stop layer 22, an n-InP contact layer 23, an n-InP buffer layer 24, an InGaAs absorption layer 25, and an n-InP cap layer 26. A P-pixel region 27 is disposed on the n-InP cap layer, a second UBM layer 28 is disposed on the P-pixel region, and a second indium bump array 29 is disposed on the second UBM layer. The second indium bump array corresponds to the first indium bump array. In Figure 3, 21 represents the InP substrate, and a passivation film 210 is also disposed on the n-InP cap layer 26. The InGaAs detector array chip layer forms an out-of-plane electrode structure, meaning that the periphery of the P-pixel region 27 does not include the traditional N-electrode hole, N-electrode metal layer, or indium bump array disposed on the N-electrode. Further, as shown in Figure 2, the P-pixel region does not exceed the vertical projection area of ​​the N-electrode of the readout circuit chip.

[0036] The optical filter film structure layer adopts an array filter film structure, which is fabricated through wafer-level processes. Examples include Fabry-Perot filter structures, polarization filter structures, metasurface color routing, and waveguide color separation structures, all of which meet wafer-level process requirements.

[0037] Further, as shown in Figure 3, the first indium bump array and the second indium bump array are flip-chip bonded together and filled with an organic polymer medium 6, forming indium bumps 5 in Figure 3 after bonding; the optical filter film structure layer is disposed on the back side of the InGaAs detector array chip layer. The N-electrode metal 4 is connected to the n-InP contact layer and the N-electrode region 12, respectively. The organic polymer medium is selected from one of low-temperature curing styrene, polyimide, and polybenzoxazole.

[0038] A top view of the entire DTW wafer is shown in Figure 4.

[0039] Example 2:

[0040] This embodiment includes an InGaAs focal plane detector based on DTW integration, as shown in Figure 1, comprising:

[0041] The silicon-based readout circuit wafer layer is fabricated using an 8-inch CMOS process. A periodically arranged array of metal pads is formed on the surface, and a Ti / Pt / Au structure UBM layer and an indium bump with a height of 5μm are sequentially fabricated on the surface of the pads.

[0042] The InGaAs detector array chip layer includes an InGaAs etch stop layer (0.2 μm thick), an n-InP contact layer (500 nm thick), an n-InP buffer layer (500 nm thick), an InGaAs absorber layer (3 μm thick), and an n-InP cap layer (500 nm thick) arranged sequentially, forming a p-type pixel region with a center-to-center spacing of 15 μm through Zn selective diffusion.

[0043] The pixel-level flip-chip interconnect structure achieves electrical interconnection between the detector array and the readout circuit through indium bumps, while the non-interconnected areas are filled with a BCB dielectric layer (8μm thick) to provide mechanical support.

[0044] The polarization grating functional layer consists of four pixels forming a macro pixel on the back electrode, with orientations of 0°, 90°, 180°, and 270°, a period of 300nm, a duty cycle of 0.5, and a height of 200nm.

[0045] The back electrode structure features a Ti / Au composite metal layer with full-chip N electrodes, used to implement electrode leads between the InGaAs detector array chip layer and the silicon-based readout circuit wafer layer.

[0046] Example 3:

[0047] This embodiment includes a method for fabricating an InGaAs focal plane detector based on DTW integration, comprising:

[0048] S1. Obtain a silicon-based wafer with integrated readout circuitry, and fabricate a first UBM layer and a first indium bump array on the silicon-based wafer.

[0049] In this embodiment, the silicon-based wafer is an 8-inch ROIC wafer fabricated using CMOS technology.

[0050] S11. Prepare the first UBM layer; the UBM layer has a thickness of 200nm~500nm, and is prepared by metal lift-off process or metal etching process. The UBM is made of TiAu or TiPtAu metal.

[0051] S12. Using a lift-off process, a first indium bump array is fabricated on the first UBM layer.

[0052] S2. Fabricating an InGaAs detector array chip, including fabricating a second UBM layer and a second indium bump array on the detector array chip:

[0053] S21. A detector chip structure is formed on an InP substrate using chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) processes.

[0054] The detector chip structure includes, in sequence: an InGaAs etch stop layer, an InP contact layer, an InP buffer layer, an InGaAs absorber layer, and an InP cap layer. The InP substrate and the InGaAs etch stop layer are removed in subsequent steps.

[0055] S22. Selectively dope the InP cap layer to form a P-pixel region on the InP cap layer.

[0056] The selective doping is performed using deposition, photolithography, etching, and diffusion processes.

[0057] S23. Prepare a second UBM layer on the P-pixel region.

[0058] The second UBM layer is prepared with a thickness of 200nm~500nm using a lift-off process or a metal etching process. The UBM is made of TiAu or TiPtAu metal.

[0059] S24. Using a lift-off process, a second indium bump array is fabricated on the second UBM layer to obtain an InP wafer; in this embodiment, the height of the bumps is 3μm~10μm.

[0060] S25. Divide the InP wafer.

[0061] Specifically, the dicing method can be laser dicing, crystal orientation dissociation, or other edge integrity preservation processes.

[0062] S3. Perform chip-to-wafer bonding on the InGaAs detector array chip and the silicon-based wafer to obtain the DTW wafer.

[0063] Specifically, the diced InGaAs detector array chip is flip-bonded to the wafer with high precision. The bonding of the first indium bump array and the second indium bump array is achieved by cold pressing, thereby constructing a complete hybrid integrated array wafer, as shown in Figure 5 after flip bonding.

[0064] S4. Post-processing of DTW wafers, including:

[0065] S41. An automatic dispensing machine is used to fill the gap between the chip and the wafer, and the filling medium is cured. The filling medium is styrene-cyclobutene (BCB), and the curing temperature is 190℃ to 220℃.

[0066] Furthermore, the filling medium can also be polyimide or polybenzoxazole.

[0067] S42. Deposit a silicon oxide thin film on the surface of the DTW wafer; in this embodiment, the deposition is performed using PECVD (TEOS) process, and the thickness of the silicon oxide thin film is 1μm~3μm. The device after the filling medium and silicon oxide thin film deposition is shown in Figure 6.

[0068] S43. Thinning of the InP substrate.

[0069] In this embodiment, mechanical thinning is used to thin the InP substrate to 50μm~100μm.

[0070] S44. Completely remove the InP substrate and the InGaAs etching stop layer; in this embodiment, chemical etching is used for complete removal.

[0071] S5. Fabricate an optical filter structure layer on the back side of the InGaAs detector array chip.

[0072] The optical filter film structure layer adopts an array filter film structure and is prepared by wafer-level process. In some embodiments, any one of the following can be selected: Fabry-Perot filter structure, polarization filter structure, metasurface color routing, and waveguide color separation structure.

[0073] S6. Fabrication of N-electrode metal on an InGaAs focal plane detector based on DTW integration; including:

[0074] S61. Using photolithography and dry etching processes, N-electrode holes are fabricated on the N-electrode region of the detector array chip and readout circuit.

[0075] S62. The N-electrode metal is prepared using a lift-off process, and the N-electrode metal is electrically connected to the N-electrode holes of the detector array chip and the N-electrode holes of the readout circuit, respectively.

[0076] S63. Through-holes for bonding pads are fabricated using photolithography and dry etching processes to expose the pads. The resulting InGaAs focal plane detector based on DTW integration is shown in Figure 7.

[0077] Furthermore, the dicing and packaging are completed to form a monolithically integrated InGaAs focal plane array with a complex optical filter structure.

[0078] Example 4:

[0079] This embodiment includes a method for fabricating an InGaAs focal plane detector based on DTW integration, comprising:

[0080] S1. Fabrication of detector array chip and readout circuit wafer. This includes:

[0081] S11. Using MOCVD epitaxy, the following layers are sequentially grown on an N-type InP substrate: a 500 nm thick n-InGaAs etching stop layer, a 500 nm thick n-InP contact layer, a 500 nm thick n-InP buffer layer, a 3 μm thick InGaAs absorber layer, and a 500 nm thick n-InP cap layer.

[0082] S12. Zn selective doping is completed by sequentially employing deposition, photolithography, etching, and diffusion processes to form a P-pixel region on the n-InP cap layer;

[0083] S13. The UBM layer and In bump array structure are fabricated sequentially on the P pixel area using a lift-off process.

[0084] S14. Using laser dicing technology, the detector wafer is cut into detector array chips, requiring the dicing path to remain intact and no particles to fall off the side of the chip.

[0085] S15. Complete the fabrication of UBM and indium bumps on the surface of an 8-inch ROIC wafer, with process parameters consistent with S13.

[0086] S2. Perform die-to-wafer bonding and integration. This includes:

[0087] S21. Flip-chip interconnection between the detector chip and the readout circuit wafer is achieved through cold-press bonding technology. The bonding temperature is room temperature, and the pressure is 30~50 N / cm. 2 The duration is 5 to 10 minutes.

[0088] S22. Using an automatic dispensing device, the detector array chips are filled one by one in a "I" or "L" shape. The filling medium is phenylcyclobutene (BCB), and the curing is completed at 190°C to 220°C, with a maximum temperature holding time of 30 minutes.

[0089] S23. Passivate the wafer surface by depositing a silicon oxide thin film with a thickness of 3μm using PECVD (TOES).

[0090] S24. The InP substrate is thinned to 50 μm by mechanical grinding and chemical mechanical polishing, and then the InP substrate and InGaAs etching stop layer are completely removed by selective wet etching.

[0091] S3. Perform the fabrication process of the array polarization grating structure, including:

[0092] S31. Deposit a titanium oxide thin film on the back of the detector array chip using an ALD device, wherein the substrate thickness is required to be 200μm~350μm and the titanium oxide thin film thickness is 350nm~600nm.

[0093] S32, spin-coated electron beam photoresist PMMA, uses an electron beam direct writing lithography machine to define nanostructures.

[0094] S33. Use RIE or ICP to selectively etch titanium oxide to remove residual photoresist and clean the equipment surface.

[0095] S34. A silicon oxide thin film is deposited on the surface of the equipment using PECVD to form a protective layer for the metasurface structure, with a thickness of 100nm~200nm.

[0096] S4. Fabrication of the N-electrode structure. This includes:

[0097] S41. Using photolithography and dry etching processes, N-electrode holes are fabricated on the N-electrode region of the detector array chip and the readout circuit.

[0098] S42. The N-electrode metal is prepared using a lift-off process, and the N-electrode metal is electrically connected to the N-electrode holes of the detector array chip and the N-electrode holes of the readout circuit, respectively.

[0099] S43. Use photolithography and dry etching processes to create bonding pad vias, exposing the pads and facilitating the packaging bonding process; create dicing tracks to facilitate the dicing process.

[0100] S44. Complete dicing and packaging to form an InGaAs focal plane detector based on DTW integration.

[0101] Finally, it should be noted that the above description only depicts some embodiments of this application. For those skilled in the art, various changes, modifications, substitutions, and variations can be conceived of these embodiments without departing from the principles and spirit of this application. The scope of protection of this application is defined by the appended claims and their equivalents, and all the above-mentioned behaviors should be covered within the scope of protection of this application.

[0102] Furthermore, in the above description of the embodiments, unless otherwise explicitly specified and limited, if the terms "upper," "lower," "horizontal," "inner," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the invention is usually placed during use, they are only for the convenience of describing this application and simplifying the description, and do not limit or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application; if the terms "first," "second," etc., appear, they are only used to distinguish the description and should not be construed as indicating or implying relative importance. The components shown and described in the accompanying drawings and embodiments can be arranged and designed in various different configurations. The term "horizontal" does not imply that the component must be absolutely horizontal, but rather that it can be slightly tilted. "Horizontal" simply means that its direction is more horizontal than "vertical," not that the structure must be completely horizontal, but rather that it can be slightly tilted. The terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

Claims

1. An InGaAs focal plane detector based on DTW integration, characterized in that, include: Silicon-based readout circuit wafer layer, InGaAs detector array chip layer, optical filter structure layer, N-electrode metal; The silicon-based readout circuit wafer layer is provided with a plurality of readout circuit chips; the readout circuit chips include: arrayed pixel units, N-electrode regions, and peripheral signal processing circuit regions; a first UBM layer is provided on the arrayed pixel units, and a first indium bump array is provided on the first UBM layer; the InGaAs detector array chip layer includes: an n-InP contact layer, an n-InP buffer layer, an InGaAs absorption layer, and an n-InP cap layer stacked sequentially; a P-pixel region is provided on the n-InP cap layer, a second UBM layer is provided on the P-pixel region, and a second indium bump array is provided on the second UBM layer; the first indium bump array and the second indium bump array are flip-chip bonded to each other, filled with an organic polymer medium, and fixed by low-temperature curing; the optical filter film structure layer adopts an array filter film structure and is prepared by wafer-level process; the optical filter film structure layer is disposed on the back side of the InGaAs detector array chip layer; the N-electrode metal is connected to the n-InP contact layer and the N-electrode region respectively.

2. The InGaAs focal plane detector based on DTW integration according to claim 1, characterized in that, The organic polymer medium is selected from one of the following: phenylcyclobutene, polyimide, and polybenzoxazole, which are low-temperature curing polymers.

3. The InGaAs focal plane detector based on DTW integration according to claim 1, characterized in that, The array filter film structure is selected from one of the following: Fabry-Perot filter structure, polarization filter structure, metasurface color routing, and waveguide color separation structure.

4. The InGaAs focal plane detector based on DTW integration according to claim 1, characterized in that, The InGaAs detector array chip layer adopts an out-of-plane electrode structure. The periphery of the P-pixel region does not include the N-electrode hole, the N-electrode metal layer, or the indium bump array set on the N-electrode, and its area does not exceed the vertical projection area of ​​the N-electrode of the readout circuit chip.

5. A method for fabricating an InGaAs focal plane detector based on DTW integration, used to fabricate an InGaAs focal plane detector based on DTW integration as described in any one of claims 1 to 4, comprising: S1. Obtain a silicon-based wafer with integrated readout circuitry, and fabricate a first UBM layer and a first indium bump array on the silicon-based wafer; S2. Fabricate an InGaAs detector array chip, and fabricate a second UBM layer and a second indium bump array on the detector array chip; S3. Perform chip-to-wafer bonding on the InGaAs detector array chip and a silicon-based wafer to obtain a DTW wafer. S4. Post-processing of DTW wafers; S5. Prepare the optical filter film structure layer; S6. Fabrication of N-electrode metal; including: S61. Fabricating N-electrode holes on the N-electrode region of the detector array chip and readout circuit using photolithography and dry etching processes; S62. The N-electrode metal is prepared using a metal stripping process, and the N-electrode metal is electrically connected to the N-electrode holes of the detector array chip and the N-electrode holes of the readout circuit, respectively. S63. The bonding pad through-holes are fabricated using photolithography and dry etching processes to expose the bonding pads.

6. The fabrication method of the InGaAs focal plane detector based on DTW integration according to claim 5, characterized in that, The fabrication of the InGaAs detector array chip, including the fabrication of a second UBM layer and a second indium bump array on the detector array chip, comprises: Step 1, forming a detector chip structure on an InP substrate using chemical vapor deposition or molecular beam epitaxy; the detector chip structure includes, in sequence: an InGaAs etch stop layer, an InP contact layer, an InP buffer layer, an InGaAs absorber layer, and an InP cap layer; wherein, the InP substrate and the InGaAs etch stop layer are removed during post-processing of the DTW wafer; Step 2, selectively doping the InP cap layer to form a P-pixel region on the InP cap layer; Step 3, fabricating a second UBM layer on the P-pixel region; Step 4, fabricating a second indium bump array on the second UBM layer using a lift-off process.

7. The fabrication method of the InGaAs focal plane detector based on DTW integration according to claim 5, characterized in that, The post-processing of the DTW wafer includes: Step 1, filling the gap between the chip and the wafer using an automatic dispensing machine and curing the filling medium; Step 2, depositing a silicon oxide thin film on the surface of the DTW wafer; Step 3, thinning the InP substrate; Step 4, completely removing the InP substrate and the InGaAs etching stop layer.

8. The fabrication method of the InGaAs focal plane detector based on DTW integration according to claim 7, characterized in that, The filling medium is selected from phenylcyclobutene, polyimide, and polybenzoxazole.

Images