Photoelectric co-packaging chip preparation method capable of improving bottom filling creeping glue

Abstract

The invention provides a photoelectric co-packaging chip preparation method for improving bottom filling creeping glue. The method comprises the following steps: step S1, providing a semiconductor substrate for reserving an optical port for mounting an optical chip; s2, manufacturing a stop block at a side position of an optical port reserved on the semiconductor substrate and used for mounting an optical chip; s3, an optical chip is attached to the semiconductor substrate according to the reserved design; and S4, carrying out glue dispensing operation on the semiconductor substrate in a manner that the bottom filling glue of the photoelectric co-packaging chip does not pollute the optical port through the blocking of the baffle block. According to the invention, the stop block is used as a physical barrier, and can effectively stop the bottom filling colloid from flowing through during the subsequent dispensing operation, so that the cleanliness of the optical port is protected, and the product yield is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and particularly relates to a method for preparing optoelectronic co-packaged chips with improved bottom-fill adhesive. Background Technology

[0002] In the manufacturing process of optoelectronic co-packaged products, it is usually necessary to attach the optical chip to a substrate and then apply adhesive to the chip as a bottom filler to enhance structural reliability and protect internal circuitry. However, during the adhesive application process, a phenomenon known as "adhesive creep" often occurs, where the adhesive spreads upwards or outwards along the chip's sidewalls. When the optical port (the input / output port of the optical signal) of the optical chip is located on the sidewall, adhesive creep can contaminate the port, severely affecting the transmission quality of the optical signal and the cleanliness of the product.

[0003] In existing technologies, the main method for controlling the glue creep height is to precisely control the glue dispensing amount. However, this method requires extremely high precision in the dispensing process, has significant operational bottlenecks, a narrow process window, and makes it difficult to completely prevent glue creep from contaminating the optical aperture, resulting in low product yield and high production costs.

[0004] Therefore, a new technical solution is urgently needed to effectively block the flow of colloid to the optical port and fundamentally solve the problem of colloid contamination. Summary of the Invention

[0005] The present invention aims to solve the problem of contamination of optical ports and reduced product yield caused by adhesive dispensing and creep during the manufacturing process of optoelectronic co-packaged chips in the prior art.

[0006] Therefore, the present invention provides a method for preparing an optoelectronic co-packaged chip with improved bottom-fill adhesive application, comprising the following steps: Step S1, providing a semiconductor substrate with a reserved optical port for mounting an optical chip; Step S2, fabricating a block on the side of the reserved optical port on the semiconductor substrate; Step S3, attaching the optical chip to the semiconductor substrate according to the reserved design; Step S4, performing an adhesive dispensing operation on the semiconductor substrate in a manner that prevents the bottom-fill adhesive of the optoelectronic co-packaged chip from contaminating the optical port by blocking the adhesive through the block.

[0007] Furthermore, preferably, in the improved optoelectronic co-packaged chip fabrication method of the present invention, step S2 further includes: step S21, applying a second layer of photoresist to the substrate on which the redistribution layer metal line fabrication and micro pad electroplating have been completed, forming a photoresist layer with a thickness of 40-50 μm; step S22, subjecting the photoresist layer to a second exposure and development to form holes with a block pattern; step S23, forming metal blocks in the holes through a second electroplating; and step S24, performing a second photoresist removal to clean the residual photoresist.

[0008] Furthermore, preferably, in the improved optoelectronic co-packaged chip preparation method of the present invention with bottom-filled adhesive, in step S22, the height of the block is 30-45 μm, the energy of the ultraviolet light used in the second exposure is 300-400 mJ, the electroplating time of the second electroplating is 30-40 minutes, and the cleaning time is 200-400 seconds.

[0009] Furthermore, preferably, in the improved optoelectronic co-packaged chip preparation method of the present invention, in step S2, the block is a strip of silicon, resin or pre-made adhesive block disposed on the substrate by means of mounting.

[0010] Furthermore, preferably, in the improved photoresist co-packaged chip preparation method of the present invention, in step S2, the block is a metal block, which is formed on the circuit layer of the substrate by electroplating, and its height is 5 to 10 μm lower than the photoresist layer coated before electroplating.

[0011] Furthermore, preferably, in the improved bottom-filled adhesive co-packaged chip preparation method of the present invention, the metal block is made of copper.

[0012] Furthermore, preferably, in the improved optoelectronic co-packaged chip preparation method of the present invention with improved bottom filling adhesive, in step S2, the block forms physical support for the bonded optoelectronic chip.

[0013] The baffle structure of the present invention is set on the substrate of the optoelectronic co-packaged product, on the side of the optical chip port, as a physical barrier, which can effectively block the bottom filler adhesive from flowing through during subsequent dispensing operations, thereby protecting the cleanliness of the optical port.

[0014] Furthermore, when the stop is a metal stop, it can be formed on the circuit layer (RDL) of the substrate through an electroplating process. Specifically, its height is 5 to 10 μm lower than the photoresist layer coated before electroplating to ensure the integrity of the electroplating fill.

[0015] In addition, this invention improves product yield, fundamentally solves the failure problem caused by glue crawling contamination, reduces the strict dependence of the process on glue dispensing control, and effectively improves the overall product yield.

[0016] In addition, it improves process integration. The metal block solution can be cleverly embedded into the existing redistribution layer & micropad process flow (by adding secondary photolithography and electroplating) without introducing additional complex equipment or significantly changing the process flow.

[0017] In addition, the block also serves as a support. After the optical chip is attached, the block structure can provide some auxiliary support to prevent the material from tilting during subsequent processing or reliability testing, thereby enhancing the structural stability of the product.

[0018] Flexible implementation: The baffle material (metal, silicon, resin, colloid) and the formation method (electroplated integration or post-mounting) are diverse and can be flexibly selected according to specific product design and production conditions. Attached Figure Description

[0019] Figure 1 This is a schematic diagram illustrating how the cleanliness of the sidewall aperture is affected by the bottom filling adhesive creep in the prior art.

[0020] Figure 2 This is a schematic diagram illustrating a method for fabricating an optoelectronic co-packaged chip according to a preferred embodiment of the present invention, in which a new baffle is added to block the flow of bottom filler adhesive.

[0021] Figure 3 This is a schematic diagram illustrating the entire manufacturing process of a method for fabricating an optoelectronic co-packaged chip according to a preferred embodiment of the present invention.

[0022] Figure 4 This is a schematic diagram illustrating the entire manufacturing process of a method for fabricating an optoelectronic co-packaged chip according to a preferred embodiment of the present invention.

[0023] Figure 5 This is a schematic diagram illustrating the product structure of an optoelectronic co-packaged chip according to a preferred embodiment of the present invention when a baffle is added during the packaging process. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Other embodiments or modifications obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.

[0025] In the existing packaging process, when the optical chip is bonded to the product substrate, the optical port is fully exposed. During subsequent dispensing, normal adhesive creep can affect the cleanliness of the optical port. The current standard improvement method is to control the amount of adhesive dispensed, thereby controlling the creep height. However, this method has significant operational bottlenecks and low product yield. Figure 1 This diagram illustrates how underfilling can affect the cleanliness of the sidewall aperture in the prior art.

[0026] Figure 2 This is a schematic diagram illustrating a method for fabricating an optoelectronic co-packaged chip according to a preferred embodiment of the present invention, in which a new baffle is added to block the flow of bottom filler adhesive.

[0027] According to a preferred embodiment of the present invention, a dam is fabricated on the substrate before the optical chip is bonded. During subsequent dispensing operations, this dam effectively blocks the flow of liquid adhesive, thereby protecting the cleanliness of the optical port. Its advantage lies in that by directly introducing the dam design and fabrication process into the micro-pad process, a dam with a height of 30-45µm is generated. In subsequent production operations, this effectively blocks the flow of bottom filler adhesive, overcoming the sidewall adhesive creep phenomenon inherent in traditional bottom filling. Furthermore, the dam provides a certain degree of support for the bonded product (PIC), preventing material tilting and effectively supporting product reliability testing.

[0028] This invention grows baffles on the circuit layer by adding a second photolithography and electroplating process during the plating of the circuit layer on the front side of the wafer (in the steps of redistribution layer and micro pads), thereby effectively improving the phenomenon of adhesive creep in subsequent dispensing operations and protecting the optical port cleanliness.

[0029] Figure 3 This is a schematic diagram illustrating the entire manufacturing process of a method for fabricating an optoelectronic co-packaged chip according to a preferred embodiment of the present invention.

[0030] In the redistribution layer 1 & micropad process, a new baffle process is added. The process flow is as follows: redistribution layer 1 → first resist application → first exposure and development → first electroplating → first resist removal → second resist application → second exposure and development → second electroplating → second resist removal. Compared to the micropad process, the new baffle process has a second resist application height of 40 to 50 μm, an exposure energy of 300 to 400 mJ, an electroplating time of 30 to 40 minutes, and a resist removal cleaning time of 200 to 400 seconds. The baffle shown in the figure can be successfully created as a barrier to prevent the bottom filler from flowing through, thereby improving resist creep and protecting the optical aperture.

[0031] Figure 4 This is a schematic diagram illustrating the entire manufacturing process of a method for fabricating an optoelectronic co-packaged chip according to a preferred embodiment of the present invention. The process flow is detailed below: It is mainly divided into 4 parts, which are described in detail below: After the micro-plating pads are completed, a second coating is applied: using a coating device, photoresist is applied to the front of the product and then rotated and spun out, using centrifugal force to distribute it evenly on the front of the product to form a coating layer. The coating height needs to be 40-50μm.

[0032] After the photoresist is applied, a second exposure and development process is performed: using an exposure device, ultraviolet light is passed through the aperture of the photomask and irradiated onto the surface of the photoresist layer, causing the photoresist to dissociate into small molecules, forming a structure that is easily soluble in the developer. Then, the developer is used to clean and remove the dissociated small molecules, forming pores.

[0033] After exposure and development, a second electroplating process is performed: using electroplating equipment, copper ions are electroplated into the pre-drilled holes using the principle of displacement reaction to form a copper metal layer. The thickness of this metal layer is 5 to 10 μm lower than the coating height.

[0034] After electroplating, a second photoresist removal process is performed: a photoresist remover is used to dissolve and clean the remaining photoresist, thus completing the process.

[0035] The key technical point of this invention is structural protection. By adding a baffle to the original structure, the phenomenon of glue crawling during bottom filling operations can be improved.

[0036] Preferably, to ensure the smooth operation of the product manufacturing process, the stop design meets the following requirements: The distance between the block and the sidewall of the PIC chip (where the optical port is located) is 5~200um; The height of the stop block must be ≤ the height of SOH ( Figure 5 (Height distance from the PIC chip to the molding compound). This height is related to the height of the bump on the product itself. Taking micro-bumps as an example, the height of the stop is set to 30~45um. The position of the block must avoid the active area on the PIC chip, and the distance from the microbump must be greater than 50um; The width of the stop is set between 2030 and 100 μm.

[0037] Figure 5 This is a schematic diagram illustrating the product structure of an optoelectronic co-packaged chip according to a preferred embodiment of the present invention when a baffle is added during the packaging process.

[0038] Based on the structure proposed in this invention, other materials can also be used to replace the stop blocks, such as replacing the metal stop blocks with strip-shaped silicon, resin, or stop block adhesive.

[0039] This invention can add a secondary coating, exposure, development, electroplating, and adhesive removal process to the redistribution layer 1 and micro pad operation process. On the original redistribution layer metal lines, a metal block is electroplated and grown, which effectively blocks the subsequent bottom filler adhesive from flowing through and protects the optical port.

[0040] Alternatively, strips of silicon, resin, or stencil adhesive can be applied to designated locations before the chip mounting (PIC) step to achieve the same desired effect.

[0041] Example 1: Structure and Method of Metal Electroplating Block In a preferred embodiment of the present invention, a step of fabricating a metal block is added to the standard redistribution layer 1 & micro pad process of optoelectronic co-packaged products.

[0042] The specific process flow for the stopper is as follows: Second coating: After the product completes the conventional redistribution layer 1 circuit fabrication and micro pad electroplating, a coating equipment (such as a spin coater) is used to coat the positive photoresist on the front side of the product (wafer). The photoresist is then spread evenly by high-speed rotation and centrifugal force to form a photoresist layer with a thickness (height) strictly controlled at 40-50μm.

[0043] Second exposure and development: Using exposure equipment such as a stepper lithography machine, ultraviolet light with a wavelength of 365nm or 405nm is passed through a photomask with a pre-designed baffle pattern and irradiates the photoresist layer. The exposure energy is controlled at 300-400mJ. The photoresist in the exposed area undergoes a photochemical reaction, and its molecular structure dissociates. Subsequently, a special developer (such as TMAH solution) is used to develop the photoresist, dissolving and washing away the dissociated photoresist in the exposed area, thereby forming holes on the photoresist layer corresponding to the baffle shape.

[0044] Second electroplating: The exposed and developed product is placed in an electroplating tank. Using electroplating equipment and copper sulfate solution as the main electroplating solution, copper ions are reduced and deposited into the pores formed in the previous step through an electrochemical reaction (displacement reaction). The electroplating time is controlled at 30-40 minutes to ensure that the pores are completely filled. The actual height of the final copper block is approximately 30-45 μm (i.e., 5 to 10 μm lower than the photoresist layer).

[0045] Second stripping: After electroplating, the product is immersed or sprayed with a specific stripping solution (such as N-methylpyrrolidone or a special stripping solution) to completely dissolve and clean the remaining photoresist that is not filled by the electroplated metal, exposing the formed copper metal block structure. The cleaning time is usually 200-400 seconds to ensure thorough removal of residual photoresist.

[0046] After completing the above-mentioned blocking process, the subsequent chip attach step is performed. When the optical chip (PIC) is attached to the substrate, its optical port on the sidewall is positioned next to the copper blocking block. During the underfill dispensing operation, the flowing adhesive is effectively blocked upon encountering the appropriately sized copper blocking block, preventing it from continuing to flow forward into the optical port area, thus perfectly protecting the cleanliness of the optical port.

[0047] Example 2: Surface Mounted Stop Structure and Method In another embodiment of the present invention, the baffle can be omitted from the redistribution layer process. Instead, it can be directly mounted onto the predetermined position corresponding to the optical port on the substrate using a high-precision die-mounting device before chip mounting. After mounting, the height of the baffle also needs to be controlled within 30-45µm. The optical chip is then mounted and adhesive is applied. This method also effectively blocks adhesive flow and protects the optical port, and is suitable for situations where there are strict limitations on process modifications or where special substrate materials are used.

[0048] Comparative experiments and results A sample with a copper baffle was fabricated using the method described in Example 1 of this invention, and compared with a conventional product without the baffle. Under the same dispensing process parameters, the conventional product showed a more than 15% rate of adhesive creepage contamination at the optical port, while the product using the baffle structure of this invention achieved a cleanliness pass rate of over 100%. Furthermore, the baffle's support for the chip demonstrated excellent structural stability during temperature cycling (-55℃ to 125℃) and mechanical shock tests.

[0049] In summary, this invention cleverly solves the long-standing problem of adhesive crawling contamination in optoelectronic co-packaging by introducing a baffle structure in the critical area of ​​the optical port, significantly improving product yield and reliability, and has high industrial application value.

[0050] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0051] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0052] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0053] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0054] The above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively describe all possible implementations here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A method for fabricating an optoelectronic co-packaged chip with improved bottom-fill adhesive, characterized in that, Includes the following steps: Step S1: Provide a semiconductor substrate with a reserved optical port for mounting optical chips; Step S2: Create a stop block on the side of the reserved optical port for mounting the optical chip on the semiconductor substrate; Step S3: Attach the optical chip to the semiconductor substrate according to the reserved design; Step S4: Perform dispensing on the semiconductor substrate in a manner that prevents the bottom filling colloid of the optoelectronic co-packaged chip from contaminating the optical port by blocking the block.

2. The method for fabricating an optoelectronic co-packaged chip according to claim 1, characterized in that, Step S2 also includes: Step S21: Apply a second layer of photoresist to the substrate on which the redistribution layer metal circuit fabrication and micro pad electroplating have been completed, forming a photoresist layer with a thickness of 40-50μm. Step S22: The photoresist layer is exposed and developed a second time to form holes in the block pattern; Step S23: A metal block is formed inside the hole by a second electroplating process; Step S24: Perform a second photoresist removal process to clean away any remaining photoresist.

3. The method for fabricating an optoelectronic co-packaged chip according to claim 2, characterized in that, In step S22, the height of the baffle is 30-45 μm, the energy of the ultraviolet light used in the second exposure is 300-400 mJ, the electroplating time of the second electroplating is 30-40 minutes, and the cleaning time is 200-400 seconds.

4. The method for fabricating an optoelectronic co-packaged chip according to claim 1, characterized in that, In step S2, the block is a strip of silicone, resin, or pre-made adhesive block that is mounted on the substrate.

5. The method for fabricating an optoelectronic co-packaged chip according to claim 1, characterized in that, In step S2, the block is a metal block, which is formed on the circuit layer of the substrate by electroplating, and its height is 5 to 10 μm lower than the photoresist layer coated before electroplating.

6. The method for fabricating an optoelectronic co-packaged chip according to claim 5, characterized in that, The metal block is made of copper.

7. The method for fabricating an optoelectronic co-packaged chip according to claim 1, characterized in that, In step S2, the block provides physical support for the bonded optical chip.

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