Three-dimensional memory device and manufacturing method of three-dimensional memory device

Abstract

A three-dimensional (3D) memory device and a method of fabricating the 3D memory device are disclosed. In certain aspects, the disclosed 3D memory device may include: a memory region; the spacer region is positioned between two adjacent storage regions, and comprises a dielectric stack body and a plurality of dielectric layers; and a conductive structure extending in a vertical direction through the dielectric stack; and conductive pads over a subset of the conductive structures, where the conductive pads are arranged in two lines in a first direction and interleaved with each other in a second direction, the first direction being perpendicular to the vertical direction, and the second direction being perpendicular to both the first direction and the vertical direction.

Description

Three-dimensional storage devices and methods for manufacturing three-dimensional storage devices Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to three-dimensional (3D) memory devices and methods for manufacturing 3D memory devices. Background Technology

[0002] With the continuous rise and development of artificial intelligence (AI), big data, the Internet of Things (IoT), mobile devices and communications, cloud storage, and other technologies, the demand for storage capacity is growing exponentially. Compared with other non-volatile memories, NAND memory has many advantages, such as high integration, low power consumption, fast programming / erasing speed, good reliability, and low cost, and has therefore gradually become the mainstream semiconductor memory in the industry.

[0003] By improving process technology, circuit design, programming algorithms, and manufacturing processes, planar NAND memory cells have been scaled down to smaller sizes. However, as the feature size of the memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. Therefore, the storage density of planar memory cells is approaching its upper limit.

[0004] Three-dimensional (3D) NAND storage architecture can overcome the density limitations of planar storage cells. A 3D storage architecture includes a storage array and peripheral devices for controlling signals to and from that array. Summary of the Invention

[0005] One aspect of this disclosure provides a semiconductor device comprising: a memory region; a spacer region between two adjacent memory regions, wherein the spacer region includes: a dielectric stack; and a conductive structure extending through the dielectric stack in a vertical direction; and conductive pads above a subset of the conductive structure, wherein the conductive pads are arranged as two lines in a first direction and intersecting each other in a second direction, the first direction being perpendicular to the vertical direction, and the second direction being perpendicular to both the first direction and the vertical direction.

[0006] In some implementations, the conductive structure is arranged in two vertical planes, each of the two vertical planes including a corresponding line of the two lines along the first direction; and the conductive structure in each vertical plane includes a first group of adjacent conductive structures and a second group of adjacent conductive structures arranged alternately along the first direction, wherein each first group includes a first number of adjacent conductive structures, each of the first number of adjacent conductive structures being located below a corresponding conductive pad, and each second group includes a second number of adjacent conductive structures not located below any conductive pad.

[0007] In some implementations, the first quantity is 1; and the second quantity is at least 1.

[0008] In some implementations, the first group of adjacent conductive structures and the second group of adjacent conductive structures are arranged periodically.

[0009] In some implementations, the first quantity is greater than 1; and the second quantity is greater than 1.

[0010] In some implementations, the semiconductor device further includes a subset of conductive pads arranged alternately along the two lines, without being located above any conductive structure.

[0011] In some implementations, each conductive pad has a first dimension along the first direction, a second dimension along the second direction, and a third dimension along the vertical direction, wherein the first dimension is in the range of approximately 0.25 μm to approximately 5 μm, the second dimension is in the range of approximately 0.25 μm to approximately 15 μm, and the third dimension is in the range of approximately 0.2 μm to approximately 1.2 μm.

[0012] In some implementations, the semiconductor device further includes peripheral circuitry, which includes transistors coupled to the conductive pads.

[0013] In some implementations, each storage region includes: a storage stack; and a channel structure extending through the storage stack along the vertical direction, and the storage stack is coupled to the peripheral circuitry.

[0014] In some implementations, the storage region is bonded to the peripheral circuitry via hybrid bonding.

[0015] In some implementations, each conductive pad has a first portion embedded in the spacing region and a second portion above the spacing region.

[0016] In some implementations, the conductive pads are formed of materials including: W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof.

[0017] Another aspect of this disclosure provides a semiconductor device comprising: a first semiconductor structure including a transistor; and a second semiconductor structure bonded to the first semiconductor structure by hybrid bonding. The second semiconductor structure includes: a memory region; a spacer region between two adjacent memory regions, wherein the spacer region includes conductive structures extending in a vertical direction; and conductive pads above a subset of the conductive structures, wherein the conductive pads are arranged as two lines along a first direction perpendicular to the vertical direction and intersect each other along a second direction perpendicular to both the first and vertical directions.

[0018] In some implementations, the conductive structure is arranged in two vertical planes, each of the two vertical planes including a corresponding line of the two lines along the first direction; and the conductive structure in each vertical plane includes a first group of adjacent conductive structures and a second group of adjacent conductive structures arranged alternately along the first direction, wherein each first group includes a first number of adjacent conductive structures, each of the first number of adjacent conductive structures being located below a corresponding conductive pad, and each second group includes a second number of adjacent conductive structures not located below any conductive pad.

[0019] In some implementations, the first quantity is 1; and the second quantity is at least 1.

[0020] In some implementations, the first group of adjacent conductive structures and the second group of adjacent conductive structures are arranged periodically.

[0021] In some implementations, the first quantity is greater than 1; and the second quantity is greater than 1.

[0022] Another aspect of this disclosure provides a method for forming a semiconductor device, the method comprising: forming a spacer region; forming an opening in an insulating layer to expose a subset of conductive structures, wherein each conductive structure extends in a vertical direction within the spacer region located between two adjacent memory regions; and forming conductive pads over the subset of conductive structures, wherein the conductive pads are arranged as two lines along a first direction and intersecting each other along a second direction, the first direction being perpendicular to the vertical direction, and the second direction being perpendicular to both the first direction and the vertical direction.

[0023] In some implementations, forming the spacing region includes: forming a dielectric stack portion located between the two adjacent storage regions; and forming the conductive structure, the conductive structure being arranged in two vertical planes and extending through the dielectric stack portion along the vertical direction, each of the two vertical planes including a corresponding line of the two lines along the first direction. The conductive structure in each vertical plane includes a first group of adjacent conductive structures and a second group of adjacent conductive structures arranged alternately along the first direction, wherein each first group includes a first number of adjacent conductive structures, and each second group includes a second number of adjacent conductive structures.

[0024] In some implementations, the method further includes: forming an insulating layer in the spacing region to cover a portion of the dielectric stack; forming an opening in the insulating layer to expose a subset of the conductive structures; and forming conductive pads on the insulating layer and in the openings, the conductive pads contacting the subset of the conductive structures.

[0025] In some implementations, the method further includes: forming a dielectric stack comprising alternating dielectric layers and sacrificial layers; forming a channel structure extending vertically through the dielectric stack in the storage region; replacing portions of the sacrificial layers in the storage region with conductive layers to convert the dielectric stack in the storage region into a storage stack; and retaining portions of the dielectric stack in the interval region between the two adjacent storage regions.

[0026] In some implementations, forming the opening in the insulating layer includes: depositing a photoresist layer on the insulating layer; patterning the photoresist layer using photolithography to define the location of the opening; and etching the insulating layer at the defined location to form the opening and expose a subset of the conductive structure.

[0027] In some implementations, forming the openings in the insulating layer further includes: retaining a first portion of each opening near the corresponding conductive structure of the opening; and expanding a second portion of each opening near the top surface of the insulating layer.

[0028] In some implementations, forming the conductive pads on the insulating layer and in the openings includes: depositing a first conductive material to fill a first portion of each opening; and depositing a second conductive material to fill a second portion of each opening, extending above the top surface of the insulating layer.

[0029] In some implementations, forming the conductive pads on the insulating layer and in the opening includes:

[0030] In some implementations, a conductive seed layer is deposited in each opening; and an electroplating process is performed to allow the conductive seed layer to grow in each opening until the conductive pad extends above the top surface of the insulating layer.

[0031] In some implementations, forming the conductive pad on the insulating layer and in the opening includes: depositing a conductive material layer over the insulating layer and depositing it into the opening; and using an etch-back process to remove excess conductive material from the top surface of the insulating layer, such that the conductive pad is partially retained within the opening and partially extends over the insulating layer.

[0032] In some implementations, forming the conductive pads includes forming the first number of adjacent conductive pads on the first number of adjacent conductive structures, without forming any conductive pads on the second number of adjacent conductive structures, wherein the first number is 1 and the second number is at least 1.

[0033] In some implementations, forming the conductive pads includes forming the first number of adjacent conductive pads on the first number of adjacent conductive structures, without forming any conductive pads on the second number of adjacent conductive structures, wherein the first number is greater than 1 and the second number is greater than 1.

[0034] In some implementations, the method further includes forming a peripheral circuit, the peripheral circuit including a transistor coupled to the conductive pad.

[0035] In some implementations, forming the storage region includes: forming a storage stack and a plurality of channel structures extending through the storage stack along the vertical direction, wherein the storage stack is coupled to the peripheral circuitry; and bonding the storage region to the peripheral circuitry by hybrid bonding.

[0036] Other aspects of this disclosure can be understood by those skilled in the art based on the specification, claims and drawings. Attached Figure Description

[0037] The accompanying drawings, which are incorporated herein and form part of this specification, illustrate aspects of this disclosure and, together with the specification, further explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0038] Figure 1 shows a schematic cross-section of an exemplary 3D storage device according to some aspects of this disclosure.

[0039] Figure 2 shows a schematic circuit diagram of an exemplary storage device according to some aspects of this disclosure.

[0040] Figure 3 shows a schematic circuit diagram of an exemplary storage device according to some aspects of this disclosure.

[0041] Figure 4 shows a schematic cross-section of an exemplary 3D storage device according to some aspects of this disclosure.

[0042] Figure 5A shows a schematic diagram of an exemplary 3D storage device according to some aspects of this disclosure in a top view.

[0043] Figure 5B shows a schematic diagram of a portion of the exemplary 3D storage device shown in Figure 5A according to some aspects of this disclosure, in an enlarged top view.

[0044] Figures 5C and 5D show cross-sectional side views of a 3D storage device as shown in Figure 5A, according to some aspects of this disclosure.

[0045] Figure 5E shows another cross-sectional side view of the 3D storage device shown in Figure 5A, according to some aspects of this disclosure.

[0046] Figures 6A-6H are schematic diagrams of exemplary 3D storage devices according to some aspects of this disclosure, shown in top view.

[0047] Figure 7 shows a block diagram of an exemplary system with a 3D storage device according to some aspects of this disclosure.

[0048] Figure 8A shows a diagram of an exemplary memory card with 3D storage devices according to some aspects of this disclosure.

[0049] Figure 8B shows a diagram of an exemplary solid-state drive (SSD) with 3D storage devices according to some aspects of this disclosure.

[0050] Figure 9 shows a flowchart of an exemplary method for forming a 3D storage device according to some aspects of this disclosure.

[0051] Figures 10A-10E show schematic cross-sectional views of exemplary 3D storage devices at specific manufacturing stages of the method shown in Figure 9, according to some aspects of this disclosure.

[0052] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0053] While specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified with each other in ways not specifically depicted in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0054] Generally, terms can be understood, at least in part, from their usage in context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, again, terms such as a(a), an(an), or the(the) can be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the term "based on" can be understood not necessarily to convey an exclusive set of factors, and can conversely allow for the presence of additional factors that are not necessarily explicitly described, again, depending at least in part on the context.

[0055] It should be readily understood that the meanings of “above,” “over,” and “on” in this disclosure should be interpreted in the broadest possible sense, such that “above” means not only directly “on” something, but also includes “on” something having an intermediate feature or intermediate layer therebetween, and “over” or “on” means not only “on” something, but also includes “above” something or “on something” without an intermediate feature or intermediate layer therebetween (directly on) something.

[0056] Furthermore, for ease of description, this document uses spatial relative terms (e.g., "below," "below," "lower," "above," "upper," etc.) to describe the relationship between one element or feature and another shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein will be interpreted accordingly.

[0057] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material (e.g., glass, plastic, or sapphire wafer).

[0058] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entire lower or upper layer, or the extent of a layer may be less than the extent of the lower or upper layer. Furthermore, a layer may be a region of a homogeneous or dissimilar continuous structure (whose thickness is less than the thickness of the continuous structure). For example, a layer may lie between any pair of horizontal planes between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or vertical interconnect access (via) contact structures are formed) and one or more dielectric layers.

[0059] As used herein, the term "nominal / nominally" refers to an expected or target value for a characteristic or parameter of a component or process operation set during the design phase of a product or process, and a range of values ​​higher and / or lower than that expected value. The range of values ​​may be due to minor variations or tolerances in the manufacturing process. As used herein, the term "about" indicates a given quantity value that can vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" can indicate a given quantity value that varies within, for example, 10%–30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0060] With advancements in semiconductor technology, three-dimensional (3D) memory devices (e.g., 3D NAND memory devices) are increasingly scaling up the number of oxide / nitride (ON) layers in the memory cell array. As the number of array layers in the 3D architecture increases, the peripheral circuitry of the complementary metal-oxide semiconductor (CMOS) requires more complex scaling and resizing. For example, a CMOS wafer (hereinafter referred to as a "CMOS wafer") is bonded to a memory cell array wafer (hereinafter referred to as an "array wafer") to form the framework of a 3D memory device. A memory cell array wafer can include multiple memory cell arrays arranged in an array configuration. The semiconductor structure in the spacing regions between adjacent memory cell arrays can lead to non-uniform topography, thereby reducing the strength of the memory device. Therefore, novel 3D memory devices with novel structural designs and methods for manufacturing 3D memory devices are provided to address this problem.

[0061] Figure 1 shows a schematic cross-sectional view of a 3D memory device 100 according to some aspects of the present disclosure. The 3D memory device 100 represents an example of a bonded chip. In some implementations, at least some of the components of the 3D memory device 100 (e.g., the first wafer / first semiconductor structure 110 and the second wafer / second semiconductor structure 120 as shown in Figure 1) are formed separately in parallel on different substrates and then bonded to form a bonded chip (a process referred to herein as a "parallel process").

[0062] Note that X / Y and Z axes have been added to Figure 1 to further illustrate the spatial relationships of the components of the semiconductor device. The substrate of a semiconductor device (e.g., a 3D memory device 100) includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (e.g., word line direction) and y-direction (e.g., bit line direction). As used herein, when the substrate is located in the lowest plane of the semiconductor device in the z-direction (vertical or thickness direction), whether one component (e.g., a layer or device) is "above," "above," or "below" another component (e.g., a layer or device) of the semiconductor device is determined relative to the substrate of the semiconductor device in the z-direction. The same concepts used throughout this disclosure to describe spatial relationships apply.

[0063] As shown in Figure 1, the 3D memory device 100 may include a first semiconductor structure 110 and a second semiconductor structure 120. The first semiconductor structure 110 includes peripheral circuitry 112, and the second semiconductor structure 120 includes a memory cell array 122. That is, the memory cell array 122 and its peripheral circuitry 112 may be partitioned into at least two other semiconductor structures (e.g., 110 and 120 in Figure 1).

[0064] In some implementations, peripheral circuitry 112 may be coupled to memory cell array 122 to perform read / program (write) / erase operations on memory cell array 122. Peripheral circuitry 112 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory cell array 122. For example, peripheral circuitry 112 may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), I / O circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). Peripheral circuitry 112 in the first semiconductor structure 110 may be implemented using CMOS technology, for example, it may utilize logic processes at any suitable technology node.

[0065] In some implementations, the second semiconductor structure 120 may include a plurality of memory cell arrays 122 separated by spacer regions 124. Each memory cell array 122 in the second semiconductor structure 120 may include an array of memory cells, such as an array of NAND flash memory cells. For ease of description, a NAND flash memory cell array may be used as an example to describe the memory cell array 122 in this disclosure. However, it should be understood that the memory cell array 122 is not limited to a NAND flash memory cell array and may include any other suitable type of memory cell array, such as a NOR flash memory cell array, a phase change memory (PCM) cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, to name a few. In some implementations, the plurality of memory cell arrays 122 may be of the same type or different types.

[0066] In some implementations, each memory cell array 122 may be a NAND flash memory device, wherein memory cells are provided in the form of an array of 3D NAND memory strings, each 3D NAND memory string extending vertically (in 3D) above the substrate via a stacked structure (e.g., a memory stack). Depending on the 3D NAND technology (e.g., the number of layers / tiers in the memory stack), a 3D NAND memory string typically includes a specific number of NAND memory cells, each of which includes a floating-gate transistor or a charge-trapping transistor. The NAND memory cells may be organized into pages or fingers, which are then organized into blocks, in which each NAND memory cell is coupled to a bit line (BL) and a word line (WL). In some implementations, a memory plane comprises a specific number of blocks coupled via the same bit lines. The first semiconductor structure 110 may include one or more memory planes.

[0067] As shown in Figure 1, a first semiconductor structure 110 and a second semiconductor structure 120 are stacked in the vertical direction (z-direction). In some implementations, the first semiconductor structure 110 and the second semiconductor structure 120 are bonded together. Therefore, the 3D memory device 100 also includes a bonding interface 130 perpendicularly between the first semiconductor structure 110 and the second semiconductor structure 120. The bonding interface 130 can be an interface between two semiconductor structures formed by any suitable bonding technique described in detail below (e.g., hybrid bonding, anodic bonding, fusion bonding, transfer bonding, binder bonding, and eutectic bonding, to name a few).

[0068] The first semiconductor structure 110 and the second semiconductor structure 120 can be fabricated individually (in parallel in some implementations) through parallel processes, such that the thermal budget for fabricating one of the first semiconductor structure 110 and the second semiconductor structure 120 does not limit the process for fabricating the other of the first semiconductor structure 110 and the second semiconductor structure 120. Furthermore, in contrast to long-distance (e.g., millimeter- or centimeter-scale) chip-to-chip data buses on a circuit board (e.g., a printed circuit board, PCB), a large number of interconnects (e.g., bonding contact structures and / or inter-layer vias (ILVs) / through substrate vias (TSVs)) can be formed across the bonding interface 130 to establish direct, short-distance (e.g., micrometer- or submicrometer-scale) electrical connections between the first semiconductor structure 110 and the second semiconductor structure 120, thereby eliminating chip interface delays and achieving high-speed I / O throughput with reduced power consumption. Data transfer between the memory cell array 122 in the first semiconductor structure 110 and the second semiconductor structure 120 and the different peripheral circuits 112 can be performed via interconnects across the bonding interface 130 (e.g., bonding contact structures and / or ILV / TSV). By vertically integrating the first semiconductor structure 110 and the second semiconductor structure 120, the chip size can be reduced and the memory cell density can be increased.

[0069] Figure 2 shows a schematic circuit diagram of a memory device 200 according to some aspects of the present disclosure. The memory device 200 may include a plurality of memory cell arrays 201 and peripheral circuitry 202 coupled to the memory cell arrays 201. A 3D memory device 100 may be an example of the memory device 200, wherein the peripheral circuitry 202 may be included in a first semiconductor structure 110 and a second semiconductor structure 120. The memory cell array 201 may be a NAND flash memory cell array, wherein memory cells 206 are provided in the form of an array of NAND memory strings 208, each NAND memory string extending vertically above a substrate (not shown). In some implementations, each NAND memory string 208 includes a plurality of memory cells 206 coupled in series and stacked vertically. Each memory cell 206 may hold a continuous analog value (e.g., voltage or charge) depending on the number of electrons trapped in the region of the memory cell 206. Each memory cell 206 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0070] In some implementations, each memory cell 206 is a single-level cell (SLC) with two possible storage states and can therefore store one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some implementations, each memory cell 206 is a multi-level cell (MLC) that can store more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell, three bits per cell (also called a triple-level cell (TLC)), or four bits per cell (also called a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0071] As shown in Figure 2, each NAND memory string 208 may include a source select gate (SSG) transistor 210 at its source end and a drain select gate (DSG) transistor 212 at its drain end. The SSG transistor 210 and DSG transistor 212 may be configured to activate the selected NAND memory string 208 (column of the array) during read and program operations. In some implementations, the SSG transistors 210 of the NAND memory strings 208 in the same block 204 are coupled, for example, to the ground via the same source line (SL) 214 (e.g., a common SL). According to some implementations, the DSG transistor 212 of each NAND memory string 208 is coupled to a corresponding bit line 216 from which data can be read or programmed via an output bus (not shown). In some implementations, each NAND memory string 208 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of DSG transistor 214) or a deselection voltage (e.g., 0V) to the corresponding DSG transistor 212 via one or more DSG lines 213 and / or by applying a selection voltage (e.g., higher than the threshold voltage of SSG transistor 210) or a deselection voltage (0V) to the corresponding SSG transistor 210 via one or more SSG lines 215.

[0072] As shown in Figure 2, NAND flash memory strings 208 can be organized into multiple blocks 204, each block 204 may have a common source line 214. In some implementations, each block 204 is the basic data unit for erase operations, that is, all memory cells 206 on the same block 204 are erased simultaneously. Memory cells 206 of adjacent NAND flash memory strings 208 can be coupled via word lines 218, which select which row of memory cells 206 is affected by read and program operations. In some implementations, multiple blocks 204 can be organized into a memory plane (not shown), which forms a memory cell array 122 as shown in Figure 1, and multiple memory planes can be formed on the same die, constituting the second semiconductor structure 120 as shown in Figure 1.

[0073] Referring to Figure 2, the peripheral circuitry 202 can be coupled to the memory cell array 201 via bit line 216, word line 218, source line 214, SSG line 215, and DSG line 213. As described above, the peripheral circuitry 202 can include any suitable circuitry for facilitating the operation of the memory cell array 201 by applying voltage and / or current signals to each target memory cell 206 via bit line 216, and sensing voltage and / or current signals from each target memory cell 206 via word line 218, source line 214, SSG line 215, and DSG line 213. The peripheral circuitry 202 can include various types of peripheral circuitry formed using CMOS technology.

[0074] For example, Figure 3 illustrates a memory device 300 including a memory cell array 201 and various exemplary peripheral circuits 202. The peripheral circuits 202 include a page buffer 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, a register 314, an interface (I / F) 316, and a data bus 318. It should be understood that in some examples, additional peripheral circuits 202 may also be included. Note that for simplicity, Figure 3 shows only one memory cell array 201, but the memory device 300 includes multiple memory cell arrays 201 and corresponding peripheral circuits 202 for each memory cell array 201.

[0075] Page buffer 304 can be configured to buffer data read from or programmed into memory cell array 201 according to control signals of control logic 312. In one example, page buffer 304 can store one page of programming data (write data) to be programmed into memory cell array 201. In another example, page buffer 304 also performs a programming verification operation to ensure that data has been correctly programmed into memory cell 206 coupled to selected word line 218.

[0076] The row decoder / word line driver 308 can be configured to be controlled by control logic 312 and to select block 204 of the memory cell array 201 and word line 218 of the selected block 204. The row decoder / word line driver 308 can also be configured to drive the memory cell array 201. For example, the row decoder / word line driver 308 can use a word line voltage generated from voltage generator 310 to drive a memory cell 206 coupled to the selected word line 218.

[0077] The column decoder / bit line driver 306 can be configured to be controlled by control logic 312 and to select one or more 3D NAND memory strings 208 by applying a bit line voltage generated from voltage generator 310. For example, the column decoder / bit line driver 306 can apply a column signal for selecting a set of N bits of data from page buffer 304 for output in a read operation.

[0078] Control logic 312 can be coupled to each peripheral circuit 202 and configured to control the operation of the peripheral circuit 202. Register 314 can be coupled to control logic 312 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses to control the operation of each peripheral circuit 202.

[0079] Interface 316 can be coupled to control logic 312 and configured to engage memory cell array 201 with a memory controller (not shown). In some implementations, interface 316 serves as a control buffer to buffer control commands received from the memory controller and / or host (not shown) and relay them to control logic 312, and to buffer status information received from control logic 312 and relay it to the memory controller and / or host. Interface 316 can also be coupled to page buffer 304 and column decoder / bitline driver 306 via data bus 318, and serves as an I / O interface and data buffer to buffer programming data received from the memory controller and / or host and relay it to page buffer 302, and to buffer data read from page buffer 304 and relay it to the memory controller and / or host. In some implementations, interface 316 and data bus 318 are part of the I / O circuitry of peripheral circuitry 202.

[0080] Voltage generator 310 can be configured to be controlled by control logic 312 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, and verification voltage) and bit line voltages to be supplied to memory cell array 201. In some implementations, voltage generator 310 is part of a voltage source that provides voltages at various levels for different peripheral circuits 202, as described in detail below. Consistent with the scope of this disclosure, in some implementations, the voltages supplied by voltage generator 310 to, for example, row decoder / word line driver 308, column decoder / bit line driver 306, and page buffer 304 are higher than specific levels sufficient to perform memory operations.

[0081] Figure 4 shows a cross-sectional side view of an exemplary 3D memory device 400 according to some aspects of the present disclosure. Note that the X and Z axes are included in Figure 4 to further illustrate the spatial relationships of the components in the 3D memory device 400. As shown in Figure 4, in some implementations, the 3D memory device 400 is a bonded chip including a first semiconductor structure 410 and a second semiconductor structure 420 stacked on the first semiconductor structure 420. According to some implementations, the first semiconductor structure 410 and the second semiconductor structure 420 are bonded at a bonding interface 450 between them.

[0082] As shown in Figure 4, the first semiconductor structure 410 may include a substrate 413 and a semiconductor layer 415. The substrate 413 may be any suitable substrate, such as a semiconductor substrate or a non-semiconductor substrate. The semiconductor layer 415 may include silicon (e.g., single-crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable semiconductor material. In some implementations, the first semiconductor structure 410 of the 3D memory device 400 may include a device layer 430 on the semiconductor layer 415. In some implementations, the device layer 430 includes a plurality of transistors 436 forming one or more of the aforementioned peripheral circuits. In some implementations, isolation regions (e.g., shallow trench isolation (STI), not shown) and doped regions (e.g., source and drain regions of transistors) may be formed in the semiconductor layer 415.

[0083] As shown in Figure 4, the second semiconductor structure 420 can be bonded face-to-face to the top of the first semiconductor structure 410 at the bonding interface 450. In some implementations, the bonding interface 450 is the result of hybrid bonding (also referred to as "metal / dielectric hybrid bonding"), a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer (e.g., solder or adhesive)) that can simultaneously achieve metal-to-metal and dielectric-to-dielectric bonding. In some implementations, the bonding interface 450 is the location where the first semiconductor structure 410 and the second semiconductor structure 420 meet and bond.

[0084] In some implementations, the first semiconductor structure 410 of the 3D memory device 400 may further include a first bonding layer 453 at a bonding interface 450. The second semiconductor structure 420 of the 3D memory device 100 may include a second bonding layer 456 bonded to the first bonding layer 453 of the first semiconductor structure 410 at the bonding interface 450. The first bonding layer 453 and the second bonding layer 456 may include a plurality of bonding contact structures and a dielectric material electrically isolating the bonding contact structures. The bonding contact structures may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining regions of the first bonding layer 453 and the second bonding layer 456 may be formed using a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contact structures in the first bonding layer 453 and the second bonding layer 456 and the surrounding dielectric material may be used for hybrid bonding. According to some implementations, the bonding contact structure of the first bonding layer 453 contacts the bonding contact structure of the second bonding layer at the bonding interface 450.

[0085] In some implementations, the first semiconductor structure 410 of the 3D memory device 400 further includes a first interconnect layer (not shown) coupled between device layers 430 and to a first bonding layer 453, and the second semiconductor structure 420 of the 3D memory device 400 further includes a second interconnect layer (not shown) between a second bonding layer 456 and a memory cell array. The first and second interconnect layers may include multiple interconnects (also referred to herein as contact structures), including lateral interconnects and vertical interconnect access (VIA) contact structures, to transmit electrical signals between peripheral circuitry and the memory cell array. As used herein, the term interconnect can broadly include any suitable type of interconnect, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The first and second interconnect layers may also include one or more interlayer dielectric (ILD) layers (also referred to as intermetallic dielectric (IMD) layers) in which interconnects and VIA contact structures can be formed. That is, the first interconnect layer and the second interconnect layer may include interconnects and VIA contact structures in multiple ILD layers. The interconnects and VIA contact structures in the first and second interconnect layers may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in the first and second interconnect layers may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-dielectric-constant (low-K) dielectrics, or any combination thereof.

[0086] In some implementations, the second semiconductor structure 420 of the 3D memory device 400 may include a plurality of memory regions 422 (also referred to as array regions or core regions) and a spacing region 424 between adjacent memory regions 422. Within each memory region 422, the second semiconductor structure 420 may include a NAND flash memory device, wherein an array of memory cells may be provided in the form of an array of NAND memory strings. Each NAND memory string may include a corresponding channel structure extending vertically through the memory stack 460. The memory stack 460 may include multiple pairs, each pair including a stack conductive layer and a stack dielectric layer. In some implementations, the stack conductive layer may include any suitable conductive material (i.e., tungsten, etc.), and the stack dielectric layer may include any suitable insulating material (i.e., silicon oxide, etc.). The staggered stack conductive layers and stack dielectric layers are part of the memory stack 460. The number of pairs of stack conductive layers and stack dielectric layers in the memory stack 460 determines the number of memory cells in the 3D memory device 400. It should be understood that in some implementations, the memory stack 460 may have a ladder structure, comprising multiple memory decks stacked on top of each other. The number of stack conductive layers and stack dielectric layers in each memory deck may be the same or different.

[0087] The memory stack 460 may include multiple staggered stacked conductive layers and stacked dielectric layers. The stacked conductive layers and stacked dielectric layers in the memory stack 460 may alternate in the vertical direction. In other words, in addition to the stacked conductive layers and stacked dielectric layers at the top or bottom of the memory stack 460, each stacked conductive layer may be adjacent to two stacked dielectric layers on both sides, and each stacked dielectric layer may be adjacent to two stacked conductive layers on both sides. The stacked conductive layers may include conductive materials, including but not limited to W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof. Each stacked conductive layer may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the stacked conductive layer may extend laterally as a word line, terminating in one or more stepped structures of the memory stack. The stacked dielectric layers may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0088] In some implementations, each channel structure may be cylindrical (e.g., columnar) and may extend vertically through staggered stacked conductive and dielectric layers of the memory stack 460. According to some implementations, each channel structure includes a channel via filled with a composite memory layer, a channel layer, and a filling structure arranged radially from the center of the column toward an outer surface. The filling structure may include a dielectric material, such as silicon oxide, and / or an air gap. The composite memory layer may radially surround the channel layer in a lateral direction. The composite memory layer may be laterally formed between the channel layer and the memory stack 460. In some implementations, the channel layer includes silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In some implementations, the channel layer may include doped and undoped portions.

[0089] In some implementations, the second semiconductor structure 420 in each memory region 422 may include a semiconductor layer 465 covering the memory stack 460 and contacting multiple channel structures. In some implementations, the semiconductor layer 465 may include doped polysilicon and contact a doped portion of the channel layer. In some implementations, the doped portions of the semiconductor layer 465 and the channel layer may include N-type dopant. The semiconductor layer 465 may serve as a common source line for the channel structure of a NAND memory string.

[0090] As shown in Figure 4, the second semiconductor structure 420 in the spacer region 424 may include a dielectric stack 470. The dielectric stack 470 may include multiple pairs, each pair including a stack sacrificial layer and a stack dielectric layer. In some implementations, the stack sacrificial layer may include any suitable dielectric material different from the stack dielectric layer (i.e., silicon nitride, etc.). Interleaved stack sacrificial layers and stack dielectric layers are part of the dielectric stack 470. In some implementations, the number of pairs of stack sacrificial layers and stack dielectric layers in the dielectric stack 470 is the same as the number of pairs of stack conductive layers and stack dielectric layers in the storage stack 460. In some implementations, the second semiconductor structure 420 in the spacer region 424 may also include a conductive structure 486 passing through the dielectric stack 470. In some implementations, the conductive structure 486 may be coupled to a transistor 436 of a peripheral circuit via a first interconnect layer and a second interconnect layer, as well as a first bonding layer and a second bonding layer.

[0091] As shown in Figure 4, the 3D storage device 400 may include conductive pads 488 on top of and coupled to the conductive structure 486. In some implementations, the conductive pads may be formed using any suitable BEOL method. The conductive structure 486 is electrically connected to the transistor 436. The conductive structure 486 may include any suitable type of conductive material. In some implementations, the conductive structure 486 may be formed using materials such as W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof.

[0092] In some implementations, an insulating layer 472 may be formed in the memory region 422 and the spacer region 424 to cover the semiconductor layer 465, the memory stack 460, and the dielectric stack 470. Openings may be formed in the insulating layer 472 to expose a subset of the conductive structures 486. In some implementations, an adhesive layer 482 may be formed on the insulating layer 472 and in the openings to contact the conductive structures 486. Conductive pads 488 may be formed on the adhesive layer 482. In some implementations, the conductive pads 488 may be formed directly in the openings without the need for the adhesive layer 482.

[0093] As shown in Figure 4, each conductive pad 488 may include a first portion 488-1 embedded in a spacer region and a second portion 488-2 above the spacer region. The bottom surface of the first portion 488-1 contacts the top surface of a corresponding conductive structure 486 extending through the insulating layer 472 to make electrical contact with a corresponding transistor 436. The conductive pad 488 may be formed of a material including W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof.

[0094] Although an exemplary 3D memory device 400 is shown in Figure 4, it should be understood that any other suitable architecture of the 3D memory device can be applied to this disclosure without further detail by changing the relative positions of the first semiconductor structure 410 and the second semiconductor structure 420, various interconnects, the use of contact structures and / or pad-outlocation (e.g., by the first semiconductor structure 410 or the second semiconductor structure 420).

[0095] Figure 5A shows a schematic top view (XY plane) of an exemplary 3D memory die 500A according to various aspects of the present disclosure. Figure 5B provides an enlarged top view of a portion 500B of the 3D memory die 500A according to various aspects of the present disclosure, in which specific elements are described in detail for clarity. Figure 5C presents a cross-sectional side view (XZ plane) of the 3D memory die 500A along lines A-A' and B-B' shown in Figure 5A. Figure 5D shows another cross-sectional side view (YZ plane) along lines C-C' and D-D' in Figure 5A. It should be noted that the 3D memory die 500A of a 3D memory device (e.g., the 3D memory device 400 in conjunction with Figure 4) may include one or more memory planes, such as the two memory planes 510 shown in Figure 5A.

[0096] As shown in Figure 5A, in some implementations, the 3D memory die 500A may include memory regions 522 and spacing regions 524 between adjacent memory regions. Each memory region 522 corresponds to a memory plane 510, which may accommodate a NAND memory cell array as part of the 3D memory die 500A. Furthermore, the 3D memory die 500A may include conductive structures 586 (e.g., conductive structure 486) and conductive pads 588 (e.g., conductive pad 488) located in the spacing regions 522.

[0097] As shown in Figure 5A, in some implementations, conductive pads 588 may be located above a subset of conductive structures 586. In each spacing region 524, conductive pads 588 may be arranged as two lines along a first direction (e.g., C-C' and D-D' lines along the Y direction, as shown in Figure 5A) and staggered along a second direction (e.g., A-A' and B-B' lines along the X direction, as shown in Figure 5A). In some implementations, the first and second directions may be perpendicular to each other. In some implementations, the first and second directions are not perpendicular to each other; this is not a limitation herein.

[0098] As shown in Figure 5B, each conductive pad 588 has a length L1 along a first direction (e.g., the Y direction) and a width W1 along a second direction (e.g., the X direction). The length L1 of each conductive pad 588 can range from approximately 0.25 μm to approximately 5 μm, while the width W1 of each conductive pad 588 can range from approximately 0.25 μm to approximately 15 μm. Furthermore, as shown in Figure 5C, each conductive pad 588 extends vertically along a vertical direction (e.g., the Z direction), with a height H1 ranging from 0.2 μm to approximately 1.2 μm. In some implementations, the first direction, the second direction, and the vertical direction can be perpendicular to each other. In some implementations, the first direction and the second direction are not perpendicular to each other, but both are perpendicular to the vertical direction. In some implementations, the first direction, the second direction, and the vertical direction are not perpendicular to each other; this is not a limitation herein.

[0099] As shown in further detail in Figures 5C and 5D, which provide cross-sectional side views along lines A-A' (upper part of Figure 5C), B-B' (lower part of Figure 5C), C-C' (upper part of Figure 5D), and D-D' (lower part of Figure 5D) in Figure 5A, conductive pads 588 are located directly above a subset of conductive structures 586. Each conductive pad 588 extends vertically along the Z-direction, a portion of which is embedded within a spacer region 524 and is in direct electrical contact with the underlying conductive structure 586. The conductive structure 586 itself extends vertically within the spacer region 524, thereby forming the necessary connections between different layers of the 3D memory die.

[0100] As shown in Figure 5D, conductive structures 586 are arranged in two vertical planes (e.g., the YZ-1 plane and the YZ-2 plane), each plane corresponding to one of two lines (e.g., the C-C' line and the D-D' line shown in Figure 5A) of the conductive pad 588 along the Y direction. The conductive structures 586 within each vertical plane are also organized into a first group and a second group of adjacent conductive structures alternating along a first direction. In some implementations, the first group and the second group of adjacent conductive structures 586 are arranged periodically. Each first group includes a first number of adjacent conductive structures 586, each conductive structure located below a corresponding conductive pad 588, and each second group includes a second number of adjacent conductive structures 586 not located below any conductive pad 588. As shown in Figure 5D, the first number can be 1, and the second number can also be 1.

[0101] Figure 5E provides another cross-sectional side view along lines C-C' and D-D' in Figure 5A, further illustrating the staggered arrangement of conductive pads 588 relative to conductive structures 586. In some implementations, the 3D memory die 500A may also include conductive pads 588 directly below which there is no corresponding conductive structure 586.

[0102] Figures 6A-6H illustrate various configurations of conductive structures 686 (e.g., conductive structures 586 in Figures 5A-5E) and conductive pads 688 (e.g., conductive pads 588 in Figures 5A-5E) in spacing regions 624 (e.g., spacing regions 524 in Figures 5A-5E) between adjacent memory regions 622 (e.g., memory regions 522 in conjunction with Figures 5A-5E) of the 3D memory devices 600A-600H. Each memory region 622 corresponds to a memory plane 610 that can accommodate an array of NAND memory cells. The spacing region 624 is located between two adjacent memory regions 622.

[0103] In all the configurations shown in Figures 6A-6H, conductive structures 686 are arranged as two lines along a first direction (e.g., the Y direction). Each conductive structure 686 extends vertically, and the two lines of the conductive structure form two vertical planes within a spacing region 624. Conductive pads 688 are located above a subset of these conductive structures 686 and are also arranged as two lines along the first direction. The conductive pads 688 in each line are staggered with each other along a second direction perpendicular to the first direction (e.g., the X direction).

[0104] The conductive structures 686 within each vertical plane are further organized into a first group of adjacent conductive structures and a second group of adjacent conductive structures alternating along a first direction. Each first group includes a first number of adjacent conductive structures 686, each of which is located below a corresponding conductive pad 688, and each second group includes a second number of adjacent conductive structures 686 that are not located below any conductive pad 688. In some implementations, the first number may be 1, and the second number may be greater than 1. For example, as shown in Figures 6A and 6B, the first number is 1, and the second number may be an odd number, such as 3 or 5. In some implementations, both the first number and the second number may be greater than 1. For example, the first number may be an even number (e.g., 2), and the second number may also be an even number (e.g., 2), as shown in Figure 6C. In some implementations, the first number may be an even number (e.g., 2), and the second number may be another even number, such as 4 (as shown in Figure 6D) or 6 (as shown in Figure 6E). In other implementations, the first quantity can be an odd number (e.g., 3), and the second quantity can be an odd number, such as 3 (as shown in Figure 6F), 5 (as shown in Figure 6G), or 7 (as shown in Figure 6H).

[0105] Figure 7 illustrates a block diagram of an exemplary system 700 with 3D storage devices according to some aspects of this disclosure. System 700 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage devices therein. As shown in Figure 7, system 700 may include a host 708 and a memory system 702 having one or more 3D storage devices 704 and a memory controller 706. Host 708 may be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). Host 708 may be configured to send data to or receive data from 3D storage devices 704.

[0106] 3D memory device 704 can be any 3D memory device disclosed herein, such as 3D memory device 400 shown in FIG. 4. In some implementations, each 3D memory device 704 includes NAND flash memory. Consistent with the scope of this disclosure, the channel layer of 3D memory device 704 may be partially doped such that a portion of the channel layer forming the source contact is highly doped to lower the barrier, while another portion of the channel layer forming the memory cell remains undoped or lightly doped. One end of each channel structure of 3D memory device 704 may be openable from the back side to expose the doped portion of the corresponding channel layer. 3D memory device 704 may also include a doped semiconductor layer electrically connected to the exposed doped portion of the channel layer to further reduce contact resistance and sheet resistance. In addition, 3D memory device 704 may include a composite dielectric film having a gate dielectric portion facing the source select gate line. The gate dielectric portion may be free of silicon nitride (e.g., consisting only of silicon oxide) and used as the gate dielectric of an SSG transistor. Therefore, the electrical performance of the 3D storage device 704 can be improved, which in turn improves the performance of the memory system 702 and system 700, for example, achieving higher operating speeds.

[0107] In some implementations, a memory controller 706 (also referred to as controller circuitry) is coupled to the 3D storage device 704 and the host 708 and is configured to control the 3D storage device 708. The memory controller 706 can manage data stored in the 3D storage device 704 and communicate with the host 708. In some implementations, the memory controller 706 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media for electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some implementations, the memory controller 706 is designed to operate in high duty cycle environments, such as in SSDs or embedded multi-media cards (eMMCs) used as data storage devices for mobile devices (e.g., smartphones, tablets, laptops, etc.) and enterprise storage arrays. The memory controller 706 can be configured to control the operation of the 3D storage device 704, such as read, erase, and program operations. The memory controller 706 can also be configured to manage various functions related to data stored in or to be stored in the 3D storage device 704, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, the memory controller 706 is also configured to handle error correction codes (ECCs) related to reading from or writing data to the 3D storage device 704. Any other suitable functions can also be performed by the memory controller 706, such as formatting the 3D storage device 704. The memory controller 706 can communicate with external devices (e.g., host 708) according to specific communication protocols.For example, the memory controller 706 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnection (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0108] The memory controller 706 and one or more 3D storage devices 704 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 702 can be implemented and packaged into different types of end electronic products. In an example shown in Figure 8A, the memory controller 706 and a single 3D storage device 704 can be integrated into a memory card 802. The memory card 802 may include PC cards (PCMCIA (personal computer memory card international association), CF cards, smart media (SM) cards, Memory Sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 802 may also include a memory card connector 804 that electrically couples the memory card 802 to a host (e.g., host 708 in Figure 7). In another example shown in Figure 8B, the memory controller 706 and multiple 3D storage devices 704 can be integrated into the SSD 806. The SSD 806 may also include an SSD connector 808 that electrically couples the SSD 806 to a host (e.g., host 708 in Figure 7). In some implementations, the storage capacity and / or operating speed of the SSD 806 is greater than the storage capacity and / or operating speed of the memory card 802.

[0109] Referring to FIG9, a flowchart of an exemplary method 900 for forming a 3D storage device according to some implementations of the present disclosure is shown. It should be understood that the operations shown in FIG9 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in a different order than that shown in FIG9. FIG10A-FIG10E show schematic cross-sectional views of an exemplary 3D storage device at a specific manufacturing stage of the method 900 shown in FIG9, according to some implementations of the present disclosure.

[0110] Referring to Figure 9, method 900 may begin with operation 910, wherein a first semiconductor structure and a second semiconductor structure may be formed, and the first semiconductor structure may be bonded to the second semiconductor structure. In some implementations, forming the first semiconductor structure may include: forming memory regions, wherein each memory region includes a memory stack and a channel structure extending vertically through the memory stack; and forming a spacing region between two adjacent memory regions. In some implementations, forming the second semiconductor structure may include forming peripheral circuitry including transistors.

[0111] Figure 10A shows a schematic cross-sectional view of a 3D semiconductor structure after operation 910, according to some implementations of the present disclosure. As shown in Figure 10A, according to some implementations, the first semiconductor structure 1010 and the second semiconductor structure 1020 are bonded together at a bonding interface 1050 between them.

[0112] As shown in FIG10A, forming the first semiconductor structure 1010 may include forming a device layer 1030 on a semiconductor layer 1015 and a substrate 1013. In some implementations, forming the device layer 1030 includes forming a transistor 1036 on the semiconductor layer 1015. In some implementations, isolation regions (e.g., shallow trench isolation (STI), not shown) and doped regions (e.g., source and drain regions of a transistor) may be formed in the semiconductor layer 1015. In some implementations, forming the first semiconductor structure 1010 may include forming a first interconnect layer (not shown) and a first bonding layer. The first interconnect layer may include multiple interconnects, and the first bonding layer may include multiple bonding contact structures. The first interconnect layer and the first bonding layer may be formed by any suitable MEOL / BEOL process.

[0113] In some implementations, forming the second semiconductor structure 1020 may include forming a memory region 1022 and a spacer region 1024, the memory region 1022 including a memory stack 1060 and the spacer region 1024 including a dielectric stack 1070. In some implementations, forming the second semiconductor structure 1020 may include forming a plurality of channel structures 1063 extending vertically through the memory stack 1060. Specifically, forming the second semiconductor structure 1020 may include: forming a dielectric stack 1070 including alternating dielectric layers and sacrificial layers; forming a plurality of channel structures 1063 extending vertically through the dielectric stack in the plurality of memory regions 1022; and replacing portions of the sacrificial layers in the plurality of memory regions 1022 with conductive layers to convert the dielectric stack 1070 in the plurality of memory regions 1022 into a plurality of memory stacks 1060. The remaining portions of the dielectric stack 1070 are located in the spacer region 1024 between the plurality of memory regions 1022.

[0114] In some implementations, forming the second semiconductor structure 1020 may further include forming a semiconductor layer 1065 in the memory region 1022, the semiconductor layer 1065 covering the memory stack 1060 and contacting the ends (e.g., the top ends) of the plurality of channel structures. In some implementations, the semiconductor layer 465 may be doped with an N-type dopant. In some implementations, forming the second semiconductor structure 1020 may further include forming a plurality of conductive structures 1086 extending vertically through the dielectric stack 1070 in the spacing region 1024.

[0115] In some implementations, forming the second semiconductor structure 1020 further includes: forming a second interconnect layer (not shown) that contacts the ends of the plurality of channel structures, and forming a second bonding layer coupled to the second interconnect layer. The second interconnect layer may include a plurality of interconnects, and the second bonding layer may include a plurality of bonding contact structures. The second interconnect layer and the second bonding layer can be formed by any suitable MEOL / BEOL process.

[0116] In some implementations, the second semiconductor structure 1020 may be bonded to the first semiconductor structure 1010 at bonding interface 1050. The first semiconductor structure 1010 and the second semiconductor structure 1020 may be bonded face-to-face. Bonding may include hybrid bonding. In some implementations, prior to bonding, a processing technique, such as plasma treatment, wet treatment, and / or thermal treatment, is applied to the bonding surfaces of the first semiconductor structure 1010 and the second semiconductor structure 1020. After bonding, corresponding bonding contact structures in the first and second bonding layers are aligned and contact each other, allowing the channel structure and the transistor 1036 to be electrically connected.

[0117] Referring back to Figure 9, method 900 proceeds to operation 920, wherein insulating layers can be formed in the spacer region and multiple storage regions to cover the dielectric stack and semiconductor layers, and openings can be formed in the insulating layer in the spacer region to expose subsets of conductive structures.

[0118] Figures 10B-10D show schematic cross-sectional views of 3D semiconductor structures according to some implementations of this disclosure at specific stages of operation 920.

[0119] As shown in Figure 10B, an insulating layer 1072 can be formed in the spacer region 1024 and the plurality of memory regions 1022 to cover the dielectric stack 1070 and the semiconductor layer 1065. The insulating layer 1072 can be formed using any suitable material and any suitable deposition process. For example, the insulating layer 1072 can be formed using dielectric materials including, but not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON).

[0120] As shown in Figure 10C, a first opening 1082 can be formed in the insulating layer 1072 using any suitable etching process to expose a subset of the conductive structure 1086. In some implementations, the process may begin by depositing a photoresist layer on the insulating layer 1072, and then patterning the photoresist layer using photolithography to define the location of the first opening. The first opening 1082 can then be created by etching the insulating layer 1072 at the defined location to expose the conductive structure 1086. This etching process can be performed using techniques such as reactive ion etching (RIE) or chemical etching, selected based on the material properties of the insulating layer 1072 and the underlying structure. The process exposes a subset of conductive structures 1086 in a manner consistent with the configuration of conductive structures shown in the previous figures (e.g., Figures 5A-5E and 6A-6H), the subset of conductive structures 1086 comprising a first group of adjacent conductive structures 1085 and a second group of adjacent conductive structures 1086 arranged alternately along a first direction, wherein each first group includes a first number of adjacent conductive structures and each second group includes a second number of adjacent conductive structures.

[0121] As shown in Figure 10D, the first opening 1082 can be further processed by maintaining a first portion near the corresponding conductive structure of each first opening 1082 while selectively enlarging a second portion of each first opening 1082 near the top surface of the insulating layer 1072, thereby forming a second opening 1084. This enlargement can be achieved by an additional etching step, which can be isotropic or anisotropic, depending on the desired final profile of the opening. Selective enlargement creates a wider area near the surface, facilitating subsequent deposition of conductive material to form conductive pads, thereby ensuring optimal electrical contact and mechanical stability.

[0122] Referring back to Figure 9, method 900 proceeds to operation 930, where conductive pads may be formed over a subset of the conductive structure. Figure 10E shows a schematic cross-sectional view of a 3D semiconductor structure according to some implementations of this disclosure after operation 930.

[0123] As shown in Figure 10E, forming conductive pads 1088 on the insulating layer 1072 and in the second openings 1084 may include depositing a first conductive material to fill a first portion of each second opening 1084. A second conductive material may then be deposited to fill a second portion of each second opening 1084, such that the conductive pads 1088 extend above the top surface of the insulating layer 1072. The first and second conductive materials may include, but are not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof. The first conductive material may be the same as the material of the conductive structure 1086. The second conductive material may be the same as or different from the first conductive material, and this is not limited herein.

[0124] In some implementations, forming conductive pads 1088 on the insulating layer 1072 and in the second opening 1084 includes depositing a conductive seed layer within each second opening 1084. An electroplating process can then be performed to grow the conductive seed layer within each second opening 1084 until the conductive pads 1088 extend above the top surface of the insulating layer 1072, as shown in FIG10D. The electroplating process can be performed using any suitable conductive material (e.g., W, Co, Cu, or Al). The conductive material used to form the conductive pads can be the same as or different from the material of the conductive structure 1086, and this is not limited herein.

[0125] In some implementations, forming conductive pads 1088 on the insulating layer 1072 and in the second opening 1084 may include depositing a conductive material layer over the insulating layer and into the second opening 1084. After deposition, an etch-back process may be applied to remove excess conductive material from the top surface of the insulating layer 1072. This process ensures that the conductive pads 1088 are partially retained within the second opening 1084 and partially extend over the insulating layer 1072. The conductive material used may include W, Co, Cu, Al, or any other suitable material. The conductive material used to form the conductive pads may be the same as or different from the material of the conductive structure 1086, and this is not limited herein.

[0126] The above description provides an exemplary implementation for forming conductive pads 1088. However, it should be understood that other suitable methods may be employed, and are not limited to the specific processes described herein. The resulting conductive pads 1088 are formed over a subset of conductive structures 1086 and are arranged as two lines along a first direction (e.g., the Y direction as shown in Figures 5A and 5D) and interleaved with each other along a second direction (the X direction as shown in Figures 5A and 5C). The first direction is perpendicular to the vertical direction (Z direction), and the second direction is perpendicular to both the first and vertical directions. As for the conductive structures 1086, the conductive structures 1086 are arranged in two vertical planes (e.g., the YZ-1 plane and the YZ-2 plane as shown in Figure 5D), wherein each conductive structure 1086 extends vertically through the dielectric stack 1070. Each of the two vertical planes includes a corresponding line of the two lines along the first direction. The conductive structures 1086 in each vertical plane are alternately arranged along the first direction as a first set of adjacent conductive structures and a second set of adjacent conductive structures. Each first group includes a first number of adjacent conductive structures, and each second group includes a second number of adjacent conductive structures. In some implementations, the first group of adjacent conductive structures and the second group of adjacent conductive structures are arranged periodically.

[0127] In some implementations, method 900 includes forming a first number of adjacent conductive pads on a first number of adjacent conductive structures, without forming any conductive pads on a second number of adjacent conductive structures, wherein the first number is 1 and the second number is at least 1.

[0128] In some implementations, method 900 includes forming a first number of adjacent conductive pads on a first number of adjacent conductive structures, without forming any conductive pads on a second number of adjacent conductive structures, wherein the first number is greater than 1 and the second number is greater than 1.

[0129] The foregoing description of the specific implementation can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the publicly disclosed implementation.

[0130] The breadth and scope of this disclosure should not be limited to any of the exemplary implementations described above, but should be defined solely by the following claims and their equivalents.

Claims

1. A semiconductor device, comprising: Storage area; An interval region located between two adjacent storage regions, wherein the interval region includes: a dielectric stack; and a conductive structure extending vertically through the dielectric stack; and conductive pads above a subset of the conductive structure, wherein the conductive pads are arranged as two lines along a first direction and intersecting each other along a second direction, wherein the first direction is perpendicular to the vertical direction, and the second direction is perpendicular to both the first direction and the vertical direction.

2. The semiconductor device according to claim 1, wherein: The conductive structures are arranged in two vertical planes, each of the two vertical planes including one of the two lines along the first direction; and the conductive structures in each vertical plane include a first group of adjacent conductive structures and a second group of adjacent conductive structures arranged alternately along the first direction, wherein each first group includes a first number of adjacent conductive structures, each of the first number of adjacent conductive structures being located below a corresponding conductive pad, and each second group includes a second number of adjacent conductive structures not located below any conductive pad.

3. The semiconductor device according to claim 2, wherein: The first quantity is 1; and the second quantity is at least 1.

4. The semiconductor device according to claim 3, wherein, The first group of adjacent conductive structures and the second group of adjacent conductive structures are arranged periodically.

5. The semiconductor device according to claim 2, wherein: The first quantity is greater than 1; and the second quantity is greater than 1.

6. The semiconductor device according to claim 2, further comprising: A subset of conductive pads, which are arranged alternately along the two lines without being located above any conductive structure.

7. The semiconductor device according to claim 1, wherein, Each conductive pad has a first dimension along the first direction, a second dimension along the second direction, and a third dimension along the vertical direction, wherein the first dimension is in the range of approximately 0.25 μm to approximately 5 μm, the second dimension is in the range of approximately 0.25 μm to approximately 15 μm, and the third dimension is in the range of approximately 0.2 μm to approximately 1.2 μm.

8. The semiconductor device according to claim 1, further comprising: The peripheral circuitry includes transistors coupled to the conductive pads.

9. The semiconductor device according to claim 8, wherein, Each storage region includes: a storage stack; and a channel structure extending through the storage stack along the vertical direction, and the storage stack is coupled to the peripheral circuitry.

10. The semiconductor device according to claim 9, wherein, The storage region is bonded to the peripheral circuitry via hybrid bonding.

11. The semiconductor device according to claim 1, wherein, Each conductive pad has a first portion embedded in the spacer region and a second portion above the spacer region.

12. The semiconductor device according to claim 11, wherein, The conductive pads are formed of materials including: W, Co, Cu, Al, polycrystalline silicon, doped silicon, silicides, or any combination thereof.

13. A semiconductor device, comprising: A first semiconductor structure, the first semiconductor structure including a transistor; And a second semiconductor structure, the second semiconductor structure being bonded to the first semiconductor structure via hybrid bonding, wherein the second semiconductor structure includes: a memory region; a spacer region located between two adjacent memory regions, wherein the spacer region includes conductive structures extending in a vertical direction; and conductive pads above a subset of the conductive structures, wherein the conductive pads are arranged as two lines along a first direction perpendicular to the vertical direction and intersecting each other along a second direction perpendicular to both the first direction and the vertical direction.

14. The semiconductor device according to claim 13, wherein: The conductive structures are arranged in two vertical planes, each of the two vertical planes including one of the two lines along the first direction; and the conductive structures in each vertical plane include a first group of adjacent conductive structures and a second group of adjacent conductive structures arranged alternately along the first direction, wherein each first group includes a first number of adjacent conductive structures, each of the first number of adjacent conductive structures being located below a corresponding conductive pad, and each second group includes a second number of adjacent conductive structures not located below any conductive pad.

15. The semiconductor device according to claim 14, wherein: The first quantity is 1; and the second quantity is at least 1.

16. The semiconductor device according to claim 15, wherein, The first group of adjacent conductive structures and the second group of adjacent conductive structures are arranged periodically.

17. The semiconductor device according to claim 14, wherein: The first quantity is greater than 1; and the second quantity is greater than 1.

18. A method of forming a semiconductor device, comprising: Forming interval regions; An opening is formed in the insulating layer to expose a subset of conductive structures, wherein each conductive structure extends in a vertical direction within a spacer region located between two adjacent storage regions; and conductive pads are formed above the subset of conductive structures, wherein the conductive pads are arranged as two lines along a first direction and intersect each other along a second direction, wherein the first direction is perpendicular to the vertical direction and the second direction is perpendicular to both the first direction and the vertical direction.

19. The method according to claim 18, wherein, Forming the interval region includes: forming a dielectric stack portion located between the two adjacent storage regions; and forming the conductive structure, the conductive structure being arranged in two vertical planes and extending through the dielectric stack portion along the vertical direction, each of the two vertical planes including a corresponding line of the two lines along the first direction, wherein the conductive structure in each vertical plane includes a first group of adjacent conductive structures and a second group of adjacent conductive structures arranged alternately along the first direction, wherein each first group includes a first number of adjacent conductive structures, and each second group includes a second number of adjacent conductive structures.

20. The method of claim 19, further comprising: An insulating layer is formed in the spaced region to cover the dielectric stack portion; An opening is formed in the insulating layer to expose a subset of the conductive structure; The conductive pads are formed on the insulating layer and in the openings, and the conductive pads are in contact with a subset of the conductive structure.

21. The method of claim 20, further comprising: Forming a dielectric stack comprising alternating dielectric layers and sacrificial layers; A channel structure extending vertically through the dielectric stack is formed in the storage region; A portion of the sacrificial layer in the storage region is replaced with a conductive layer to convert the dielectric stack in the storage region into a storage stack; And the dielectric stack portion retained in the interval region between the two adjacent storage regions.

22. The method of claim 20, wherein forming the opening in the insulating layer comprises: A photoresist layer is deposited on the insulating layer; The photoresist layer is patterned using photolithography to define the location of the opening; And etching the insulating layer at the defined location to form the opening and expose a subset of the conductive structure.

23. The method of claim 20, wherein, Forming the opening in the insulating layer further includes: retaining a first portion of each opening near the corresponding conductive structure of the opening; and widening a second portion of each opening near the top surface of the insulating layer.

24. The method according to claim 23, wherein, Forming the conductive pads on the insulating layer and in the openings includes: depositing a first conductive material to fill a first portion of each opening; and depositing a second conductive material to fill a second portion of each opening, extending above the top surface of the insulating layer.

25. The method according to claim 23, wherein, Forming the conductive pads on the insulating layer and in the openings includes: depositing a conductive seed layer in each opening; and performing an electroplating process to grow the conductive seed layer in each opening until the conductive pads extend above the top surface of the insulating layer.

26. The method according to claim 23, wherein, Forming the conductive pad on the insulating layer and in the opening includes: depositing a conductive material layer over the insulating layer and depositing it into the opening; and using an etch-back process to remove excess conductive material from the top surface of the insulating layer, such that the conductive pad is partially retained within the opening and partially extends over the insulating layer.

27. The method according to claim 23, wherein, Forming the conductive pads includes: forming the first number of adjacent conductive pads on the first number of adjacent conductive structures, without forming any conductive pads on the second number of adjacent conductive structures, wherein the first number is 1 and the second number is at least 1.

28. The method according to claim 23, wherein, Forming the conductive pads includes: forming the first number of adjacent conductive pads on the first number of adjacent conductive structures, without forming any conductive pads on the second number of adjacent conductive structures, wherein the first number is greater than 1 and the second number is greater than 1.

29. The method of claim 18, further comprising: An external circuit is formed, the external circuit including a transistor coupled to the conductive pad.

30. The method according to claim 29, wherein, Forming the storage region includes: forming a storage stack and a plurality of channel structures extending through the storage stack along the vertical direction, wherein the storage stack is coupled to the peripheral circuitry; and bonding the storage region to the peripheral circuitry by hybrid bonding.

Images