Integrated circuit chip operation parameter on-line monitoring system and method

Abstract

The invention provides an integrated circuit chip operation parameter on-line monitoring system and method, relates to the technical field of chip function testing, and aims to apply functional test excitation which does not influence the main function of a to-be-tested chip during operation of the to-be-tested chip, perform failure identification on heat distribution information, and improve the reliability of the to-be-tested chip. Obtaining the thermal fatigue characteristics of the chip to be tested in the non-uniform heat dissipation state, and determining the health sensitivity of the chip to be tested in the current heat dissipation state according to the thermal fatigue characteristics; determining a working state index on a test operation pin according to the current test signal, and performing defect fitting on the working state index and the health sensitivity to obtain a function retention value of the to-be-tested chip in the current operation state; and monitoring and judging the current function state of the to-be-tested chip according to the function holding value. According to the application, fusion monitoring can be carried out on the thermal characteristics and the electrical characteristics of the chip on the premise of not interfering the main function operation of the chip to be tested, so that the reliability of judging the operation state of the chip is improved.

Description

Technical Field

[0001] This application relates to the field of chip functional testing technology, and more specifically, to an online monitoring system and method for integrated circuit chip operating parameters. Background Technology

[0002] Chip functional testing is widely used in the research and development verification, factory screening, and application assurance of various integrated circuit chips in consumer electronics, industrial control, aerospace, automotive electronics, and other fields. Chip functional testing involves core aspects such as electrical performance parameter testing, logic function integrity verification, and operational stability verification. The test objects cover various types, including computing chips, communication chips, and memory chips. It is characterized by the need for test stimuli to be adapted to the chip architecture, the need for accurate acquisition of response signals, and the need for result judgment to conform to design standards. Furthermore, the test results directly determine whether the chip meets application requirements, serving as a crucial foundation for ensuring the stable operation of terminal devices, the normal implementation of system functions, and the secure implementation of industry applications.

[0003] However, current online monitoring of integrated circuit chip operating parameters largely relies on the acquisition of single electrical parameters and excitation testing methods that interfere with the main function. This makes it impossible to extract heat distribution information when the chip's operating temperature changes from the response signal, thus failing to identify thermal fatigue characteristics under uneven heat dissipation and determine health sensitivity. Furthermore, it is difficult to accurately acquire current test signals along a specified path and calculate the operating state index, making it impossible to obtain functional retention values ​​by correlating thermal and electrical characteristics through defect-based calibration. Consequently, it is impossible to accurately monitor and determine the functional status of the chip under actual operating conditions. Therefore, how to integrate the monitoring of the chip's thermal and electrical characteristics without interfering with the main function of the chip under test, in order to improve the reliability of chip operating status determination, is a problem facing the industry. Summary of the Invention

[0004] This application provides an online monitoring system and method for integrated circuit chip operating parameters, which can perform integrated monitoring of the thermal and electrical characteristics of the chip without interfering with the main function operation of the chip under test, thereby improving the reliability of chip operating status determination.

[0005] In a first aspect, this application provides an online monitoring method for the operating parameters of an integrated circuit chip, the monitoring method comprising the following steps: During the operation of the chip under test, a functional test stimulus that does not affect the main function of the chip under test is applied, and the stimulus response signal generated by the chip under test under the functional test stimulus is collected synchronously. Based on the excitation response signal, the heat distribution information of the chip when the operating temperature changes is determined, and the heat distribution information is used to identify failures, thereby obtaining the thermal fatigue characteristics of the chip under test under uneven heat dissipation. Then, the health sensitivity of the chip under test in the current heat dissipation state is determined by the thermal fatigue characteristics. Acquire the current test signal flowing through the specified path in the chip under test, determine the working state index on the test operation pin based on the current test signal, perform defect fitting between the working state index and the health sensitivity, and obtain the function retention value of the chip under test in the current operating state. Based on the function retention value, the current functional state of the chip under test is monitored and determined, and the determination result is output.

[0006] In this embodiment, determining the heat distribution information of the chip during operating temperature changes based on the excitation response signal specifically includes: Extract the transient thermal response values ​​from each test circuit of the chip from the excitation response signal; Based on the thermal-electric analogy distributed consensus algorithm, all transient thermal response values ​​are synchronized to obtain thermal distribution attributes; The heat distribution information of the chip when the operating temperature changes is generated from the heat distribution attributes.

[0007] In this embodiment, the failure identification is a process used to identify potential failure risks of the chip under test caused by thermal effects and to output circuit logic signals corresponding to abnormal thermal modes.

[0008] In this embodiment, determining the health sensitivity of the chip under test in the current heat dissipation state based on the thermal fatigue characteristics specifically includes: The fatigue risk of the chip under test in the current heat dissipation state is determined based on the thermal fatigue characteristics. The vulnerability index of each test circuit under the current heat dissipation condition is determined by the fatigue risk quantity. Based on a collaborative decision made using all vulnerability indices and the global load state of the chip under test, the health sensitivity of the chip under test in the current heat dissipation state is obtained.

[0009] In this embodiment, the health sensitivity refers to the quantitative value of the degree to which the overall performance status of the chip under test is affected by the current heat dissipation conditions.

[0010] In this embodiment, obtaining the current test signal flowing through a specified path in the chip under test specifically includes: The original current sampling sequence of the specified path is determined based on the excitation load conditions of the chip under test; Each sampling test pin performs a running test on the original current sampling sequence to obtain current tag values ​​for multiple specified paths; The current test signal flowing through the specified path in the chip under test is determined based on all current tag values.

[0011] In this embodiment, determining the operating state index on the test operation pin based on the current test signal specifically includes: The current test signal is decomposed to extract the corresponding current pulse characteristics of each test operation pin; Reconstruct all current pulse characteristics to obtain the state deviation of each test operation pin; By comparing the deviation of each state with the corresponding operating reference value of the test pin, the operating state index of the test operating pin is obtained.

[0012] In this embodiment, the function retention value refers to a quantitative indicator of the current functional integrity of the chip under test.

[0013] In this embodiment, the functional states include normal operation state, performance degradation state, and failure risk state.

[0014] Secondly, this application provides an online monitoring system for operating parameters of an integrated circuit chip, used to execute an online monitoring method for operating parameters of an integrated circuit chip, the monitoring system comprising: The signal acquisition module is used to apply functional test stimuli that do not affect the main function of the chip under test during operation, and to simultaneously acquire the stimulus response signal generated by the chip under test under the functional test stimuli. The failure testing module is used to determine the heat distribution information of the chip when the operating temperature changes based on the excitation response signal, perform failure identification on the heat distribution information, obtain the thermal fatigue characteristics of the chip under test under uneven heat dissipation, and then determine the health sensitivity of the chip under test in the current heat dissipation state based on the thermal fatigue characteristics. The defect identification module is used to acquire the current test signal flowing through the specified path in the chip under test, determine the working state index on the test operation pin based on the current test signal, and perform defect fitting between the working state index and the health sensitivity to obtain the function retention value of the chip under test in the current operating state. The functional testing module is used to monitor and determine the current functional state of the chip under test based on the functional retention value, and output the determination result.

[0015] The technical solutions provided by the embodiments disclosed in this application have the following beneficial effects: During chip-under-test (DUT) operation, functional test stimuli that do not affect the main function of the DUT are applied, and the stimulus response signal generated by the DUT under the functional test stimuli is collected simultaneously. Based on the stimulus response signal, the heat distribution information of the chip under temperature changes is determined, and failure identification is performed on the heat distribution information to obtain the thermal fatigue characteristics of the DUT under uneven heat dissipation. Then, the health sensitivity of the DUT in the current heat dissipation state is determined from the thermal fatigue characteristics. The current test signal flowing through a specified path in the DUT is acquired, and the operating state index on the test operation pin is determined based on the current test signal. The operating state index is then fitted with the health sensitivity to obtain the function retention value of the DUT in the current operating state. Based on the function retention value, the current functional state of the DUT is monitored and judged, and the judgment result is output.

[0016] Therefore, this application demonstrates that online monitoring of chip operating parameters can be achieved without interfering with the main function operation of the chip under test (DUT). Specifically, by applying functional test stimuli that do not affect the main function of the DUT and simultaneously acquiring the stimulus response signal, the limitations of offline testing or interference-based stimulus testing can be overcome. This allows for the acquisition of multi-dimensional data sources containing both electrical and physical characteristics, ensuring consistency between the monitoring data and the chip's actual operating conditions. By determining heat distribution information, identifying thermal fatigue characteristics, and calculating health sensitivity based on the stimulus response signal, the cumulative thermal damage pattern under uneven heat dissipation conditions can be accurately captured, and the health sensitivity of the chip under heat dissipation conditions can be quantified, compensating for the lack of precise thermal characteristic analysis. By acquiring current test signals along a specified path, calculating the operating state index, and performing defect fitting with the health sensitivity, multi-dimensional fusion of chip thermal and electrical characteristics can be achieved. The correlation data of these two types of indicators can be aligned and standardized, generating a function retention value that comprehensively characterizes the chip's functional state. By monitoring and judging the functional state of the DUT based on the function retention value and outputting the results, precise classification of the chip's functional state can be achieved based on quantitative indicators, outputting a judgment report including abnormal indicators, and improving the accuracy of chip operational reliability assessment.

[0017] In summary, the technical solution adopted in this application can perform integrated monitoring of the thermal and electrical characteristics of the chip without interfering with the main function operation of the chip under test, thereby improving the reliability of chip operating status determination. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only for this embodiment of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is an exemplary flowchart of an online monitoring method for operating parameters of an integrated circuit chip according to the present application; Figure 2 This is a flowchart illustrating the determination of thermal fatigue characteristics provided in this application; Figure 3 This is a flowchart illustrating the process for determining the functional retention value provided in this application; Figure 4 This is a module structure diagram of an online monitoring system for operating parameters of an integrated circuit chip, provided in this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0021] This application provides an online monitoring system and method for integrated circuit chip operating parameters. The core of this system involves applying functional test stimuli that do not affect the main function of the chip under test (DUT) during operation, and simultaneously acquiring the stimulus response signal generated by the DUT under the functional test stimuli. Based on the stimulus response signal, the system determines the heat distribution information of the chip when the operating temperature changes. Failure identification is performed on the heat distribution information to obtain the thermal fatigue characteristics of the DUT under uneven heat dissipation. Then, the health sensitivity of the DUT in the current heat dissipation state is determined from the thermal fatigue characteristics. The system acquires the current test signal flowing through a specified path in the DUT, determines the operating state index on the test operation pin based on the current test signal, performs defect fitting between the operating state index and the health sensitivity, and obtains the function retention value of the DUT in the current operating state. Based on the function retention value, the system monitors and judges the current functional state of the DUT and outputs the judgment result.

[0022] Example 1: To better understand the above technical solution, the following will provide a detailed description of the technical solution in conjunction with the accompanying drawings and specific implementation methods. (Refer to...) Figure 1 As shown in the figure, this is an exemplary flowchart of an online monitoring method for operating parameters of an integrated circuit chip according to this embodiment of the present application. The monitoring method includes the following steps: In step S1, a functional test stimulus that does not affect the main function of the chip under test is applied during the operation of the chip under test, and the stimulus response signal generated by the chip under test under the functional test stimulus is collected synchronously.

[0023] In practice, firstly, based on the product manual and main functional logic of the chip under test (DUT), functional test stimuli adapted to the chip type are designed. Redundancy check instructions are designed for the computing chip, and standard link self-test data packets are designed for the communication chip. Multiple rounds of pre-testing verify that the chip's main function output is without deviation after the stimuli are applied. Then, an Agilent 33522B function signal generator is used to generate calibrated excitation signals with amplitude, frequency, and timing parameters, which are then applied to the running DUT. Simultaneously, a FLIR X650sc high-resolution thermal imager is fixed 5-10 cm directly above the chip. The voltage probe of a Tektronix MDO3024 mixed-domain oscilloscope is connected to the chip's key pins, and a Tektronix P6021A current probe is clamped to a specified path of wires. The results are then transmitted via Keysight. The synchronous triggering function of the 34980A data acquisition unit starts all acquisition devices at the same timestamp of the excitation loading, acquires the chip surface temperature signal at a sampling frequency of 50Hz, and acquires the pin voltage and path current signals at a sampling frequency of 10GHz. Finally, the acquired data is classified and stored in the local server according to the format of "timestamp-signal type-value", thus completing the synchronous acquisition of the functional excitation and the excitation response signal. In other embodiments, other methods can also be used to acquire the excitation response signal generated by the chip under test under the functional test excitation, which is not limited here.

[0024] It should be noted that, in this application, the functional test stimulus refers to the signal that stably triggers the monitoring feedback; the stimulus response signal refers to the data information containing electrical and physical characteristics output by the chip under test after receiving the functional test stimulus.

[0025] In step S2, the heat distribution information of the chip when the operating temperature changes is determined based on the excitation response signal. The heat distribution information is used for failure identification to obtain the thermal fatigue characteristics of the chip under test under uneven heat dissipation. Then, the health sensitivity of the chip under test in the current heat dissipation state is determined by the thermal fatigue characteristics.

[0026] In this embodiment, determining the heat distribution information of the chip during operating temperature changes based on the excitation response signal can be achieved through the following steps: Extract the transient thermal response values ​​from each test circuit of the chip from the excitation response signal; Based on the thermal-electric analogy distributed consensus algorithm, all transient thermal response values ​​are synchronized to obtain thermal distribution attributes; The heat distribution information of the chip when the operating temperature changes is generated from the heat distribution attributes.

[0027] In practice, firstly, temperature time-domain signals corresponding to each test circuit of the chip are selected from the synchronously acquired excitation response signals. Environmental interference noise is removed using a moving average method, and the average of five consecutive sampling points is used to replace single-point data. The signal for the entire period from excitation application to temperature steady state is extracted, and the difference between the real-time temperature value and the initial temperature value at each time point is calculated to obtain the transient thermal response value of each test circuit. Then, the transient thermal response value of each test circuit is analogized to the circuit node voltage, and the heat conduction path is analogized to the equivalent resistance, constructing a thermal-electric equivalent network. Each test circuit is set as a consensus node, and its transient thermal response value is input, initiating algorithm iteration: in each round, the difference in response value between the node and its adjacent nodes is calculated, and the node values ​​are linearly adjusted according to the difference ratio until the difference between all nodes is less than a preset threshold of 0.1℃, with no more than 50 iterations. After synchronization, parameters such as the equivalent thermal resistance and temperature change rate of each node are extracted and integrated to form thermal distribution attributes. Finally, the thermal distribution attributes are mapped to the three-dimensional structural model of the chip under test, and the chip area is divided according to the physical location of the test circuit. By substituting the thermal distribution parameters of each region into the heat conduction equation, the model is discretized into a microgrid using the finite volume method. The temperature value of each grid at different time points is iteratively solved. Based on the solution results, temperature distribution cloud maps of the chip surface and interior are plotted, and the temperature gradient and change trend of each region are marked. These are then integrated to form the heat distribution information of the chip when the operating temperature changes.

[0028] It should be noted that, in this application, transient thermal response value refers to the quantitative parameter of the dynamic change of temperature of each test circuit of the chip under test over time; thermal-electric analogy distributed consensus algorithm refers to the algorithm that compares the thermal conduction characteristics of the chip to the electrical characteristics of the circuit and realizes the synchronization of transient thermal response value through multi-node data iterative calibration; thermal distribution attribute refers to the set of correlation laws of thermal characteristics of each test circuit of the chip; heat distribution information refers to the information of temperature values, temperature gradients and changing trends of each region inside and on the surface of the chip under test during the process of temperature change.

[0029] Preferably, in this embodiment, the heat distribution information is used for failure identification to obtain the thermal fatigue characteristics of the chip under test under uneven heat dissipation, with reference to... Figure 2 As shown in the figure, this is a schematic flowchart of determining thermal fatigue characteristics in some embodiments of this application. In this embodiment, determining thermal fatigue characteristics can be achieved by the following steps: In step S21, the temperature change evolution conditions of the chip's internal temperature are constructed based on the heat distribution information; In step S22, dynamic failure indicators are extracted from each test circuit from all temperature change evolution conditions; In step S23, all dynamic failure indicators are compared with preset thermal-electric coupling parameters to obtain the circuit logic signals of the chip under test in abnormal thermal mode. In step S24, the thermal fatigue characteristics of the chip under test under uneven heat dissipation are determined based on the circuit logic signal.

[0030] In practice, firstly, temperature values ​​and temperature gradient data of each test circuit at different time points are extracted from the generated heat distribution information, dividing the chip operation process into three stages: heating, steady state, and cooling. Combining the heat conduction equation, constraints are set for the rate of temperature change and the temperature difference between adjacent circuits in each stage, constructing the temperature evolution conditions within the chip. Next, based on the temperature evolution conditions, the peak temperature of hotspots and the amplitude of temperature changes during the temperature cycling process of each test circuit are screened. The effective temperature cycle count for each test circuit is counted using the rainflow counting method, which achieves accurate counting of cycle counts by sequentially pairing the peak and trough values ​​of the temperature-time curve. Combining the thermal fatigue threshold of the chip material, the duration of hotspot temperature exceeding the limit and the cumulative value of temperature cycle damage for each test circuit are calculated. Integrating these three parameters yields a dynamic failure index that quantifies the failure risk of each test circuit, i.e., the dynamic failure index for each test circuit. Then, 200 normal chips of the same model are collected, and the average dynamic failure index of each test circuit is obtained under standard operating conditions. Combined with the chip's electrical parameters, a thermal-electric coupling parameter library is constructed. The dynamic failure indicators of each test circuit of the chip under test (DUT) are compared one by one with the corresponding parameters in the parameter library, with a deviation threshold set at 1.5 times the normal parameter fluctuation range. If an indicator exceeds the threshold, it is marked as an abnormal state. The normal and abnormal states of all test circuits are encoded according to their circuit locations and converted into circuit logic signals that reflect the circuit operation status under abnormal thermal conditions. These circuit logic signals are used as the circuit logic signals of the DUT under abnormal thermal conditions. Finally, the test circuit location and abnormality level data corresponding to the abnormal state are extracted from the circuit logic signals, combined with the chip material characteristics and packaging structure parameters at that circuit location. The finite element method is used to simulate the thermal stress distribution in this area under abnormal thermal conditions, and the thermal deformation and thermal stress accumulation are calculated. At the same time, the number of temperature cycle damages in this area is counted. The three parameters of thermal deformation, thermal stress accumulation, and temperature cycle damages are integrated to form a thermal fatigue characteristic that can comprehensively characterize the degree of thermal damage to the chip, i.e., the thermal fatigue characteristic of the DUT under uneven heat dissipation.

[0031] It should be noted that, in this application, failure identification is the process of identifying potential failure risks of the chip under test (DUT) due to thermal effects and outputting circuit logic signals corresponding to abnormal thermal modes; temperature evolution conditions refer to the set of constraint parameters governing the dynamic change of the internal temperature of the DUT over time; dynamic failure indices refer to parameters that quantify the failure risk of each test circuit under temperature changes; thermo-electric coupling parameters refer to the benchmark parameters that correlate the thermal and electrical characteristics of the chip; abnormal thermal modes refer to the thermal state of the DUT where the local hot spot temperature exceeds the standard, the cumulative value of temperature cycle damage is too high, and the temperature gradient is abnormal; circuit logic signals refer to the signals indicating the operating state of the chip circuit under abnormal thermal modes; uneven heat dissipation state refers to the operating state where there are significant differences in the heat dissipation rate and temperature distribution of different areas inside and on the surface of the DUT during operation, resulting in the accumulation of heat in local areas to form hot spots and the temperature gradient between areas exceeding the normal range; thermal fatigue characteristics refer to the set of indices representing the degree of thermal damage accumulation of the DUT under uneven heat dissipation states.

[0032] In this embodiment, determining the health sensitivity of the chip under test in the current heat dissipation state based on the thermal fatigue characteristics can be achieved through the following steps: The fatigue risk of the chip under test in the current heat dissipation state is determined based on the thermal fatigue characteristics. The vulnerability index of each test circuit under the current heat dissipation condition is determined by the fatigue risk quantity. Based on a collaborative decision made using all vulnerability indices and the global load state of the chip under test, the health sensitivity of the chip under test in the current heat dissipation state is obtained.

[0033] In specific implementation, firstly, three core parameters are extracted from the thermal fatigue characteristics: thermal deformation, cumulative thermal stress, and number of temperature cycle damage cycles. The weights of each parameter are determined using the analytic hierarchy process (AHP). This determination can be achieved by: conducting simulations using 10 sets of analog experiments, using the average of the simulation results as the weight of each parameter, constructing a judgment matrix, calculating the eigenvector corresponding to the largest eigenvalue, and normalizing the result to obtain the weight. Each parameter value is then multiplied by its weight and summed, and the sum is used as the fatigue risk of the chip under test in its current heat dissipation state. Next, the functional importance levels of the test circuits are classified: core computing circuits are level one, interface circuits are level two, and auxiliary circuits are level three, with corresponding weights set to 0.6, 0.3, and 0.1, respectively (the weights can be determined by scoring the results of multiple sets of experiments; this is not limited here). A linear regression model is constructed, using the fatigue risk as the input variable and the manually calibrated circuit vulnerability level (levels 1-5, with higher values ​​indicating greater vulnerability) as the output variable. The model is trained using measured data from 100 sets of chips to determine the model coefficients. The fatigue risk of each test circuit is substituted into the trained model, and the normalized output value is used as the vulnerability index of each test circuit under the current heat dissipation state. Finally, a fuzzy comprehensive evaluation model is constructed, using the vulnerability index of each test circuit as the evaluation factor set. The global load state is divided into three levels: low load, medium load, and high load, and weights are assigned. The higher the load, the greater the weight of the impact of heat dissipation on the chip. The membership function of each factor is determined, and the vulnerability index and load state parameters are substituted into the function to calculate the membership degree. Then, the comprehensive membership degree is calculated using the weighted average method. The comprehensive membership degree is mapped to a normalized value in the 0-1 interval, and this normalized value is used as the health sensitivity of the chip under test under the current heat dissipation state.

[0034] It should be noted that, in this application, fatigue risk refers to the numerical value of the risk of functional failure of each test circuit of the chip under test due to thermal damage; vulnerability index refers to the quantitative indicator of the degree to which the functional stability of each test circuit is affected by the current heat dissipation state; global load state refers to the parameter set of the overall operating load of the chip under test, including the current computing power, power consumption ratio and resource utilization rate of the chip under test; collaborative decision refers to the process of determining the change in health sensitivity after the overall performance of the chip under test is affected by the current heat dissipation state; health sensitivity refers to the quantitative value of the degree to which the overall performance state of the chip under test is affected by the current heat dissipation conditions.

[0035] In step S3, the current test signal flowing through the specified path in the chip under test is acquired, the working state index on the test operation pin is determined based on the current test signal, and the working state index is fitted with the health sensitivity to obtain the function retention value of the chip under test in the current operating state.

[0036] In this embodiment, obtaining the current test signal flowing through a specified path in the chip under test can be achieved using the following steps: The original current sampling sequence of the specified path is determined based on the excitation load conditions of the chip under test; Each sampling test pin performs a running test on the original current sampling sequence to obtain current tag values ​​for multiple specified paths; The current test signal flowing through the specified path in the chip under test is determined based on all current tag values.

[0037] In practice, the process begins by extracting the computational load and power consumption percentages from the excitation load conditions, and then defining the path location and current transfer characteristics based on the chip's datasheet. A current probe is clamped to the wires along the specified path, and connected to an oscilloscope. The oscilloscope's sampling frequency is set to 10 times the signal frequency to ensure compliance with the Nyquist sampling theorem. The acquisition device is then activated to collect current data throughout the entire period of functional test excitation applied to the chip, forming a raw current sampling sequence. Next, a one-to-one correspondence is established between each sampling test pin and its corresponding raw current sampling sequence, and the sequence is analyzed by the pin's built-in detection module. First, the three core parameters of the sequence—effective current value, fluctuation coefficient, and peak value—are calculated. Then, the parameter benchmark values ​​of a normal chip of the same model under standard operating conditions are retrieved, and the measured parameters are compared with the benchmark values. Based on the comparison results, each sequence is labeled with a feature tag, including an effective value tag, a stability tag, and a peak value tag. The quantized values ​​of these three tags are integrated to form the current tag value for the specified path. Finally, all current tag values ​​are categorized and archived according to the prescribed path numbers, and tag value validity judgment rules are set: valid tags are those whose valid values ​​are within ±10% of the reference value and whose fluctuation coefficient is less than a preset threshold. All valid tag values ​​are filtered out, and the corresponding original current sampling sequence segments are extracted and sorted and spliced ​​according to timestamps. Linear interpolation is used to complete the missing sampling points in the spliced ​​data sequence to ensure data continuity. The completed sequence is imported into the signal standardization module and converted into an amplitude-normalized time-domain signal. This time-domain signal is used as the current test signal flowing through the prescribed path in the chip under test.

[0038] It should be noted that, in this application, the excitation load condition refers to the set of operating load parameters of the chip under test when a functional test excitation is applied; the raw current sampling sequence refers to the unprocessed current time-domain data sequence collected from the specified path of the chip under test under the excitation load condition; the sampling test operation pin refers to the dedicated pin deployed on the specified path of the chip under test for collecting and detecting current data; operation detection refers to the analysis process of comparing the effective value, fluctuation coefficient, and peak value of the current with the parameter reference values ​​under the standard operating conditions of a normal chip of the same model, and generating current tag values ​​for marking current characteristic attributes; the current tag value refers to the quantitative parameter generated by the sampling test operation pin after detecting the raw current sampling sequence, marking the current characteristic attributes; and the current test signal refers to the standardized signal reflecting the current operating characteristics of the specified path.

[0039] In this embodiment, determining the operating state index on the test operation pin based on the current test signal can be achieved using the following steps: The current test signal is decomposed to extract the corresponding current pulse characteristics of each test operation pin; Reconstruct all current pulse characteristics to obtain the state deviation of each test operation pin; By comparing the deviation of each state with the corresponding operating reference value of the test pin, the operating state index of the test operating pin is obtained.

[0040] In practical implementation, firstly, the current test signal can be decomposed into five levels of detail components and one level of approximation components using the db4 wavelet basis function. The detail components corresponding to high-frequency noise are discarded, and the effective components are retained for reconstruction. From the reconstructed signal, the current pulse features corresponding to each test pin are extracted, including four core parameters: pulse amplitude, rise time, fall time, and pulse width. Then, a backpropagation neural network model is constructed, using the extracted current pulse features as the model's input layer parameters. The number of input layer nodes is set to 4, the number of hidden layer nodes to 10, and the number of output layer nodes to 1. 200 sets of chip sample data are collected to train the model, including 100 sets of pulse features from normal chips and 100 sets from faulty chips. The mean of the normal chip features is set as the model's output target value. The model weights and biases are iteratively optimized using gradient descent until the model's prediction error is less than a preset threshold. The pulse features of the chip under test are input into the trained model, and the absolute value of the difference between the output value and the target value represents the state deviation of each test pin. Finally, 200 normal chips of the same model can be selected, and the state deviation of each pin can be tested under standard excitation load conditions. The mean and standard deviation are calculated, and the mean plus three times the standard deviation is set as the operating reference value for that pin. The state deviation of each tested operating pin of the chip under test is compared with the corresponding operating reference value, and the operating state index is calculated using the formula: Operating State Index = 1 - (State Deviation / Operating Reference Value). The calculation result is normalized to the range of 0-1, and the closer the value is to 1, the more stable the pin's operating state.

[0041] It should be noted that, in this application, current pulse characteristics refer to the set of current signal waveform characteristics on the test operation pin of the chip under test; state deviation refers to a numerical value that quantitatively reflects the degree of difference between the actual current state of the test operation pin and the normal reference state; operating reference quantity refers to the reference value of the state deviation of the test operation pin under standard operating conditions; and operating state index refers to a quantitative index of the electrical operating stability of the test operation pin.

[0042] Preferably, in this embodiment, the working state index and the health sensitivity are fitted together to obtain the function retention value of the chip under test in the current operating state, with reference to... Figure 3 As shown in the figure, this is a flowchart illustrating the process of determining the function retention value in some embodiments of this application. In this embodiment, the function retention value can be determined by the following steps: In step S31, the working state index and the health sensitivity are fused to obtain the defect update signal on different defect propagation paths in the chip under test; In step S32, all defect update signals are fitted with preset operational failure features in the chip under test to obtain defect persistence information of the chip under test in the current operating state. In step S33, the functional loss of the chip under test during operation is determined based on the defect persistence information; In step S34, the function retention value of the chip under test in the current operating state is determined based on the function loss degree.

[0043] In practice, firstly, based on the defect propagation paths of the chip under test, it is divided into two categories: electrical failure propagation paths and thermal failure propagation paths. The weights of the two paths are determined using the analytic hierarchy process (AHP). The importance of the operating status index and health sensitivity is scored based on multiple rounds of laboratory simulation tests, and a judgment matrix is ​​constructed to calculate the eigenvectors. After normalization, the weights are obtained. The operating status index is multiplied by the weight of the electrical failure path, and the health sensitivity is multiplied by the weight of the thermal failure path. The product results are then integrated according to the path classification to generate defect update signals for different defect propagation paths in the chip under test. Next, a failure feature library is constructed, collecting test data from 200 chips of the same model, including 100 normal chips and 100 faulty chips. Feature parameters of electrical failure (excessive current fluctuation) and thermal failure (excessive hotspot temperature) are extracted as preset failure features. The least squares method is used to fit the defect update signals to the failure features, with the objective function being the minimum sum of squared residuals. The fitting coefficients are iteratively calculated until the residuals are less than a preset threshold. The parameters obtained from the fitting, such as defect development rate and defect impact range, are integrated and used as the defect persistence information of the chip under test in its current operating state. Next, a correlation model between defect persistence information and functional loss is constructed. 150 chip samples at different defect development stages are selected, with the defect development rate and impact range from the defect persistence information used as input variables, and the manually calibrated functional loss (0-1 interval, 0 for no loss, 1 for complete failure) used as the output variable. The model is trained using a support vector regression algorithm, with a radial basis function kernel function selected. The penalty parameters and kernel function parameters are optimized using a grid search method until the model prediction error is less than a preset value. The defect persistence information of the chip under test is input into the trained model, and the normalized output value is used as the functional loss of the chip under test during operation. Finally, the calculation model for the functional retention value is determined, which can be achieved using the linear transformation formula: Functional retention value = 1 - Functional loss. 100 chip samples in different functional states are collected, and their functional loss and corresponding functional retention values ​​are calculated to verify the effectiveness of the formula. Substituting the functional loss into the formula yields the initial functional retention value. The initial value is then calibrated using the min-max normalization method. Based on the maximum and minimum values ​​of the function retention values ​​of 100 samples, the initial value is mapped to the 0-1 range to ensure that the value can intuitively reflect the functional status of the chip, that is, to obtain the function retention value of the chip under test in the current operating state.

[0044] It should be noted that, in this application, the defect update signal refers to the quantitative signal of the degree of damage on different defect propagation paths of the chip under test; the operational failure characteristics refer to the set of benchmark characteristics that are preset based on the actual test data of the same model of chip and cover electrical failure and thermal failure modes; the defect persistence information refers to the set of parameters that show the change of the defect trend of the chip under test over time; the functional loss degree refers to the value of the degree of functional attenuation of the chip under test compared with the normal state, with a value range of 0-1, and the larger the value, the more severe the functional attenuation; the functional retention value refers to the quantitative index of the current functional integrity of the chip under test.

[0045] In step S4, the current functional state of the chip under test is monitored and determined according to the function retention value, and the determination result is output.

[0046] In practice, the first step is to construct a functional retention value judgment benchmark library, collecting functional retention value sample data for 100 normally operating chips, 80 performance-degraded chips, and 50 failure-risk chips. A threshold interval judgment method can be used: calculate the minimum functional retention value for normally operating chips and the minimum for degraded chips in the sample data, and divide the data into threshold intervals: ≥0.8 indicates normal operation, 0.5≤value<0.8 indicates performance degradation, and value<0.5 indicates failure risk. Substitute the functional retention value of the chip under test into the threshold interval for comparison. After determining the corresponding state, extract abnormal indicators of the chip's thermal and electrical characteristics, and generate a judgment report containing the state level, the specific value of the functional retention value, the location of the abnormality, and maintenance recommendations. Alternatively, a fuzzy comprehensive judgment method can be used: the function retention value is used as the evaluation factor set, the three types of functional states are used as the evaluation comment set, a membership function is constructed based on the sample data, the membership degree of the function retention value of the chip under test corresponding to each type of state is calculated, the state corresponding to the maximum membership degree is selected as the preliminary judgment result, and the judgment result is corrected by combining the changing trend of the chip's three most recent historical monitoring data, and a judgment report with confidence is output, such as "performance degradation state (confidence 87%)". In other embodiments, other methods can also be used to monitor and judge the chip under test, which will not be elaborated here.

[0047] It should be noted that, in this application, the functional state refers to the classification of the current functional integrity and operational reliability of the chip under test, including normal operation state, performance degradation state, and failure risk state.

[0048] Therefore, this application demonstrates that online monitoring of chip operating parameters can be achieved without interfering with the main function operation of the chip under test (DUT). Specifically, by applying functional test stimuli that do not affect the main function of the DUT and simultaneously acquiring the stimulus response signal, the limitations of offline testing or interference-based stimulus testing can be overcome. This allows for the acquisition of multi-dimensional data sources containing both electrical and physical characteristics, ensuring consistency between the monitoring data and the chip's actual operating conditions. By determining heat distribution information, identifying thermal fatigue characteristics, and calculating health sensitivity based on the stimulus response signal, the cumulative thermal damage pattern under uneven heat dissipation conditions can be accurately captured, and the health sensitivity of the chip under heat dissipation conditions can be quantified, compensating for the lack of precise thermal characteristic analysis. By acquiring current test signals along a specified path, calculating the operating state index, and performing defect fitting with the health sensitivity, multi-dimensional fusion of chip thermal and electrical characteristics can be achieved. The correlation data of these two types of indicators can be aligned and standardized, generating a function retention value that comprehensively characterizes the chip's functional state. By monitoring and judging the functional state of the DUT based on the function retention value and outputting the results, precise classification of the chip's functional state can be achieved based on quantitative indicators, outputting a judgment report including abnormal indicators, and improving the accuracy of chip operational reliability assessment.

[0049] In summary, the technical solution adopted in this application can perform integrated monitoring of the thermal and electrical characteristics of the chip without interfering with the main function operation of the chip under test, thereby improving the reliability of chip operating status determination.

[0050] Example 2: This application provides an online monitoring system for the operating parameters of an integrated circuit chip, referring to... Figure 4 As shown in the figure, this is a module structure diagram of an online monitoring system for operating parameters of an integrated circuit chip according to this embodiment of the present application. The monitoring system includes: The signal acquisition module 100 is used to apply functional test stimuli that do not affect the main function of the chip under test during operation, and to synchronously acquire the stimulus response signal generated by the chip under test under the functional test stimuli. The failure test module 200 is used to determine the heat distribution information of the chip when the operating temperature changes based on the excitation response signal, perform failure identification on the heat distribution information, obtain the thermal fatigue characteristics of the chip under test under uneven heat dissipation, and then determine the health sensitivity of the chip under test under the current heat dissipation state based on the thermal fatigue characteristics. The defect identification module 300 is used to acquire the current test signal flowing through the specified path in the chip under test, determine the working state index on the test operation pin according to the current test signal, and perform defect fitting between the working state index and the health sensitivity to obtain the function retention value of the chip under test in the current operating state. The functional test module 400 is used to monitor and determine the current functional state of the chip under test based on the functional retention value, and output the determination result.

[0051] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0052] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, including read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically-Erasable Programmable Read-Only Memory (EEPROM), compactdisc read-only memory (CD-ROM) or other optical disc storage, disk storage, magnetic tape storage, or any other computer-readable medium capable of carrying or storing data.

[0053] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

Claims

1. A method for online monitoring of operating parameters of an integrated circuit chip, characterized in that, The monitoring method includes the following steps: During the operation of the chip under test, a functional test stimulus that does not affect the main function of the chip under test is applied, and the stimulus response signal generated by the chip under test under the functional test stimulus is collected synchronously. Based on the excitation response signal, the heat distribution information of the chip when the operating temperature changes is determined, and the heat distribution information is used to identify failures, thereby obtaining the thermal fatigue characteristics of the chip under test under uneven heat dissipation. Then, the health sensitivity of the chip under test in the current heat dissipation state is determined by the thermal fatigue characteristics. Acquire the current test signal flowing through the specified path in the chip under test, determine the working state index on the test operation pin based on the current test signal, perform defect fitting between the working state index and the health sensitivity, and obtain the function retention value of the chip under test in the current operating state. Based on the function retention value, the current functional state of the chip under test is monitored and determined, and the determination result is output.

2. The method for online monitoring of operating parameters of an integrated circuit chip as described in claim 1, characterized in that, Determining the heat distribution information of the chip under changing operating temperature based on the excitation response signal specifically includes: Extract the transient thermal response values ​​from each test circuit of the chip from the excitation response signal; Based on the thermal-electric analogy distributed consensus algorithm, all transient thermal response values ​​are synchronized to obtain thermal distribution attributes; The heat distribution information of the chip when the operating temperature changes is generated from the heat distribution attributes.

3. The method for online monitoring of operating parameters of an integrated circuit chip as described in claim 1, characterized in that, The aforementioned failure identification is a process used to identify potential failure risks of the chip under test caused by thermal effects and to output circuit logic signals corresponding to abnormal thermal modes.

4. The method for online monitoring of operating parameters of an integrated circuit chip as described in claim 1, characterized in that, Determining the health sensitivity of the chip under test in the current heat dissipation state based on the aforementioned thermal fatigue characteristics specifically includes: The fatigue risk of the chip under test in the current heat dissipation state is determined based on the thermal fatigue characteristics. The vulnerability index of each test circuit under the current heat dissipation condition is determined by the fatigue risk quantity. Based on a collaborative decision made using all vulnerability indices and the global load state of the chip under test, the health sensitivity of the chip under test in the current heat dissipation state is obtained.

5. The method for online monitoring of operating parameters of an integrated circuit chip as described in claim 1, characterized in that, The health sensitivity refers to the quantitative value of the degree to which the overall performance of the chip under test is affected by the current heat dissipation conditions.

6. The method for online monitoring of operating parameters of an integrated circuit chip as described in claim 1, characterized in that, Obtaining the current test signal flowing through a specified path in the chip under test specifically includes: The original current sampling sequence of the specified path is determined based on the excitation load conditions of the chip under test; Each sampling test pin performs a running test on the original current sampling sequence to obtain current tag values ​​for multiple specified paths; The current test signal flowing through the specified path in the chip under test is determined based on all current tag values.

7. The method for online monitoring of operating parameters of an integrated circuit chip as described in claim 1, characterized in that, Determining the operating status index on the test operation pin based on the current test signal specifically includes: The current test signal is decomposed to extract the corresponding current pulse characteristics of each test operation pin; Reconstruct all current pulse characteristics to obtain the state deviation of each test operation pin; By comparing the deviation of each state with the corresponding operating reference value of the test pin, the operating state index of the test operating pin is obtained.

8. The method for online monitoring of operating parameters of an integrated circuit chip as described in claim 1, characterized in that, The aforementioned functional retention value refers to a quantitative indicator of the current functional integrity of the chip under test.

9. The method for online monitoring of operating parameters of an integrated circuit chip as described in claim 1, characterized in that, The functional states include normal operation state, performance degradation state, and failure risk state.

10. An online monitoring system for operating parameters of an integrated circuit chip, used to execute the online monitoring method for operating parameters of an integrated circuit chip as described in any one of claims 1 to 9, characterized in that, The monitoring system includes: The signal acquisition module is used to apply functional test stimuli that do not affect the main function of the chip under test during operation, and to simultaneously acquire the stimulus response signal generated by the chip under test under the functional test stimuli. The failure testing module is used to determine the heat distribution information of the chip when the operating temperature changes based on the excitation response signal, perform failure identification on the heat distribution information, obtain the thermal fatigue characteristics of the chip under test under uneven heat dissipation, and then determine the health sensitivity of the chip under test in the current heat dissipation state based on the thermal fatigue characteristics. The defect identification module is used to acquire the current test signal flowing through the specified path in the chip under test, determine the working state index on the test operation pin based on the current test signal, and perform defect fitting between the working state index and the health sensitivity to obtain the function retention value of the chip under test in the current operating state. The functional testing module is used to monitor and determine the current functional state of the chip under test based on the functional retention value, and output the determination result.

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