Ranging radar device based on ultra-wideband analyzable chaotic synchronization

Abstract

The invention provides a range radar device based on ultra-wideband resolvable chaotic synchronization, which relates to the technical field of radar range finding and comprises a first ultra-wideband resolvable chaotic signal generation circuit unit, a second digital excitation circuit unit, a third ultra-wideband resolvable chaotic signal synchronization circuit unit and a fourth wideband related receiving circuit unit. According to the invention, the problem of radar real-time ranging with high resolution and high measurement signal-to-noise ratio is solved, high-resolution real-time correlation ranging is realized through the generation circuit and the receiving circuit of the ultra-wideband analyzable chaotic signal, correlation receiving is completed only by simulating a matched filter, and high-sampling-rate data pressure and large correlation calculation amount are avoided. In addition, a receiving end can analyze synchronization of chaotic signals through driving of a digital excitation circuit, and chaotic echo signals are accurately reconstructed to improve the signal-to-noise ratio of distance measurement.

Description

Technical Field

[0001] This invention relates to the field of radar ranging technology, and in particular to a high-resolution, high-signal-to-noise-ratio real-time ranging device, specifically a ranging radar device based on ultra-wideband resolvable chaotic synchronization. Background Technology

[0002] Radar ranging is a key technology for acquiring one-dimensional distance information of targets. This one-dimensional distance information is not only basic spatial data, but also a crucial foundation for applications such as target localization and tracking, two-dimensional / three-dimensional imaging, life detection, and behavior perception. Therefore, radar ranging technology holds an indispensable and important position in numerous ranging systems.

[0003] Existing radar devices are categorized by signal type into linear frequency modulated (LFM) continuous wave (CFW) radar, stepped-frequency (PMC) continuous wave (CFW) radar, ultra-wideband (UWB) pulse radar, and random signal radar. LFM / PMC CFW radar achieves ranging by calculating the difference in phase or frequency; UWB pulse radar calculates target distance using ultra-narrow pulse flight time. However, the unambiguous detection performance of LFM / PMC CFW radar is limited by its high range sidelobes. UWB pulse radar requires high pulse energy for long-range detection and narrow pulse width for high-resolution detection, but generating high-energy, extremely narrow pulses is relatively difficult, requiring a trade-off between detection range and resolution. Furthermore, the above three types of radar are susceptible to external electromagnetic interference, resulting in limited anti-interference capabilities. Random signal radar, represented by chaotic radar, obtains the distance information between the target and the radar by performing correlation processing on the reference signal and the echo signal. Chaotic signals, due to their wide bandwidth, low autocorrelation sidelobes, and large time-bandwidth product, endow radar with high range resolution, strong anti-jamming capabilities, and electronic countermeasures capabilities, and are widely used in through-wall imaging, life detection, underground target identification, and human behavior perception. However, traditional chaotic radar requires high-speed sampling of broadband signals before performing related calculations, resulting in difficulties in real-time processing, heavy computational burden, and large storage resource consumption, which limits the scan rate and real-time performance of chaotic radar.

[0004] Analytical chaos is a hybrid system involving second-order differential equations and discrete switching conditions. Its analytical solution can be written as a linear convolution of a binary discrete sequence and fixed basis functions, allowing correlation reception to be achieved through a simple analog matched filter without digital sampling or signal processing. The first proposed analytical chaotic oscillator was based on an -RLC oscillator circuit. Subsequently, an alternative solution using a common-base Colpitts oscillator was implemented. Recently, a method to compensate for the propagation delay defect of analytical chaotic oscillators based on -RLC oscillators has also been proposed. Both methods effectively increase the fundamental frequency of the analytical chaotic signal, thereby improving the ranging accuracy of analytical chaotic radar. Furthermore, based on the synchronization characteristics of the analytical chaotic signal, accurate reconstruction of the echo signal can be achieved, effectively improving the signal-to-noise ratio of correlation ranging.

[0005] In summary, researching a ranging radar based on ultra-wideband resolvable chaotic synchronization has significant practical implications, as it can achieve real-time ranging with high range resolution and high measurement signal-to-noise ratio. Summary of the Invention

[0006] This invention addresses the problems of traditional chaotic radar, which requires high-speed sampling of broadband signals before correlation calculations, leading to difficulties in real-time processing, heavy computational burden, and high storage resource consumption. It provides a ranging radar device based on ultra-wideband resolvable chaotic synchronization, achieving high-resolution, high-signal-to-noise ratio real-time ranging. High-resolution real-time correlation ranging is achieved through ultra-wideband resolvable chaotic signal generation and receiving circuits, requiring only an analog matched filter for correlation reception, thus avoiding the pressure of high sampling rate data and large correlation calculations. Furthermore, synchronization of the resolvable chaotic signal at the receiving end is achieved through a digital excitation circuit, accurately reconstructing the chaotic echo signal to improve the ranging signal-to-noise ratio.

[0007] The above-mentioned technical objective of the present invention is achieved through the following technical solution:

[0008] A ranging radar device based on ultra-wideband resolvable chaotic synchronization includes a first unit ultra-wideband resolvable chaotic signal generation circuit, a second unit digital excitation circuit, a third unit ultra-wideband resolvable chaotic signal synchronization circuit, and a fourth unit wideband correlation receiving circuit; the ultra-wideband resolvable chaotic signal generation circuit is used to generate the transmitted signal V. P (t), an ultra-wideband resolvable chaotic signal synchronization circuit is used to receive the echo signal V formed by the reflection of the target after the transmitted signal propagates through the medium. E(t), the digital excitation circuit is used to generate physical random codes and send them to the ultra-wideband resolvable chaotic signal generation circuit and the ultra-wideband resolvable chaotic signal synchronization circuit. The broadband correlation receiving circuit receives the signals output by the ultra-wideband resolvable chaotic signal generation circuit and the ultra-wideband resolvable chaotic signal synchronization circuit to measure the time delay and realize the ranging.

[0009] The first ultra-wideband resolvable chaotic signal generation circuit unit includes a two-stage improved Colpitts oscillator circuit, comparator 1, D flip-flop, differentiator circuit, zero-crossing detector, switching compensation circuit, and gain adjustment forcing function.

[0010] Wherein: the second-stage improved Colpitts oscillator circuit includes the base power supply voltage V of transistor Q1. bb V bb The output terminal is connected to the first resistor R1; the other end of the first resistor R1 is connected to the base of transistor Q1; the collector power supply voltage of transistor Q1 is V. cc V cc The output terminal is connected to the second resistor R2; the other end of the second resistor R2 is connected to the collector of transistor Q1, one end of the first capacitor C1, and one end of the ninth resistor R9. A fourth capacitor C4 is also connected between the collector and base of transistor Q1; the other end of the first capacitor C1 is connected to the emitter of transistor Q1 and one end of the second capacitor C2; the emitter of transistor Q1 is connected to the collector of transistor Q2, and a fifth capacitor C5 is also connected between the collector and base of transistor Q2; the other end of the second capacitor C2 is connected to the emitter of transistor Q2 and one end of the third capacitor C3; the emitter of transistor Q2 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the emitter power supply voltage V of transistor Q2. ee The other end of C3 is connected to ground; the base of transistor Q2 is connected to one end of inductor L, the other end of inductor L is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to ground. The common connection of the second resistor R2, the first capacitor C1, and the ninth resistor R9 is the ultra-wideband resolvable chaotic signal V. P (t) Output terminal.

[0011] The common terminal of the second resistor R2, the first capacitor C1, and the ninth resistor R9 is connected to the positive input terminal of comparator 1, the inverting input terminal of comparator 1 is connected to ground, and the output terminal of comparator 1 is connected to the signal input terminal D of the D flip-flop.

[0012] The differentiating circuit includes a ninth resistor R9, the other end of which is connected to a sixth capacitor C6; the other end of the sixth capacitor C6 is connected to the inverting input of operational amplifier 4 and one end of a tenth resistor R10; the non-inverting input of operational amplifier 4 is connected to ground, and the output of operational amplifier 4 is connected to the tenth resistor R10. 10The other end.

[0013] The zero-crossing detector includes comparator 2, the output of operational amplifier 4 is connected to the inverting input of comparator 2 and the non-inverting input of comparator 3, the non-inverting input of comparator 2 is connected to ground, and the output of comparator 2 is connected to input 1 of NOR gate; the inverting input of comparator 3 is connected to ground, and the output of comparator 3 is connected to input 2 of NOR gate; the output of NOR gate is connected to the clock input CLK of D flip-flop.

[0014] The switching compensation circuit includes operational amplifier 1. The positive input terminal of operational amplifier 1 is connected to one end of the ninth resistor R9, the inverting input terminal of operational amplifier 1 is connected to the output terminal of operational amplifier 1, and the output terminal of operational amplifier 1 is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is connected to the inverting input terminal of operational amplifier 3. The output terminal of operational amplifier 3 is connected to the inverting input terminal of operational amplifier 3 and one end of the eighth resistor R8. The other end of the eighth resistor R8 is connected to ground, and the middle tap of the eighth resistor R8 is connected to the output terminal of the NOR gate. The positive input terminal of operational amplifier 2 is connected to the positive input terminal of operational amplifier 1, the inverting input terminal of operational amplifier 2 is connected to the output terminal of operational amplifier 2, and the output terminal of operational amplifier 2 is connected to one end of the sixth resistor R6. The other end of the sixth resistor R6 is connected to one end of the seventh resistor R7 and the positive input terminal of operational amplifier 3, and the other end of the seventh resistor R7 is connected to ground.

[0015] The gain adjustment forcing function includes operational amplifier 5, the output of which is connected to the positive input of operational amplifier 2 and the eleventh resistor R. 11 Eleventh resistor R 11 The other end is connected to the inverting input of op-amp 5, and the non-inverting input of op-amp 5 is connected through the twelfth resistor R. 12 Connect to the output Q terminal of the D flip-flop.

[0016] The second digital excitation circuit unit includes an autonomous Boolean network and a D flip-flop 1. The autonomous Boolean network includes six XOR gates U1-U6 with three-input three-output functions and one XOR NOT gate U7 with three-input three-output functions. The output terminal 1 of U1 is connected to the input terminal 1 of U2, the output terminal 1 of U2 is connected to the input terminal 1 of U3, the output terminal 1 of U3 is connected to the input terminal 1 of U4, the output terminal 1 of U4 is connected to the input terminal 1 of U5, the output terminal 1 of U5 is connected to the input terminal 1 of U6, the output terminal 1 of U6 is connected to the input terminal 1 of U7, and the output terminal 1 of U7 is connected to the input terminal 1 of U1. The output terminal 2 of U1 is connected to the input terminal 2 of U7, the output terminal 2 of U7 is connected to the input terminal 2 of U6, the output terminal 2 of U6 is connected to the input terminal 2 of U5, the output terminal 2 of U5 is connected to the input terminal 2 of U4, and the output terminal 2 of U4 is connected to the input terminal 2 of U3. Terminal 2 of U3 is connected to input terminal 2 of U2, and output terminal 2 of U2 is connected to input terminal 2 of U1; output terminal 3 of U1 is connected to input terminal 3 of U6, output terminal 3 of U2 is connected to input terminal 3 of U7, output terminal 3 of U3 is connected to input terminal 3 of U1, output terminal 3 of U4 is connected to input terminal 3 of U2, output terminal 3 of U5 is connected to input terminal 3 of U3, output terminal 3 of U6 is connected to input terminal 3 of U4, and output terminal 3 of U7 is connected to input terminal 3 of U5; output terminal 3 of U7 outputs a Boolean chaotic signal connected to the signal input D terminal of D flip-flop 1, and the clock signal connected to the clock input CLK terminal of D flip-flop 1; output terminal Q of D flip-flop 1 outputs a physical random code V. rand (t) Simultaneously connected to the transmit signal output V of the first ultra-wideband resolvable chaotic signal generation circuit unit P (t) End and the echo signal reception of the third ultra-wideband resolvable chaotic signal synchronization circuit unit V E (t) end.

[0017] The third ultra-wideband resolvable chaotic signal synchronization circuit unit includes a two-stage improved Colpitts oscillator circuit, comparator 1, D flip-flop, differentiator circuit, zero-crossing detector, switching compensation circuit, and gain adjustment forcing function.

[0018] Wherein: the second-stage improved Colpitts oscillator circuit includes the base power supply voltage V of transistor Q1. bb V bb The output terminal is connected to the first resistor R1; the other end of the first resistor R1 is connected to the base of transistor Q1; the collector power supply voltage of transistor Q1 is V. cc V ccThe output terminal is connected to the second resistor R2; the other end of the second resistor R2 is connected to the collector of transistor Q1, one end of the first capacitor C1, and one end of the ninth resistor R9. A fourth capacitor C4 is also connected between the collector and base of transistor Q1; the other end of the first capacitor C1 is connected to the emitter of transistor Q1 and one end of the second capacitor C2; the emitter of transistor Q1 is connected to the collector of transistor Q2, and a fifth capacitor C5 is also connected between the collector and base of transistor Q2; the other end of the second capacitor C2 is connected to the emitter of transistor Q2 and one end of the third capacitor C3; the emitter of transistor Q2 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the emitter power supply voltage V of transistor Q2. ee The other end of C3 is connected to ground; the base of transistor Q2 is connected to one end of inductor L, the other end of inductor L is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to ground. The common connection of the second resistor R2, the first capacitor C1, and the ninth resistor R9 is the ultra-wideband resolvable chaotic echo signal V. E (t) Input terminal.

[0019] The common terminal of the second resistor R2, the first capacitor C1, and the ninth resistor R9 is connected to the positive input terminal of comparator 1, the inverting input terminal of comparator 1 is connected to ground, and the output terminal of comparator 1 is connected to the signal input terminal D of the D flip-flop.

[0020] The differentiating circuit includes a ninth resistor R9, the other end of which is connected to a sixth capacitor C6; the other end of the sixth capacitor C6 is connected to the inverting input of operational amplifier 4 and a tenth resistor R. 10 One end of the circuit is connected; the positive input terminal of op-amp 4 is connected to ground, and the output terminal of op-amp 4 is connected to the tenth resistor R. 10 The other end.

[0021] The zero-crossing detector includes comparator 2, the output of operational amplifier 4 is connected to the inverting input of comparator 2 and the non-inverting input of comparator 3, the non-inverting input of comparator 2 is connected to ground, and the output of comparator 2 is connected to input 1 of NOR gate; the inverting input of comparator 3 is connected to ground, and the output of comparator 3 is connected to input 2 of NOR gate; the output of NOR gate is connected to the clock input CLK of D flip-flop.

[0022] The switching compensation circuit includes operational amplifier 1. The positive input terminal of operational amplifier 1 is connected to one end of the ninth resistor R9, the inverting input terminal of operational amplifier 1 is connected to the output terminal of operational amplifier 1, and the output terminal of operational amplifier 1 is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is connected to the inverting input terminal of operational amplifier 3. The output terminal of operational amplifier 3 is connected to the inverting input terminal of operational amplifier 3 and one end of the eighth resistor R8. The other end of the eighth resistor R8 is connected to ground, and the middle tap of the eighth resistor R8 is connected to the output terminal of the NOR gate. The positive input terminal of operational amplifier 2 is connected to the positive input terminal of operational amplifier 1, the inverting input terminal of operational amplifier 2 is connected to the output terminal of operational amplifier 2, and the output terminal of operational amplifier 2 is connected to one end of the sixth resistor R6. The other end of the sixth resistor R6 is connected to one end of the seventh resistor R7 and the positive input terminal of operational amplifier 3, and the other end of the seventh resistor R7 is connected to ground.

[0023] The gain adjustment forcing function includes operational amplifier 5, the output of which is connected to the positive input of operational amplifier 2 and the eleventh resistor R. 11 Eleventh resistor R 11 The other end is connected to the inverting input of op-amp 5, and the non-inverting input of op-amp 5 is connected through the twelfth resistor R. 12 Connect to the output Q terminal of the D flip-flop.

[0024] The fourth broadband correlated receiver circuit unit includes a high-speed shift register and a high-speed tap delay line.

[0025] Among them, the ultra-wideband analyzable chaotic emission signal V of the first unit P (t) Connected to the inverting input of comparator 4 in the broadband correlation receiver circuit; the output signal V of the gain adjustment forced function circuit. s (t) is connected to the positive input of comparator 4; the output signal S(t) of the output Q of the D flip-flop is connected to the data input DATA of the high-speed shift register and input 1 of the XOR gate U8; the output of comparator 4 is connected to input 2 of the XOR gate U8; the output of the XOR gate U8 is connected to the clock signal input CLK of the high-speed shift register and the input of the counter; the output of the counter outputs a trigger signal and is connected to the enable signal input EN of the high-speed shift register; the output signal S1 of the high-speed shift register is connected to input 1 of multiplier 1, the output signal S2 is connected to input 1 of multiplier 2, and the output signal S... n-1 Connect to input terminal 1 of multiplier n-1, output signal S n Connect to input terminal 1 of multiplier n.

[0026] The ultrawideband analytical chaotic synchronization signal V' output by the gain-adjusted forcing function of the third unit. E(t) Connect to the input of the high-speed tapped delay line; output terminal 1 of the high-speed tapped delay line is connected to the positive input of differential amplifier 1; output terminal 2 is connected to the inverting input of differential amplifier 1 and the positive input of differential amplifier 2; output terminal n-1 is connected to the inverting input of differential amplifier n-1 and the positive input of differential amplifier n; output terminal n is connected to the inverting input of differential amplifier n; output terminal of differential amplifier 1 is connected to input terminal 2 of multiplier 1; output terminal of differential amplifier 2 is connected to input terminal 2 of multiplier 2; output terminal of differential amplifier n-1 is connected to input terminal 2 of multiplier n-1; output terminal of differential amplifier n is connected to input terminal 2 of multiplier n; output terminal of multiplier 1 is connected to one end of resistor R1; the other end of resistor R1 is connected to the positive input of operational amplifier; output terminal of multiplier 2 is connected to one end of resistor R2; the other end of resistor R2 is connected to the positive input of operational amplifier; output terminal of multiplier n-1 is connected to resistor R... n-1 One end, resistor R n-1 The other end is connected to the positive input of the operational amplifier; the output of multiplier n is connected to resistor R. n One end, resistor R n The other end is connected to the positive input terminal of the operational amplifier; the positive input terminal of the operational amplifier is connected to one end of capacitor C1, and the other end of capacitor C1 is connected to the output terminal of the operational amplifier; the inverting input terminal of the operational amplifier is connected to ground; the output terminal of the operational amplifier is connected to one end of inductor L; the other end of inductor L is connected to one end of resistor R and capacitor C2, and the other end of resistor R is connected to the other end of capacitor C2 and ground.

[0027] The beneficial effects of this invention are as follows: This invention provides a high-resolution, high-signal-to-noise ratio real-time ranging radar device, specifically a ranging radar device based on ultra-wideband resolvable chaotic synchronization. High-resolution real-time correlation ranging is achieved through the generation and synchronization circuits of ultra-wideband resolvable chaotic signals, requiring only an analog matched filter for correlation reception, thus avoiding the pressure of high sampling rate data and large correlation computation. Furthermore, synchronization of the resolvable chaotic signal at the receiving end is achieved through a digital excitation circuit, accurately reconstructing the chaotic echo signal to improve the signal-to-noise ratio of the ranging. Therefore, this ranging radar device can be applied to through-wall imaging, life detection, underground target identification, and human behavior perception, among other applications. Attached Figure Description

[0028] Figure 1 This is a circuit diagram for transmitting and receiving ultra-wideband resolvable chaotic signals provided in an embodiment of the present invention.

[0029] Figure 2 This is a system schematic diagram of a ranging radar device based on ultra-wideband resolvable chaotic synchronization. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] In chaos generation circuits, the Colpitts chaotic circuit structure is relatively simple, which facilitates the integration of analytical chaotic circuits and improves the achievable operating frequency of analytical chaotic circuits. The above-mentioned technical objective of this invention is achieved through the following technical solutions:

[0032] A ranging radar device based on ultra-wideband resolvable chaotic synchronization includes a first unit ultra-wideband resolvable chaotic signal generation circuit, a second unit digital excitation circuit, a third unit ultra-wideband resolvable chaotic signal synchronization circuit, and a fourth unit wideband correlation receiving circuit; the ultra-wideband resolvable chaotic signal generation circuit is used to generate the transmitted signal V. P (t), transmitted signal V P (t) The target is detected via mixer 1, power amplifier, and transmitting antenna. The ultra-wideband resolvable chaotic signal synchronization circuit is used to receive the echo signal V that is reflected back by the target after the transmitted signal propagates through the medium and is transmitted back via receiving antenna, low-noise amplifier, and mixer 2. E (t), The digital excitation circuit is used to generate physical random codes, and the broadband correlation receiving circuit is used to measure the time delay to achieve distance measurement.

[0033] Among them: the two-stage improved Colpitts oscillator circuit in the ultra-wideband resolvable chaotic signal generation circuit includes the base power supply voltage V of transistor Q1. bb V bb The output terminal is connected to the first resistor R1; the other end of the first resistor R1 is connected to the base of transistor Q1; the collector power supply voltage of transistor Q1 is V. cc V cc The output terminal is connected to the second resistor R2; the other end of the second resistor R2 is connected to the collector of transistor Q1, one end of the first capacitor C1, and one end of the ninth resistor R9. A fourth capacitor C4 is also connected between the collector and base of transistor Q1; the other end of the first capacitor C1 is connected to the emitter of transistor Q1 and one end of the second capacitor C2; the emitter of transistor Q1 is connected to the collector of transistor Q2, and a fifth capacitor C5 is also connected between the collector and base of transistor Q2; the other end of the second capacitor C2 is connected to the emitter of transistor Q2 and one end of the third capacitor C3; the emitter of transistor Q2 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the emitter power supply voltage V of transistor Q2. eeThe other end of the third capacitor C3 is connected to ground; the base of transistor Q2 is connected to one end of inductor L, the other end of inductor L is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to ground. The common connection terminal of the second resistor R2, the first capacitor C1, and the ninth resistor R9 is the ultra-wideband resolvable chaotic signal V. P (t) Output terminal. In the two-stage improved Colpitts oscillator circuit, capacitors C1, C2, and C3, and inductor L constitute the basic resonant unit of the oscillator circuit. C4 and C5 are the parasitic capacitances of transistors Q1 and Q2, respectively. To make the circuit's dynamic equations closer to the actual circuit, the two parasitic capacitances are included in the dynamic equations, and the capacitors and inductors are the resonant elements of the circuit. V cc and V bb To provide DC bias and power to the oscillator circuit, R4 and V ee This is the equivalent current source I0. Between the base and emitter, a current source controlled by V can be used. BE Controlled nonlinear resistor R E To replace it. And between the base and collector, a current-receiving electrode can be used. E A controlled linear current source is used instead. Where I C= αI E I E As shown in the following formula,

[0034] (1)

[0035] In the formula, α is the common-base forward short-circuit current gain of the transistor, and I s For reverse saturation current, V T Let I be a constant, approximately 26 mV at room temperature. L The voltages across capacitors C1, C2, C3, C4, and C5 are respectively V. C1 V C2 V C3 V C4 V C5 Using Kirchhoff's voltage law and current law, the state equation of the circuit can be derived as follows:

[0036] (2)

[0037] The second digital excitation circuit unit includes an autonomous Boolean network and a D flip-flop 1. The autonomous Boolean network includes six XOR gates U1-U6 with three-input, three-output functions, and one XOR NOT gate U7 with three-input, three-output functions. The output terminal 1 of U1 is connected to the input terminal 1 of U2, the output terminal 1 of U2 is connected to the input terminal 1 of U3, the output terminal 1 of U3 is connected to the input terminal 1 of U4, the output terminal 1 of U4 is connected to the input terminal 1 of U5, the output terminal 1 of U5 is connected to the input terminal 1 of U6, the output terminal 1 of U6 is connected to the input terminal 1 of U7, and the output terminal 1 of U7 is connected to the input terminal 1 of U1. The output terminal 2 of U1 is connected to the input terminal 2 of U7, the output terminal 2 of U7 is connected to the input terminal 2 of U6, the output terminal 2 of U6 is connected to the input terminal 2 of U5, and the output terminal 2 of U5 is connected to the input terminal 2 of U4. Input terminal 2 of U4 is connected to input terminal 2 of U3, output terminal 2 of U3 is connected to input terminal 2 of U2, and output terminal 2 of U2 is connected to input terminal 2 of U1. Output terminal 3 of U1 is connected to input terminal 3 of U6, output terminal 3 of U2 is connected to input terminal 3 of U7, output terminal 3 of U3 is connected to input terminal 3 of U1, output terminal 3 of U4 is connected to input terminal 3 of U2, output terminal 3 of U5 is connected to input terminal 3 of U3, output terminal 3 of U6 is connected to input terminal 3 of U4, and output terminal 3 of U7 is connected to input terminal 3 of U5. Output terminal 3 of U7 outputs a Boolean chaotic signal, which is connected to the signal input D terminal of D flip-flop 1. The Boolean delay equation is shown below:

[0038] (3)

[0039] In the formula: x i ∈B={0, 1}, 1≤i≤n, each Boolean variable x i Both depend on time t and on x at the previous moment. j; τ ij (1≤i≤n, 1≤j≤n) represents the time delay caused by the transmission of logic signals on the inter-node line; the function f n This represents the logical operation performed by the Boolean delay equation.

[0040] The clock signal is connected to the clock input CLK terminal of D flip-flop 1, and the output Q terminal of D flip-flop 1 outputs the physical random code V. rand (t) Simultaneously connected to the chaotic signal output V of the first ultra-wideband resolvable chaotic signal generation circuit unit P (t) terminal and the third ultra-wideband resolvable chaotic signal synchronization circuit unit chaotic signal receiver V E (t) end.

[0041] Assume the digital excitation signal after Boolean chaotic signal conversion is V randThe oscillator (t) exhibits random pulse characteristics and can be represented as a series of randomly occurring pulse signals, each with an amplitude of V0 (e.g., a high level in a digital circuit), a width of τ, and a pulse interval of T. Assume two second-order improved Colpitts oscillators, system A and system B, with state variables xA and xB respectively (in reality, each system has multiple state variables, such as voltage and current; for simplicity, a single variable is used here). Under the influence of the digital excitation signal, the dynamic behavior of each oscillator is mainly driven by the digital excitation signal and influenced by its own nonlinear feedback mechanism. The digital excitation signal is the common signal that simultaneously drives both second-order improved Colpitts oscillators, enabling them to influence each other and ultimately achieve synchronization.

[0042] To describe the synchronization relationship between the chaotic output signals of two two-stage improved Colpitts oscillators under digital excitation, a simplified synchronization formula is given below.

[0043] For system A:

[0044] (4)

[0045] For system B:

[0046] (5)

[0047] Where fA(xA) and fB(xB) represent the nonlinear dynamic behaviors of system A and system B, respectively, such as the relationship between the base current and emitter current of a transistor, and the rate of change of current in an inductor. These behaviors are determined by the circuit structure and component parameters of the two-stage improved Colpitts oscillator. gA(V rand (t)) and gB(V rand (t) represent the digital excitation signal V respectively. rand (t) The driving effect on system A and system B. Due to V rand (t) is a voltage pulse signal converted from a digital signal, and its driving effect on the analog chaotic circuit is described by an appropriate circuit model (e.g., through coupling of components such as resistors and capacitors). Assuming the coupling method is simple linear injection, then gA(V rand (t)) and gB(V rand (t) can be represented as gAV rand (t) and gBV rand(t), where gA and gB are coupling coefficients, reflecting the magnitude of the driving strength of the digital excitation signal on the two systems. k(xA-xB) is the feedback control term, where k is the feedback coefficient, used to adjust the coupling strength between the two systems. To achieve synchronization between the two systems, it is desirable that xA(t)→xB(t) as t→∞, that is, the state variables of the two systems gradually converge together. To this end, the above equation is finite, yielding:

[0048] (6)

[0049] Assuming that the two systems exhibit similar nonlinear behaviors under synchronous conditions, i.e., fA(xA)≈fB(xB), and that they are driven by the same digital excitation signal (i.e., gA=gB=g), then the above equation can be simplified to:

[0050] (7)

[0051] Solving this differential equation yields:

[0052] (8)

[0053] This indicates that as t→∞, as long as the feedback coefficient k>0, the state difference between the two systems will decay exponentially over time, eventually achieving synchronization.

[0054] The common terminal of the second resistor R2, the first capacitor C1, and the ninth resistor R9 is connected to the positive input terminal of comparator 1, the inverting input terminal of comparator 1 is connected to ground, and the output terminal of comparator 1 is connected to the signal input terminal D of the D flip-flop.

[0055] The differentiating circuit includes a ninth resistor R9, the other end of which is connected to a sixth capacitor C6; the other end of the sixth capacitor C6 is connected to the inverting input of operational amplifier 4 and a tenth resistor R. 10 One end of the circuit is connected; the positive input terminal of op-amp 4 is connected to ground, and the output terminal of op-amp 4 is connected to the tenth resistor R. 10 The other end.

[0056] The zero-crossing detector includes comparator 2, the output of operational amplifier 4 is connected to the inverting input of comparator 2 and the non-inverting input of comparator 3, the non-inverting input of comparator 2 is connected to ground, the inverting input of comparator 3 is connected to ground, the output of comparator 2 is connected to input 1 of NOR gate, the output of comparator 3 is connected to input 2 of NOR gate, and the output of NOR gate is connected to the clock input CLK of D flip-flop.

[0057] The switching compensation circuit includes operational amplifier 1. The positive input terminal of operational amplifier 1 is connected to one end of the ninth resistor R9, the inverting input terminal of operational amplifier 1 is connected to the output terminal of operational amplifier 1, and the output terminal of operational amplifier 1 is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is connected to the inverting input terminal of operational amplifier 3. The output terminal of operational amplifier 3 is connected to the inverting input terminal of operational amplifier 3 and one end of the eighth resistor R8. The other end of the eighth resistor R8 is connected to ground, and the middle tap of the eighth resistor R8 is connected to the output terminal of the NOR gate in the zero-crossing detector. The positive input terminal of operational amplifier 2 is connected to the positive input terminal of operational amplifier 1, the inverting input terminal of operational amplifier 2 is connected to the output terminal of operational amplifier 2, and the output terminal of operational amplifier 2 is connected to one end of the sixth resistor R6. The other end of the sixth resistor R6 is connected to one end of the seventh resistor R7 and the positive input terminal of operational amplifier 3, and the other end of the seventh resistor R7 is connected to ground.

[0058] The gain adjustment forcing function includes operational amplifier 5, the output of which is connected to the positive input of operational amplifier 2 and the eleventh resistor R. 11 Eleventh resistor R 11 The other end is connected to the inverting input of op-amp 5, and the non-inverting input of op-amp 5 is connected to the output Q of the D flip-flop through the twentieth resistor R12.

[0059] The first ultra-wideband resolvable chaotic signal generation circuit unit is defined by the following formula.

[0060] (9)

[0061] Where u is a continuously time-varying variable, and S(t) is a nonlinear switching event. These are the positive Lyapunov exponents of the linear second-order differential equations that provide energy to the system. Defined as the normalized frequency, equal to 2π. Discrete-state switching occurs when the discrete states of a nonlinear switching event satisfy the following protection conditions:

[0062] (10)

[0063] The nonlinear switching event defined by S(t) switches states when the protection condition is met, occurring in the output u(t) and its derivative. Simultaneously crossing zero. The nonlinear switching function in the above equation defines the system's equilibrium point or bias point.

[0064] The third ultra-wideband resolvable chaotic signal synchronization circuit unit includes a two-stage improved Colpitts oscillator circuit, comparator 1, D flip-flop, differentiator circuit, zero-crossing detector, switching compensation circuit, and gain adjustment forcing function.

[0065] Wherein: the second-stage improved Colpitts oscillator circuit includes the base power supply voltage V of transistor Q1.bb V bb The output terminal is connected to the first resistor R1; the other end of the first resistor R1 is connected to the base of transistor Q1; the collector power supply voltage of transistor Q1 is V. cc V cc The output terminal is connected to the second resistor R2; the other end of the second resistor R2 is connected to the collector of transistor Q1, one end of the first capacitor C1, and one end of the ninth resistor R9. A fourth capacitor C4 is also connected between the collector and base of transistor Q1; the other end of the first capacitor C1 is connected to the emitter of transistor Q1 and one end of the second capacitor C2; the emitter of transistor Q1 is connected to the collector of transistor Q2, and a fifth capacitor C5 is also connected between the collector and base of transistor Q2; the other end of the second capacitor C2 is connected to the emitter of transistor Q2 and one end of the third capacitor C3; the emitter of transistor Q2 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the emitter power supply voltage V of transistor Q2. ee The other end of C3 is connected to ground; the base of transistor Q2 is connected to one end of inductor L, the other end of inductor L is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to ground. The common connection of the second resistor R2, the first capacitor C1, and the ninth resistor R9 is the ultra-wideband resolvable chaotic echo signal V. E (t) Input terminal.

[0066] The common terminal of the second resistor R2, the first capacitor C1, and the ninth resistor R9 is connected to the positive input terminal of comparator 1, the inverting input terminal of comparator 1 is connected to ground, and the output terminal of comparator 1 is connected to the signal input terminal D of the D flip-flop.

[0067] The differentiating circuit includes a ninth resistor R9, the other end of which is connected to a sixth capacitor C6; the other end of the sixth capacitor C6 is connected to the inverting input of operational amplifier 4 and a tenth resistor R. 10 One end of the circuit is connected; the positive input terminal of op-amp 4 is connected to ground, and the output terminal of op-amp 4 is connected to the tenth resistor R. 10 The other end.

[0068] The zero-crossing detector includes comparator 2, the output of operational amplifier 4 is connected to the inverting input of comparator 2 and the non-inverting input of comparator 3, the non-inverting input of comparator 2 is connected to ground, and the output of comparator 2 is connected to input 1 of NOR gate; the output of comparator 3 is connected to input 2 of NOR gate, and the inverting input of comparator 3 is connected to ground; the output of NOR gate is connected to the clock input CLK of D flip-flop.

[0069] The switching compensation circuit includes operational amplifier 1. The positive input terminal of operational amplifier 1 is connected to one end of the ninth resistor R9, the inverting input terminal of operational amplifier 1 is connected to the output terminal of operational amplifier 1, and the output terminal of operational amplifier 1 is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is connected to the inverting input terminal of operational amplifier 3. The output terminal of operational amplifier 3 is connected to the inverting input terminal of operational amplifier 3 and one end of the eighth resistor R8. The other end of the eighth resistor R8 is connected to ground, and the middle tap of the eighth resistor R8 is connected to the output terminal of the NOR gate. The positive input terminal of operational amplifier 2 is connected to the positive input terminal of operational amplifier 1, the inverting input terminal of operational amplifier 2 is connected to the output terminal of operational amplifier 2, and the output terminal of operational amplifier 2 is connected to one end of the sixth resistor R6. The other end of the sixth resistor R6 is connected to one end of the seventh resistor R7 and the positive input terminal of operational amplifier 3, and the other end of the seventh resistor R7 is connected to ground.

[0070] The gain adjustment forcing function includes operational amplifier 5, the output of which is connected to the positive input of operational amplifier 2 and the eleventh resistor R. 11 Eleventh resistor R 11 The other end is connected to the inverting input of op-amp 5, and the non-inverting input of op-amp 5 is connected through the twelfth resistor R. 12 Connect to the output Q terminal of the D flip-flop.

[0071] The fourth broadband correlated receiver circuit unit includes a high-speed shift register and a high-speed tap delay line.

[0072] Among them, the ultra-wideband analyzable chaotic emission signal V of the first unit P (t) Connected to the inverting input of comparator 4 in the broadband correlation receiver circuit; the output signal V of the gain adjustment forced function circuit. s (t) is connected to the positive input of comparator 4; the output signal S(t) of the output Q of the D flip-flop is connected to the data input DATA of the high-speed shift register and input 1 of the XOR gate U8; the output of comparator 4 is connected to input 2 of the XOR gate U8; the output of the XOR gate U8 is connected to the clock signal input CLK of the high-speed shift register and the input of the counter; the output of the counter outputs a trigger signal and is connected to the enable signal input EN of the high-speed shift register; the output signal S1 of the high-speed shift register is connected to input 1 of multiplier 1, the output signal S2 is connected to input 1 of multiplier 2, and the output signal S... n-1 Connect to input terminal 1 of multiplier n-1, output signal S n Connect to input terminal 1 of multiplier n.

[0073] The third unit features an ultrawideband resolvable chaotic synchronization signal V'. E(t) Connect to the input of the high-speed tapped delay line; output terminal 1 of the high-speed tapped delay line is connected to the positive input of differential amplifier 1; output terminal 2 is connected to the inverting input of differential amplifier 1 and the positive input of differential amplifier 2; output terminal n-1 is connected to the inverting input of differential amplifier n-1 and the positive input of differential amplifier n; output terminal n is connected to the inverting input of differential amplifier n; output terminal of differential amplifier 1 is connected to input terminal 2 of multiplier 1; output terminal of differential amplifier 2 is connected to input terminal 2 of multiplier 2; output terminal of differential amplifier n-1 is connected to input terminal 2 of multiplier n-1; output terminal of differential amplifier n is connected to input terminal 2 of multiplier n; output terminal of multiplier 1 is connected to one end of resistor R1; the other end of resistor R1 is connected to the positive input of operational amplifier; output terminal of multiplier 2 is connected to one end of resistor R2; the other end of resistor R2 is connected to the positive input of operational amplifier; output terminal of multiplier n-1 is connected to resistor R... n-1 One end, resistor R n-1 The other end is connected to the positive input of the operational amplifier; the output of multiplier n is connected to resistor R. n One end, resistor R n The other end is connected to the positive input terminal of the operational amplifier; the positive input terminal of the operational amplifier is connected to one end of capacitor C1, and the other end of capacitor C1 is connected to the output terminal of the operational amplifier; the inverting input terminal of the operational amplifier is connected to ground; the output terminal of the operational amplifier is connected to one end of inductor L; the other end of inductor L is connected to one end of resistor R and capacitor C2, and the other end of resistor R is connected to the other end of capacitor C2 and ground.

Claims

1. A ranging radar device based on ultra-wideband analytic chaotic synchronization, characterized in that, It includes a first unit of ultra-wideband resolvable chaotic signal generation circuit, a second unit of digital excitation circuit, a third unit of ultra-wideband resolvable chaotic signal synchronization circuit, and a fourth unit of wideband correlation receiving circuit; the ultra-wideband resolvable chaotic signal generation circuit is used to generate the transmitted signal V. P (t), an ultra-wideband resolvable chaotic signal synchronization circuit is used to receive the echo signal V formed by the reflection of the target after the transmitted signal propagates through the medium. E (t), the digital excitation circuit is used to generate physical random codes and send them to the ultra-wideband resolvable chaotic signal generation circuit and the ultra-wideband resolvable chaotic signal synchronization circuit. The broadband correlation receiving circuit receives the signals output by the ultra-wideband resolvable chaotic signal generation circuit and the ultra-wideband resolvable chaotic signal synchronization circuit to measure the time delay and realize the ranging.

2. The ranging radar device based on ultra-wideband analytic chaotic synchronization according to claim 1, characterized in that, The first unit's ultra-wideband resolvable chaotic signal generation circuit includes a two-stage improved Colpitts oscillator circuit, comparator 1, a D flip-flop, a differentiating circuit, a zero-crossing detector, a switching compensation circuit, and a gain adjustment forcing function; Wherein: the second-stage improved Colpitts oscillator circuit includes the base power supply voltage V of transistor Q1. bb V bb The output terminal is connected to the first resistor R1; the other end of the first resistor R1 is connected to the base of transistor Q1; the collector power supply voltage of transistor Q1 is V. cc V cc The output terminal is connected to the second resistor R2; the other end of the second resistor R2 is connected to the collector of transistor Q1, one end of the first capacitor C1, and one end of the ninth resistor R9. A fourth capacitor C4 is also connected between the collector and base of transistor Q1; the other end of the first capacitor C1 is connected to the emitter of transistor Q1 and one end of the second capacitor C2; the emitter of transistor Q1 is connected to the collector of transistor Q2, and a fifth capacitor C5 is also connected between the collector and base of transistor Q2; the other end of the second capacitor C2 is connected to the emitter of transistor Q2 and one end of the third capacitor C3; the emitter of transistor Q2 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the emitter power supply voltage V of transistor Q2. ee The other end of C3 is connected to ground; the base of transistor Q2 is connected to one end of inductor L, the other end of inductor L is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to ground; the common connection terminal of the second resistor R2, the first capacitor C1, and the ninth resistor R9 is the transmission signal V. P (t) Output terminal; The common terminal of the second resistor R2, the first capacitor C1, and the ninth resistor R9 is connected to the positive input terminal of comparator 1, the inverting input terminal of comparator 1 is connected to ground, and the output terminal of comparator 1 is connected to the signal input terminal D of the D flip-flop. The differentiating circuit includes a ninth resistor R9, the other end of which is connected to a sixth capacitor C6; the other end of the sixth capacitor C6 is connected to the inverting input of operational amplifier 4 and a tenth resistor R. 10 One end of the circuit is connected; the positive input terminal of op-amp 4 is connected to ground, and the output terminal of op-amp 4 is connected to the tenth resistor R. 10 The other end; The zero-crossing detector includes comparator 2, the output of operational amplifier 4 is connected to the inverting input of comparator 2 and the non-inverting input of comparator 3, the non-inverting input of comparator 2 is connected to ground, and the output of comparator 2 is connected to input 1 of NOR gate; the inverting input of comparator 3 is connected to ground, and the output of comparator 3 is connected to input 2 of NOR gate; the output of NOR gate is connected to the clock input CLK of D flip-flop. The switching compensation circuit includes operational amplifier 1. The positive input terminal of operational amplifier 1 is connected to one end of the ninth resistor R9, the inverting input terminal of operational amplifier 1 is connected to the output terminal of operational amplifier 1, and the output terminal of operational amplifier 1 is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is connected to the inverting input terminal of operational amplifier 3. The output terminal of operational amplifier 3 is connected to the inverting input terminal of operational amplifier 3 and one end of the eighth resistor R8. The other end of the eighth resistor R8 is connected to ground, and the middle tap of the eighth resistor R8 is connected to the output terminal of the NOR gate. The positive input terminal of operational amplifier 2 is connected to the positive input terminal of operational amplifier 1, the inverting input terminal of operational amplifier 2 is connected to the output terminal of operational amplifier 2, and the output terminal of operational amplifier 2 is connected to one end of the sixth resistor R6. The other end of the sixth resistor R6 is connected to one end of the seventh resistor R7 and the positive input terminal of operational amplifier 3, and the other end of the seventh resistor R7 is connected to ground. The gain adjustment forcing function includes operational amplifier 5, the output of which is connected to the positive input of operational amplifier 2 and the eleventh resistor R. 11 Eleventh resistor R 11 The other end is connected to the inverting input of op-amp 5, and the non-inverting input of op-amp 5 is connected through the twelfth resistor R. 12 Connect to the output Q terminal of the D flip-flop.

3. A ranging radar device based on ultra-wideband analytic chaotic synchronization according to claim 2, characterized in that, The second unit's digital excitation circuit includes an autonomous Boolean network and a D flip-flop 1. The autonomous Boolean network includes six XOR gates U1-U6 with three-input, three-output functions, and one XOR NOT gate U7 with three-input, three-output functions. The output terminal 1 of U1 is connected to the input terminal 1 of U2, the output terminal 1 of U2 is connected to the input terminal 1 of U3, the output terminal 1 of U3 is connected to the input terminal 1 of U4, the output terminal 1 of U4 is connected to the input terminal 1 of U5, the output terminal 1 of U5 is connected to the input terminal 1 of U6, the output terminal 1 of U6 is connected to the input terminal 1 of U7, and the output terminal 1 of U7 is connected to the input terminal 1 of U1. The output terminal 2 of U1 is connected to the input terminal 2 of U7, the output terminal 2 of U7 is connected to the input terminal 2 of U6, the output terminal 2 of U6 is connected to the input terminal 2 of U5, the output terminal 2 of U5 is connected to the input terminal 2 of U4, and the output terminal 2 of U4 is connected to the input terminal 2 of U3. Terminal 2 of U3 is connected to input terminal 2 of U2, and output terminal 2 of U2 is connected to input terminal 2 of U1; output terminal 3 of U1 is connected to input terminal 3 of U6, output terminal 3 of U2 is connected to input terminal 3 of U7, output terminal 3 of U3 is connected to input terminal 3 of U1, output terminal 3 of U4 is connected to input terminal 3 of U2, output terminal 3 of U5 is connected to input terminal 3 of U3, output terminal 3 of U6 is connected to input terminal 3 of U4, and output terminal 3 of U7 is connected to input terminal 3 of U5; output terminal 3 of U7 outputs a Boolean chaotic signal connected to the signal input D terminal of D flip-flop 1, and the clock signal connected to the clock input CLK terminal of D flip-flop 1; output terminal Q of D flip-flop 1 outputs a physical random code V. rand (t) Simultaneously connected to the transmit signal output V of the first ultra-wideband resolvable chaotic signal generation circuit unit P (t) End and the echo signal reception of the third ultra-wideband resolvable chaotic signal synchronization circuit unit V E (t) end.

4. A ranging radar device based on ultra-wideband analytic chaotic synchronization according to claim 3, characterized in that, The third unit ultrawideband resolvable chaotic signal synchronization circuit includes a two-stage improved Colpitts oscillator circuit, comparator 1, D flip-flop, differentiator circuit, zero-crossing detector, switching compensation circuit, and gain adjustment forcing function; Wherein: the second-stage improved Colpitts oscillator circuit includes the base power supply voltage V of transistor Q1. bb V bb The output terminal is connected to the first resistor R1; the other end of the first resistor R1 is connected to the base of transistor Q1; the collector power supply voltage of transistor Q1 is V. cc V cc The output terminal is connected to the second resistor R2; the other end of the second resistor R2 is connected to the collector of transistor Q1, one end of the first capacitor C1, and one end of the ninth resistor R9. A fourth capacitor C4 is also connected between the collector and base of transistor Q1; the other end of the first capacitor C1 is connected to the emitter of transistor Q1 and one end of the second capacitor C2; the emitter of transistor Q1 is connected to the collector of transistor Q2, and a fifth capacitor C5 is also connected between the collector and base of transistor Q2; the other end of the second capacitor C2 is connected to the emitter of transistor Q2 and one end of the third capacitor C3; the emitter of transistor Q2 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the emitter power supply voltage V of transistor Q2. ee The other end of C3 is connected to ground; the base of transistor Q2 is connected to one end of inductor L, the other end of inductor L is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to ground; the common connection of the second resistor R2, the first capacitor C1, and the ninth resistor R9 is the ultra-wideband resolvable chaotic echo signal V. E (t) Input terminal; The common terminal of the second resistor R2, the first capacitor C1, and the ninth resistor R9 is connected to the positive input terminal of comparator 1, the inverting input terminal of comparator 1 is connected to ground, and the output terminal of comparator 1 is connected to the signal input terminal D of the D flip-flop. The differentiating circuit includes a ninth resistor R9, the other end of which is connected to a sixth capacitor C6; the other end of the sixth capacitor C6 is connected to the inverting input of operational amplifier 4 and a tenth resistor R. 10 One end of the circuit is connected; the positive input terminal of op-amp 4 is connected to ground, and the output terminal of op-amp 4 is connected to the tenth resistor R. 10 The other end; The zero-crossing detector includes comparator 2, the output of operational amplifier 4 is connected to the inverting input of comparator 2 and the non-inverting input of comparator 3, the non-inverting input of comparator 2 is connected to ground, and the output of comparator 2 is connected to input 1 of NOR gate; the inverting input of comparator 3 is connected to ground, and the output of comparator 3 is connected to input 2 of NOR gate; the output of NOR gate is connected to the clock input CLK of D flip-flop. The switching compensation circuit includes operational amplifier 1. The positive input terminal of operational amplifier 1 is connected to one end of the ninth resistor R9, the inverting input terminal of operational amplifier 1 is connected to the output terminal of operational amplifier 1, and the output terminal of operational amplifier 1 is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is connected to the inverting input terminal of operational amplifier 3. The output terminal of operational amplifier 3 is connected to the inverting input terminal of operational amplifier 3 and one end of the eighth resistor R8. The other end of the eighth resistor R8 is connected to ground, and the middle tap of the eighth resistor R8 is connected to the output terminal of the NOR gate. The positive input terminal of operational amplifier 2 is connected to the positive input terminal of operational amplifier 1, the inverting input terminal of operational amplifier 2 is connected to the output terminal of operational amplifier 2, and the output terminal of operational amplifier 2 is connected to one end of the sixth resistor R6. The other end of the sixth resistor R6 is connected to one end of the seventh resistor R7 and the positive input terminal of operational amplifier 3, and the other end of the seventh resistor R7 is connected to ground. The gain adjustment forcing function includes operational amplifier 5, the output of which is connected to the positive input of operational amplifier 2 and the eleventh resistor R. 11 The other end of the eleventh resistor R11 is connected to the inverting input of op-amp 5, and the non-inverting input of op-amp 5 is connected to the twelfth resistor R. 12 Connect to the output Q terminal of the D flip-flop.

5. A ranging radar device based on ultra-wideband analytic chaotic synchronization according to claim 4, characterized in that, The fourth unit broadband correlation receiving circuit includes a high-speed shift register and a high-speed tap delay line; The first unit features an ultra-wideband resolvable chaotic emission signal V. P (t) Connected to the inverting input of comparator 4 in the broadband correlation receiver circuit; the output signal V of the gain adjustment forced function. s (t) is connected to the positive input of comparator 4; the output signal S(t) of the output Q of the D flip-flop is connected to the data input DATA of the high-speed shift register and input 1 of the XOR gate U8; the output of comparator 4 is connected to input 2 of the XOR gate U8; the output of the XOR gate U8 is connected to the clock signal input CLK of the high-speed shift register and the input of the counter; the output of the counter outputs a trigger signal and is connected to the enable signal input EN of the high-speed shift register; the output signal S1 of the high-speed shift register is connected to input 1 of multiplier 1, the output signal S2 is connected to input 1 of multiplier 2, and the output signal S... n-1 Connect to input terminal 1 of multiplier n-1, output signal S n Connect to input terminal 1 of multiplier n; The ultrawideband analytical chaotic synchronization signal V' output by the gain-adjusted forcing function of the third unit. E (t) Connect to the input of the high-speed tapped delay line; output terminal 1 of the high-speed tapped delay line is connected to the positive input of differential amplifier 1; output terminal 2 is connected to the inverting input of differential amplifier 1 and the positive input of differential amplifier 2; output terminal n-1 is connected to the inverting input of differential amplifier n-1 and the positive input of differential amplifier n; output terminal n is connected to the inverting input of differential amplifier n; output terminal of differential amplifier 1 is connected to input terminal 2 of multiplier 1; output terminal of differential amplifier 2 is connected to input terminal 2 of multiplier 2; output terminal of differential amplifier n-1 is connected to input terminal 2 of multiplier n-1; output terminal of differential amplifier n is connected to input terminal 2 of multiplier n; output terminal of multiplier 1 is connected to one end of resistor R1; the other end of resistor R1 is connected to the positive input of operational amplifier; output terminal of multiplier 2 is connected to one end of resistor R2; the other end of resistor R2 is connected to the positive input of operational amplifier; output terminal of multiplier n-1 is connected to resistor R... n-1 One end, resistor R n-1 The other end is connected to the positive input of the operational amplifier; the output of multiplier n is connected to resistor R. n One end, resistor R n The other end is connected to the positive input terminal of the operational amplifier; the positive input terminal of the operational amplifier is connected to one end of capacitor C1, and the other end of capacitor C1 is connected to the output terminal of the operational amplifier; the inverting input terminal of the operational amplifier is connected to ground; the output terminal of the operational amplifier is connected to one end of inductor L; the other end of inductor L is connected to one end of resistor R and capacitor C2, and the other end of resistor R is connected to the other end of capacitor C2 and ground.

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