Programmable online kernel self-diagnosis implementation method and storage medium

Abstract

The invention discloses a programmable online kernel self-diagnosis implementation method and a storage medium. The method comprises the following steps: S1, constructing a hardware architecture; s2, test excitation and signature pre-generation; s3, software programmable configuration is carried out; the CPU sets a test mode, the number of execution SEEDs, test granularity, clock distribution and start / stop through the configuration register; s4, preparing before testing; s5, executing an online test; reading SEED from the ROM, generating excitation by a Pattern generator, loading the excitation to a kernel scan chain, capturing output, generating an MISR, and comparing the MISR with a GOLDEN MISR; s6, fault processing and a safety mechanism; and S7, recovering after testing. The storage medium is realized based on the method. The method has the advantages of simple principle, wide application range, good flexibility, high coverage rate and the like.

Description

Technical Field

[0001] This invention mainly relates to the field of semiconductor chip functional safety testing technology, specifically a programmable online kernel self-diagnosis implementation method and storage medium, applicable to chip design that meets functional safety standards in the automotive, industrial, and home appliance fields. Background Technology

[0002] As a critical execution component in a chip, the CPU core is the core execution component in automotive-grade, industrial-grade, and consumer appliance chips, and its correct operation directly determines system safety. Even after a chip passes factory testing, hardware defects can still occur during actual operation due to factors such as mechanical vibration, voltage fluctuations, temperature drift, and particle bombardment, leading to system malfunctions, shutdowns, and safety incidents. With the widespread application of semiconductors in the automotive and industrial markets, functional safety has become a key dimension in semiconductor design, in addition to traditional aspects such as power consumption, performance, and area. To meet functional safety requirements, the automotive sector adheres to ISO 26262, the industrial sector to IEC 61508, and the consumer appliance sector to IEC 60730 Class B, all of which mandate that the core possess online real-time fault detection capabilities.

[0003] In existing technologies, kernel testing technology still has some shortcomings: 1. It relies on external ATE equipment and can only perform offline factory testing; it cannot run tests online. 2. The test mode is fixed, and it can only perform a full test at once, and cannot be sliced ​​and executed in time-sharing mode; 3. The testing is granular and time-consuming, consumes a lot of CPU resources, and interferes with the main business. 4. Fault coverage is low under limited excitation, typically below 90%; 5. Without I / O isolation mechanism, test signals interfere with other subsystems of the chip; 6. There is no on-site save / restore mechanism, and the original program cannot be executed again after testing; 7. Lacks HWBIST self-verification mechanism, making it prone to misjudgment; 8. No timeout protection, which may cause the CPU to lock up in case of an abnormality.

[0004] Therefore, many industries in this technical field urgently need an online, programmable, low-interference, high-coverage kernel self-diagnosis method with security protection. Summary of the Invention

[0005] The technical problem to be solved by this invention is: in view of the technical problems existing in the prior art, this invention provides a programmable online kernel self-diagnosis implementation method and storage medium that is simple in principle, has a wide range of applications, good flexibility, and high coverage.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: A programmable online kernel self-diagnosis implementation method, comprising: Step S1: Hardware architecture setup; Step S2: Test stimulus and signature pre-generation; the Flextest tool is used to iteratively select several groups of SEEDs with the best coverage, each group corresponding to a GOLDEN MISR, which is then stored in ROM; Step S3: Software programmable configuration; the CPU sets the following through configuration registers: test mode, number of SEEDs to be executed, test granularity, clock allocation, and start / stop; Step S4: Preparation before testing; Step S5: Online test execution; read the SEED from ROM, generate stimuli using the Pattern generator, load it into the kernel scan chain, capture the output, generate the MISR, and compare it with the GOLDEN MISR; Step S6: Fault handling and safety mechanisms; Step S7: Post-test recovery; includes: kernel reset, restoring the context, releasing and handling cached interrupts, and returning CPU control.

[0007] As a further improvement of the present invention: the hardware architecture of step S1 includes: The controller, through CPU configuration registers, generates and outputs control signals to manage pattern generation, test granularity, test status settings, and clock allocation control. The pattern generator uses the SEED in ROM as the source to generate scan test stimuli, loads them into the kernel scan chain, and tests the kernel logic. The ROM storage module is used to control ROM read and write operations, store the optimal SEED and corresponding GOLDEN MISR, and automatically generate addresses, enable functions, and read data. The output capture and MISR module is used to capture the scan chain output, compress it using an XOR tree to generate a MISR signature, and compare it with the GOLDEN MISR to output the judgment result. I / O isolated logic unit, input is set to fixed standard level, output is set to high impedance / invalid state; The interrupt recording module buffers interrupt signals during the test and handles them uniformly after the test ends.

[0008] As a further improvement of the present invention: a coverage optimization strategy is adopted, including: after the netlist is generated, Flextest is used to perform fault coverage analysis, iteratively selecting SEEDs, recording uncovered faults, and filling them in one by one; the top few SEEDs with the highest coverage are selected and stored in ROM; during online testing, the current coverage is calculated in real time according to the number of completed SEEDs.

[0009] As a further improvement of the present invention: a full node excitable and observable model based on a scan chain is adopted: all flip-flops inside the kernel are connected in series to form a complete scan chain, so that all internal logic can be shifted input and shifted output; ensuring that every logic gate and every signal line can be covered by test excitation and observed.

[0010] As a further improvement of the present invention: an automated tool is used to iteratively optimize the SEED: the following process is performed using the Flextest fault simulation tool: generate a kernel netlist and establish a complete fault model; input a SEED, generate test vectors, perform simulation, and count the covered faults; record the list of uncovered faults as the optimization target for the next round of SEEDs; iterate in a loop and continuously supplement the SEEDs that can cover new faults.

[0011] As a further improvement to this invention: High-value SEEDs are carefully selected, and the top few optimal combinations are retained: all candidate SEEDs are sorted by coverage contribution; the top few SEED groups with the highest coverage, shortest vectors, and strongest complementarity are selected; each SEED group corresponds to a unique GOLDEN MISR, which is stored in ROM; test vectors are used to cover undetected faults: in each round of simulation, undetected faults are used as the generation target for the next SEED; subsequent vectors specifically cover logic not detected in the previous tests; MISR signature compression does not lose fault information: the scan output is compressed using an XOR tree + MISR multi-input feature register; any bit logic error will result in a completely different final signature.

[0012] As a further improvement of the present invention: step S4 employs a fault self-checking method to detect the correctness of the HWBIST automatic test and timeout functions; including: If HWBIST can reliably detect a known fault by artificially injecting it, it indicates that: The pattern generator is working correctly. The scan chain is normal; MISR compression and comparison are normal; The fault reporting channel is normal; If any step fails, the self-verification will fail, thus preventing the "diagnostic module from being broken without our knowledge"; If HWBIST itself is damaged, the following will occur: the kernel is really broken, but HWBIST cannot detect it, the system runs with the fault, and a security incident occurs.

[0013] As a further improvement to the present invention, a timeout exit mechanism is included, namely, the HWBIST test time is fixed, and if the test is not completed within the expected time, the test stops immediately, the kernel resets and issues an NMI interrupt to recover from the indeterminate state; once the hwbist module enters self-test mode, the software cannot disable this function; after the reset is completed, the HWBIST status register is read to understand the reason for the reset and take measures.

[0014] As a further improvement of the present invention: step S6 includes: If the comparison is inconsistent, a fault flag is set, an NMI interrupt is triggered, and the test is stopped. Test timed out, forced kernel reset, exit abnormal state; Error injection to verify the validity of HWBIST itself.

[0015] The present invention also provides a storage medium that can be read by a computer or processor, wherein the storage medium stores a computer program for executing any of the above methods.

[0016] Compared with the prior art, the advantages of the present invention are as follows: 1. The programmable online kernel self-diagnosis implementation method and storage medium of the present invention are simple in principle, have a wide range of applications, and are highly flexible. They can overcome the shortcomings of existing technologies, such as inability to perform online real-time detection, poor flexibility, low coverage, strong interference, and lack of security protection. They can achieve seamless testing during online operation, programmable full / slice / cumulative testing, fault coverage >90% under limited excitation, testing does not interfere with the system, and can automatically restore the field. They also have self-verification and anti-freezing protection, and can meet functional safety standards.

[0017] 2. The programmable online kernel self-diagnosis implementation method and storage medium of the present invention is a scan-based programmable online kernel self-test method (HWBIST). It can be configured via registers to perform a complete test at once, or to perform intermittent tests during CPU idle periods, accumulating multiple tests to complete the entire test. Under limited test stimuli, it can achieve coverage exceeding 90%. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating the method of the present invention in a specific embodiment.

[0019] Figure 2 This is a schematic diagram of the topological principle implemented in a specific embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of the HWBIST execution state in a specific embodiment of the method of the present invention. Detailed Implementation

[0021] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] In the description of this application, it should be understood that the abbreviations used herein have the following meanings: HWBIST is a built-in hardware self-test; CPU stands for Central Processing Unit; MCU stands for Microcontroller Unit; ATE stands for Automated Test Equipment; SEED is a test seed; Pattern is the test stimulus; MISR stands for Multi-Input Feature Register; GOLDEN MISR is the gold standard signature; XOR stands for Exclusive OR gate; Scan Chain refers to the chain of scans. LFSR stands for Linear Feedback Shift Register; NMI stands for Non-Maskable Interrupt; I / O stands for Input / Output Port. ROM stands for Read-Only Memory; ISO 26262 is the functional safety standard for automobiles; IEC 61508 is an industrial functional safety standard; IEC 60730 is the safety standard for household appliances; ASIL stands for Automotive Safety Integrity Level; SIL stands for Industrial Safety Integrity Level. Class B refers to the safety category B for household appliances.

[0023] like Figure 1 and Figure 2 As shown, this invention discloses a programmable online kernel self-diagnosis implementation method, which includes: Step S1: Hardware architecture setup; The entire hardware architecture includes: controller, pattern generator, ROM storage module, output capture and MISR module, I / O isolation logic unit, and interrupt recording module; Step S2: Test stimulus and signature pre-generation; The Flextest tool was used to iteratively screen the 800 groups of seeds with the best coverage, each group corresponding to a GOLDENMISR, which was then stored in ROM; Step S3: Software-programmable configuration; The CPU configures the following settings via configuration registers: test mode, number of SEEDs to execute, test granularity, clock allocation, and start / stop. Step S4: Preparation before testing; In a specific application example, step S4 specifically includes: opening the interrupt buffer, saving the kernel context, and isolating I / O ports; Step S5: Execute online test; The SEED is read from ROM, the stimuli are generated by the Pattern generator, loaded into the kernel scan chain, the output is captured, the MISR is generated, and compared with the GOLDEN MISR. Step S6: Fault handling and safety mechanisms; Step S6 specifically includes: If the comparison is inconsistent, a fault flag is set, an NMI interrupt is triggered, and the test is stopped; Test timed out, forced kernel reset, exit abnormal state; Error injection to verify the validity of HWBIST itself.

[0024] Step S7: Restore after testing; In a specific application example, step S7 specifically includes: kernel reset, restoring the context, releasing and handling cached interrupts, and returning CPU control.

[0025] In a specific application example, the hardware architecture of step S1 specifically includes: The controller, through the CPU configuration registers, generates and outputs control signals to manage pattern generation, test granularity, test state settings, clock allocation, and other controls. The pattern generator uses the SEED in ROM as the source to generate scan test stimuli, loads them into the kernel scan chain, and tests the kernel logic. The ROM storage module is used to control ROM read and write operations, storing 800 optimal seeds and their corresponding golden MISRs. It automatically generates addresses, enables, and reads data. The ROM stores seed seeds and golden MISRs, with each seed corresponding to a golden MISR. Based on the configuration in the controller, it automatically generates the logic for reading and writing ROM addresses, enabling, and data. The seed seeds in the read data are sent to the pattern generator to generate stimuli, while the golden MISRs in the data serve as a reference standard and are compared with the MISRs generated after the scan chain. If they match, the detection passes; otherwise, a kernel fault exists.

[0026] The output capture and MISR module is used to capture the scan chain output, compress it using an XOR tree to generate a MISR signature, and compare it with the GOLDEN MISR to output the judgment result. In other words, it captures the scan chain output and generates a MISR signature using an XOR tree. If the kernel logic is fault-free, the generated MISR signature should match the corresponding seed's GOLDEN MISR signature; otherwise, it indicates a kernel logic fault, in which case the test will stop, an interrupt will be issued, and the relevant status registers will be set.

[0027] The I / O isolation logic unit sets the inputs to a fixed standard level and the outputs to a high-impedance / invalid state to avoid interference with other subsystems. To prevent the kernel module's input / output logic from affecting MISR generation during HWBIST testing, the kernel's inputs and outputs need to be isolated. The isolation value for input signals needs to be consistent with the value used to generate the GOLDEN MISR, while for output signals, only signals affecting other subsystems of the chip need to be isolated and controlled to an invalid state.

[0028] The interrupt recording module buffers interrupt signals during the test and handles them uniformly after the test. That is, it records interrupt signals during HWBIST execution and responds to these interrupts after HWBIST execution is completed.

[0029] In specific application examples, a coverage optimization strategy is adopted during the execution of the above method, including: after the netlist is generated, Flextest is used to perform fault coverage analysis, iteratively selects SEEDs, records uncovered faults, and completes them one by one; the top 800 SEEDs with the highest coverage are selected and stored in ROM; during online testing, the current coverage is calculated in real time based on the number of completed SEEDs.

[0030] The fault coverage rate serves to quantitatively characterize the kernel self-diagnostic method's ability to detect hardware faults, ensuring sufficient and complete fault detection of the CPU kernel logic implementation, avoiding missed detection of critical defects, meeting the functional safety standards' requirements for detection completeness, and providing a basis for test stimulus optimization and online test progress evaluation. Therefore, fault coverage rate is the core indicator for measuring the detection capability of this programmable online kernel self-diagnostic method. It is used to quantify and ensure that the diagnostic method can discover the vast majority of hardware defects in the kernel, ensuring sufficient and complete detection, and meeting the mandatory requirements of functional safety standards for fault detection completeness. The method described in this invention utilizes four key techniques: optimal test seed (SEED) selection, full scan chain observation, precise MISR signature determination, and targeted completion of uncovered faults. Under limited test stimulus conditions, this method achieves a stable CPU kernel fault coverage rate exceeding 90%.

[0031] The minimum detection time in HWBIST is determined by the detection time of a single seed. Each seed generates stimuli to test the kernel, covering a certain number of faults. Seed selection is crucial; the goal is to achieve maximum fault detection coverage with the fewest possible seeds. Coverage statistics are performed using the tool Flextest. After the netlist is generated, a seed and the number of generated patterns are specified, and coverage analysis is performed. Undetected faults are recorded and added to the fault list for the next seed, and this process continues until no more faults can be detected. The fault coverage of all seeds is statistically analyzed, and the top 800 seeds with the highest coverage and their corresponding MISRs are stored in ROM. During HWBIST testing, the test coverage can be calculated based on the number of seeds tested.

[0032] Specifically, in order to ensure fault coverage, the means employed in the above-described method of the present invention include: Full node excitability and observability based on scan chain: All flip-flops inside the kernel are connected in series to form a complete scan chain, making all internal logic shiftable inputs and shiftable outputs; ensuring that every logic gate and every signal line can be covered and observed by test excitability; eliminating "unmeasurable dead zones" from a physical structure perspective, laying the hardware foundation for high coverage.

[0033] An automated tool is used to iteratively optimize the selection of seeds: The following process is executed using the Flextest fault simulation tool: A kernel netlist is generated, and a complete fault model is established (fixed 0, fixed 1, bridging, open circuit, etc.); a seed is input, test vectors are generated, simulation is performed, and the covered faults are counted; a list of uncovered faults is recorded as the optimization target for the next round of seeds; this process is iterated repeatedly, continuously supplementing the selection with seeds that can cover new faults. This ensures that each seed covers as many new faults as possible, avoiding vector redundancy.

[0034] We select high-value seeds and retain the top 800 optimal combinations: sort all candidate seeds by coverage contribution; select the top 800 seed groups with the highest coverage, shortest vectors, and strongest complementarity; each seed group corresponds to a unique GOLDEN MISR and is stored in ROM; in this way, we can achieve maximum coverage with the minimum number of stimuli, which is suitable for online, low-overhead testing.

[0035] Test vector targeted coverage of undetected faults: Each round of simulation uses undetected faults as the target for generating the next SEED; allowing subsequent vectors to specifically cover logic that was not tested in the previous rounds; this enables precise blind filling and continuously improves coverage until convergence.

[0036] MISR signature compression does not lose fault information: The scan output is compressed by XOR tree + MISR multi-input feature register; any bit logic error will result in a completely different final signature; the compression will not lose fault or reduce coverage; thus, it can ensure that faults are not lost, misjudged, or missed.

[0037] Unified testing of the entire kernel logic: Coverage includes: arithmetic unit, register file, control unit, selector, internal bus, etc., without omitting any functional module. This ensures high overall coverage, rather than partial coverage.

[0038] In the above process, the accurate determination of the MISR (Multiple Input Feature Register) signature involves compressing the massive response data output from the kernel scan chain into a unique fixed-length signature using a hardware XOR tree, and then comparing it bit by bit with the pre-stored gold standard signature (GOLDENMISR) to achieve accurate detection without losing faults, misjudging, or missing any cases. Its detailed process includes: Test stimulus injection and kernel response output: The pattern generator generates test vectors based on the SEED in the ROM; the test vectors are serially shifted in through the kernel scan chain, covering all flip-flops and combinational logic; after the stimulus flows through the kernel logic, the original circuit response is obtained at the scan output; all output responses are serially shifted out from the scan chain bit by bit and clock cycle by cycle. Scan output capture and XOR tree compression: The scan output signal is sent bit by bit to the output capture module; all bits enter the compression tree composed of multiple levels of XOR gates; the XOR tree compresses all output bits bit by bit, condensing a large amount of data into a fixed-length feature; the compression result is sent to the MISR multi-input feature register; MISR Signature Generation: The MISR is essentially a shift register with feedback. With each scan clock cycle, a new bit is output and entered into the MISR. Internally, the register state is continuously updated through an XOR feedback structure. After all the data in the entire scan chain has been shifted out, the final state retained in the MISR is the measured MISR signature in this test. During this process, as long as there are no faults in the core logic, the same SEED will always generate the exact same MISR. If any bit in the core logic is faulty, the final signature will be completely different.

[0039] Gold Standard Signature (GOLDEN MISR) Pre-Storage: During the chip design phase, a fault-free netlist is used for simulation to generate a corresponding correct standard signature for each SEED; each SEED is bound to a Gold Standard Signature and stored in the on-chip ROM; during testing, the controller automatically reads the standard signature corresponding to the current SEED. Hardware-level bit-by-bit comparison: After the test is completed, the measured MISR and GOLDEN MISR are simultaneously sent to the hardware comparator; the comparator performs a bit-by-bit equality comparison. If every bit is the same, the kernel is determined to be fault-free; if any bit is different, the kernel is determined to have a hardware fault. Subsequent processing of the judgment results: If there is no fault and the comparison is consistent, the test ends normally and continues to execute the next SEED or exits the test; if a fault is detected and the comparison is inconsistent, the test stops immediately; the fault status register is set, triggering the NMI non-maskable interrupt and notifying the system to enter safe processing; if the test is abnormal and fails to complete the timeout, the kernel is forced to reset, exit the indeterminate state, and the cause of the fault is recorded.

[0040] In a specific application example, step S4 employs a fault self-verification (error injection) method. This is a key safety mechanism in the HWBIST online self-diagnosis method specifically used to verify the effectiveness of the diagnostic system itself. It ensures that HWBIST itself is not corrupted, does not make false judgments, and does not miss any cases, thus making the entire kernel diagnostic process "trustworthy" and meeting the mandatory requirements of functional safety standards. By injecting fault functionality, the correctness of HWBIST's automatic testing and timeout functions can be detected, which can be used to check whether the HWBIST controller functions are operating normally.

[0041] By artificially injecting a known fault (fixed 0 / fixed 1), if HWBIST can reliably detect this fault, it indicates that: The pattern generator is working correctly. The scan chain is normal; MISR compression and comparison are normal; The fault reporting channel is normal; If any step fails, the self-verification will fail, thus preventing the "diagnostic module from being broken without our knowledge".

[0042] If HWBIST itself is damaged, the following will occur: the kernel is really broken, but HWBIST cannot detect it, the system runs with the fault, and a security incident occurs; therefore, error injection can detect HWBIST failure in advance and eliminate the fatal risk of "not being able to detect" from the root.

[0043] Furthermore, the effectiveness of the fault reporting and interrupt mechanism was verified. If a fault occurs, the status register is set, the NMI interrupt is triggered, and the link is completely unobstructed.

[0044] Furthermore, in conjunction with injection anomalies, we will verify whether timeouts can force a reset and exit the stuck state.

[0045] Furthermore, this invention includes a timeout exit mechanism, meaning the HWBIST test duration is fixed. If the test is not completed within the expected time, the test immediately stops, the kernel resets, and an NMI interrupt is issued, recovering from the indeterminate state. Once the hwbist module enters self-test mode, this function cannot be disabled by software. After the reset is complete, the HWBIST status register can be read to understand the reason for the reset and take the necessary actions.

[0046] The effectiveness of HWBIST's own test stimulus generation, scan chain transmission, MISR signature comparison, fault diagnosis, interrupt reporting, and timeout protection functions is verified to prevent HWBIST hardware failure from causing missed or misjudged kernel faults, ensuring the self-diagnostic system is trustworthy and reliable, meeting the functional safety standard's self-testing requirements for monitoring modules, and achieving dual-layer security protection.

[0047] HWBIST is initiated by software. Because the entire kernel is in a state of unordered activity during HWBIST execution, a state saving is required before starting the HWBIST test. After the HWBIST test is completed, kernel control is returned to the system, restoring the state before HWBIST execution and resuming the execution of previous system programs. For specific application examples, see [link to relevant documentation]. Figure 3 The specific process of the method of the present invention includes: Step S100: Configure HWBIST mode; Software writes to registers: test SEED count, test enable, coverage calculation enable.

[0048] Step S200: Enable interrupt buffer; Enable interrupt cache to temporarily store all interrupt requests during the test.

[0049] Step S300: Save the kernel state; Save CPU general-purpose registers, program counter, context, and running state.

[0050] Step S400: Start the HWBIST test; Controller initiates test → ROM outputs SEED → Pattern generates stimulus → Scan injection → Capture output → Generate MISR → Signature comparison.

[0051] Step S500: Fault / Timeout Handling; Signature mismatch: Set fault status register → trigger NMI interrupt → stop test.

[0052] Timeout incomplete: Force kernel reset → Exit indeterminate state → Record reset reason.

[0053] Step S600: Restore the kernel context; Test complete → Kernel soft reset → Context restored → Interrupt buffer released → CPU returns to the breakpoint before the test and continues execution.

[0054] Specific application scenario example 1 of the present invention: Automotive MCU body control chip (ISO 26262 ASIL-D) Scenario: Main MCU for car windows, door locks, lights, and windshield wipers.

[0055] Implementation process: 1. Power-on startup: Perform a full test of 800 sets of SEEDs.

[0056] 2. During operation: Perform slice tests during task downtime, with 10-20 seeds per test, for total full coverage.

[0057] 3. Fault Trigger: MISR mismatch → NMI interrupt → enter safe state → cut off drive output.

[0058] 4. Abnormal protection: Test timeout → kernel automatically reset → record DTC fault code.

[0059] Results: Continuous online monitoring during driving prevents loss of control and malfunctions, and is ASIL certified.

[0060] Example 2 of a specific application scenario of the present invention: Industrial servo drive main control chip (IEC 61508 SIL-3) Scenario: Servo motor position / speed control, 24-hour continuous operation.

[0061] Implementation process: 1. Quick Start Test: Executes 200 sets of SEEDs and passes quickly, enabling devices to go online rapidly.

[0062] 2. Operating intervals: When the motor stops / operates at low speed, the slices are retested, with a total of 800 sets completed.

[0063] 3. Periodic self-verification: Initiate error injection to confirm that HWBIST is normal.

[0064] 4. Fault Handling: If a fault is detected, immediately stop the emergency and report to the EtherCAT / Modbus host computer.

[0065] Results: No impact on production cycle time; meets high availability and functional safety requirements.

[0066] Table 1. Comparison of test results between traditional testing techniques and the technical solution of this invention.

[0067] In summary, by employing the method described above, online programmable time-slice testing can be completed, with a minimum test unit of 19 clock cycles. Testing is performed during CPU idle periods, accumulating to complete the full test. An optimal seed selection mechanism is used, achieving >90% fault coverage with 800 seed groups. Throughout the execution of the method, I / O is fully isolated and field protection and recovery are implemented, ensuring that testing does not interfere with the system and services are not interrupted. Triple security protection is employed during execution: MISR signature comparison, error injection self-verification, and timeout forced exit. The entire method is functionally safe and user-friendly, capable of fault reporting (NMI), status verification, and resettable recovery, meeting standards such as ISO 26262.

[0068] The present invention also provides a storage medium that can be read by a computer or processor, wherein the storage medium stores a computer program for executing any of the above methods.

[0069] Those skilled in the art will understand that the above embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0070] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A programmable online kernel self-diagnosis implementation method, characterized in that, include: Step S1: Hardware architecture setup; Step S2: Test stimulus and signature pre-generation; the Flextest tool is used to iteratively select several groups of SEEDs with the best coverage, each group corresponding to a GOLDEN MISR, which is then stored in ROM; Step S3: Software programmable configuration; the CPU sets the following through configuration registers: test mode, number of SEEDs to be executed, test granularity, clock allocation, and start / stop; Step S4: Preparation before testing; Step S5: Online test execution; read the SEED from ROM, generate stimuli using the Pattern generator, load it into the kernel scan chain, capture the output, generate the MISR, and compare it with the GOLDEN MISR; Step S6: Fault handling and safety mechanisms; Step S7: Post-test recovery; includes: kernel reset, restoring the context, releasing and handling cached interrupts, and returning CPU control.

2. The programmable online kernel self-diagnosis implementation method according to claim 1, characterized in that, The hardware architecture of step S1 includes: The controller, through CPU configuration registers, generates and outputs control signals to manage pattern generation, test granularity, test status settings, and clock allocation control. The pattern generator uses the SEED in ROM as the source to generate scan test stimuli, loads them into the kernel scan chain, and tests the kernel logic. The ROM storage module is used to control ROM read and write operations, store the optimal SEED and corresponding GOLDEN MISR, and automatically generate addresses, enable functions, and read data. The output capture and MISR module is used to capture the scan chain output, compress it using an XOR tree to generate a MISR signature, and compare it with the GOLDEN MISR to output the judgment result. I / O isolated logic unit, input is set to fixed standard level, output is set to high impedance / invalid state; The interrupt recording module buffers interrupt signals during the test and handles them uniformly after the test ends.

3. The programmable online kernel self-diagnosis implementation method according to claim 1, characterized in that, A coverage optimization strategy is adopted, including: after the netlist is generated, Flextest is used to perform fault coverage analysis, iteratively selects SEEDs, records uncovered faults, and completes the list step by step; the top few SEEDs with the highest coverage are selected and stored in ROM; during online testing, the current coverage is calculated in real time based on the number of completed SEEDs.

4. The programmable online kernel self-diagnosis implementation method according to claim 3, characterized in that, Employing a full-node stimulability and observability based on scan chains: all flip-flops inside the kernel are connected in series to form a complete scan chain, allowing all internal logic to have shiftable inputs and shiftable outputs; ensuring that every logic gate and every signal line can be covered by test stimuli and observed.

5. The programmable online kernel self-diagnosis implementation method according to claim 3, characterized in that, Automated SEED optimization is performed using the following process: Generate kernel netlist and build a complete fault model using the Flextest fault simulation tool. Input a SEED, generate test vectors, execute simulation, and count the covered faults; record the list of uncovered faults as the optimization target for the next round of SEEDs; iterate in a loop, continuously adding SEEDs that can cover new faults.

6. The programmable online kernel self-diagnosis implementation method according to claim 5, characterized in that, We carefully select high-value seeds and retain the top few optimal combinations: All candidate seeds are sorted by coverage contribution; the top few seed groups with the highest coverage, shortest vectors, and strongest complementarity are selected; each seed group corresponds to a unique GOLDEN MISR, stored in ROM; test vectors are used to cover undetected faults: each simulation round uses undetected faults as the generation target for the next seed; subsequent vectors specifically cover logic not detected in previous tests; MISR signature compression does not lose fault information: the scan output is compressed using an XOR tree + MISR multi-input feature register; any bit logic error will result in a completely different final signature.

7. The programmable online kernel self-diagnosis implementation method according to any one of claims 1-6, characterized in that, Step S4 employs a fault self-checking method to verify the correctness of the HWBIST automatic testing and timeout functions; including: If HWBIST can reliably detect a known fault by artificially injecting it, it indicates that: The pattern generator is working correctly. The scan chain is normal; MISR compression and comparison are normal; The fault reporting channel is normal; If any step fails, the self-check will fail, thus preventing the "diagnostic module from being broken without our knowledge"; If HWBIST itself is damaged, the following will occur: the kernel is really broken, but HWBIST cannot detect it, the system runs with the fault, and a security incident occurs.

8. The programmable online kernel self-diagnosis implementation method according to any one of claims 1-6, characterized in that, This includes a timeout exit mechanism, meaning the HWBIST test has a fixed duration. If the test is not completed within the expected time, it stops immediately, the kernel resets, and issues an NMI interrupt to recover from the indeterminate state. Once the hwbist module enters self-test mode, this function cannot be disabled by the software. After the reset is complete, the HWBIST status register is read to understand the reason for the reset and take appropriate measures.

9. The programmable online kernel self-diagnosis implementation method according to any one of claims 1-6, characterized in that, Step S6 includes: If the comparison is inconsistent, a fault flag is set, an NMI interrupt is triggered, and the test is stopped. Test timed out, forced kernel reset, exit abnormal state; Error injection to verify the validity of HWBIST itself.

10. A storage medium capable of being read by a computer or processor, characterized in that, The storage medium stores a computer program for performing the method described in any one of claims 1 to 9.

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