In-situ sidewall passivation towards bottom of high aspect ratio features

Abstract

A semiconductor processing method may include providing a silicon-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be received within the processing region. Features may extend through one or more layers of material disposed on the substrate. The method may include forming a plasma effluent of the silicon-containing precursor and the oxygen-containing precursor. The method can include contacting the substrate with the plasma effluent of the silicon-containing precursor and the oxygen-containing precursor. The contact may form a silicon and oxygen containing material on at least a bottom portion of the feature. The temperature in the treatment region may be maintained at less than or about 0 DEG C.

Description

Technical Field

[0001] This application claims the benefit and priority of U.S. Patent Application No. 18 / 370,536, filed September 20, 2023, entitled “IN-SITU SIDEWALL PASSIVATION TOWARD THE BOTTOM OF HIGH ASPECT RATIO FEATURES”, the entire contents of which are incorporated herein by reference.

[0002] This technology relates to semiconductor systems and processes. More specifically, this technology relates to sidewall passivation processes for high aspect ratio features. Background Technology

[0003] Integrated circuits may be fabricated through processes that create complex patterned material layers on a substrate surface. Creating patterned material on the substrate requires controlled methods for removing exposed material. Chemical etching is used for various purposes, including transferring patterns from photoresist to underlying layers, thinning layers, or thinning the lateral dimensions of features already present on the surface. It is often desirable to have an etching process that etches one material faster than another, thereby facilitating, for example, pattern transfer processes. This type of etching process is referred to as material-selective. Due to the diversity of materials, circuits, and processes, material-selective etching processes have been developed.

[0004] As the aspect ratio of features etched into the material continues to increase, etching may not result in features with uniform dimensions. To address the contour control issue, passivation materials can be used to protect the sidewalls of existing features during further etching. However, as the aspect ratio continues to increase, passivation materials may require additional processing operations and / or may block features.

[0005] Therefore, there is a need for improved systems and methods that can be used to produce high-quality components and structures. These and other needs are addressed by this technology. Summary of the Invention

[0006] Semiconductor processing methods may include providing a silicon-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. Features may extend through one or more material layers disposed on the substrate. The method may include forming a plasma effluent containing the silicon-containing precursor and the oxygen-containing precursor. The method may include contacting the substrate with the plasma effluent containing the silicon-containing precursor and the oxygen-containing precursor. The contact may form silicon and oxygen-containing materials on at least the bottom portion of the feature. The temperature in the processing region may be maintained at less than or about 0°C.

[0007] In some embodiments, the silicon-containing precursor may further comprise a halogen. The silicon-containing precursor may be or comprise silicon tetrafluoride (SiF4). The oxygen-containing precursor may be or comprise diatomic oxygen (O2). Features can be characterized at a depth greater than or about 150 nm. One or more material layers may be or comprise alternating layers of oxygen-containing and nitrogen-containing materials. Plasma effluents of the silicon-containing and oxygen-containing precursors may be formed at a plasma power of less than or about 2,000 W. The method may include applying a bias power while contacting the substrate with the plasma effluents of the silicon-containing and oxygen-containing precursors. The bias power may be less than or about 2,500 W. The method may include etching features in the substrate before providing the silicon-containing and oxygen-containing precursors to the processing area.

[0008] Some embodiments of this technology may cover semiconductor processing methods. The methods may include providing a silicon- and halogen-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. Features may extend through one or more material layers disposed on the substrate. The methods may include forming a plasma effluent containing the silicon- and halogen-containing precursor and the oxygen-containing precursor. The methods may include contacting the substrate with the plasma effluent containing the silicon- and halogen-containing precursor and the oxygen-containing precursor. The contact may form a silicon- and oxygen- and halogen-containing material on at least the bottom portion of the feature.

[0009] In some embodiments, the flow rate ratio of the silicon-containing to the halogen-containing precursor relative to the oxygen-containing precursor may be greater than or about 10:1. The flow rate of the oxygen-containing precursor may be less than or about 25 sccm. The silicon-oxygen-halogen material may be formed in the same semiconductor processing chamber in which the feature is etched. The silicon-oxygen-halogen material may be physically adsorbed onto the feature. The temperature in the processing region may be maintained at less than or about -20°C. The pressure in the processing region may be maintained at less than or about 100 mTorr.

[0010] Some embodiments of this technology may cover semiconductor processing methods. Methods may include providing one or more etchant precursors to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. The substrate may include one or more material layers. Methods may include contacting the substrate with one or more etchant precursors. The contact may etch features into one or more material layers. Methods may include stopping the flow of one or more etchant precursors. Methods may include providing silicon-containing precursors and oxygen-containing precursors to the processing region. Methods may include forming plasma effluents of silicon-containing precursors and oxygen-containing precursors. Methods may include contacting the substrate with plasma effluents of silicon-containing precursors and oxygen-containing precursors. The contact may form a passivation material on at least the bottom portion of the feature. The temperature in the processing region may be maintained at less than or about 0°C.

[0011] In some embodiments, features can be characterized at a depth greater than or about 300 nm. The passivation material may be or include silicon-oxygen and halogen-containing materials.

[0012] This technology offers several advantages over conventional systems and techniques. For example, the process can provide non-conformal passivation materials that can be formed in situ. Furthermore, the passivation material can be formed at low temperatures to allow for physical adsorption rather than chemical adsorption, which prevents clogging of the openings of the features. These and other embodiments, along with their many advantages and features, will be described in more detail below with reference to the accompanying drawings. Attached Figure Description

[0013] A further understanding of the nature and advantages of the disclosed technology can be achieved by referring to the remainder of the specification and the accompanying drawings.

[0014] Figure 1 A schematic top plan view of an exemplary processing system according to some embodiments of the present technology is shown.

[0015] Figure 2 A schematic cross-sectional view of an exemplary processing system according to some embodiments of the present technology is shown.

[0016] Figure 3 The illustration shows selected operations in a semiconductor processing method according to some embodiments of the present technology.

[0017] Figures 4A to 4C The illustration shows a schematic cross-sectional view of the etched material according to some embodiments of the present technology.

[0018] Several accompanying drawings are included as schematic diagrams. It will be understood that the drawings are for illustrative purposes and are not considered to be to scale unless specifically mentioned otherwise. Furthermore, as schematic diagrams, the drawings are provided to aid understanding and may not include all aspects or information compared to the actual representation, and may include exaggerated material for illustrative purposes.

[0019] In the accompanying drawings, similar parts and / or features may have the same reference numerals. Additionally, parts of the same type may be distinguished by reference numerals followed by letters that differentiate them. If only the first reference numeral is used in this specification, the description applies to any of the similar parts having the same first reference numeral, regardless of the letters. Detailed Implementation

[0020] When features (such as trenches or holes) are etched into one or more material layers, passivation sidewalls maintain the profile throughout the entire depth of the etched feature. Subsequent etching is ideally selective for the material being etched and at least partially maintains the passivation material during subsequent etching. Conventional processes can perform ex-situ atomic layer deposition (ALD) to form the passivation material. However, these conventional processes require transferring the substrate to a separate tool, such as a separate semiconductor processing chamber. This ex-situ process requires additional steps in the processing flow, reduces throughput, and increases manufacturing costs. Other conventional processes have performed in-situ non-conformal passivation deposition. However, this deposition typically only protects a shallow portion of the feature and commonly results in clogging of the feature's openings. The resulting blockage prevents both etchant material and passivation material from penetrating the entire depth of the etched feature.

[0021] This technology overcomes these limitations by performing in-situ formation of passivation material at a reduced temperature. By forming the passivation material at a lower temperature, the passivation material may not chemically adsorb onto the sidewalls of the feature. Instead, the passivation material can be physically adsorbed and diffuse towards the bottom of the feature. Thus, this technology breaks down the conventional trade-off between blockage and contour control.

[0022] While the remainder of this disclosure will conventionally identify specific etching and deposition processes utilizing the disclosed techniques, it will be readily understood that the systems and methods are equivalently applicable to a variety of other processes that can occur within the described chambers. Therefore, the techniques should not be considered limited to use only with the described etching and deposition processes. Before describing methods or operations for systems and exemplary process sequences according to some embodiments of the present technology, this disclosure will discuss a possible system and chamber that can be used with the present technology. It will be understood that the present technology is not limited to the described apparatus and that the discussed processes can be performed in any number of processing chambers and systems.

[0023] Figure 1 The illustration shows a top plan view of one embodiment of a processing system 10 having deposition, etching, baking, and / or curing chambers according to an embodiment. Figure 1 The tool or processing system 10 depicted may include multiple processing chambers 24a-d, a transfer chamber 20, a service chamber 26, an integrated metering chamber 28, and a pair of load-locking chambers 16a-b. The processing chambers may include any number of structures or components, and any number of processing chambers or combinations of processing chambers.

[0024] For transporting substrates within a chamber, a transfer chamber 20 may include a robotic transport mechanism 22. The transport mechanism 22 may have a pair of remotely attached substrate transport blades 22a, each attached to an extendable arm 22b. The blades 22a can be used to carry individual substrates into and out of the processing chamber. In operation, one of the substrate transport blades (such as blade 22a of the transport mechanism 22) can retrieve a substrate W from one of the load-locking chambers (such as chambers 16a-b) and carry the substrate W to a first stage of processing, for example, the processing steps described below in chambers 24a-d. Chambers may be included to perform independent or combined operations of the described techniques. For example, while one or more chambers may be configured to perform deposition or etching operations, one or more other chambers may be configured to perform the described preprocessing operations and / or one or more post-processing operations. Any number of configurations are covered by this technology, and such configurations may also perform any number of additional manufacturing operations typically performed in semiconductor processing.

[0025] If a chamber is occupied, the robot can wait until processing is complete and then remove the processed substrate from the chamber using a blade 22a, and insert a new substrate using a second blade. Once the substrate has been processed, it can then be moved to the second stage of processing. For each move, the transport mechanism 22 typically has a blade carrying the substrate and an empty blade for performing substrate exchange. The transport mechanism 22 can wait at each chamber until the exchange can be completed.

[0026] Once processing is completed within the processing chamber, transport mechanism 22 can move substrate W from the final processing chamber and transport substrate W to a cassette within load-locking chambers 16a-b. The substrate can then be moved from load-locking chambers 16a-b into factory interface 12. Factory interface 12 is generally operable to transfer substrates between cassette loaders 14a-d and load-locking chambers 16a-b in an atmospheric pressure clean environment. For example, the clean environment in factory interface 12 can typically be provided by an air filtration process such as HEPA filtration. Factory interface 12 may also include a substrate orienter / aligner for properly aligning the substrate prior to processing. At least one substrate robot (such as robot 18a-b) can be positioned within factory interface 12 to transport substrates between various locations within factory interface 12 and to other locations in communication with it. Robot 18a-b can be configured to travel from a first end to a second end of factory interface 12 along a track system within factory interface 12.

[0027] The processing system 10 may further include an integrated metrology chamber 28 to provide control signals that can adaptively control any of the processes performed within the processing chamber. The integrated metrology chamber 28 may include any of various metrology elements to measure various film properties, such as thickness, roughness, and composition, and the metrology elements may further be capable of automatically characterizing grating parameters under vacuum, such as critical dimensions, sidewall angles, and feature heights.

[0028] Each of the processing chambers 24a-d can be configured to perform one or more processing steps during the fabrication of a semiconductor structure, and any number of processing chambers and combinations of processing chambers can be used in the multi-chamber processing system 10. For example, any of the processing chambers can be configured to perform several substrate processing operations, including any number of deposition processes, including cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, and other operations including etching, pre-cleaning, pretreatment, post-treatment, annealing, plasma treatment, degassing, orientation, and other substrate processes. Some specific processes that can be performed in any of the chambers or in any combination of chambers may be metal deposition, surface cleaning and preparation, thermal annealing (such as rapid thermal processing), and plasma treatment. Those skilled in the art will readily appreciate that any other process can be similarly performed in a specific chamber integrated into the multi-chamber processing system 10, including any processes described below.

[0029] Figure 2 A schematic cross-sectional view of an exemplary processing chamber 100 suitable for patterning a material layer disposed on a substrate 102 within a processing chamber 100 is shown. The exemplary processing chamber 100 is suitable for performing patterning processes, but it will be understood that aspects of this technology can be performed in any number of chambers, and substrate supports according to this technology can be included in etching chambers, deposition chambers, processing chambers, or any other processing chambers. The plasma processing chamber 100 may include a chamber body 105 defining a chamber volume 101 in which a substrate can be processed. The chamber body 105 may have sidewalls 112 coupled to a ground 126 and a bottom 118. The sidewalls 112 may have pads 115 for protecting the sidewalls 112 and extending the time between maintenance cycles of the plasma processing chamber 100. The dimensions of the chamber body 105 and related components of the plasma processing chamber 100 are not limited and are generally proportionally larger than the size of the substrate 102 to be processed therein. Examples of substrate sizes include 200 mm, 250 mm, 300 mm, and 450 mm diameters, as well as other diameters, such as those for display or solar cell substrates.

[0030] The chamber body 105 supports the chamber cover assembly 110 to enclose the chamber volume 101. The chamber body 105 may be made of aluminum or other suitable materials. A substrate inlet / outlet 113 may be formed through the sidewall 112 of the chamber body 105 to facilitate the transfer of the substrate 102 into and out of the plasma processing chamber 100. The inlet / outlet 113 may be coupled to the transfer chamber and / or other chambers of the substrate processing system as previously described. A pump port 145 may be formed through the sidewall 112 of the chamber body 105 and connected to the chamber volume 101. A pumping device may be coupled through the pump port 145 to the chamber volume 101 to evacuate and control the pressure within the processing volume. The pumping device may include one or more pumps and throttle valves.

[0031] Gas panel 160 can be coupled to chamber body 105 via gas line 167 to supply process gas to chamber volume 101. Gas panel 160 may include one or more process gas sources 161, 162, 163, 164 and may additionally include inert gases, non-reactive gases, and reactive gases, for use in any number of processes. Examples of process gases that can be provided by gas panel 160 include, but are not limited to, hydrocarbon gases, including methane, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon gases, argon, chlorine, nitrogen, helium, or oxygen, and any number of additional materials. In addition, process gases may include gases containing nitrogen, chlorine, fluorine, oxygen, and hydrogen, such as SiF4, O2, BCl3, C2F4, C4F8, C4F6, CHF3, CH2F2, CH3F, NF3, NH3, CO2, SO2, CO, N2, NO2, N2O, and H2, and any number of additional precursors.

[0032] Valve 166 controls the flow of process gas from sources 161, 162, 163, 164 from gas panel 160 and can be managed by controller 165. The flow of gas supplied from gas panel 160 to chamber body 105 may include a combination of gases from one or more sources. Cover assembly 110 may include nozzle 114. Nozzle 114 may be one or more ports for introducing process gas from sources 161, 162, 164, 163 of gas panel 160 into chamber volume 101. After the process gas is introduced into plasma processing chamber 100, the gas may be excited to form plasma. Antenna 148 (such as one or more inductor coils) may be provided adjacent to plasma processing chamber 100. Antenna power supply 142 may power antenna 148 via matching circuit 141 to inductively couple energy (such as RF energy) to the process gas to maintain plasma formed by the process gas in chamber volume 101 of plasma processing chamber 100. Alternatively, or in addition to the antenna power supply 142, processing electrodes below and / or above the substrate 102 may be used to couple RF power capacitors to the processing gas to maintain plasma within the chamber volume 101. The operation of the power supply 142 may be controlled by a controller (such as controller 165) that also controls the operation of other components in the plasma processing chamber 100.

[0033] A substrate support base 135 may be disposed within chamber volume 101 to support substrate 102 during processing. The substrate support base 135 may include an electrostatic chuck 122 for holding substrate 102 during processing. The electrostatic chuck (ESC) 122 may use electrostatic attraction to hold substrate 102 to substrate support base 135. ESC 122 may be powered by an RF power supply 125 integrated with matching circuitry 124. ESC 122 may include electrodes 121 embedded within a dielectric body. Electrodes 121 may be coupled to the RF power supply 125 and may provide a bias voltage to ESC 122 and substrate 102 resting on the base, attracting plasma ions formed by processing gases in chamber volume 101. During processing of substrate 102, the RF power supply 125 may be cyclically turned on and off, or pulsed. ESC 122 may have an isolator 128 to reduce the attraction of the sidewalls of ESC 122 to the plasma, thereby extending the maintenance life cycle of ESC 122. Additionally, the substrate support base 135 may have a cathode pad 136 to protect the sidewalls of the substrate support base 135 from the plasma gas and extend the time between maintenance cycles in the plasma processing chamber 100.

[0034] Electrode 121 may be coupled to power supply 150. Power supply 150 may provide a clamping voltage of about 200 volts to about 2000 volts to electrode 121. Power supply 150 may also include a system controller for controlling the operation of electrode 121 by directing DC current to electrode 121 for clamping and declamping substrate 102. ESC 122 may include a heater disposed within a base and connected to the power supply for heating the substrate, while cooling substrate 129 supporting ESC 122 may include conduits for circulating heat transfer fluid to maintain the temperature of ESC 122 and substrate 102 disposed thereon. ESC 122 may be configured to operate within the temperature range required by the thermal budget of the components manufactured on substrate 102. For example, depending on the process performed, ESC 122 may be configured to maintain substrate 102 at a temperature of about -150°C or lower to about 500°C or higher.

[0035] A cooling substrate 129 may be provided to assist in controlling the temperature of substrate 102. To mitigate process drift and time, the temperature of substrate 102 may be maintained substantially constant by the cooling substrate 129 throughout the time substrate 102 is in the cleaning chamber. In some embodiments, the temperature of substrate 102 may be maintained at a temperature between about -150°C and about 500°C throughout the subsequent cleaning process, but any temperature may be used. A cover ring 130 may be disposed on ESC 122 and along the periphery of substrate support base 135. Cover ring 130 may be configured to confine etching gases to a desired portion of the exposed top surface of substrate 102, while shielding the top surface of substrate support base 135 from the plasma environment inside plasma processing chamber 100. A lifting rod may be selectively translated across substrate support base 135 via a transfer robot as previously described or other suitable transfer mechanism to lift substrate 102 above substrate support base 135 to facilitate pickup of substrate 102.

[0036] The controller 165 can be used to control the process sequence, thereby regulating gas flow from the gas panel 160 to the plasma processing chamber 100, and other process parameters. When executed by the CPU, software routines transform the CPU into a dedicated computer, such as a controller, which can control the plasma processing chamber 100 to perform the process according to this disclosure. The software routines can also be stored and / or executed by a second controller, which can be associated with the plasma processing chamber 100.

[0037] The chambers discussed earlier can be used when performing exemplary methods including etching and deposition. (Go to...) Figure 3The illustration depicts exemplary operations in method 300 according to an embodiment of the present technology. Method 300 may include one or more operations prior to the start of the method, including pretreatment, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations. Method 300 may include several optional operations, which may or may not be specifically associated with some embodiments of the method according to the present technology. For example, many operations are described to provide a broader range of performed processes, but such operations are not critical to the technology or may be performed by alternative methods that will be discussed further below. Method 300 may be described in Figures 4A to 4C The operations illustrated in the figures are described in conjunction with the operational description of method 300. It will be understood that the figures show only partial schematic diagrams, and the substrate may contain any number of additional materials and features having the various properties and aspects shown in the figures.

[0038] Method 300 may or may not involve optional operations for developing semiconductor structures to specific manufacturing operations. It will be understood that method 300 can be performed on any number of semiconductor structures 400 or substrates 405, such as Figure 4A The illustration shows an exemplary structure on which passivation material deposition operations can be performed. The exemplary semiconductor structure may include trenches, vias, or other recessed features that may include one or more exposed materials. For example, the exemplary substrate may contain silicon or some other semiconductor substrate material and an interlayer dielectric material through which recesses, trenches, vias, or isolation structures may be formed. One or more material layers may be disposed on the substrate. For example, the material exposed at any time during the process may be or include one or more dielectric materials, contact materials, transistor materials, or any other materials that may be used in the semiconductor process.

[0039] For example, such as Figure 4A As shown, alternating layers of a first material layer 410 and a second material layer 415 may cover a substrate 405. The substrate 405 may be any number of materials used in semiconductor processing. The material of the substrate 405 may be or include silicon, germanium, dielectric materials including silicon oxide or silicon nitride, metallic materials, or any combination of these materials, which may be the substrate 405 or the material formed in structure 400. Figure 4A In the illustrated structure 400, the first material layer 410 may be an oxygen-containing material, such as a silicon-oxygen-containing material (e.g., silicon oxide). The second material layer 415 may be a nitrogen-containing material, such as a silicon-nitrogen-containing material (e.g., silicon nitride). Any number of pairs of the first material layer 410 and the second material layer 415 may exist on the substrate. A rigid molding material 420 may cover alternating layers of the first material layer 410 and the second material layer 415. The rigid molding material 420 may be patterned to include holes 425. The holes 425 may expose the underlying material, such as the first material layer 410 or the second material layer 415.

[0040] It will be understood that any amount of additional material may be formed in the illustrated structure 400. It will be understood that the structures mentioned are not intended to be limiting and similarly encompass any of a variety of other semiconductor structures. Other exemplary structures may include two-dimensional and three-dimensional structures common in semiconductor manufacturing, where passivation materials are required to maintain the dimensions and contours of features etched through one or more layers disposed on the substrate. For example, although this technique discusses a first material layer 410 or a second material layer 415 disposed on substrate 405, any other material (such as a carbon-containing material) may benefit from the passivation material deposition of this technique. Furthermore, while high aspect ratio structures may benefit from this technique, it is equally applicable to lower aspect ratios and any other structures.

[0041] like Figure 4B As shown, method 300 may include an optional operation of etching features into one or more material layers (such as a first material layer 410 or a second material layer 415) disposed on substrate 405. For example, method 300 may include providing one or more etchant precursors to a processing region of a semiconductor processing chamber at optional operation 305. The etchant precursor may include, for example, a halogen-containing precursor and a hydrogen-containing precursor. In an embodiment, the halogen-containing precursor may be a fluorine-containing precursor, such as nitrogen trifluoride (NF3). The hydrogen-containing precursor may be, for example, diatomic hydrogen (H2). Plasma effluents of the halogen-containing precursor and the hydrogen-containing precursor may be formed at optional operation 310. At optional operation 315, substrate 405 may be contacted with one or more etchant precursors or their plasma effluents. Contact may etch feature 430 into one or more material layers (such as a first material layer 410 or a second material layer 415) on the substrate. Although in Figure 4B Only one feature 430 is shown, but any number of features can be etched across structure 400.

[0042] The aspect ratio or height-to-width ratio of feature 430 may be greater than or about 2:1, greater than or about 3:1, greater than or about 5:1, greater than or about 10:1, greater than or about 20:1, or greater. Feature 430 may be characterized by a depth greater than or about 150 nm, and may be characterized by depths greater than or about 200 nm, greater than or about 250 nm, greater than or about 300 nm, greater than or about 350 nm, greater than or about 400 nm, greater than or about 450 nm, greater than or about 500 nm, greater than or about 550 nm, or greater.

[0043] To maintain the contour of feature 430 during subsequent etching, passivation material can be deposited within feature 430. In the prior art, conformal pads can be deposited using atomic layer deposition (ALD). However, ALD may require different semiconductor processing chambers, and conformal pads can be deposited ex-situ. Transferring substrates between different semiconductor processing chambers can reduce queue time and increase throughput. Additional prior art techniques can perform in-situ nonconformal deposition, but such prior art deposition can result in blockage toward the top of the feature (such as at the opening of the feature) and / or limited passivation or no passivation at the bottom of the feature. Such prior art in-situ nonconformal deposition can form passivation material that is chemically adsorbed and cannot reach the lower portion of the feature. Instead, as further discussed below, this technique provides passivation material that can be physically adsorbed in-situ onto the surface defining feature 430, which allows the passivation material to diffuse to the bottom of feature 430 and / or the etch front of feature 430.

[0044] After stopping the flow of one or more etchant precursors at optional operation 320, method 300 may include providing one or more deposition precursors to a processing region of a semiconductor processing chamber at operation 325. The one or more deposition precursors may include silicon-containing precursors and hydrogen-containing precursors. Plasma effluent from one or more precursors may be formed at operation 330. The plasma effluent from one or more deposition precursors (such as silicon-containing precursors and hydrogen-containing precursors) may contact a substrate 405 including the first material layer 410 and the second material layer 415 exposed in feature 430. Figure 4C As shown, a passivation material 435 may be formed in the contact 430. The passivation material 435 may be or include a silicon-containing material, such as a silicon-oxygen-containing material or a silicon-oxygen-halogen-containing material.

[0045] As previously discussed, the precursors used during method 300 and provided at operation 305 may include silicon-containing precursors and oxygen-containing precursors. In embodiments, the silicon-containing precursor may further include halogens. Halogens may be, but are not limited to, fluorine. Non-limiting silicon-containing precursors may be or include silanes (SiH4), disilanes (Si2H6), silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), or any other silicon-containing material. Furthermore, non-limiting oxygen-containing precursors may include diatomic oxygen (O2), water (H2O), hydrogen peroxide (H2O2), or any other oxygen-containing material. In embodiments, one or more inert precursors or carrier gases may be provided together with the silicon-containing precursor and the oxygen-containing precursor. In some embodiments, exemplary inert precursors or carrier gases may include one or more of argon, xenon, or helium, and any other non-reactive material.

[0046] In this embodiment, the flow rate of the silicon-containing precursor may be greater than that of the oxygen-containing precursor. For example, the flow rate ratio of the silicon-containing precursor to the oxygen-containing precursor may be greater than or about 10:1, and the flow rate ratio of the silicon-containing precursor to the oxygen-containing precursor may be greater than or about 11:1, greater than or about 12:1, greater than or about 13:1, greater than or about 14:1, greater than or about 15:1, greater than or about 16:1, greater than or about 17:1, greater than or about 18:1, greater than or about 20:1, greater than or about 25:1, greater than or about 30:1, greater than or about 35:1, or higher. The increased flow rate of the silicon-containing precursor may dilute the oxygen-containing precursor, which may unintentionally oxidize other materials disposed on the substrate 405.

[0047] In embodiments, the flow rate of the silicon-containing precursor may be greater than or about 50 sccm, and may be greater than or about 75 sccm, greater than or about 100 sccm, greater than or about 125 sccm, greater than or about 150 sccm, greater than or about 160 sccm, greater than or about 170 sccm, greater than or about 180 sccm, greater than or about 190 sccm, or greater. In embodiments, the flow rate of the oxygen-containing precursor may be less than or about 25 sccm, and may be less than or about 20 sccm, less than or about 15 sccm, less than or about 10 sccm, less than or about 9 sccm, less than or about 8 sccm, less than or about 7 sccm, less than or about 6 sccm, less than or about 5 sccm, or less.

[0048] Plasma effluents containing silicon and oxygen precursors can be formed at plasma powers of less than or about 2,500 W, and can be formed at plasma powers of less than or about 2,250 W, less than or about 2,000 W, less than or about 1,750 W, less than or about 1,500 W, less than or about 1,250 W, less than or about 1,000 W, less than or about 750 W, less than or about 500 W, or even lower. At higher plasma powers, the deposition rate can be increased, and the precise control over the deposition of the passivation material 435 can be reduced.

[0049] In an embodiment, method 200 may include applying a bias power while contacting the substrate 405 with the plasma effluent containing the silicon precursor and the oxygen precursor. The bias power may sputter a passivation material 435 at the bottom of feature 430, thereby leaving the passivation material only on the sidewalls of feature 430. To limit the sputtering of the passivation material 435 and minimize damage to other materials of structure 400, the bias power may be less than or about 2,500 W, and may be less than or about 2,250 W, less than or about 2,000 W, less than or about 1,750 W, less than or about 1,500 W, less than or about 1,250 W, less than or about 1,000 W, less than or about 750 W, less than or about 500 W, or even less.

[0050] like Figure 4C As shown, a passivation material 435 can be deposited in feature 430 at the contact at operation 335. Depending on the deposition precursor provided to the processing area, the passivation material can be a silicon-containing material, such as a silicon-oxygen-containing material or a silicon-oxygen-halogen-containing material. Although shown as an etch front covering feature 430, as previously discussed, the application of bias power can sputter the passivation material 435 from the etch front. In an embodiment, as previously discussed, the passivation material 435 (such as a silicon-oxygen-halogen-containing material) can be formed in the same semiconductor processing chamber in which feature 430 is etched.

[0051] Processing conditions can influence and promote deposition according to the present technology. For example, the temperature at which the operation is performed can affect the formation location of the passivation material 435. During contact between the substrate 405 and the plasma effluent, a reduced temperature can promote the physical adsorption of the passivation material 435 and prevent chemisorption. By preventing chemisorption, the passivation material 435 can diffuse to the bottom of the feature 430, which prevents blockage of the opening of the feature 430. Thus, in some embodiments of the present technology, method 300 can be performed at a substrate, base, and / or chamber temperature below or about 50°C, and at temperatures below or about 25°C, below or about 0°C, below or about -10°C, below or about -20°C, below or about -30°C, below or about -40°C, below or about -50°C, below or about -60°C, below or about -70°C, below or about -80°C, below or about -90°C, below or about -100°C, or lower. Temperature can also be maintained within these ranges, within a smaller range covered by these ranges, or at any temperature between any of these ranges.

[0052] The pressure within the processing area of ​​the semiconductor processing chamber can also affect the performed operation. To facilitate the deposition of passivation material 435, the processing pressure can be less than or about 100 mTorr, and can be maintained at less than or about 80 mTorr, less than or about 60 mTorr, less than or about 40 mTorr, less than or about 20 mTorr, less than or about 15 mTorr, less than or about 10 mTorr, or even lower. The pressure can also be maintained within these ranges, within a smaller range encompassed by these ranges, or at any pressure between any of these ranges.

[0053] In the foregoing description, several details have been set forth for illustrative purposes to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0054] Given that several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, several well-known processes and elements have not been described to avoid unnecessarily obscuring the technology. Therefore, the above description should not be considered as limiting the scope of the technology.

[0055] Where a range of values ​​is provided, it will be understood that, unless the context explicitly indicates otherwise, the minimum fraction of each mediating value to the lower limit unit between the upper and lower limits of that range is also specifically disclosed. This encompasses any narrower range between any mentioned value or mediating value not mentioned in the mentioned range and any other mentioned value or mediating value in the mentioned range. The upper and lower limits of such narrower ranges may independently include or exclude them, and each range (where any limit, no limit, or both limit values ​​are included in the narrower range) is also covered within the scope of any specifically excluded limit value in the mentioned range. Where a mentioned range includes one or two limit values, the range excluding any one or both of those included limit values ​​is also included.

[0056] As used herein and in the appended claims, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” include plural references. Thus, for example, reference to “a precursor” includes a plurality of such precursors, and reference to “the material” includes reference to one or more materials and their equivalents known to those skilled in the art, etc.

[0057] Furthermore, when used in this specification and the following claims, the terms “comprise(s)”, “comprising”, “contain(s)”, “containing”, “include(s)”, and “including” are intended to specify the presence of the mentioned feature, integer, component, or operation, but such terms do not exclude the presence or addition of one or more other features, integers, components, operations, actions, or groups.

Claims

1. A semiconductor processing method, comprising: A silicon-containing precursor and an oxygen-containing precursor are provided to a processing region of a semiconductor processing chamber, wherein a substrate is housed within the processing region, and wherein features are described. Extending through one or more material layers disposed on the substrate; Plasma effluents forming the silicon-containing precursor and the oxygen-containing precursor; as well as The substrate is brought into contact with the plasma effluent of the silicon-containing precursor and the oxygen-containing precursor, wherein the contact forms a silicon- and oxygen-containing material on at least one bottom portion of the feature, and wherein the temperature in the processing region is maintained at less than or about 0°C.

2. The semiconductor processing method of claim 1, wherein the silicon-containing precursor further comprises a halogen.

3. The semiconductor processing method of claim 1, wherein the silicon-containing precursor comprises silicon tetrafluoride (SiF4).

4. The semiconductor processing method of claim 1, wherein the oxygen-containing precursor comprises diatomic oxygen (O2).

5. The semiconductor processing method of claim 1, wherein the feature is characterized by a depth greater than or about 150 nm.

6. The semiconductor processing method of claim 1, wherein the one or more material layers comprise alternating layers of oxygen-containing materials and nitrogen-containing materials.

7. The semiconductor processing method of claim 1, wherein the plasma effluent of the silicon-containing precursor and the oxygen-containing precursor is formed at a plasma power of less than or about 2,000 W.

8. The semiconductor processing method of claim 1, further comprising: A bias power is applied when the substrate is brought into contact with the plasma effluent of the silicon-containing precursor and the oxygen-containing precursor.

9. The semiconductor processing method of claim 8, wherein the bias power is less than or about 2,500 W.

10. The semiconductor processing method of claim 1, further comprising: The features are etched in the substrate before the silicon-containing precursor and the oxygen-containing precursor are provided to the processing region.

11. A semiconductor processing method, comprising: A silicon-containing and halogen-containing precursor and an oxygen-containing precursor are provided to a processing region of a semiconductor processing chamber, wherein a substrate is housed within the processing region, and wherein features are described. Extending through one or more material layers disposed on the substrate; The plasma effluent containing the silicon and halogen precursors and the oxygen-containing precursors is formed; as well as The substrate is brought into contact with the plasma effluent of the silicon- and halogen-containing precursor and the oxygen-containing precursor, wherein the contact forms a silicon-, oxygen-, and halogen-containing material on at least the bottom portion of the feature.

12. The semiconductor processing method of claim 11, wherein the flow rate ratio of the silicon-containing precursor to the halogen precursor relative to the oxygen-containing precursor is greater than or about 10:

1.

13. The semiconductor processing method of claim 11, wherein the flow rate of the oxygen-containing precursor is less than or about 25 sccm.

14. The semiconductor processing method of claim 11, wherein the silicon-oxygen and halogen-containing material is formed in the same semiconductor processing chamber in which the features are etched.

15. The semiconductor processing method of claim 11, wherein the silicon-containing oxygen and halogen material are physically adsorbed onto the feature.

16. The semiconductor processing method of claim 11, wherein the temperature in the processing region is maintained at less than or about -20°C.

17. The semiconductor processing method of claim 11, wherein the pressure in the processing region is maintained at less than or about 100 mTorr.

18. A semiconductor processing method, comprising: One or more etchant precursors are provided to a processing region of a semiconductor processing chamber, wherein a substrate is housed within the processing region, and wherein the substrate comprises one or more material layers; The substrate is brought into contact with one or more etchant precursors, wherein the contact etches features into one or more material layers; Stop the flow of the one or more etchant precursors; The silicon-containing precursor and the oxygen-containing precursor are provided to the processing area; Plasma effluents forming the silicon-containing precursor and the oxygen-containing precursor; as well as The substrate is brought into contact with the plasma effluent of the silicon-containing precursor and the oxygen-containing precursor, wherein the contact forms a passivation material on at least the bottom portion of the feature, and wherein the temperature in the processing region is maintained at less than or about 0°C.

19. The semiconductor processing method of claim 18, wherein the feature is characterized by a depth greater than or about 300 nm.

20. The semiconductor processing method of claim 18, wherein the passivation material comprises a silicon-oxygen and halogen-containing material.

Images