Relay protection test waveform generation method and system, terminal and storage medium

Abstract

The invention discloses a relay protection test waveform generation method and system, a terminal and a storage medium, and belongs to the field of relay protection test waveform generation, and the method is applied to a harmonic processing device, and comprises the steps: obtaining harmonic data based on a preset harmonic generation algorithm and harmonic parameters; receiving fundamental wave data sent by the fundamental wave processing device, and superposing the fundamental wave data and the harmonic wave data to obtain fundamental harmonic mixed waveform data; obtaining a current harmonic storage state and a current direct current attenuation storage state, and obtaining a current mixed transmission state based on the fundamental harmonic mixed waveform data, the current harmonic storage state and the current direct current attenuation storage state; and transmitting the fundamental harmonic mixed waveform data to a direct current attenuation processing device based on the current mixed transmission state, so that the direct current attenuation processing device obtains a direct current attenuation parameter to obtain direct current attenuation data, and then superposing the fundamental harmonic mixed waveform data and the direct current attenuation parameter to obtain a relay protection test waveform. Therefore, the accuracy of the generated relay protection test waveform is improved.

Description

Technical Field

[0001] This invention relates to the field of relay protection test waveform generation technology, and in particular to a relay protection test waveform generation method, system, terminal and storage medium. Background Technology

[0002] With the continuous development of power systems and the improvement of their intelligence level, relay protection testing equipment plays an increasingly important role in power systems. Relay protection testing equipment often needs to generate a variety of complex test waveforms to verify the accuracy of relay protection device operation.

[0003] Currently, multi-stage pipeline processing technology is commonly used to decompose complex test tasks into multiple small modules, each completing a specific task. These modules are connected in a pipeline manner, enabling them to execute in parallel. In other words, traditional relay protection test waveform generation schemes mostly adopt a serial processing architecture, where the generation and superposition of fundamental, harmonic, and DC attenuation data must be performed in a fixed order.

[0004] This method has significant technical bottlenecks, such as interstage blocking leading to waveform breakage: in the serial processing architecture of fundamental, harmonic, and transient disturbances, downstream module processing delays can cause upstream data loss, especially when simulating high-frequency transients, where waveform continuity cannot be guaranteed. Accumulated phase synchronization errors: the propagation delay of handshake signals in multi-stage pipelines can cause phase mismatch between the fundamental and harmonics, leading to distortion of harmonic analysis results, etc. Summary of the Invention

[0005] This invention provides a method, system, terminal, and storage medium for generating relay protection test waveforms, which can improve the accuracy of the generated relay protection test waveforms.

[0006] This invention discloses a method for generating test waveforms for relay protection, applied to a harmonic processing device. The method includes: Harmonic parameters are obtained, and harmonic data is obtained based on a preset harmonic generation algorithm and the harmonic parameters; The fundamental wave data sent by the fundamental wave processing device is received, and then the fundamental wave data and the harmonic data are superimposed to obtain fundamental-harmonic mixed waveform data. Obtain the current harmonic storage state and the current DC attenuation storage state, and then obtain the current hybrid transmission state based on the fundamental harmonic hybrid waveform data, the current harmonic storage state, and the current DC attenuation storage state; Based on the current hybrid transmission state, the fundamental harmonic hybrid waveform data is transmitted to the DC attenuation processing device so that the DC attenuation processing device can obtain the DC attenuation parameters and obtain the DC attenuation data based on the preset DC attenuation generation algorithm and the DC attenuation parameters. Then, the fundamental harmonic hybrid waveform data and the DC attenuation parameters are superimposed to obtain the relay protection test waveform. The step of obtaining the harmonic parameters based on the fundamental wave processing device includes: Obtain the fundamental wave parameters, and based on the preset fundamental wave generation algorithm and the fundamental wave parameters, obtain the fundamental wave data; Obtain the current fundamental wave storage state, and obtain the current fundamental wave transmission state based on the fundamental wave data, the current fundamental wave storage state, and the current harmonic storage state; Based on the current fundamental wave transmission state, the fundamental wave data is transmitted to the harmonic processing device.

[0007] In the above scheme, the fundamental wave processing device accurately determines the current fundamental wave transmission state by acquiring the current fundamental wave storage state and the current harmonic storage state of the harmonic processing device, thus avoiding the loss of fundamental wave data due to the harmonic processing device being full. The harmonic processing device determines the current mixed transmission state by acquiring the current harmonic storage state and the current DC attenuation storage state of the DC attenuation processing device, ensuring stable transmission of fundamental and harmonic mixed waveform data, effectively solving the waveform breakage problem in traditional schemes, eliminating interstage transmission blockage, and ensuring waveform continuity. The fundamental wave processing device transmits fundamental wave data to the harmonic processing device based on the current fundamental wave transmission state, ensuring the timeliness of the superposition of fundamental wave and harmonic data. The harmonic processing device transmits fundamental-harmonic hybrid waveform data to the DC attenuation processing device based on the current mixed transmission state, ensuring accurate superposition of the fundamental-harmonic hybrid waveform data and DC attenuation data. This avoids waveform distortion caused by data asynchrony in traditional solutions, improving the accuracy of relay protection test waveforms. In the system, the fundamental wave processing device processes fundamental wave parameters based on a preset fundamental wave generation algorithm, the harmonic processing device processes harmonic parameters based on a preset harmonic wave generation algorithm, and the DC attenuation processing device processes DC attenuation parameters based on a preset DC attenuation generation algorithm. Furthermore, each device collaboratively optimizes the data transmission rhythm through stored states, improving the efficiency of relay protection test waveform generation. In summary, this improves the accuracy and reliability of the generated relay protection test waveforms.

[0008] Further, the step of transmitting the fundamental frequency data to the harmonic processing device based on the current fundamental frequency transmission state includes: Retrieve data stored in the harmonic buffer register and the harmonic output register; The current harmonic storage state is determined based on the data stored in the harmonic buffer register and the data stored in the harmonic output register.

[0009] In the above scheme, by obtaining the data stored in the harmonic buffer register and the harmonic output register, the data storage status of the harmonic processing device can be accurately grasped, providing a direct basis for subsequent judgment of the current harmonic storage status and providing a data foundation for judging the storage status of the harmonic processing device.

[0010] Further, determining the current harmonic storage state based on the data stored in the harmonic buffer register and the data stored in the harmonic output register includes: When the harmonic buffer register stores no fundamental wave data and the harmonic output register stores fundamental wave data, or when neither the harmonic buffer register nor the harmonic output register stores fundamental wave data, the current harmonic storage state is determined to be acceptable. When the fundamental wave data is received and the current harmonic storage state is receivable, the current fundamental wave transmission state is updated to allow the fundamental wave data to be transmitted to the harmonic processing device.

[0011] In the above scheme, based on the data stored in the harmonic buffer register and the data stored in the harmonic output register, when the data stored in the harmonic buffer register does not contain the fundamental wave data, and the data stored in the harmonic output register does contain the fundamental wave data, or when neither the data stored in the harmonic buffer register nor the data stored in the harmonic output register contains the fundamental wave data, it indicates that the harmonic processing device still has space to receive new data. Therefore, the current harmonic storage state is accurately determined to be receivable. When the fundamental wave data is received and the harmonic storage state is receivable, the current fundamental wave transmission state is updated to be transmittable in a timely manner, ensuring that the fundamental wave data can be successfully transmitted when the harmonic processing device is receivable, and avoiding problems caused by improper data transmission timing.

[0012] Further, determining the current harmonic storage state based on the data stored in the harmonic buffer register and the data stored in the harmonic output register includes: When both the harmonic buffer register and the harmonic output register store the fundamental wave data, the current fundamental wave transmission status is updated to indicate that the fundamental wave data cannot be transmitted to the harmonic processing device.

[0013] In the above scheme, when both the harmonic buffer register and the harmonic output register contain fundamental wave data, it means that the harmonic processing device has no extra space to receive data. Therefore, updating the current fundamental wave transmission status to non-transmittable can effectively prevent fundamental wave data from continuing to be transmitted when the harmonic processing device is full, avoid data redundancy or overwriting, and ensure the rationality of data transmission.

[0014] Further, the step of obtaining the current harmonic storage state and the current DC attenuation storage state, and then obtaining the current hybrid transmission state based on the fundamental harmonic hybrid waveform data, the current harmonic storage state, and the current DC attenuation storage state, includes: Retrieve the data stored in the DC attenuation buffer register and the DC attenuation output register; When both the DC attenuation buffer register and the DC attenuation output register do not store the fundamental harmonic mixed waveform data, or when the DC attenuation buffer register does not store the fundamental harmonic mixed waveform data and the DC attenuation output register stores the fundamental harmonic mixed waveform data, then the current DC attenuation storage state is acceptable. When the fundamental harmonic mixed waveform data is received and the current DC attenuation storage state is receivable, the current mixed transmission state is updated to allow the transmission of the fundamental harmonic mixed waveform data to the DC attenuation processing device.

[0015] In the above scheme, the data stored in the DC attenuation buffer register and the DC attenuation output register are obtained. When there is still extra space in the DC attenuation processing device, the current DC attenuation storage state is determined. When the DC attenuation storage state is receivable and the fundamental harmonic mixed waveform data is received, the current mixed transmission state is updated to be transmittable. This ensures that the fundamental harmonic mixed waveform data is accurately transmitted when the DC attenuation processing device is receivable, thereby improving the effectiveness of data transmission.

[0016] Further, the step of obtaining the current harmonic storage state and the current DC attenuation storage state, and then obtaining the current hybrid transmission state based on the fundamental harmonic hybrid waveform data, the current harmonic storage state, and the current DC attenuation storage state, includes: When both the DC attenuation buffer register and the DC attenuation output register store the fundamental harmonic mixed waveform data, the current mixed transmission state is updated to indicate that the fundamental harmonic mixed waveform data cannot be transmitted to the DC attenuation processing device.

[0017] In the above scheme, if both the DC attenuation buffer register and the DC attenuation output register store fundamental harmonic mixed waveform data, it indicates that the DC attenuation processing device is saturated. Therefore, updating the current mixed transmission status to non-transmittable can prevent the fundamental harmonic mixed waveform data from continuing to be transmitted when the DC attenuation processing device is saturated, thus preventing data abnormalities and ensuring the stability of data transmission.

[0018] Further, the DC attenuation parameters include DC attenuation amplitude and time constant parameters. Based on the current mixed transmission state, the fundamental harmonic mixed waveform data is transmitted to the DC attenuation processing device, so that the DC attenuation processing device obtains the DC attenuation parameters and, based on a preset DC attenuation generation algorithm and the DC attenuation parameters, obtains DC attenuation data. Then, the fundamental harmonic mixed waveform data and the DC attenuation parameters are superimposed to obtain the relay protection test waveform, including: The DC attenuation amplitude is accumulated by using the time constant parameter to obtain the DC attenuation data.

[0019] In the above scheme, the DC attenuation amplitude is accumulated by using the time constant parameter to obtain DC attenuation data. Combined with the fundamental harmonic mixed waveform data, the waveform of DC attenuation data can be accurately generated.

[0020] Another embodiment of the present invention provides a relay protection test waveform generation system, comprising: a fundamental wave processing device, a harmonic wave processing device, and a DC attenuation processing device, wherein: The fundamental wave processing device acquires fundamental wave parameters and obtains fundamental wave data based on a preset fundamental wave generation algorithm and the fundamental wave parameters; The fundamental wave processing device acquires the current fundamental wave storage state and obtains the current fundamental wave transmission state based on the fundamental wave data, the current fundamental wave storage state, and the current harmonic storage state. Based on the current fundamental wave transmission state, the fundamental wave processing device transmits the fundamental wave data to the harmonic processing device; The harmonic processing device receives the harmonic parameters sent by the fundamental wave processing device, and obtains harmonic data based on the preset harmonic generation algorithm and the harmonic parameters. Then, the fundamental wave data and the harmonic data are superimposed to obtain fundamental-harmonic hybrid waveform data. The harmonic processing device acquires the current harmonic storage state and the current DC attenuation storage state, and then obtains the current hybrid transmission state based on the fundamental harmonic hybrid waveform data, the current harmonic storage state, and the current DC attenuation storage state; Based on the current mixed transmission state, the harmonic processing device transmits the fundamental harmonic mixed waveform data to the DC attenuation processing device; The DC attenuation processing device acquires DC attenuation parameters, and obtains DC attenuation data based on a preset DC attenuation generation algorithm and the DC attenuation parameters. Then, the fundamental harmonic mixed waveform data and the DC attenuation parameters are superimposed to obtain the relay protection test waveform.

[0021] Another embodiment of the present invention provides a terminal device, including: a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the steps of the relay protection test waveform generation method of the present invention.

[0022] Another embodiment of the present invention provides a computer-readable storage medium item, including: a stored computer program, which, when the computer program is running, controls the device where the computer-readable storage medium is located to perform the steps of the relay protection test waveform generation method of the present invention. Attached Figure Description

[0023] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 This is a flowchart illustrating a relay protection test waveform generation method provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a relay protection test waveform generation system provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of the harmonic temporary storage buffer in the harmonic processing device provided in the embodiment of the present invention; Figure 4 This is a schematic diagram of the timing of the synchronous handshake between the output data validity signal and the storage state provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the asynchronous handshake timing of the output data valid signal and storage state provided in an embodiment of the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0027] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0028] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0029] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0030] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0031] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0032] See Figure 1To improve the accuracy of generated relay protection test waveforms, an embodiment of the present invention provides a relay protection test waveform generation method, applied to a harmonic processing device, the method comprising: Step S1: Obtain harmonic parameters and, based on the preset harmonic generation algorithm and harmonic parameters, obtain harmonic data; Step S2: Receive the fundamental wave data sent by the fundamental wave processing device, and then superimpose the fundamental wave data and harmonic data to obtain fundamental harmonic mixed waveform data; Step S3: Obtain the current harmonic storage state and the current DC attenuation storage state, and then obtain the current hybrid transmission state based on the fundamental harmonic hybrid waveform data, the current harmonic storage state, and the current DC attenuation storage state; Step S4: Based on the current mixed transmission state, transmit the fundamental harmonic mixed waveform data to the DC attenuation processing device so that the DC attenuation processing device can obtain the DC attenuation parameters and obtain the DC attenuation data based on the preset DC attenuation generation algorithm and the DC attenuation parameters. Then, the fundamental harmonic mixed waveform data and the DC attenuation parameters are superimposed to obtain the relay protection test waveform. The steps for obtaining harmonic parameters based on the fundamental wave processing device include: Obtain the fundamental wave parameters, and based on the preset fundamental wave generation algorithm and fundamental wave parameters, obtain the fundamental wave data; Obtain the current fundamental wave storage state, and based on the fundamental wave data, the current fundamental wave storage state, and the current harmonic storage state, obtain the current fundamental wave transmission state; Based on the current fundamental wave transmission status, the fundamental wave data is transmitted to the harmonic processing device.

[0033] In the above scheme, the fundamental wave processing device accurately determines the current fundamental wave transmission state by acquiring the current fundamental wave storage state and the current harmonic storage state of the harmonic processing device, thus avoiding the loss of fundamental wave data due to the harmonic processing device being full. The harmonic processing device determines the current mixed transmission state by acquiring the current harmonic storage state and the current DC attenuation storage state of the DC attenuation processing device, ensuring stable transmission of fundamental and harmonic mixed waveform data, effectively solving the waveform breakage problem in traditional schemes, eliminating interstage transmission blockage, and ensuring waveform continuity. The fundamental wave processing device transmits fundamental wave data to the harmonic processing device based on the current fundamental wave transmission state, ensuring the timeliness of the superposition of fundamental wave and harmonic data. The harmonic processing device transmits fundamental-harmonic hybrid waveform data to the DC attenuation processing device based on the current mixed transmission state, ensuring accurate superposition of the fundamental-harmonic hybrid waveform data and DC attenuation data. This avoids waveform distortion caused by data asynchrony in traditional solutions, improving the accuracy of relay protection test waveforms. In the system, the fundamental wave processing device processes fundamental wave parameters based on a preset fundamental wave generation algorithm, the harmonic processing device processes harmonic parameters based on a preset harmonic wave generation algorithm, and the DC attenuation processing device processes DC attenuation parameters based on a preset DC attenuation generation algorithm. Furthermore, each device collaboratively optimizes the data transmission rhythm through stored states, improving the efficiency of relay protection test waveform generation. In summary, this improves the accuracy and reliability of the generated relay protection test waveforms.

[0034] Furthermore, the step of obtaining the harmonic parameters based on the fundamental wave processing device includes: Obtain the fundamental wave parameters, and based on the preset fundamental wave generation algorithm and the fundamental wave parameters, obtain the fundamental wave data; Obtain the current fundamental wave storage state, and obtain the current fundamental wave transmission state based on the fundamental wave data, the current fundamental wave storage state, and the current harmonic storage state; Based on the current fundamental wave transmission state, the fundamental wave data is transmitted to the harmonic processing device.

[0035] Specifically, in this scheme, the fundamental frequency processing unit is PIPE1, the harmonic processing unit is PIPE2, and the DC attenuation processing unit is PIPE3. PIPE1, PIPE2, and PIPE3 together constitute an FPGA multi-stage pipelined architecture. Each processing unit includes a generation unit, registers, and a temporary buffer. The temporary buffer includes a data path and a control path, with the control path consisting of a state control module. The data path includes an N-bit wide data buffer register, an N-bit wide data output register, and a 2-to-1 selector. The fundamental frequency processing unit, harmonic processing unit, and DC attenuation processing unit perform pipelined processing sequentially. For example, for the harmonic processing unit, the fundamental frequency processing unit is upstream, and the DC attenuation processing unit is downstream. The state control module receives the upstream output data valid signal and the downstream storage status signal, and generates a storage status signal for the current pipeline level and an output data valid signal for the downstream pipeline to complete the control handshake with the upstream and downstream pipelines. Simultaneously, it generates a first write control signal for the data buffer register, a second write control signal for the data output register, and a selection control signal for the 2-to-1 selector to control the data flow selection in the data path. The data input signal is first connected to the data buffer register and written into it under the action of the first write control signal generated by the state control module. The data buffer register and the data input of this pipeline are connected together to the data selector. Then, the state control module generates a data selection signal to determine whether the data output of this pipeline is a data input signal or a data buffer signal. Finally, the state control module generates a second write control signal to determine whether the signal output by the selector is written to the data output register.

[0036] Furthermore, the state control module generates state signals and control signals. It mainly consists of a state machine, and its state transition diagram is as follows: Figure 3 As shown in the diagram. The EMPTY state indicates that neither the data buffer register nor the data output register contains data; the BUSY state indicates that the data output register has data to be processed, while the data buffer register is empty; and the FULL state indicates that both the data buffer register and the data output register contain data to be processed.

[0037] Furthermore, an input-side handshake signal is defined, which is valid when the upstream output data valid signal and the current pipeline's storage status signal are high (i.e., logic 1, representing executable status). An output-side handshake signal is also defined, which is valid when the current pipeline's output data valid signal to the downstream and the storage status signal from the downstream are high. When the state control module is in EMPTY state, only input-side data handshake is supported; when the state control module is in FULL state, only output-side data handshake is supported. This avoids data overwriting and secondary reading.

[0038] Furthermore, based on the state transition diagram of the state control module, five state transition operations are defined. The initial system state is EMPTY, meaning neither the data buffer register nor the data output register contains data. If an input handshake signal is valid, data will be directly loaded into the data output register, and the system state will transition to BUSY. This operation is defined as Load. When the system state is BUSY, meaning the data buffer register is empty but the data output register contains data, if there is an input handshake but no output handshake (input handshake signal valid, output handshake signal invalid), the first write control signal is pulled high. Input data is then filled into the data buffer register, and the system state will transition to FULL. This operation is defined as Fill. When the system state is BUSY, if both input and output handshake signals are present (input handshake signal valid, output handshake signal valid), the data output... While the register data is received by the downstream pipeline, the input data is filled into the data output register, and the system remains in the BUSY state. This operation is defined as Flow. When the system is in the BUSY state, if there is an output handshake but no input handshake (input handshake signal is invalid, output handshake signal is valid), the data in the data output register is received by the downstream pipeline, and both the data buffer register and the data output register are empty. The system state will transition to the EMPTY state. This operation is defined as Unload. When the system is in the FULL state, if there is an output handshake but no input handshake (input handshake signal is invalid, output handshake signal is valid), the data in the data output register is received by the downstream pipeline, and the data in the data buffer register is loaded into the data output register. The system state will transition to the BUSY state. This operation is defined as Flush. This process repeats to complete the state transition. Load: Loading operation. Unload: Unload operation; Fill: Fill operation; Flush: Clear operation; Flow: Flow operation.

[0039] The following is for reference Figure 2 and Figure 3Taking a harmonic processing device as an example: the harmonic processing device includes a harmonic waveform generation unit, a harmonic register, and a harmonic temporary storage buffer. The harmonic waveform generation unit receives harmonic parameters and generates harmonic data. After calculating the harmonic data at the current moment, the harmonic waveform generation unit stores it in the harmonic register, and the harmonic temporary storage buffer can retrieve data from the harmonic register. The harmonic temporary storage buffer includes a harmonic data path and a harmonic control path. The harmonic control path consists of a harmonic state control module. The harmonic data path includes an N-bit wide harmonic buffer register, an N-bit wide harmonic output register, and a 2-to-1 harmonic selector. The harmonic state control module receives the output data validity signal from the upstream fundamental wave processing device and sends the current harmonic storage state to the upstream fundamental wave processing device. The harmonic state control module receives the attenuation storage state signal output by the downstream DC attenuation processing device, i.e., the current DC attenuation storage state. Simultaneously, the harmonic processing device generates an output data validity signal for the downstream DC attenuation processing device to complete the control handshake with the downstream flow. Simultaneously, the harmonic state control module generates a first harmonic write control signal for the harmonic buffer register, a second harmonic write control signal for the harmonic output register, and a harmonic selection control signal for the 2-to-1 harmonic selector to complete the data stream selection control of the harmonic data path. The fundamental frequency data is first connected to the harmonic data buffer register and written into it under the action of the first harmonic write control signal generated by the harmonic state control module. The harmonic data buffer register and the current pipeline's input harmonic data are connected together to the harmonic selector. Then, the harmonic state control module generates a harmonic selection control signal to control the harmonic selector to determine whether the current pipeline's output data is the latest current pipeline input fundamental frequency data or fundamental frequency data buffered in the harmonic data buffer. Finally, the harmonic state control module generates a second harmonic write control signal to determine whether the signal output by the harmonic selector is written to the harmonic output register.

[0040] In another embodiment, transmitting the fundamental frequency data to the harmonic processing device based on the current fundamental frequency transmission state includes: Retrieve data stored in the harmonic buffer register and the harmonic output register; The current harmonic storage state is determined based on the data stored in the harmonic buffer register and the data stored in the harmonic output register.

[0041] It should be noted that the data buffer register in the harmonic processing device is the same as the harmonic buffer register, and the data output register is the same as the harmonic output register. Correspondingly, the storage status of the harmonic buffer register is obtained to get the data stored in the harmonic buffer register, and the storage status of the harmonic output register is obtained to get the data stored in the harmonic output register. The current harmonic storage state is determined based on the data stored in the harmonic buffer register and the data stored in the harmonic output register.

[0042] In another embodiment, determining the current harmonic storage state based on the data stored in the harmonic buffer register and the data stored in the harmonic output register includes: When the harmonic buffer register stores no fundamental wave data and the harmonic output register stores fundamental wave data, or when neither the harmonic buffer register nor the harmonic output register stores fundamental wave data, the current harmonic storage state is determined to be acceptable. When the fundamental wave data is received and the current harmonic storage state is receivable, the current fundamental wave transmission state is updated to allow the fundamental wave data to be transmitted to the harmonic processing device.

[0043] It should be noted that since the fundamental frequency processing module is in the first position, there is no need to define the input-side handshake signal for the fundamental frequency processing module. Instead, an output-side handshake signal for the fundamental frequency processing module is defined. This signal is valid when the output data valid signal to the harmonic processing module and the current harmonic storage state from the harmonic processing module are both high (a high output data valid signal to the harmonic processing module indicates the presence of fundamental frequency data, and a high current harmonic storage state from the harmonic processing module indicates that the current harmonic storage state is receivable; the harmonic processing module is either idle or busy). This confirms that the current fundamental frequency transmission state is ready to transmit the fundamental frequency data to the harmonic processing device. Specifically, the harmonic processing module state EMPTY (idle) indicates that there is no fundamental frequency data in either the fundamental frequency buffer register or the fundamental frequency output register; the harmonic processing module state BUSY (busy) indicates that the fundamental frequency output register has fundamental frequency data to be processed, while the fundamental frequency buffer register has no fundamental frequency data; and the harmonic processing module state FULL (saturated) indicates that both the fundamental frequency buffer register and the fundamental frequency output register have fundamental frequency data to be processed. What is understandable is that the harmonic buffer register and the harmonic output register both store the fundamental wave data to be processed. Then, the fundamental wave data in the harmonic output register is superimposed with the harmonic data to obtain the fundamental-harmonic mixed waveform data.

[0044] In another embodiment, determining the current harmonic storage state based on the data stored in the harmonic buffer register and the data stored in the harmonic output register includes: When both the harmonic buffer register and the harmonic output register store the fundamental wave data, the current fundamental wave transmission status is updated to indicate that the fundamental wave data cannot be transmitted to the harmonic processing device.

[0045] It should be noted that when both the harmonic buffer register and the harmonic output register store the fundamental wave data (i.e., the harmonic processing module is saturated), it means that the harmonic processing module can no longer receive any extra data. Therefore, the current fundamental wave transmission status is updated to indicate that the fundamental wave data cannot be transmitted to the harmonic processing device.

[0046] In another embodiment, obtaining the current harmonic storage state and the current DC attenuation storage state, and then obtaining the current hybrid transmission state based on the fundamental harmonic hybrid waveform data, the current harmonic storage state, and the current DC attenuation storage state, includes: Retrieve the data stored in the DC attenuation buffer register and the DC attenuation output register; When both the DC attenuation buffer register and the DC attenuation output register do not store the fundamental harmonic mixed waveform data, or when the DC attenuation buffer register does not store the fundamental harmonic mixed waveform data and the DC attenuation output register stores the fundamental harmonic mixed waveform data, then the current DC attenuation storage state is acceptable. When the fundamental harmonic mixed waveform data is received and the current DC attenuation storage state is receivable, the current mixed transmission state is updated to allow the transmission of the fundamental harmonic mixed waveform data to the DC attenuation processing device.

[0047] It should be noted that the data buffer register in the DC attenuation processing device is the same as the DC attenuation buffer register, and the data output register is the same as the DC attenuation output register. Correspondingly, the storage status of the DC attenuation buffer register is obtained to get the stored data of the DC attenuation buffer register, and the storage status of the DC attenuation output register is obtained to get the stored data of the DC attenuation output register. The current DC attenuation storage state is determined based on the stored data of the DC attenuation buffer register and the stored data of the DC attenuation output register. The input-side handshake signal of the harmonic processing module is defined as follows: it is valid when the valid signal of the output data of the harmonic processing module from the upstream fundamental wave processing module and the current harmonic storage state from this flow harmonic processing module are high. Specifically, when the fundamental harmonic mixed waveform data is received from the harmonic processing module, the valid signal of the output data of the harmonic processing module is high, and the harmonic processing module is either idle or busy. That is, when both the stored data of the DC attenuation buffer register and the stored data of the DC attenuation output register do not store the fundamental harmonic mixed waveform data, or when the stored data of the DC attenuation buffer register does not store the fundamental harmonic mixed waveform data, and the DC attenuation output register is busy. When the device stores the fundamental harmonic mixed waveform data, the current harmonic storage state is pulled high. A handshake signal is defined on the output side of the harmonic processing module. When both the output data valid signal to the harmonic processing module and the current harmonic storage state from the harmonic processing module are pulled high (a high output data valid signal to the DC attenuation processing module indicates the presence of fundamental harmonic mixed waveform data, and a high current DC attenuation storage state from the DC attenuation processing module indicates that the current DC attenuation storage state is receivable; the DC attenuation processing module is either idle or busy), it is valid (i.e., it determines that the current mixed transmission state is ready to transmit the fundamental harmonic mixed waveform data to the DC attenuation processing device). Specifically, the DC attenuation processing module state EMPTY (idle) indicates that neither the DC attenuation buffer register nor the DC attenuation output register contains fundamental harmonic mixed waveform data; the DC attenuation processing module state BUSY (busy) indicates that the DC attenuation output register has fundamental harmonic mixed waveform data to be processed, while the DC attenuation buffer register has no fundamental harmonic mixed waveform data; and the DC attenuation processing module state FULL (saturated) indicates that both the DC attenuation buffer register and the DC attenuation output register have fundamental harmonic mixed waveform data to be processed. What is understandable is that the DC attenuation buffer register and the DC attenuation output register both store the fundamental harmonic mixed waveform data to be processed. Then, the fundamental harmonic mixed waveform data in the DC attenuation output register is superimposed with the DC attenuation data to obtain the relay protection test waveform.

[0048] In another embodiment, obtaining the current harmonic storage state and the current DC attenuation storage state, and then obtaining the current hybrid transmission state based on the fundamental harmonic hybrid waveform data, the current harmonic storage state, and the current DC attenuation storage state, includes: When both the DC attenuation buffer register and the DC attenuation output register store the fundamental harmonic mixed waveform data, the current mixed transmission state is updated to indicate that the fundamental harmonic mixed waveform data cannot be transmitted to the DC attenuation processing device.

[0049] It should be noted that when both the DC attenuation buffer register and the DC attenuation output register store the fundamental harmonic mixed waveform data (i.e., the DC attenuation processing module is saturated), it means that the DC attenuation processing module can no longer receive any extra data. Therefore, the current harmonic transmission status is updated to indicate that the fundamental harmonic mixed waveform data cannot be transmitted to the DC attenuation processing device.

[0050] In another embodiment, the DC attenuation parameters include DC attenuation amplitude and time constant parameters. Based on the current hybrid transmission state, the fundamental harmonic hybrid waveform data is transmitted to the DC attenuation processing device, so that the DC attenuation processing device obtains the DC attenuation parameters and, based on a preset DC attenuation generation algorithm and the DC attenuation parameters, obtains DC attenuation data. Then, the fundamental harmonic hybrid waveform data and the DC attenuation parameters are superimposed to obtain a relay protection test waveform, including: The DC attenuation amplitude is accumulated by using the time constant parameter to obtain the DC attenuation data.

[0051] It should be noted that the DC attenuation waveform generation unit of PIPE3 (DC attenuation processing device) receives DC attenuation parameters and generates DC attenuation data. Its preset DC attenuation generation algorithm formula is as follows: trans_wave represents DC attenuation data, and the DC attenuation parameters include... DC attenuation amplitude Here, t is the time constant parameter. After receiving the fundamental harmonic mixed waveform data from PIPE2 (harmonic processing device), the DC attenuation buffer sends it to the DC attenuation waveform generation unit. The DC attenuation waveform generation unit superimposes the generated DC attenuation data with the fundamental harmonic mixed waveform data and stores it in the mixed waveform register. Once there is sufficient space downstream of the DC attenuation processing device to receive data, the DC attenuation buffer can retrieve the data from the mixed waveform register. At this point, the relay protection test waveform generation is complete. It is understandable that the downstream of the DC attenuation processing device is not necessarily related to the waveform processing device; whether there is sufficient space to receive data is determined based on the relevant model used in the actual situation.

[0052] Furthermore, the fundamental waveform generation unit of PIPE2 (harmonic processing device) receives harmonic parameters and generates harmonic data. Its preset harmonic generation algorithm formula is as follows: harm_wave represents harmonic data, and harmonic parameters include harmonic amplitude. Harmonic frequencies Harmonic phase parameters After receiving the fundamental wave data sent by PIPE1 (fundamental wave processing device), the harmonic buffer sends it to the fundamental wave waveform generation unit. The fundamental wave waveform generation unit superimposes the generated harmonic data with the received fundamental wave data and stores it in the fundamental harmonic register. When the current DC attenuation storage state of the downstream DC attenuation processing device of the harmonic processing device is pulled high, the harmonic buffer can retrieve data from the fundamental harmonic register.

[0053] The following uses the fundamental wave processing device PIPE1 as an example to illustrate its workflow: (1): The fundamental wave processing device is initialized to the EMPTY state. The fundamental wave state control module raises the current fundamental wave storage state of the current flow according to the current system state (that is, the fundamental wave processing device is currently accepting fundamental wave parameter input) and lowers the downstream harmonic storage state (that is, the fundamental wave processing device is currently not accepting fundamental wave data output). At this time, output handshake cannot be performed.

[0054] Specifically, after the fundamental waveform generation unit calculates the fundamental data for the current moment and stores it in the fundamental register, the input handshake signal of the fundamental processing device goes high, and the state machine executes a Load operation, entering the BUSY state. It can be understood that high represents a logic 1, pulling it high changes the logic to 1, allowing data input and output; low represents a logic 0, pulling it low changes the logic to 0, disallowing data input and output.

[0055] (2): When the fundamental wave processing device is in BUSY state, the fundamental wave state control module maintains the current fundamental wave storage state as high according to the system state, pulls up the output data valid signal (that is, it means there is fundamental wave data) to the downstream, and input and output handshake can be performed at this time.

[0056] Specifically, when the fundamental frequency register is read and the current harmonic storage state fed back to the fundamental frequency processing device is high, the output handshake signal is high, the state machine will perform an Unload operation and enter the EMPTY state.

[0057] Specifically, when there is new data written to the fundamental frequency register but not yet read, the input handshake signal is high. Furthermore, if the current harmonic storage state fed back from the harmonic processing device to the fundamental frequency processing device is low, the output handshake signal is low, and the state machine will execute a Fill operation, entering the FULL state.

[0058] (3): When the fundamental wave processing device is in FULL state, the fundamental wave state control module pulls down the current fundamental wave storage state according to the current state of the system to maintain a valid signal for the output data to the downstream. At this time, input handshake cannot be performed.

[0059] Specifically, when the current fundamental frequency storage state fed back from the harmonic processing device to the fundamental frequency processing device is high, the output handshake signal is high, and the state machine will perform a Flush operation and enter the BUSY state.

[0060] In this invention, the fundamental waveform generation unit of the first-stage pipeline PIPE1 (fundamental waveform processing device) receives the input fundamental waveform parameters and generates fundamental waveform data. This fundamental waveform data is stored by a fundamental waveform temporary storage buffer, which employs a double-buffering mechanism, simultaneously pre-storing the fundamental waveform data for the next cycle while outputting the fundamental waveform data for the current cycle. The fundamental waveform generation unit of the second-stage pipeline PIPE2 (harmonic waveform processing device) receives harmonic parameters and generates harmonic data. This harmonic data is then superimposed on the fundamental waveform data received by the harmonic temporary storage buffer and returned to the buffer. The harmonic temporary storage buffer also employs a double-buffering mechanism, simultaneously pre-storing the fundamental waveform input data for the next cycle while outputting the mixed fundamental and harmonic waveform data for the current stage. The DC attenuation waveform generation unit module of the third-level flow PIPE3 (DC attenuation processing device) receives the input DC attenuation parameters and generates DC attenuation data. After superimposing it with the fundamental harmonic mixed waveform data received by the DC attenuation temporary storage buffer, it is returned to the DC attenuation temporary storage buffer. The DC attenuation temporary storage buffer is a double buffer mechanism. While outputting the superimposed waveform data of the fundamental, harmonic and DC attenuation of this level, that is, the relay protection test waveform, it pre-stores the fundamental harmonic mixed waveform data of the next cycle.

[0061] refer to Figure 4 and Figure 5 Under system clock conditions, the input-side handshake signal includes a valid output data signal from the upstream and the storage state of the corresponding processing device in this pipeline. The output-side handshake signal includes a valid output data signal from the corresponding processing device in this pipeline to the downstream and the storage state from the downstream. It can be seen that... Figure 4 In this system, the input and output handshakes are completed synchronously within the same clock cycle, and the data "input-processing-output" process has no timing delay, representing ideal zero-wait data interaction. However, in this scenario, propagation delays in the handshake signals of multi-stage pipelines can cause phase mismatches between different waveforms, such as fundamental and harmonic data, leading to distortion of harmonic analysis results. (Reference) Figure 5 In this scheme, the input and output handshakes are completed over multiple clock cycles. In real-world scenarios, this enables dynamic changes in module status. When there are blockages in the data transmission path, delayed handshakes are used to prevent data loss or errors.

[0062] This invention employs a layered architecture design, comprising fundamental wave generation pipeline, harmonic wave generation pipeline, and transient disturbance generation pipeline, combined with a distributed double-buffer mechanism and dynamic state machine scheduling, to achieve zero-blocking synthesis and real-time injection of complex waveforms such as short-circuit current, harmonic distortion, and transient oscillations. This method solves the problems of inter-stage blocking, waveform phase inaccuracy, and resource contention in traditional solutions, significantly improving the data throughput and waveform fidelity of testing equipment, and meeting the requirements of next-generation relay protection devices for high-dynamic and high-precision testing scenarios.

[0063] like Figure 2 As shown, based on the above method embodiments, corresponding system embodiments are provided; An embodiment of the present invention provides a relay protection test waveform generation system, comprising: a fundamental wave processing device, a harmonic wave processing device, and a DC attenuation processing device, wherein: The fundamental wave processing device acquires fundamental wave parameters and obtains fundamental wave data based on a preset fundamental wave generation algorithm and the fundamental wave parameters; The fundamental wave processing device acquires the current fundamental wave storage state and obtains the current fundamental wave transmission state based on the fundamental wave data, the current fundamental wave storage state, and the current harmonic storage state. Based on the current fundamental wave transmission state, the fundamental wave processing device transmits the fundamental wave data to the harmonic processing device; The harmonic processing device receives the harmonic parameters sent by the fundamental wave processing device, and obtains harmonic data based on the preset harmonic generation algorithm and the harmonic parameters. Then, the fundamental wave data and the harmonic data are superimposed to obtain fundamental-harmonic hybrid waveform data. The harmonic processing device acquires the current harmonic storage state and the current DC attenuation storage state, and then obtains the current hybrid transmission state based on the fundamental harmonic hybrid waveform data, the current harmonic storage state, and the current DC attenuation storage state; Based on the current mixed transmission state, the harmonic processing device transmits the fundamental harmonic mixed waveform data to the DC attenuation processing device; The DC attenuation processing device acquires DC attenuation parameters, and obtains DC attenuation data based on a preset DC attenuation generation algorithm and the DC attenuation parameters. Then, the fundamental harmonic mixed waveform data and the DC attenuation parameters are superimposed to obtain the relay protection test waveform.

[0064] It is understood that the above-described device embodiments correspond to the method embodiments of the present invention, and can implement the relay protection test waveform generation method provided by any of the above-described method embodiments of the present invention.

[0065] It should be noted that the device embodiments described above are merely illustrative, and some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the device embodiments provided by this invention, the connection relationships between modules indicate that they have communication connections, which can specifically be implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.

[0066] Based on the above embodiment of a relay protection test waveform generation method, another embodiment of the present invention provides a terminal device, which includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements a relay protection test waveform generation method according to any embodiment of the present invention.

[0067] For example, in this embodiment, the computer program can be divided into one or more modules, which are stored in the memory and executed by the processor to complete the present invention. The one or more modules may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in the terminal device.

[0068] The terminal device may be a desktop computer, laptop, handheld computer, or cloud server, etc. The terminal device may include, but is not limited to, a processor and a memory.

[0069] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. The processor is the control center of the terminal device, connecting all parts of the terminal device via various interfaces and lines.

[0070] Based on the above-described method embodiments, another embodiment of the present invention provides a computer-readable storage medium including a stored computer program, wherein, when the computer program is executed, it controls the device where the computer-readable storage medium is located to execute a relay protection test waveform generation method as described in any of the above-described method embodiments of the present invention.

[0071] The modules / units integrated in the device / terminal equipment, if implemented as software functional units and sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the above embodiments of the present invention can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium, etc.

[0072] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for generating test waveforms for relay protection, characterized in that, Applied to harmonic processing devices, the method includes: Harmonic parameters are obtained, and harmonic data is obtained based on a preset harmonic generation algorithm and the harmonic parameters; The fundamental wave data sent by the fundamental wave processing device is received, and then the fundamental wave data and the harmonic data are superimposed to obtain fundamental-harmonic mixed waveform data. Obtain the current harmonic storage state and the current DC attenuation storage state, and then obtain the current hybrid transmission state based on the fundamental harmonic hybrid waveform data, the current harmonic storage state, and the current DC attenuation storage state; Based on the current hybrid transmission state, the fundamental harmonic hybrid waveform data is transmitted to the DC attenuation processing device so that the DC attenuation processing device can obtain the DC attenuation parameters and obtain the DC attenuation data based on the preset DC attenuation generation algorithm and the DC attenuation parameters. Then, the fundamental harmonic hybrid waveform data and the DC attenuation parameters are superimposed to obtain the relay protection test waveform. The step of obtaining the harmonic parameters based on the fundamental wave processing device includes: Obtain the fundamental wave parameters, and based on the preset fundamental wave generation algorithm and the fundamental wave parameters, obtain the fundamental wave data; Obtain the current fundamental wave storage state, and obtain the current fundamental wave transmission state based on the fundamental wave data, the current fundamental wave storage state, and the current harmonic storage state; Based on the current fundamental wave transmission state, the fundamental wave data is transmitted to the harmonic processing device.

2. The relay protection test waveform generation method according to claim 1, characterized in that, The step of transmitting the fundamental wave data to the harmonic processing device based on the current fundamental wave transmission state includes: Retrieve data stored in the harmonic buffer register and the harmonic output register; The current harmonic storage state is determined based on the data stored in the harmonic buffer register and the data stored in the harmonic output register.

3. The method for generating a relay protection test waveform according to claim 2, characterized in that, Determining the current harmonic storage state based on the data stored in the harmonic buffer register and the data stored in the harmonic output register includes: When the harmonic buffer register stores no fundamental wave data and the harmonic output register stores fundamental wave data, or when neither the harmonic buffer register nor the harmonic output register stores fundamental wave data, the current harmonic storage state is determined to be acceptable. When the fundamental wave data is received and the current harmonic storage state is receivable, the current fundamental wave transmission state is updated to allow the fundamental wave data to be transmitted to the harmonic processing device.

4. The method for generating a relay protection test waveform according to claim 2, characterized in that, Determining the current harmonic storage state based on the data stored in the harmonic buffer register and the data stored in the harmonic output register includes: When both the harmonic buffer register and the harmonic output register store the fundamental wave data, the current fundamental wave transmission status is updated to indicate that the fundamental wave data cannot be transmitted to the harmonic processing device.

5. The method for generating a relay protection test waveform according to claim 1, characterized in that, The step of obtaining the current harmonic storage state and the current DC attenuation storage state, and then obtaining the current hybrid transmission state based on the fundamental harmonic hybrid waveform data, the current harmonic storage state, and the current DC attenuation storage state, includes: Retrieve the data stored in the DC attenuation buffer register and the DC attenuation output register; When both the DC attenuation buffer register and the DC attenuation output register do not store the fundamental harmonic mixed waveform data, or when the DC attenuation buffer register does not store the fundamental harmonic mixed waveform data and the DC attenuation output register stores the fundamental harmonic mixed waveform data, then the current DC attenuation storage state is acceptable. When the fundamental harmonic mixed waveform data is received and the current DC attenuation storage state is receivable, the current mixed transmission state is updated to allow the transmission of the fundamental harmonic mixed waveform data to the DC attenuation processing device.

6. The method for generating a relay protection test waveform according to claim 5, characterized in that, The step of obtaining the current harmonic storage state and the current DC attenuation storage state, and then obtaining the current hybrid transmission state based on the fundamental harmonic hybrid waveform data, the current harmonic storage state, and the current DC attenuation storage state, includes: When both the DC attenuation buffer register and the DC attenuation output register store the fundamental harmonic mixed waveform data, the current mixed transmission state is updated to indicate that the fundamental harmonic mixed waveform data cannot be transmitted to the DC attenuation processing device.

7. The method for generating a relay protection test waveform according to claim 1, characterized in that, The DC attenuation parameters include DC attenuation amplitude and time constant parameters. Based on the current mixed transmission state, the fundamental harmonic mixed waveform data is transmitted to the DC attenuation processing device, so that the DC attenuation processing device obtains the DC attenuation parameters and, based on a preset DC attenuation generation algorithm and the DC attenuation parameters, obtains DC attenuation data. Then, the fundamental harmonic mixed waveform data and the DC attenuation parameters are superimposed to obtain the relay protection test waveform, including: The DC attenuation amplitude is accumulated by using the time constant parameter to obtain the DC attenuation data.

8. A relay protection test waveform generation system, characterized in that, include: The device includes a fundamental frequency processing unit, a harmonic frequency processing unit, and a DC attenuation processing unit, wherein: The fundamental wave processing device acquires fundamental wave parameters and obtains fundamental wave data based on a preset fundamental wave generation algorithm and the fundamental wave parameters; The fundamental wave processing device acquires the current fundamental wave storage state and obtains the current fundamental wave transmission state based on the fundamental wave data, the current fundamental wave storage state, and the current harmonic storage state. Based on the current fundamental wave transmission state, the fundamental wave processing device transmits the fundamental wave data to the harmonic processing device; The harmonic processing device receives the harmonic parameters sent by the fundamental wave processing device, and obtains harmonic data based on the preset harmonic generation algorithm and the harmonic parameters. Then, the fundamental wave data and the harmonic data are superimposed to obtain fundamental-harmonic hybrid waveform data. The harmonic processing device acquires the current harmonic storage state and the current DC attenuation storage state, and then obtains the current hybrid transmission state based on the fundamental harmonic hybrid waveform data, the current harmonic storage state, and the current DC attenuation storage state; Based on the current mixed transmission state, the harmonic processing device transmits the fundamental harmonic mixed waveform data to the DC attenuation processing device; The DC attenuation processing device acquires DC attenuation parameters, and obtains DC attenuation data based on a preset DC attenuation generation algorithm and the DC attenuation parameters. Then, the fundamental harmonic mixed waveform data and the DC attenuation parameters are superimposed to obtain the relay protection test waveform.

9. A terminal device, characterized in that, The device includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, it implements a relay protection test waveform generation method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, include: A stored computer program, wherein, when the computer program is executed, it controls the device containing the computer-readable storage medium to perform a relay protection test waveform generation method as described in any one of claims 1-7.

Images