Electronic equipment, chip, IIC interface device and power consumption control method thereof
By setting multiple address comparison points in the address of the access command for matching, the problem of high power consumption of peripheral devices of mobile electronic devices in low power mode is solved, and the effects of low power consumption and low false wake-up are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHIPONE (SHENZHEN) TECH CO LTD
- Filing Date
- 2025-12-22
- Publication Date
- 2026-05-08
AI Technical Summary
Peripherals of mobile electronic devices cannot effectively reduce power consumption in low-power mode, and adding a dedicated wake-up pin will increase system integration costs and complexity.
Set at least two address comparison points in the address of the received access command, perform at least two address matches to determine whether to wake up the IIC device, and start the power and clock in advance before waking up.
It greatly reduces power consumption, minimizes the possibility of false wake-ups, ensures that IIC devices can respond to access commands in a timely manner, and avoids communication failures.
Smart Images
Figure CN121996050A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communication technology, specifically to an electronic device, a chip, an IIC interface device, and a power consumption control method thereof. Background Technology
[0002] As mobile electronic devices become increasingly prevalent, their functional requirements are also growing. Mobile electronic devices typically consist of a main controller and numerous peripheral devices, with many functions gradually shifting to peripheral devices (such as wearable devices). Wearable devices experience very short battery life when the screen is constantly on or during prolonged use. Frequent charging is inconvenient for users, and excessive power consumption leading to overheating also negatively impacts the user experience. To achieve goals such as thinness, low power consumption, and an excellent user experience, peripheral devices enter a low-power mode when there are no tasks to process.
[0003] Taking the use of IIC as a slave device interface for peripheral devices as an example, in order to respond to access commands at any time, peripheral devices typically only turn off part of their clock when there are no transactions to process. However, this approach cannot reduce power consumption to the ideal target. Alternatively, a dedicated wake-up pin can be set up on the peripheral device. When access to the peripheral device is needed, the dedicated wake-up pin triggers the exit from low-power mode to working mode. However, the addition of a dedicated wake-up pin increases the system integration cost and makes the wake-up process more complex. Summary of the Invention
[0004] To address the aforementioned technical problems, this application provides an electronic device, chip, IIC interface device, and power consumption control method thereof that can reduce power consumption and false wake-up.
[0005] According to one aspect of this application, a power consumption control method for an IIC interface device is provided, comprising: setting at least two address comparison points in the address of a received access instruction, wherein the access instruction includes at least an address and an operation word; performing address matching with the address of an IIC device in a low-power state at each address comparison point; and determining whether to wake up the IIC device based on the results of the at least two address matchings.
[0006] Optionally, it further includes: returning the response instruction generated by the IIC device when the IIC device is woken up and the access instruction has been read.
[0007] Optionally, determining whether to wake up the IIC device according to the at least two address matching results includes: determining whether to start the power supply and clock of the IIC device according to the address matching result of the address comparison point before the last address comparison point; and in the case of starting the power supply and clock of the IIC device, determining whether to wake up the IIC device according to the address matching result of the last address comparison point.
[0008] Optionally, setting at least two address comparison points in the address of the received access instruction includes: setting a first address comparison point at the nth bit of the address of the access instruction; setting a second address comparison point at the mth bit of the address of the access instruction, where the address in the access instruction includes m bits, n < m, and n and m are positive integers.
[0009] Optionally, m - n > 1.
[0010] Optionally, performing address matching between each address comparison point and the address of the IIC device in the low-power state includes: at the first address comparison point, performing a first address matching between the first n bits of the address in the access instruction and the first n bits of the address of the IIC device; and at the second address comparison point, performing a second address matching between the complete address in the access instruction and the complete address of the IIC device.
[0011] Optionally, when the first address matching is successful, start the power supply and clock of the IIC device and continue the second address matching, otherwise end the address matching between the IIC device and the access instruction.
[0012] Optionally, when the second address matching is successful, wake up the IIC device, otherwise turn off the power supply and clock of the IIC device.
[0013] According to another aspect of the present application, there is provided an IIC interface device, including: a setting unit that sets at least two address comparison points in the address of the received access instruction, the access instruction at least including an address and an operation word; an addressing unit that performs address matching between each address comparison point and the address of the IIC device in the low-power state; and a control unit that determines whether to wake up the IIC device according to the at least two address matching results.
[0014] According to yet another aspect of the present application, there is provided an electronic device including the IIC interface device as described above.
[0015] According to yet another aspect of the present application, there is provided a chip including the IIC interface device as described above.
[0016] The electronic device, chip, IIC interface device and power consumption control method provided in this application can greatly reduce power consumption and reduce the possibility of false wake-up by setting at least two address comparison points in the address of the received access instruction, matching the address of the IIC device in a low power state at each address comparison point, and determining whether to wake up the IIC device based on the results of at least two address matchings.
[0017] Furthermore, this application determines whether to power on the IIC device and its clock based on the address matching results at the address comparison points before the last address comparison point. If the IIC device's power on and clock are powered on, it determines whether to wake up the IIC device based on the address matching results at the last address comparison point, and returns the response command generated by the IIC device after waking up the IIC device and reading the access command. In other words, this application powers on the IIC device and its clock in advance before waking it up through at least two address matches, thereby greatly reducing power consumption, minimizing the possibility of false wake-ups, and ensuring that the response command can be correctly generated to respond to the access command, avoiding communication failure due to the inability to respond to the access command in a timely manner.
[0018] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit this application. Attached Figure Description
[0019] Figure 1 A waveform diagram of a power consumption control method is shown;
[0020] Figure 2 A flowchart illustrating the power consumption control method provided according to the first embodiment of this application is shown;
[0021] Figure 3 A flowchart illustrating a power consumption control method according to a second embodiment of this application is shown.
[0022] Figure 4 A flowchart illustrating a power consumption control method according to a third embodiment of this application is shown.
[0023] Figure 5 A waveform diagram of a power consumption control method according to a third embodiment of this application is shown;
[0024] Figure 6 This diagram illustrates the structure of a communication system according to a fourth embodiment of the present application.
[0025] Figure 7 A schematic diagram of the structure of the IIC interface device in a communication system according to the fourth embodiment of this application is shown. Detailed Implementation
[0026] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.
[0027] Figure 1 A waveform diagram of a power consumption control method is shown.
[0028] like Figure 1 As shown, the IIC interface device of the IIC device communicates with the device connected to the bus via the serial data line SDA and the serial clock line SCL. When the IIC interface device receives an access command (such as a read or write operation), it matches the address ADDRESS in the access command with the IIC device's own address after reading it. If the address match is successful, it provides a valid enable signal OSCI_ENN to start the IIC device's clock and wake up the IIC device in a low-power state. When the IIC device wakes up and finishes reading the access command, it needs to directly generate an ACK command to acknowledge the request. The IIC device requires its own clock and power supply to generate the ACK command.
[0029] Ideally, the clock signal OSCI_Ideal should be triggered when the valid edge of the enable signal OSCI_ENN arrives. However, the actual clock signal OSCI_Real should be triggered a certain time after the valid edge of the enable signal OSCI_ENN arrives. This means that in practice, the clock on an IIC device may not be activated quickly enough to respond to access commands promptly, leading to communication failure.
[0030] In response to the above situation, the need to manually separate the address and data phases imposes requirements beyond the communication protocol on the compatibility between IIC devices, which can cause many inconveniences during actual debugging.
[0031] This application provides an electronic device, chip, IIC interface device, and power control method thereof that can reduce power consumption and false wake-up. The power control method provided in this application is executed by the IIC interface device in the IIC device. Further, the aforementioned IIC device is, for example, a slave device in a communication system.
[0032] Figure 2 A flowchart illustrating the power consumption control method provided according to the first embodiment of this application is shown.
[0033] like Figure 2 As shown, the power consumption control method provided in the first embodiment includes the following steps:
[0034] Step S100: Set at least two address comparison points in the address of the received access instruction. The access instruction includes at least an address and an operand.
[0035] Step S200: At each address comparison point, perform address matching with the address of the IIC device in a low-power state. Further, a low-power state refers to a sleep state where other hardware modules of the IIC device are turned off, retaining only the wake-up path. In other embodiments, a low-power state can also be a sleep state where some modules are selectively turned off (not necessary), maintaining low-load operation of critical modules.
[0036] Step S300: Determine whether to wake up the IIC device based on at least two address matching results.
[0037] In the first embodiment of this application, at least two address comparison points are set at different positions of the address of the access instruction. At each address comparison point, the address read from the access instruction is matched with the corresponding address of the IIC device in a low-power state. Based on the results of at least two address matching operations, it is determined whether to wake up the IIC device. This can greatly reduce power consumption and decrease the possibility of false wake-ups.
[0038] Furthermore, waking up refers to switching the IIC device from a low-power state (sleep state / hibernation state) to a normal operating state. In this application, the power supply and clock of the IIC device are activated, for example, before waking up the IIC device. The power supply and clock of the IIC device, after startup, provide available power and clock signals, for example, before or after waking up the IIC device, or both simultaneously.
[0039] Furthermore, in this application, the power supply and clock of the IIC device are provided with available power and clock signals after startup, before feedback response instructions are given.
[0040] Figure 3 A flowchart illustrating the power consumption control method provided according to the second embodiment of this application is shown.
[0041] like Figure 3 As shown, the power consumption control method provided in the second embodiment includes the following steps:
[0042] Step S100: Set at least two address comparison points in the address of the received access instruction.
[0043] Step S200: At each address comparison point, perform address matching with the address of the IIC device in a low-power state.
[0044] Step S310: Determine whether to activate the power supply and clock of the IIC device based on the address matching result of the address comparison points before the last address comparison point, and determine whether to wake up the IIC device based on the address matching result at the last address comparison point in the case of activating the power supply and clock of the IIC device.
[0045] Step S400: Return the response instruction generated by the IIC device when the IIC device is woken up and the access instruction has been read.
[0046] In the second embodiment of the present application, it is further determined whether to prematurely activate the power supply and clock of the IIC device based on the address matching result of the address comparison points before the last address comparison point, and determine whether to wake up the IIC device based on the address matching result at the last address comparison point in the case of prematurely activating the power supply and clock of the IIC device, and return the response instruction generated by the IIC device when the IIC device is woken up and the access instruction has been read. That is, the second embodiment prematurely activates the power supply and clock of the IIC device before waking up the IIC device, thereby greatly reducing power consumption and the possibility of false wake-up, and ensuring that the woken-up IIC device can generate a response instruction in time to respond to the access instruction with the support of the power supply and clock of the IIC device, avoiding communication failure caused by the inability to respond to the access instruction in time.
[0047] Figure 4 The flowchart showing the power consumption control method provided by the third embodiment of the present application. Figure 5 The waveform diagram showing the power consumption control method provided by the third embodiment of the present application.
[0048] In the third embodiment, the address of the access instruction and the address of the IIC device in the low power consumption state are, for example, subjected to two address matches. It should be noted that the implementation of the present application is not limited to this. For example, the address of the access instruction and the address of the IIC device in the low power consumption state may also be subjected to three address matches, and it is determined whether to activate the power supply and clock of the IIC device according to the first or second address matching result, and it is determined whether to wake up the IIC device according to the third address matching result.
[0049] As Figure 4 shown, the power consumption control method provided by the third embodiment includes the following steps:
[0050] Step S510: Set a first address comparison point at the nth bit of the address of the access instruction, and set a second address comparison point at the mth bit of the address of the access instruction. Wherein, the address in the access instruction includes m bits, n < m, and n, m are positive integers. Further, m - n > 1. Exemplarily, as Figure 5As shown, an access instruction (e.g., a read or write operation) includes an address (ADDRESS) and an operation word (R / W) following the address (ADDRESS). Furthermore, data on the IIC bus is transmitted in 8-bit bytes. The transmitter releases the data line during the 9th clock pulse after transmitting each byte, and the receiver sends an acknowledge signal. For example, the first address comparison point is set in the nth bit (e.g., n=3) of the address (ADDRESS) in the access instruction, and the second address comparison point is set in the mth bit (e.g., m=7) of the address (ADDRESS) in the access instruction.
[0051] Step S520: At the first address comparison point, perform the first address matching by comparing the first n bits of the address in the access instruction with the first n bits of the address in the IIC device. Address matching refers to comparing each bit of the address in the currently read access instruction with the corresponding bit in the address of the IIC device.
[0052] If the first address match fails, proceed to step S540: end the address matching between the IIC device and the access command. This allows step S510 to be re-executed upon receiving the next access command.
[0053] If the first address match is successful, proceed to step S530: power on and clock the IIC device. For example, as... Figure 5 As shown, an enable signal OSCI_ENN is provided to start the clock of the IIC device upon successful address matching for the first time. That is, if address matching is performed at the first address comparison point and the result is a successful address match, the valid edge of the enable signal OSCI_ENN arrives. Furthermore, the clock startup required by the IIC device typically takes 8-15µs or more to provide a usable internal clock signal. For example, at a communication rate of 400K, the bus clock cycle tscl is approximately 2.5µs. In this embodiment, the clock and power supply of the IIC device are provided, for example, by the 6th bit of the address ADDRESS in the access instruction, providing the usable clock signal OSCI.
[0054] Next, step S550 is executed: at the second address comparison point, the complete address in the access instruction is matched with the complete address of the IIC device for the second time.
[0055] If the second address match fails, step S570 is executed: the power supply and clock of the IIC device are turned off. The IIC device re-enters the low-power state. That is, the clock of the IIC device provides the clock signal OSCI_false. This application turns on the clock and power of the IIC device in advance after the first address match is successful, and turns off the clock and power of the IIC device and controls the IIC device to re-enter the low-power state when the second address match fails. This eliminates the need for other modules to participate in the confirmation, further reducing power consumption and system control complexity.
[0056] If the second address match is successful, step S560 is executed: wake up the IIC device. Since the IIC device's clock and power were already turned on before waking it up, subsequent communication will proceed after the IIC device is woken up. That is, the IIC device's clock provides the clock signal OSCI_true.
[0057] Next, step S580 is executed: upon completion of reading the access command, the response command generated by the IIC device is returned. Further, the IIC device generates a response command ACK on the next (9th) clock pulse after reading the access command, and the IIC interface device returns the response command ACK.
[0058] In the third embodiment of this application, a first address comparison point is set at the nth bit of the address of the access instruction, and a second address comparison point is set at the mth bit of the address of the access instruction. Based on the address matching result at the first address comparison point, it is determined whether to pre-start the power and clock of the IIC device. If the power and clock of the IIC device are pre-started, it is determined whether to wake up the IIC device based on the address matching result at the second address comparison point. Upon waking up the IIC device and reading the access instruction, a response instruction generated by the IIC device is returned. This third embodiment ensures that the woken-up IIC device generates a timely response instruction to the access instruction by pre-starting the power and clock of the IIC device before waking it up, and with the support of the IIC device's power and clock.
[0059] Figure 6 A schematic diagram of the structure of a communication system provided according to the fourth embodiment of this application is shown. Figure 7 A schematic diagram of the structure of the IIC interface device in a communication system according to the fourth embodiment of this application is shown.
[0060] like Figure 6 As shown, the communication system includes a master device 610 and a slave device 620 that communicate via an IIC interface. The IIC interface communicates via a serial clock line SCL and a serial data line SDA. The power consumption control method provided in this application is implemented, for example, on the IIC interface device 630 of the slave device 620. However, the implementation of this application is not limited thereto.
[0061] like Figure 7 As shown, the IIC interface device 630 includes a setting unit 631, an addressing unit 632, and a control unit 633.
[0062] The setting unit 631 sets at least two address comparison points in the address of the received access instruction, and the access instruction at least includes an address and an operation word. Exemplarily, a first address comparison point is set at the nth bit of the address of the access instruction, and a second address comparison point is set at the mth bit of the address of the access instruction. Wherein, the address in the access instruction includes m bits, n < m, and n and m are positive integers.
[0063] The addressing unit 632 performs address matching between each address comparison point and the address of the IIC device in the low power state. Exemplarily, at the first address comparison point, the first n bits of the address in the access instruction are subjected to the first address matching with the first n bits of the address of the IIC device. At the second address comparison point, the complete address in the access instruction is subjected to the second address matching with the complete address of the IIC device.
[0064] The control unit 633 determines whether to wake up the IIC device according to at least two address matching results. Exemplarily, when the first address matching is successful, the control unit 633 starts the power supply and clock of the IIC device and continues the second address matching, otherwise, it ends the address matching between the IIC device and the access instruction. When the second address matching is successful, the control unit 633 wakes up the IIC device, otherwise, it shuts down the power supply and clock of the IIC device.
[0065] The electronic device, chip, IIC interface device and its power consumption control method provided by the present application set at least two address comparison points in the address of the received access instruction, perform address matching between each address comparison point and the address of the IIC device in the low power state, and determine whether to wake up the IIC device according to at least two address matching results, thereby greatly reducing power consumption and reducing the possibility of false wake-up.
[0066] Further, the present application determines whether to start the power supply and clock of the IIC device according to the address matching result of the address comparison point before the last address comparison point. When the power supply and clock of the IIC device are started, it determines whether to wake up the IIC device according to the address matching result of the last address comparison point, and returns the response instruction generated by the IIC device when the IIC device is woken up and the access instruction is read completely. That is, the present application starts the power supply and clock of the IIC device in advance before waking up the IIC device through at least two address matchings, thereby greatly reducing power consumption and reducing the possibility of false wake-up, while ensuring that the response instruction can be correctly generated to respond to the access instruction, and avoiding communication failure caused by the inability to respond to the access instruction in time.
[0067] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this application and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
[0068] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.
Claims
1. A power consumption control method for an IIC interface device, characterized in that, Comprising: Setting at least two address comparison points in the address of the received access instruction, the access instruction at least including an address and an operation word; Performing address matching between each address comparison point and the address of the IIC device in a low-power state, and Determining whether to wake up the IIC device according to the results of the at least two address matches.
2. The power consumption control method according to claim 1, characterized in that, Further comprising: Returning the response instruction generated by the IIC device when the IIC device is woken up and the access instruction is read completely.
3. The power consumption control method according to claim 1, characterized in that, Determining whether to wake up the IIC device according to the results of the at least two address matches includes: Determining whether to start the power supply and clock of the IIC device according to the address match result of the address comparison point before the last address comparison point; and In the case of starting the power supply and clock of the IIC device, determining whether to wake up the IIC device according to the address match result of the last address comparison point.
4. The power consumption control method according to any one of claims 1 to 3, characterized in that, Setting at least two address comparison points in the address of the received access instruction includes: Setting a first address comparison point at the nth bit of the address of the access instruction; Setting a second address comparison point at the mth bit of the address of the access instruction, wherein the address in the access instruction includes m bits, n < m, and n, m are positive integers.
5. The power consumption control method according to claim 4, characterized in that, m - n > 1.
6. The power consumption control method according to claim 4, characterized in that, Performing address matching between each address comparison point and the address of the IIC device in a low-power state includes: At the first address comparison point, performing a first address match between the first n bits of the address in the access instruction and the first n bits of the address of the IIC device; and At the second address comparison point, performing a second address match between the complete address in the access instruction and the complete address of the IIC device.
7. The power consumption control method according to claim 6, characterized in that When the first address match is successful, starting the power supply and clock of the IIC device and continuing the second address match, otherwise ending the address match between the IIC device and the access instruction.
8. The power consumption control method according to claim 6, characterized in that, When the second address match is successful, waking up the IIC device, otherwise turning off the power supply and clock of the IIC device.
9. An IIC interface device, characterized in that, Comprising: A setting unit for setting at least two address comparison points in the address of the received access instruction, the access instruction at least including an address and an operation word; An addressing unit for performing address matching between each address comparison point and the address of the IIC device in a low-power state; And A control unit for determining whether to wake up the IIC device according to the results of the at least two address matches.
10. An electronic device, characterized in that, Including the IIC interface device according to claim 9.
11. A chip, characterized in that, Including the IIC interface device according to claim 9.